M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM 240pin Unbuffered DDR2 SDRAM MODULE Based on 64Mx8 DDR2 SDRAM Features * Programmable Operation: - Device Latency: 3, 4, 5 - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * JEDEC Standard 240-pin Dual In-Line Memory Module * 64Mx64 and 128Mx64 DDR2 Unbuffered DIMM based on 64Mx8 DDR2 SDRAM * Performance: PC2-3200 PC2-4200 PC2-5300 Speed Sort DIMM Latency* f CK Clock Frequency t CK Clock Cycle f DQ DQ Burst Frequency Unit 5A 37B 3C 3 4 5 200 266 333 MHz 5 3.7 3 ns 400 533 667 MHz * 14/10/1 Addressing (row/column/rank) - M2Y51264TU88A2B, M2Y51264TU88A0B M2U51264TU88A2B, M2U51264TU88A0B M2U51264TU88A2F, M2U51264TU88A0F * 14/10/2 Addressing (row/column/rank) - M2Y1G64TU8HA2B, M2Y1G64TU8HA0B M2U1G64TU8HA2B, M2U1G64TU8HA0B * 7.8 s Max. Average Periodic Refresh Interval * Serial Presence Detect * Gold contacts * SDRAMs in 60-ball FBGA Package * RoHs compliance - M2Y1G64TU8HA2B, M2Y1G64TU8HA0B M2Y51264TU88A2B, M2Y51264TU88A0B * Intended for 200 MHz, 266MHz, and 333MHz applications * Inputs and outputs are SSTL-18 compatible * VDD = VDDQ = 1.8Volt 0.1 * SDRAM have 4 internal banks for concurrent operation * Differential clock inputs * Data is read or written on both clock edges * Bi-directional data strobe with one clock cycle preamble and one-half clock post-amble * Address and control signals are fully synchronous to positive clock edge Description M2Y51264TU88A2B, M2Y51264TU88A0B, M2Y1G64TU8HA2B, M2Y1G64TU8HA0B, M2U51264TU88A2B, M2U51264TU88A0B, M2U51264TU88A0F, M2U51264TU88A2F, M2U1G64TU8HA0B and M2U1G64TU8HA2B are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM), organized as a one-rank 64Mx64 and two ranks 128Mx64 high-speed memory array. Modules use eight 64Mx8 (M2Y51264TU88A2B, M2Y51264TU88A0B, M2U51264TU88A2B, M2U51264TU88A0F, M2U51264TU88A2F and M2U51264TU88A0B) and sixteen 64Mx8 (M2Y1G64TU8HA2B, M2Y1G64TU8HA0B, M2U1G64TU88A2B and M2U1G64TU88A0B) DDR2 SDRAMs in FBGA packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 200MHz (266MHz and 333MHz) clock speeds and achieves high-speed data transfer rates of up to 400MHz (533MHz and 667MHz). Prior to any access operation, the device latency and burst / length / operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.0 08/2006 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Ordering Information Part Number Speed Organization Leads Power M2Y1G64TU8HA2B-5A Note Green M2Y1G64TU8HA0B-5A 128Mx64 M2U1G64TU8HA2B-5A M2U1G64TU8HA0B-5A M2Y51264TU88A2B-5A M2Y51264TU88A0B-5A 200MHz (5ns @ CL = 3) DDR2-400 Green PC2-3200 M2U51264TU88A2B-5A 64Mx64 M2U51264TU88A0B-5A M2U51264TU88A0F-5A M2U51264TU88A2F-5A M2Y1G64TU8HA2B-37B Green M2Y1G64TU8HA0B-37B 128Mx64 M2U1G64TU8HA2B-37B M2U1G64TU8HA0B-37B M2Y51264TU88A2B-37B M2Y51264TU88A0B-37B 266MHz (3.7ns @ CL = 4) DDR2-533 PC2-4200 M2U51264TU88A2B-37B Gold 1.8V Green 64Mx64 M2U51264TU88A0B-37B M2U51264TU88A0F-37B M2U51264TU88A2F-37B M2Y1G64TU8HA2B-3C Green M2Y1G64TU8HA0B-3C 128Mx64 M2U1G64TU8HA2B-3C M2U1G64TU8HA0B-3C M2Y51264TU88A2B-3C M2Y51264TU88A0B-3C 333MHz (3ns @ CL = 5) DDR2-667 M2U51264TU88A2B-3C Green PC2-5300 64Mx64 M2U51264TU88A0B-3C M2U51264TU88A0F-3C M2U51264TU88A2F-3C REV 1.0 08/2006 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Pin Description CK0, CKE0, CKE1 Differential Clock Inputs DQ0-DQ63 Clock Enable DQS0-DQS8 Row Address Strobe - Write Enable , A10/AP BA0, BA1 Chip Selects Address Inputs NC REV 1.0 08/2006 Differential data strobes VDD Power (1.8V) VREF Ref. Voltage for SSTL_18 inputs VDDSPD Serial EEPROM positive power supply Column Address Input/Auto-precharge VSS Ground SDRAM Bank Address Inputs SCL Serial Presence Detect Clock Input Reset pin ODT0, ODT1 Bidirectional data strobes DM0-DM8/DQS9-17 Input Data Mask/High Data Strobes Column Address Strobe A0-A9, A11-A13 Data input/output SDA Active termination control lines SA0-2 Serial Presence Detect Data input/output Serial Presence Detect Address Inputs No Connect 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Pinout Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 VREF 42 NC 82 VSS 121 VSS 162 NC 202 DM4 2 VSS 43 NC 83 122 DQ4 163 VSS 203 NC 3 DQ0 44 VSS 84 DQS4 123 DQ5 164 NC 204 VSS 4 DQ1 45 NC 85 VSS 124 VSS 165 NC 205 DQ38 5 VSS 46 NC 86 DQ34 125 DM0, DQS9 166 VSS 206 DQ39 47 VSS 87 DQ35 126 167 NC 207 VSS DQS0 48 NC 88 VSS 127 VSS 168 NC 208 DQ44 8 VSS 49 NC 89 DQ40 128 DQ6 169 VSS 209 DQ45 9 DQ2 50 VSS 90 DQ41 129 DQ7 170 VDDQ 210 VSS 10 DQ3 51 VDDQ 91 VSS 130 VSS 171 CKE1 211 DM5 11 VSS 52 CKE0 92 131 DQ12 172 VDD 212 NC 12 DQ8 53 VDD 93 DQS5 132 DQ13 173 NC 213 VSS 13 DQ9 54 NC 94 VSS 133 VSS 174 NC 214 DQ46 14 VSS 55 NC 95 DQ42 134 DM1, DQS10 DQ47 56 VDDQ 96 DQ43 135 A11 97 VSS 136 VSS CK1 6 7 15 16 DQS1 57 17 VSS 58 A7 98 DQ48 137 18 NC 59 VDD 99 DQ49 138 19 NC 60 A5 100 VSS 139 20 VSS 61 A4 101 SA2 21 DQ10 62 VDDQ 102 22 DQ11 63 A2 103 23 VSS 64 VDD 104 24 DQ16 25 DQ17 65 26 VSS 27 175 VDDQ 215 176 A12 216 VSS 177 A9 217 DQ52 DQ53 178 VDD 218 179 A8 219 VSS VSS 180 A6 220 CK2 140 DQ14 181 VDDQ 221 NC 141 DQ15 182 A3 222 VSS VSS 142 VSS 183 A1 223 DM6 184 VDD 224 NC 225 VSS 226 DQ54 227 DQ55 143 DQ20 105 DQS6 144 DQ21 VSS 106 VSS 145 VSS 185 66 VSS 107 DQ50 146 DM2 186 67 VDD 108 DQ51 147 NC 187 VDD 228 VSS KEY KEY CK0 28 DQS2 68 NC 109 VSS 148 VSS 188 A0 229 DQ60 29 VSS 69 VDD 110 DQ56 149 DQ22 189 VDD 230 DQ61 30 DQ18 70 A10/AP 111 DQ57 150 DQ23 190 BA1 231 VSS 31 DQ19 71 BA0 112 VSS 151 VSS 191 VDDQ 232 DM7 32 VSS 72 VDDQ 113 152 DQ28 192 233 NC 33 DQ24 73 114 DQS7 153 DQ29 193 234 VSS 34 DQ25 74 115 VSS 154 VSS 194 VDDQ 235 DQ62 35 VSS 75 116 DQ58 155 DM3 195 ODT0 236 DQ63 117 DQ59 156 NC 196 A13 237 VSS 36 VDDQ 76 37 DQS3 77 ODT1 118 VSS 157 VSS 197 VDD 238 VDDSPD 38 VSS 78 VDDQ 119 SDA 158 DQ30 198 VSS 239 SA0 39 DQ26 79 VSS 120 SCL 159 DQ31 199 DQ36 240 SA1 40 DQ27 80 DQ32 160 VSS 200 DQ37 41 VSS 81 DQ33 161 NC 201 VSS REV 1.0 08/2006 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Input/Output Functional Description Symbol CK0, CK1, CK2 , , Type Polarity Function (SSTL) The positive differential clock inputs which drives the input to the on-DIMM PLL. All the Positive DDR2 SDRAM address and control inputs are sampled on the rising edge of their Edge associated clocks. (SSTL) Negative The negative edge of system clock inputs which drives the input to the on-DIMM PLL. Edge CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. , (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. (SSTL) Active Low When sampled at the positive rising edge of the clock, command to be executed. , , , , define the VREF Supply Reference voltage for SSTL-18 inputs VDDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity ODT0, ODT1 Input Active High BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. (SSTL) - During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA10) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. (SSTL) Active High A0 - A9 A10/AP A11 - A13 DQ0 - DQ63 VDD, VSS Supply DQS0 - DQS8 - (SSTL) DM0 - DM8 Input On-Die Termination control signals Data and Check Bit Input/Output pins. Power and ground for the DDR SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. VDDSPD REV 1.0 08/2006 Supply Serial EEPROM positive power supply. 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) # " & ' # ## # #" #& #' # #! $% $% $% $% # $% $% " $% & $% ' $% $% $% $% # $% $% " $% & $% ' " " ! # " $% $% $% $% # $% $% " $% & $% ' # " & ' $% $% $% $% # $% $% " $% & $% ' " & & & ' ! # ! " " " "# " "" # ' # ' " & ' ! # # 5 $% $% $% $% # $% $% " $% & $% ' $% $% $% $% # $% $% " $% & $% ' 5 5 # 2 % 8 2 % 8 "& "' " "! & & & &# # 5 # $% $% $% $% # $% $% " $% & $% ' $% $% $% $% # $% $% " $% & $% ' & ' ' ' ' ' ' ' ' ( $% ) *+, - . /0 *+ 1 ) 0* .- ( ( $ $ $ 2 $ *0 , * *1 0 )*( #( $ $ %0, 3$ "4 ( 5 67 67 7 7 "( %0, 3$ "4 "( 11 *1/ * %0, 3$ "4 REV 1.0 08/2006 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (1GB, 2 Rank, 64Mx8 DDR2 SDRAMs) $% $% $% $% # $% $% " $% & $% ' # " & ' # ## # #" #& #' # #! $% $% $% $% # $% $% " $% & $% ' $% $% $% $% # $% $% " $% & $% ' $% $% $% $% # $% $% " $% & $% ' $% $% $% $% # $% $% " $% & $% ' $% $% $% $% # $% $% " $% & $% ' " " $% $% $% $% # $% $% " $% & $% ' ! # " $% $% $% $% # $% $% " $% & $% ' # ! " & ' " # & & & ' $% $% $% $% # $% $% " $% & $% ' ! # $% $% $% $% # $% $% " $% & $% ' ! " " " "# " "" # ' # ' $% $% $% $% # $% $% " $% & $% ' " & ' ! # # 5 # 5 5 # 2 2 % 8 % 8 "& "' " "! & & & &# $% $% $% $% # $% $% " $% & $% ' 5 # 2 2 % 8 % 8 $% $% $% $% # $% $% " $% & $% ' $% $% $% $% # $% $% " $% & $% ' & ' $% $% $% $% # $% $% " $% & $% ' $% $% $% $% # $% $% " $% & $% ' " " " " " " ' " ' " ( $% ) *+ , -. /0 *+ 1) 0* .- ( ( $ $ $ 2 $ *0 , * *1 0 )*( #( $ $ %0, 3$ "4 ( 5 67 67 7 7 "( %0, 3$ "4 "( 11 *1/ * %0, 3$ "4 REV 1.0 08/2006 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect - Part 1 of 2 (512MB) 64Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Serial PD Data Entry (Hexadecimal) SPD Entry Value Description -5A -37B -3C -5A -37B -3C 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 5 6 Data Width of this Assembly 7 8 9 DDR2 SDRAM Device Cycle Time at Maximum Support Latency CL=5 5ns 3.75ns 3ns 50 3D 30 10 DDR2 SDRAM Device Access Time (tac) from Clock at CL=5 0.6ns 0.5ns 0.45ns 60 50 45 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Primary DDRII SDRAM Width 14 Error Checking DDRII SDRAM Device Width 15 Reserved 16 17 18 DDR2 SDRAM Device Attributes: 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 24 Maximum Data Access Time (tac) from Clock at CL=4 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time (tac) from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 7.5ns 1E 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum Active to Precharge Time (tRAS) 45ns 2D 31 Module Bank Density 512MB 80 32 Address and Command Input Setup Time Before Clock (tIS) 0.35ns 0.25ns 0.2ns 35 25 20 33 Address and Command Input Hold Time After Clock (tIH) 0.475ns 0.375ns 0.275ns 47 37 27 34 Data Input Setup Time Before Clock (tDS) 0.15ns 0.1ns 0.1ns 15 10 10 35 Data Input Hold Time After Clock (tDH) 0.275ns 0.225ns 0.175ns 27 22 17 36 Write Recovery Time (tWR) 37 Internal Write to Read Command delay (tWTR) 38 Internal Read to Precharge Command delay (tRTP) 39 Memory Analysis Probe Characteristics DDR2-SDRAM 08 14 0E Number of Column Addresses on Assembly 10 0A Number of DIMM Bank, Package, and Height 1 rank, Height=30mm 60 X64 40 Reserved Undefined 00 Voltage Interface Level of this Assembly SSTL_1.8V 05 00 7.89s/self 82 X8 08 N/A 00 Undefined 00 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 3/4/5 38 REV 1.0 08/2006 Non - ECC Latencies Supported X <= 4.1mm 01 Regular UDIMM (133.35mm) 02 Normal DIMM 00 Support weak driver 01 5ns 3.75ns 3.75ns 50 0.6ns 0.5ns 0.5ns 60 5ns 7.5ns 03 3D 50 50 15ns 10ns Note 3C 7.5ns 28 1E 7.5ns 1E Undefined 00 1E 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect - Part 2 of 2 (512MB) 64Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte SPD Entry Value Description -5A -37B -3C Serial PD Data Entry (Hexadecimal) -5A -37B The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 Minimum Core Cycle Time (tRC) 60ns 3C Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69 8ns 80 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 42 43 Maximum Clock Cycle Time (tCK max) 44 Max. DQS-DQ Skew Factor (tQHS) 0.35ns 0.3ns 0.24ns 23 1E 18 45 Read Data Hold Skew Factor (tQHS) 0.45ns 0.4ns 0.34ns 2D 28 22 46 PLL Relock Time 47 Tcasemax 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 16C 18C 20C 43 4B 53 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 37C 47C 58C 25 2E 3A 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 39C 39C 39C 27 27 27 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 27C 33C 39C 1B 21 27 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 30C 37C 44C 1E 25 2C 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 23C 23C 28C 17 17 1C 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 23C 26C 38C 2E 34 4C 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 30C 35C 37C 1E 23 25 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 35C 37C 40C 23 25 28 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Revision 63 Checksum Data N/A 1C 08/2006 1C 3C 51 122C/W 51 52 7A 1.2 72-255 Reserved REV 1.0 00 Checksum Data 64-71 Manufacturer's JEDEC ID Code Note -3C 12 50 F7 F9 NANYA 7F7F7F0B00000000 Undefined -- 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (1GB) 128Mx64 2 BANKS UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Serial PD Data Entry (Hexadecimal) SPD Entry Value Description -5A 0 Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 4 -37B -3C -5A -37B 128 80 256 08 DDR2-SDRAM 08 Number of Row Addresses on Assembly 14 0E Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Bank, Package, and Height 2 rank, Height=30mm 61 6 Data Width of this Assembly 7 -3C X64 40 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 9 DDR2 SDRAM Device Cycle Time at Maximum Support Latency CL=5 5ns 3.75ns 3ns 50 3D 30 10 DDR2 SDRAM Device Access Time (tac) from Clock at CL=5 0.6ns 0.5ns 0.45ns 60 50 45 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Non - ECC 00 7.89s/self 82 Primary DDRII SDRAM Width X8 08 14 Error Checking DDRII SDRAM Device Width N/A 00 15 Reserved 16 DDR2 SDRAM Device Attributes: Burst Length Supported 17 DDR2 SDRAM Device Attributes: Number of Device Banks 18 DDR2 SDRAM Device Attributes: 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 24 Maximum Data Access Time (tac) from Clock at CL=4 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time (tac) from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 7.5ns 1E 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum Active to Precharge Time (tRAS) 45ns 2D 31 Module Bank Density 32 Address and Command Input Setup Time Before Clock (tIS) 0.35ns 0.25ns 0.2ns 35 25 20 33 Address and Command Input Hold Time After Clock (tIH) 0.475ns 0.375ns 0.275ns 47 37 27 34 Data Input Setup Time Before Clock (tDS) 0.15ns 0.1ns 0.1ns 15 10 10 35 Data Input Hold Time After Clock (tDH) 0.275ns 0.225ns 0.175ns 27 22 17 36 Write Recovery Time (tWR) 37 Internal Write to Read Command delay (tWTR) 38 Internal Read to Precharge Command delay (tRTP) 39 Memory Analysis Probe Characteristics REV 1.0 08/2006 Undefined 00 4,8 0C 4 04 3/4/5 38 X <= 4.1mm 01 Regular UDIMM (133.35mm) 02 Latencies Supported Normal DIMM 00 Support weak driver 01 5ns 3.75ns 3.75ns 50 0.6ns 0.5ns 0.5ns 60 5ns 50 80 15ns 7.5ns 03 3D 50 512MB 10ns Note 3C 7.5ns 28 1E 7.5ns 1E Undefined 00 1E 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (1GB) 128Mx64 2 BANKS UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte SPD Entry Value Description -5A -37B -3C Serial PD Data Entry (Hexadecimal) -5A -37B The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 Minimum Core Cycle Time (tRC) 60ns 3C 42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69 43 Maximum Clock Cycle Time (tCK max) 8ns 80 44 Max. DQS-DQ Skew Factor (tQHS) 0.35ns 0.3ns 0.24ns 23 1E 18 45 Read Data Hold Skew Factor (tQHS) 0.45ns 0.4ns 0.34ns 2D 28 22 46 PLL Relock Time 47 Tcasemax 3C 51 51 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 16C 18C 20C 43 4B 53 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 37C 47C 58C 25 2E 3A 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 39C 39C 39C 27 27 27 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 27C 33C 39C 1B 21 27 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 30C 37C 44C 1E 25 2C 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 23C 23C 28C 17 17 1C 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 23C 26C 38C 2E 34 4C 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 30C 35C 37C 1E 23 25 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 35C 37C 40C 23 25 28 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Revision 63 Checksum Data 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 N/A 1C REV 1.0 08/2006 00 1C 122C/W 1.2 Undefined 52 7A Checksum Data 64-255 Reserved Note -3C 12 51 F8 FA -- 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Absolute Maximum Ratings Symbol Rating Units -0.5 to +2.3 V Voltage on VDD pins relative to Vss -1.0 to +2.3 V VDDQ Voltage on VDDQ pins relative to Vss -0.5 to +2.3 V VDDL Voltage on VDDL pins relative to Vss -0.5 to +2.3 V TSTG Storage Temperature (Plastic) -55 to +100 C VIN, VOUT VDD Parameter Voltage on I/O pins relative to Vss Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating temperature Conditions Symbol TCASE Note: 1. 2. Parameter Operating Temperature (Ambient) Rating Units Note 0 to 95 C 1 Case temperature is measured at top and center side of any DRAMs. tREFI = 3.9 9s tCASE > 85C DC Electrical Characteristics and Operating Conditions Min Max Units Notes VDD Supply Voltage 1.7 1.9 V 1 VDDL DLL Supply Voltage 1.7 1.9 V 1 VDDQ Output Supply Voltage 1.7 1.9 V 1 0 0 V Symbol Parameter VSS, VSSQ VREF Supply Voltage, I/O Supply Voltage Input Reference Voltage VTT Termination Voltage 0.49VDDQ 0.51VDDQ V 1, 2 VREF - 0.04 VREF + 0.04 V 3 Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT of transmitting device must track VREF of receiving device. Input AC/DC logic level Min Max Units VIH (AC) Symbol Input High (Logic1) Voltage Parameter VREF + 0.250 - V Notes 1 VIL (AC) Input Low (Logic0) Voltage - VREF - 0.250 V 1 VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V 1 On Die Termination (ODT) Current Parameter Symbol IODTO Enabled ODT current per DQ ODT is HIGH; Data Bus inputs are FLOATING IODTT Active ODT current per DQ ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING REV 1.0 08/2006 Min Max Units EMRS(1) State 5 7.5 mA/DQ A6=0, A2=1 2.5 3.75 mA/DQ A6=1, A2=0 10 15 mA/DQ A6=0, A2=1 5 7.5 mA/DQ A6=1, A2=0 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) Symbol Parameter/Condition PC2-3200 (-5A) PC2-4200 (-37B) PC2-5300 (-3C) Unit I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 520 560 600 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 560 640 720 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 40 40 40 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 256 320 400 mA I DD2Q Precharge quiet standby current; All banks idle; tCK=tCK(IDD); CKE is HIGH; is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. - - 320 I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 104 128 152 mA I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 40 40 48 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 280 336 400 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 640 720 1040 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 600 760 1120 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 1040 1200 1280 mA I DD6 Self-Refresh Current: CKE 0.2V 40 40 40 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1200 1280 1360 mA Note: REV 1.0 08/2006 Notes Module IDD was calculated from component IDD. It may different from the actual measurement. 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs) Symbol Parameter/Condition PC2-3200 (-5A) PC2-4200 (-37B) PC2-5300 (-3C) Unit I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 776 880 1000 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 816 960 1120 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 80 80 80 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 512 640 800 mA I DD2Q Precharge quiet standby current; All banks idle; tCK=tCK(IDD); CKE is HIGH; is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. - - 640 I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 208 256 304 mA I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 80 80 96 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 536 656 800 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 896 1040 1440 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 856 1080 1520 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 1296 1520 1680 mA I DD6 Self-Refresh Current: CKE 0.2V 80 80 80 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1456 1600 1760 mA Note: REV 1.0 08/2006 Notes Module IDD was calculated from component IDD. It may different from the actual measurement. 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol -5A (DDR2-400) Parameter Min. tAC -37B (DDR2-533) Max. Min. -3C (DDR2-667) Max. Min. Max. Unit DQ output access time from CK/ -0.6 0.6 -0.5 0.5 -0.45 0.45 DQS output access time from CK/ -0.5 0.5 -0.45 0.45 -0.4 0.4 ns tCH CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK tCL CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time Min(tCL, tCH) - Min(tCL, tCH) - Min(tCL, tCH) - tCK tDQSCK ns tCK Clock cycle time 5 8 3.75 8 3 8 ns tDH DQ and DM input hold time(differential data strobe) 0.275 - 0.225 - 0.175 - ns tDS DQ and DM input setup time(differential data strobe) 0.15 - 0.1 - 0.1 - ns tIPW Input pulse width 0.6 - 0.6 - 0.6 - tCK DQ and DM input pulse width (each input) 0.35 - 0.35 - 0.35 - tCK - tAC max - tAC max - tAC max ns tDIPW tHZ Data-out high-impedance time from CK/ tLZ(DQ) Data-out low-impedance time from CK/ 2tAC min tAC max 2tAC min tAC max 2tAC min tAC max ns tLZ(DQS) DQS low-impedance time from CK/ ns tAC min tAC max tAC min tAC max tAC min DQS-DQ skew (DQS & associated DQ signals) - 0.35 - 0.3 0.24 ns tQHS Data hold Skew Factor - 0.45 - 0.4 0.34 ns tQH Data output hold time from DQS tHP tQHS - tHP tQHS - tHP tQHS - ns tDQSQ tDQSS tAC max Write command to 1st DQS latching transition -0.25 0.25 -0.25 0.25 -0.25 0.25 tCK DQS input low (high) pulse width (write cycle) 0.35 - 0.35 - 0.35 - tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - 0.2 - 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - 0.2 - 0.2 - tCK tDQSL,(H) tMRD Mode register set command cycle time 2 - 2 - 2 - tCK tWPST Write postamble 0.4 0.6 0.4 0.6 0.4 0.6 tCK tWPRE Write preamble 0.35 - 0.35 - 0.35 - tCK 0.475 - 0.375 - 0.275 - ns - tIH tIS Address and control input hold time Address and control input setup time 0.35 - 0.35 - 0.2 tRPRE Read preamble 0.9 1.1 0.9 1.1 0.35 tRPST Read postamble 0.4 0.6 0.4 0.6 0.4 0.6 tCK tRRD Active bank A to Active bank B command 7.5 - 7.5 - 10 - ns tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tIS+tCK+ tIH - tIS+tCK+ tIH - tIS+tCK+ tIH - ns tREFI Average Periodic Refresh Interval (85C < TCASE : 95C) 3.9 tOIT OCD drive mode output delay tRFC Auto-Refresh to Active/Auto-Refresh command period tCCD REV 1.0 08/2006 us 7.8 Average Periodic Refresh Interval (0C : TCASE : 85C) 0 to 12 0 12 us 0 12 105 2 - 2 - ns tCK ns ns 2 0 tCK 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE= 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol -5A (DDR2-400) Parameter tWR Write recovery time without Auto-Precharge WR Write recovery time with Auto-Precharge tDAL Auto precharge write recovery + precharge time tWTR Internal write to read command delay tRTP Internal read to precharge command delay tXSNR Exit self refresh to a Non-read command tXSRD Exit self refresh to a Read command Min. Max. 15 - tWR/tCK -37B (DDR2-533) Min. Max. 15 - tWR/tCK -3C (DDR2-667) Min. Unit Max. 15 ns tWR/tCK WR + tRP - WR + tRP - WR + tRP tCK 10 - 7.5 - 10 ns 7.5 7.5 7.5 ns tRFC + 10 tRFC + 10 tRFC + 10 ns 200 200 200 tCK Exit precharge power down to any Non- read command 2 - 2 - 2 tCK tXARD Exit active power down to read command 2 - 2 - 2 tCK tXARDS Exit active power down to read command 6 - AL 6 - AL 6 - AL tCK 3 3 3 tCK tXP tCKE CKE minimum pulse width ODT tAOND tAON tAONPD tAOFD ODT turn-on delay 2 tCK ODT turn-on t (max) t (max) t (max) tAC(min) AC tAC(min) AC tAC(min) AC +1 +1 +1 ns ODT turn-on (Power down mode) 2tCK + 2tCK + 2tCK + tAC(min) tAC(min) tAC(min) tAC(max) tAC(max) tAC(max) +2 +2 +2 +1 +1 +1 ns ODT turn-off delay 2.5 2.5 2.5 2.5 2.5 2.5 tCK ODT turn-off t (max) t (max) t (max) tAC(min) AC tAC(min) AC tAC(min) AC +0.6 +0.6 +0.6 ns tAOFPD ODT turn-off (Power down mode) 2.5tCK + 2.5tCK + 2.5tCK + tAC(min) tAC(min) tAC(min) tAC(max) tAC(max) tAC(max) +2 +2 +2 +1 +1 +1 ns tANPD ODT to power down entry latency 3 - 3 - 3 - tCK tAXPD ODT power down exit latency 8 - 8 - 8 - tCK tRAS Row Active Time 40 70000 45 70000 45 70000 ns tRC Row Cycle Time 55 - 60 - 60 - ns RAS to CAS delay 15 - 15 - 15 - ns Row Precharge Time 15 - 15 - 15 - ns tAOF Speed Grade Definition tRCD tRP REV 1.0 08/2006 16 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) FRONT 133.35 5.250 131.35 5.171 128.95 5.077 2.47 0.097 Detail A 2.5 0.098 Detail B BACK 63.00 Detail B 2.50 0.098 4. 00 0.157 3. 80 0. 15 1.27 +0. 10/-0 .10 0. 050 +0. 004/-0. 004 55.00 2.17 2.48 Detail A 2.30 0.091 17.80 0.700 10.0 0. 394 30.00 1. 180 (2X) 4.00 0.157 SIDE 5.00 0.197 0 .8 +/- 0.5 Width 0 .003 +/- 0.020 1.00 Pitch 0.039 1 .50 +/- 0.1 0 .05 +/- 0.04 Note: All dimensions are typical with tolerances of+/- 0.15 (0.006) unless otherwise stated. Units: Millimeters(Inches) * Device position is only for reference. REV 1.0 08/2006 17 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs) FRONT 133.35 5.250 131.35 5.171 128.95 5.077 4.00 0.157 Detail A 2.5 0.098 63.00 Detail B 2.50 0.098 4. 00 0.157 Detail A 1.27 +0.10/-0.10 0.050 +0.004/-0.004 55.00 2.17 2.48 3. 80 0. 15 Detail B BACK 2. 30 0.091 17.80 0.700 10.0 0. 394 30.00 1. 180 (2X) 4.00 0.157 SIDE 5.00 0.197 0.8 +/- 0.5 Width 0.003 +/- 0.020 1.00 Pitch 0.039 1.50 +/- 0.1 0.05 +/- 0.04 Note: All dimensions are typical with tolerances of+/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches) * Device position is only for reference. REV 1.0 08/2006 18 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M2U51264TU88A2B/ M2Y51264TU88A2B (Green) M2U1G64TU8HA2B / M2Y1G64TU8HA2B (Green) M2U51264TU88A0B/ M2Y51264TU88A0B (Green) M2U1G64TU8HA0B / M2Y1G64TU8HA0B (Green) M2U51264TU88A0F/ M2U51264TU88A2F 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Revision Log Rev Date 1.0 08/2006 REV 1.0 08/2006 Modification Official Release 19 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.