CAT5269WI-00 - Catalyst Semiconductor, Inc.

CAT5269

Characteristics subject to change without notice

Dual Digitally Programmable Potentiometers

(DPP™) with 256 Taps and 2-wire Interface

FEATURES

 Four linear taper digitally programmable

potentiometers

 256 resistor taps per potentiometer

 End to end resistance 50kΩ or 100kΩ

 Potentiometer control and memory access via

2-wire interface (I2C like)

 Low wiper resistance, typically 100Ω

 Nonvolatile memory storage for up to four

wiper settings for each potentiometer

 Automatic recall of saved wiper settings at

power up

 2.5 to 6.0 volt operation

 Standby current less than 1µA

 1,000,000 nonvolatile WRITE cycles

 100 year nonvolatile memory data retention

 24-lead SOIC and TSSOP packages

 Industrial temperature range

For Ordering Information details, see page 15.

PIN CONFIGURATION

SOIC (W)

TSSOP (Y)

NC 1 24 A3

A0 2 23 SCL

NC 3 22 NC

NC 4

21 NC

NC 5 20 NC

NC 6 19 NC

VCC 7

18 GND

RLO 8 17 RW1

RHO 9 16 RH1

RWO 10

15 RL1

A2 11 14 A1

WP

¯¯¯ 12 13 SDA

DESCRIPTION

The CAT5259 is two digitally programmable poten–

tiometers (DPPs™) integrated with control logic and

18 bytes of NVRAM memory. Each DPP consists of a

series of resistive elements connected between two

externally accessible end points. The tap points

between each resistive element are connected to the

wiper outputs with CMOS switches. A separate 8-bit

control register (WCR) independently controls the

wiper tap switches for each DPP. Associated with

each wiper control register are four 8-bit non-volatile

memory data registers (DR) used for storing up to four

wiper settings. Writing to the wiper control register or

any of the non-volatile data registers is via a 2-wire

serial bus. On power-up, the contents of the first data

register (DR0) for each of the four potentiometers is

automatically loaded into its respective wiper control

registers.

The CAT5259 can be used as a potentiometer or as a

two terminal, variable resistor. It is intended for circuit

level or system level adjustments in a wide variety of

applications. It is available in the -40ºC to 85ºC

industrial operating temperature ranges and offered in

a 24-lead SOIC and TSSOP package.

FUNCTIONAL DIAGRAM

R

W0

R

W1

R

H0

A1

A2

A0

A3

R

H1

R

L0

R

L1

NONVOLATILE

DATA

REGISTERS

WIPER

CONTROL

REGISTERS

CONTROL

LOGIC

2-WIRE BUS

INTERFACE

WP

SCL

SDA

CAT5269

Doc. No. MD-2123 Rev. C 2 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

PIN DESCRIPTIONS PIN DESCRIPTION

SCL: Serial Clock

The CAT5269 serial clock input pin is used to

clock all data transfers into or out of the

device.

SDA: Serial Data

The CAT5269 bidirectional serial data pin is

used to transfer data into and out of the

device. The SDA pin is an open drain output

and can be wire-Ored with the other open

drain or open collector I/Os.

A0, A1, A2, A3: Device Address Inputs

These inputs set the device address when

addressing multiple devices. A total of sixteen

devices can be addressed on a single bus. A

match in the slave address must be made with

the address input in order to initiate

communication with the CAT5269.

RH, RL: Resistor End Points

The two sets of RH and RL pins are equivalent

to the terminal connections on a mechanical

potentiometer.

RW: Wiper

The RW pins are equivalent to the wiper

terminal of a mechanical potentiometer.

WP

¯¯¯: Write Protect Input

The WP

¯¯¯ pin when tied low prevents non-

volatile writes to the data register (change of

wiper control register is allowed) and when

tied high or left floating normal read/write

operations are allowed. See Write Protection

on page 7 for more details.

DEVICE OPERATION

The CAT5269 is two resistor arrays integrated with a 2-wire serial interface, two 8-bit wiper control registers and

eight 8-bit, non-volatile memory data registers. Each resistor array contains 255 separate resistive elements

connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical

potentiometer (RH and RL). The tap positions between and at the ends of the series resistors are connected to the

output wiper terminals (RW) by a CMOS transistor switch. Only one tap point for each potentiometer is connected

to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or

written to the wiper control registers or the non-volatile memory data registers via the 2-wire bus. Additional

instructions allow data to be transferred between the wiper control registers and each respective potentiometer's

non-volatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode.

Pin # Name Function

1 NC No Connect

2 A0 Device Address, LSB

3 NC No Connect

4 NC No Connect

5 NC No Connect

6 NC No Connect

7 VCC Supply Voltage

8 RL0 Low Reference Terminal for Potentiometer 0

9 RH0 High Reference Terminal for Potentiometer 0

10 RW0 Wiper Terminal for Potentiometer 0

11 A2 Device Address

12 WP

¯¯¯ Write Protection

13 SDA Serial Data Input/Output

14 A1 Device Address

15 RL1 Low Reference Terminal for Potentiometer 1

16 RH1 High Reference Terminal for Potentiometer 1

17 RW1 Wiper Terminal for Potentiometer 1

18 GND Ground

19 NC No Connect

20 NC No Connect

21 NC No Connect

22 NC No Connect

23 SCL Bus Serial Clock

24 A3 Device Address

CAT5269

Characteristics subject to change without notice

ABSOLUTE MAXIMUM RATINGS(1)

Parameters Ratings Units

Temperature Under Bias -55 to +125 ºC

Storage Temperature -65 to +150 °C

Voltage on Any Pin with Respect to VSS(1) (2) -2.0 to +VCC + 2.0 V

VCC with Respect to Ground -2.0 to +7.0 V

Package Power Dissipation Capability (TA = 25ºC) 1.0 W

Lead Soldering Temperature (10secs) 300 ºC

Wiper Current ±6 mA

RECOMMENDED OPERATING CONDITIONS

Parameters Ratings Units

VCC +2.5 to +6 V

Industrial Temperature -40 to +85 °C

POTENTIOMETER CHARACTERISTICS

(Over recommended operating conditions unless otherwise stated.)

Limits

Symbol Parameter Test Conditions Min Typ. Max Units

RPOT Potentiometer Resistance (100kΩ) 100 kΩ

RPOT Potentiometer Resistance (50kΩ) 50 kΩ

Potentiometer Resistance

Tolerance ±20 %

R

POT Matching 1 %

Power Rating 25°C, each pot 50 mW

IW Wiper Current ±3 mA

RW Wiper Resistance IW = ±3mA @ VCC = 3V 200 300 Ω

RW Wiper Resistance IW = ±3mA @ VCC = 5V 100 150 Ω

VTERM Voltage on any RH or RL Pin VSS = 0V VSS V

CC V

VN Noise (4) nV

√

Hz

Resolution 0.4 %

Absolute Linearity (5) R

w(n)(actual)-R(n)(expected)(8) ±1 LSB (7)

Relative Linearity (6) R

w(n+1)-[Rw(n)+LSB](8) ±0.2 LSB (7)

TCRPOT Temperature Coefficient of RPOT (4) ±300 ppm/ºC

TCRATIO Ratiometric Temp. Coefficient (4) 20 ppm/ºC

CH/CL/CW Potentiometer Capacitances (4) 10/10/25 pF

fc Frequency Response RPOT = 50kΩ (4) 0.4 MHz

Notes:

(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this

specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns.

(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.

(4) This parameter is tested initially and after a design or process change that affects the parameter.

(5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.

(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentio-

meter. It is a measure of the error in step size.

(7) LSB = RTOT / 255 or (RH - RL) / 255, single pot

(8) n = 0, 1, 2, ..., 255

CAT5269

Doc. No. MD-2123 Rev. C 4 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

D.C. OPERATING CHARACTERISTICS

VCC = +2.5V to +6.0V, unless otherwise specified.

Symbol Parameter Test Conditions Min Max Units

ICC1 Power Supply Current fSCL = 400kHz, SDA = Open

VCC = 6V, Inputs = GND 1 mA

ICC2 Power Supply Current

Non-volatile WRITE

fSCK = 400kHz, SDA Open

VCC = 6V, Input = GND 5 mA

ISB Standby Current (VCC = 5.0V) VIN = GND or VCC, SDA = Open 5 µA

ILI Input Leakage Current VIN = GND to VCC 10 µA

ILO Output Leakage Current VOUT = GND to VCC 10 µA

VIL Input Low Voltage -1 VCC x 0.3 V

VIH Input High Voltage VCC x 0.7 VCC + 1.0 V

VOL1 Output Low Voltage (VCC = 3.0V) IOL = 3mA 0.4 V

VOL2 Output Low Voltage (VCC = 1.8V) IOL = 1.5mA 0.5 V

CAPACITANCE

TA = 25ºC, f = 1.0MHz, VCC = 5V

Symbol Test Conditions Max Units

CI/O(1) Input/Output Capacitance (SDA) VI/O = 0V 8 pF

CIN(1) Input Capacitance (A0, A1, A2, A3, SCL, WP

¯¯¯) VIN = 0V 6 pF

A.C. CHARACTERISTICS

2.5V - 6.0V

Symbol Parameter Min Max

Units

fSCL Clock Frequency 400 kHz

TI(1) Noise Suppression Time Constant at SCL, SDA Inputs 200 ns

tAA SLC Low to SDA Data Out and ACK Out 1 µs

tBUF(1) Time the bus must be free before a new transmission can start 1.2 µs

tHD:STA Start Condition Hold Time 0.6 µs

tLOW Clock Low Period 1.2 µs

tHIGH Clock High Period 0.6 µs

tSU:STA Start Condition SetupTime (for a Repeated Start Condition) 0.6 µs

tHD:DAT Data in Hold Time 0 ns

tSU:DAT Data in Setup Time 50 ns

tR(1) SDA and SCL Rise Time 0.3 µs

tF(1) SDA and SCL Fall Time 300 ns

tSU:STO Stop Condition Setup Time 0.6 µs

tDH Data Out Hold Time 100 ns

Note:

This parameter is tested initially and after a design or process change that affects the parameter.

CAT5269

Characteristics subject to change without notice

POWER UP TIMING (1)(2)

Symbol Parameter Max Units

tPUR Power-up to Read Operation 1 ms

tPUW Power-up to Write Operation 1 ms

XDCP TIMING

Symbol Parameter Min Max Units

tWRPO Wiper Response Time After Power Supply Stable 5 10 µs

tWRL Wiper Response Time After Instruction Issued 5 10 µs

WRITE CYCLE LIMITS (3)

Symbol Parameter Max Units

tWR Write Cycle Time 5 ms

RELIABILITY CHARACTERISTICS

Symbol Parameter Reference Test Method Min Max Units

NEND(1) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte

TDR(1) Data Retention MIL-STD-883, Test Method 1008 100 Years

VZAP(1) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 V

ILTH(1) Latch-Up JEDEC Standard 17 100 mA

Notes:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.

(3) The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write

cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

Figure 1. Bus Timing

tHIGH

SCL

SDA IN

S

D

AOUT

tLOW

tF

tLOW

tR

tBUF

tSU:STO

tSU:DAT

tHD:DAT

tHD:STA

tSU:STA

tAA tDH

CAT5269

Doc. No. MD-2123 Rev. C 6 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

SERIAL BUS PROTOCOL

The following defines the features of the 2-wire bus

protocol:

(1) Data transfer may be initiated only when the bus

is not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock is high will

be interpreted as a START or STOP condition.

The device controlling the transfer is a master,

typically a processor or controller, and the device

being controlled is the slave. The master will always

initiate data transfers and provide the clock for both

transmit and receive operations. Therefore, the

CAT5269 will be considered a slave device in all

applications.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT5269 monitors the

SDA and SCL lines and will not respond until this

condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must

end with a STOP condition.

DEVICE ADDRESSING

The bus Master begins a transmission by sending a

START condition. The Master then sends the address

of the particular slave device it is requesting. The four

most significant bits of the 8-bit slave address are

fixed as 0101 for the CAT5269 (see Figure 5). The

next four significant bits (A3, A2, A1, A0) are the

device address bits and define which device the

Master is accessing. Up to sixteen devices may be

individually addressed by the system. Typically, +5V

and ground are hard-wired to these pins to establish

the device's address.

After the Master sends a START condition and the

slave address byte, the CAT5269 monitors the bus and

responds with an acknowledge (on the SDA line) when

its address matches the transmitted slave address.

Acknowledge

After a successful data transfer, each receiving device

is required to generate an acknowledge. The

Acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8

bits of data.

The CAT5269 responds with an acknowledge after

receiving a START condition and its slave address. If

the device has been selected along with a write

operation, it responds with an acknowledge after

receiving each 8-bit byte.

When the CAT5269 is in a READ mode it transmits 8

bits of data, releases the SDA line, and monitors the

line for an acknowledge. Once it receives this

acknowledge, the CAT5269 will continue to transmit

data. If no acknowledge is sent by the Master, the

device terminates data transmission and waits for a

STOP condition.

Write Operations

In the Write mode, the Master device sends the

START condition and the slave address information to

the Slave device. After the Slave generates an

acknowledge, the Master sends the instruction byte

that defines the requested operation of CAT5269. The

instruction byte consist of a four-bit opcode followed

by two register selection bits and two pot selection

bits. After receiving another acknowledge from the

Slave, the Master device transmits the data to be

written into the selected register. The CAT5269

acknowledges once more and the Master generates

the STOP condition, at which time if a nonvolatile data

register is being selected, the device begins an

internal programming cycle to non-volatile memory.

While this internal cycle is in progress, the device will

not respond to any request from the Master device.

Acknowledge Polling

The disabling of the inputs can be used to take

advantage of the typical write cycle time. Once the

stop condition is issued to indicate the end of the

host's write operation, the CAT5269 initiates the

internal write cycle. ACK polling can be initiated

immediately. This involves issuing the start condition

followed by the slave address. If the CAT5269 is still

busy with the write operation, no ACK will be returned.

If the CAT5269 has completed the write operation, an

ACK will be returned and the host can then proceed

with the next instruction operation.

Write Protection

The Write Protection feature allows the user to protect

against inadvertent programming of the non-volatile

data registers. If the WP

¯¯¯ pin is tied to LOW, the data

registers are protected and become read only.

Similarly, the WP

¯¯¯ pin going low after start will interrupt

a nonvolatile write to data registers, while the WP

¯¯¯ pin

going low after an internal write cycle has stated will

have no effect on any write operation (see also

CAT5409 or CAT5259). The CAT5269 will accept both

slave addresses and instructions, but the data registers

are protected from programming by the device’s failure

to send an acknowledge after data is received.

CAT5269

Characteristics subject to change without notice

Figure 2. Write Cycle Timing

Figure 3. Start/Stop Condition

Figure 4. Acknowledge Condition

Figure 5. Slave Address Bits

CAT5269 0 101A3A2A1A0

* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.

** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.

tWR

STOP

CONDITION

START

CONDITION

ADDRESS

ACK8TH BIT

BYTE n

SCL

SDA

START CONDITION

SDA

STOP CONDITION

SCL

ACKNOWLEDGE

1

STAR

T

SCL FROM

MASTER 89

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

CAT5269

Doc. No. MD-2123 Rev. C 8 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

INSTRUCTION AND REGISTER

DESCRIPTION

SLAVE ADDRESS BYTE

The first byte sent to the CAT5269 from the

master/processor is called the Slave/DPP Address

Byte. The most significant four bits of the slave

address are a device type identifier. These bits for the

CAT5269 are fixed at 0101[B] (refer to Table 1).

The next four bits, A3 - A0, are the internal slave

address and must match the physical device address

which is defined by the state of the A3 - A0 input pins

for the CAT5269 to successfully continue the

command sequence. Only the device which slave

address matches the incoming device address sent by

the master executes the instruction. The A3 - A0

inputs can be actively driven by CMOS input signals

or tied to VCC or VSS.

INSTRUCTION BYTE

The next byte sent to the CAT5269 contains the

instruction and register pointer information. The four

most significant bits used provide the instruction

opcode I3 - I0. The R1 and R0 bits point to one of the

four data registers of each associated potentiometer.

The least two significant bits point to one of four Wiper

Control Registers. The format is shown in Table 2.

Data Register Selection

Data Register Selected R1 R0

DR0 0 0

DR1 0 1

Figure 6. Write Timing

Table 1. Identification Byte Format

Table 2. Instruction Byte Format

S

A

C

K

A

C

K

DR1 WCRDATA

S

T

O

P

BUS ACTIVITY:

MASTER

SDA LINE

S

T

A

R

T

A

C

K

SLAVE/DPP

ADDRESS

INSTRUCTION

BYTE

Fixed Variable op code

Register

Address

Pot1 WCR

Address

ID3 ID2 ID1 ID0 A3 A2 A1 A0

0101

(

MSB

)

(

LSB

)

Device Type

Identifier Slave Address

I3 I2 I1 I0 R1 R0 P1 P0

(MSB) (LSB)

Instruction Data Register

WCR/Pot Selection

Opcode Selection

CAT5269

Characteristics subject to change without notice

WIPER CONTROL AND DATA REGISTERS

Wiper Control Register (WCR)

The CAT5269 contains two 8-bit Wiper Control

Registers, one for each potentiometer. The Wiper

Control Register output is decoded to select one of

256 switches along its resistor array. The contents of

the WCR can be altered in four ways: it may be

written by the host via Write Wiper Control Register

instruction; it may be written by transferring the

contents of one of four associated Data Registers via

the XFR Data Register instruction, it can be modified

one step at a time by the Increment/decrement

instruction (see Instruction section for more details).

Finally, it is loaded with the content of its data register

zero (DR0) upon power-up.

The Wiper Control Register is a volatile register that

loses its contents when the CAT5269 is powered-

down. Although the register is automatically loaded

with the value in DR0 upon power-up, this may be

different from the value present at power-down.

Data Registers (DR)

Each potentiometer has four 8-bit non-volatile Data

Registers. These can be read or written directly by the

host. Data can also be transferred between any of the

four Data Registers and the associated Wiper Control

Register. Any data changes in one of the Data

Registers is a non-volatile operation and will take a

maximum of 10ms.

If the application does not require storage of multiple

settings for the potentiometer, the Data Registers can

be used as standard memory locations for system

parameters or user preference data.

INSTRUCTIONS

Four of the nine instructions are three bytes in length.

These instructions are:

— Read Wiper Control Register – read the current

wiper position of the selected potentiometer in the

WCR

— Write Wiper Control Register – change current

wiper position in the WCR of the selected

potentiometer

— Read Data Register – read the contents of the

selected Data Register

— Write Data Register – write a new value to the

selected Data Register

The basic sequence of the three byte instructions is

illustrated in Figure 8. These three-byte instructions

Table 3. Instruction Set

Instruction Set

Instruction I3 I2 I1 I0 R1 R0 WCR1/P1 WCR0/P0 Operation

Read Wiper Control

Register

1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper

Control Register pointed to by P1-P0

Write Wiper Control

Register

1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Control

Register pointed to by P1-P0

Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data

Register pointed to by P1-P0 and R1-

R0

Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register

pointed to by P1-P0 and R1-R0

XFR Data Register to

Wiper Control Register

1 1 0 1 1/0 1/0 1/0 1/0 Transfer the contents of the Data

Register pointed to by P1-P0 and R1-

R0 to its associated Wiper Control

Register

XFR Wiper Control

Register to Data

Register

1 1 1 0 1/0 1/0 1/0 1/0 Transfer the contents of the Wiper

Control Register pointed to by P1-P0

to the Data Register pointed to by R1-

R0

Gang XFR Data

Registers to Wiper

Control Registers

0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data

Registers pointed to by R1-R0 of both

pots to their respective Wiper Control

Registers

Gang XFR Wiper

Control Registers to

Data Register

1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper

Control Registers to their respective

data Registers pointed to by R1-R0 of

both pots

Increment/Decrement

Wiper Control Register

0 0 1 0 0 0 1/0 1/0 Enable Increment/decrement of the

Control Latch pointed to by P1-P0

Note: 1/0 = data is one or zero

CAT5269

Doc. No. MD-2123 Rev. C 10 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

exchange data between the WCR and one of the Data

Registers. The WCR controls the position of the wiper.

The response of the wiper to this action will be

delayed by tWR. A transfer from the WCR (current

wiper position), to a Data Register is a write to non-

volatile memory and takes a minimum of tWR to

complete. The transfer can occur between one of the

two potentiometers and one of its associated

registers; or the transfer can occur between both

potentiometers and one associated register.

Four instructions require a two-byte sequence to

complete, as illustrated in Figure 7. These instructions

transfer data between the host/processor and the

CAT5269; either between the host and one of the data

registers or directly between the host and the Wiper

Control Register. These instructions are:

— XFR Data Register to Wiper Control Register

This transfers the contents of one specified Data

Register to the associated Wiper Control Register.

— XFR Wiper Control Register to Data Register

This transfers the contents of the specified Wiper

Control Register to the specified associated Data

Register.

— Gang XFR Data Register to Wiper Control

Register

This transfers the contents of all specified Data

Registers to the associated Wiper Control

Registers.

— Gang XFR Wiper Counter Register to Data

Register

This transfers the contents of all Wiper Control

Registers to the specified associated Data

Registers.

INCREMENT/DECREMENT COMMAND

The final command is Increment/Decrement (Figure 9

and 10). The Increment/Decrement command is differ-

ent from the other commands. Once the command is

issued and the CAT5269 has responded with an ac-

knowledge, the master can clock the selected wiper

up and/or down in one segment steps; thereby

providing a fine tuning capability to the host. For each

SCL clock pulse (tHIGH) while SDA is HIGH, the

selected wiper will move one resistor segment

towards the RH terminal. Similarly, for each SCL clock

pulse while SDA is LOW, the selected wiper will move

one resistor segment towards the RL terminal.

See Instructions format for more detail.

Figure 7. Two-Byte Instruction Sequence

Figure 8. Three-Byte Instruction Sequence

Figure 9. Increment/Decrement Instruction Sequence

S

T

A

R

T

0101

A2 A0 A

C

K

I2 I1 I0 R1 R0 P1 A

C

K

SDA

S

T

O

P

ID3 ID2 ID1 ID0 P0

Device ID Internal Instruction

Opcode

Address Register

Address

Pot/WCR

Address

A1

A3 I3

I3 I2 I1 I0 R1 R0

ID3 ID2

ID1

ID0

Device ID Internal Instruction

Opcode

Address Data

Register

Address

Pot/WCR

Address

WCR[7:0]

or

Data Register D[7:0]

S

T

A

R

T

0101

A2 A1 A0 A

C

K

P1 P0 A

C

K

SDA

S

T

O

P

A

C

K

D7 D6 D5 D4 D3 D2 D1 D0

A3

I3 I2 I1 I0

ID3 ID2 ID1 ID0

Device ID Internal Instruction

Opcode

Address

Data

Register

Address

Pot/WCR

Address

S

T

A

R

T

0101

A2 A1 A0 A

C

K

R0 P1 P0 A

C

K

SDA

S

T

O

P

I

N

C

1

I

N

C

2

I

N

C

n

D

E

C

1

D

E

C

n

R1

A3

CAT5269

Characteristics subject to change without notice

Figure 10. Increment/Decrement Timing Limits

INSTRUCTION FORMAT

Read Wiper Control Register (WCR)

DEVICE ADDRESSES INSTRUCTION DATA

0 1 0 1 A A A A 1 0 0 1 00PP 76543210

S

T

A

R

T

3 2 1 0

A

C

K 10

A

C

K

A

C

K

S

T

O

P

Write Wiper Control Register (WCR)

DEVICE ADDRESSES INSTRUCTION DATA

0 1 0 1 A A A A 1 0 1 0 00PP 76543210

S

T

A

R

T

3 2 1 0

A

C

K 10

A

C

K

A

C

K

S

T

O

P

Read Data Register (DR)

DEVICE ADDRESSES INSTRUCTION DATA

0 1 0 1 A A A A 1 0 1 1 RRPP 76543210

S

T

A

R

T

3 2 1 0

A

C

K 1010

A

C

K

A

C

K

S

T

O

P

Write Data Register (DR)

DEVICE ADDRESSES INSTRUCTION DATA

0 1 0 1 A A A A 1 1 0 0 RRPP 76543210

S

T

A

R

T

3 2 1 0

A

C

K 1010

A

C

K

A

C

K

S

T

O

P

SCL

SDA

R

W

INC/DEC

Command

Issued

Voltage Out

t

WRL

CAT5269

Characteristics subject to change without notice

INSTRUCTION FORMAT (CONTINUED)

Gang Transfer Data Register (DR) to Wiper Control Register (WCR)

DEVICE ADDRESSES INSTRUCTION

0 1 0 1 A A A A 0 0 0 1 R R 0 0

S

T

A

R

T

3 2 1 0

A

C

K 10

A

C

K

S

T

O

P

Gang Transfer Wiper Control Register (WCR) to Data Register (DR)

DEVICE ADDRESSES INSTRUCTION

0 1 0 1 A A A A 1 0 0 0 R R 0 0

S

T

A

R

T

3 2 1 0

A

C

K 10

A

C

K

S

T

O

P

Transfer Wiper Control Register (WCR) to Data Register (DR)

DEVICE ADDRESSES INSTRUCTION

0 1 0 1 A A A A 1 1 1 0 R R P P

S

T

A

R

T

3 2 1 0

A

C

K 1010

A

C

K

S

T

O

P

Transfer Data Register (DR) to Wiper Control Register (WCR)

DEVICE ADDRESSES INSTRUCTION

0 1 0 1 A A A A 1 1 0 1 R R P P

S

T

A

R

T

3 2 1 0

A

C

K 1010

A

C

K

S

T

O

P

Increment (I)/Decrement (D) Wiper Control Register (WCR)

DEVICE ADDRESSES INSTRUCTION DATA

0 1 0 1 A A A A 0 0 1 0 0 0 P P

S

T

A

R

T

3 2 1 0

A

C

K 10

A

C

KI

/

D

I

/

D. . .

I

/

D

I

/

D

A

C

K

S

T

O

P

Note:

(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.

CAT5269

Characteristics subject to change without notice

PACKAGE OUTLINE DRAWINGS

SOIC 24-Lead 300mils (W)

θ

E1 E

A1

A2

e

PIN#1 IDENTIFICATION

b

D

c

A

TOP VIEW

SIDE VIEW END VIEW

θ1

h

L

SYMBOL MIN NOM MAX

A2.35 2.65

A1 0.10 0.30

A2 2.05 2.55

b0.31 0.51

c0.20 0.33

D 15.20 15.40

E 10.11 10.51

E1 7.34 7.60

e 1.27 BSC

h0.25 0.75

L0.40 1.27

θ0° 8°

θ1 5° 15°

Notes:

(1) All dimensions in millimeters. Angles in degrees.

(2) Complies with JEDEC standard MS-013.

2HFor current Tape and Reel information, download the PDF file

from:

CAT5269

Characteristics subject to change without notice

TSSOP 24-LEAD 4.4mm (Y)

Notes:

(1) All dimensions in millimeters. Angles in degrees.

(2) Complies with JEDEC standard MO-153.

3HFor current Tape and Reel information, download the PDF file

from:

θ1

A

1

A2

D

TOP VIEW

SIDE VIEW END VIEW

e

E1 E

b

L1

c

L

A

SYMBOL MIN NOM MAX

A1.20

A1 0.05 0.15

A2 0.80 1.05

b0.19 0.30

c0.09 0.20

D 7.70 7.80 7.90

E 6.25 6.40 6.55

E1 4.30 4.40 4.50

e0.65 BSC

L1.00 REF

L1 0.50 0.60 0.70

θ10° 8°

CAT5269

Characteristics subject to change without notice

EXAMPLE OF ORDERING INFORMATION

Notes:

(1) All packages are RoHS-compliant (Lead-free, Halogen-free).

(2) The device used in the above example is a CAT5269WI-00-T1 (SOIC, Industrial Temperature, 100kΩ, Tape & Reel).

(3) The lead finish is Matte-Tin.

Ordering Part Number

CAT5269WI-50

CAT5269WI-00

CAT5269YI-50

CAT5269YI-00

Prefix Device # Suf

f

ix

CAT 5269 W I -00 - T1

Company ID

Package

W: SOIC

Y: TSSOP

Temperature Range

I = Industrial (-40ºC to 85ºC)

Product Numbe

r

5269

Resistance

50: 50kΩ

00: 100kΩ

Tape & Reel

T: Tape & Reel

1: 1000/Reel - SOIC

2: 2000/Reel - TSSOP

REVISION HISTORY

Date Rev. Reason

11/18/2003 A Initial Issue

05/06/2004 B Added TSSOP package in all areas

Updated Functional Diagram

Updated Pin Descriptions

Updated notes in Absolute Max Ratings

Updated Potentiometer Characteristics table

Updated DC Characteristics table Added XDCP Timing table

Updated Write Cycle Limits table

Changed Figure 3 drawing to Start/Stop Condition from Start/Stop Timing

Changed Figure 4 title to Acknowledge Condition (from Acknowledge Timing)

Updated Table 3 Gang XFR Operation information

Corrected Instruction Format for Gang Transfer Data Register (DR) to Wiper Control

Register (WCR)

10/16/2007 C

Updated Example of Ordering Information

Update Package Outline Drawings

Added MD- to document number

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Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™

Catalyst Semiconductor has been issued U. S. and foreign patents and has patent applications pending that protect its products.

CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS

PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE

RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING

OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal

injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled

"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical

semiconductor applications and may not be complete.

Catalyst Semiconductor, Inc.

Corporate Headquarters

2975 Stender Way

Santa Clara, CA 95054

Phone: 408.542.1000 Document No: MD-2123

Fax: 408.542.1200 Revision: C

1Hwww.catsemi.com Issue date: 10

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16

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