MX25V1006E MX25V1006E DATASHEET P/N: PM1752 1 REV. 1.5, June 02, 2016 MX25V1006E Contents FEATURES................................................................................................................................................................... 4 GENERAL........................................................................................................................................................... 4 PERFORMANCE................................................................................................................................................ 4 SOFTWARE FEATURES.................................................................................................................................... 4 HARDWARE FEATURES.................................................................................................................................... 5 GENERAL DESCRIPTION.......................................................................................................................................... 5 PIN CONFIGURATIONS............................................................................................................................................... 6 8-LAND USON (2x3mm) .................................................................................................................................... 6 8-PIN TSSOP (173mil) ....................................................................................................................................... 6 8-PIN SOP (150mil) ............................................................................................................................................ 6 PIN DESCRIPTION....................................................................................................................................................... 6 BLOCK DIAGRAM........................................................................................................................................................ 7 DATA PROTECTION..................................................................................................................................................... 8 Table 1. Protected Area Sizes............................................................................................................................. 8 HOLD FEATURE........................................................................................................................................................... 9 Figure 1. Hold Condition Operation .................................................................................................................... 9 Table 2. COMMAND DEFINITION.................................................................................................................... 10 MEMORY ORGANIZATION........................................................................................................................................ 11 Table 3. Memory Organization ......................................................................................................................... 11 DEVICE OPERATION................................................................................................................................................. 12 Figure 2. Serial Modes Supported.................................................................................................................... 12 COMMAND DESCRIPTION........................................................................................................................................ 13 (1) Write Enable (WREN).................................................................................................................................. 13 (2) Write Disable (WRDI)................................................................................................................................... 13 (3) Read Identification (RDID)........................................................................................................................... 13 (4) Read Status Register (RDSR)..................................................................................................................... 14 Status Register.................................................................................................................................................. 14 (5) Write Status Register (WRSR)..................................................................................................................... 15 Table 4. Protection Modes................................................................................................................................. 15 (6) Read Data Bytes (READ)............................................................................................................................ 16 (7) Read Data Bytes at Higher Speed (FAST_READ)...................................................................................... 16 (8) Dual Output Mode (DREAD)........................................................................................................................ 16 (9) Sector Erase (SE)........................................................................................................................................ 16 (10) Block Erase (BE)....................................................................................................................................... 17 (11) Chip Erase (CE)......................................................................................................................................... 17 (12) Page Program (PP)................................................................................................................................... 17 (13) Deep Power-down (DP)............................................................................................................................. 18 (14) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ............................................ 18 (15) Read Electronic Manufacturer ID & Device ID (REMS)............................................................................. 19 Table of ID Definitions....................................................................................................................................... 19 P/N: PM1752 2 REV. 1.5, June 02, 2016 MX25V1006E POWER-ON STATE.................................................................................................................................................... 20 ELECTRICAL SPECIFICATIONS............................................................................................................................... 21 ABSOLUTE MAXIMUM RATINGS.................................................................................................................... 21 CAPACITANCE TA = 25C, f = 1.0 MHz............................................................................................................ 21 Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................. 22 Figure 6. OUTPUT LOADING.......................................................................................................................... 22 Table 5. DC CHARACTERISTICS ................................................................................................................... 23 Table 6. AC CHARACTERISTICS ................................................................................................................... 24 Table 7. Power-Up Timing................................................................................................................................. 25 INITIAL DELIVERY STATE............................................................................................................................... 25 Timing Analysis......................................................................................................................................................... 26 Figure 7. Serial Input Timing............................................................................................................................. 26 Figure 8. Output Timing..................................................................................................................................... 26 Figure 9. Hold Timing........................................................................................................................................ 27 Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1.............................................. 27 Figure 11. Write Enable (WREN) Sequence (Command 06)............................................................................ 28 Figure 12. Write Disable (WRDI) Sequence (Command 04)............................................................................. 28 Figure 13. Read Identification (RDID) Sequence (Command 9F)..................................................................... 28 Figure 14. Read Status Register (RDSR) Sequence (Command 05)............................................................... 29 Figure 15. Write Status Register (WRSR) Sequence (Command 01).............................................................. 29 Figure 16. Read Data Bytes (READ) Sequence (Command 03)..................................................................... 29 Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................. 30 Figure 18. Dual Output Read Mode Sequence (Command 3B)........................................................................ 30 Figure 19. Page Program (PP) Sequence (Command 02).............................................................................. 31 Figure 20. Sector Erase (SE) Sequence (Command 20)................................................................................. 32 Figure 21. Block Erase (BE) Sequence (Command 52 or D8)......................................................................... 32 Figure 22. Chip Erase (CE) Sequence (Command 60 or C7).......................................................................... 33 Figure 23. Deep Power-down (DP) Sequence (Command B9)....................................................................... 33 Figure 24. Read Electronic Signature (RES) Sequence (Command AB)......................................................... 33 Figure 25. Release from Deep Power-down (RDP) Sequence (Command AB).............................................. 34 Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)............................ 34 Figure 27. Power-up Timing.............................................................................................................................. 35 RECOMMENDED OPERATING CONDITIONS.......................................................................................................... 36 Figure 28. AC Timing at Device Power-Up........................................................................................................ 36 Figure 29. Power-Down Sequence................................................................................................................... 37 ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 38 DATA RETENTION..................................................................................................................................................... 38 LATCH-UP CHARACTERISTICS............................................................................................................................... 38 ORDERING INFORMATION....................................................................................................................................... 39 PART NAME DESCRIPTION...................................................................................................................................... 40 PACKAGE INFORMATION......................................................................................................................................... 41 REVISION HISTORY .................................................................................................................................................. 44 P/N: PM1752 3 REV. 1.5, June 02, 2016 MX25V1006E 1M-BIT [x 1/x 2] CMOS SERIAL FLASH FEATURES GENERAL * Supports Serial Peripheral Interface -- Mode 0 and Mode 3 * 1,048,576 x 1 bit structure or 524,288 x 2 bits (Dual Output mode) Structure * 32 Equal Sectors with 4K byte each - Any Sector can be erased individually * 2 Equal Blocks with 64K byte each - Any Block can be erased individually * Single Power Supply Operation - 2.35 to 3.6 volt for read, erase, and program operations * Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE * High Performance - Fast access time: 75MHz serial clock - Serial clock of Dual Output mode: 70MHz - Fast program time: 0.6ms(typ.) and 1ms(max.)/page (256-byte per page) - Byte program time: 9us - Fast erase time: 40ms(typ.)/sector (4K-byte per sector) ; 0.8s(typ.) and 2s(max.)/chip * Low Power Consumption - Low active read current: 12mA(max.) at 75MHz and 4mA(max.) at 33MHz - Low active programming current: 13mA (typ.) - Low active sector erase current: 9mA (typ.) - Low standby current: 13uA (typ.) - Deep power-down mode: 0.8uA (typ.) * Minimum 100,000 erase/program cycles * 20 years data retention SOFTWARE FEATURES * Input Data Format - 1-byte Command code * Block Lock protection - The BP0-BP1 status bit defines the size of the area to be software protected against Program and Erase instructions. * Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) * Status Register Feature * Electronic Identification - JEDEC 2-byte Device ID - RES command, 1-byte Device ID P/N: PM1752 4 REV. 1.5, June 02, 2016 MX25V1006E HARDWARE FEATURES * SCLK Input - Serial clock input * SI/SIO0 - Serial Data Input or Serial Data Output for Dual output mode * SO/SIO1 - Serial Data Output or Serial Data Output for Dual output mode * WP# pin - Hardware write protection * HOLD# pin - pause the chip without diselecting the chip * PACKAGE - 8-USON (2x3mm) - 8-pin TSSOP (173mil) - 8-pin SOP (150mil) - All devices are RoHS compliant and Halogen-free GENERAL DESCRIPTION MX25V1006E is a CMOS 1,048,576 bit serial Flash memory, which is configured as 131,072 x 8 internally. MX25V1006E features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. MX25V1006E provides sequential read operation on whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase command is executes on chip or sector (4K-bytes) or block (64K-bytes). To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode. The MX25V1006E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. P/N: PM1752 5 REV. 1.5, June 02, 2016 MX25V1006E PIN DESCRIPTION PIN CONFIGURATIONS SYMBOL DESCRIPTION CS# Chip Select Serial Data Input (for 1 x I/O)/ Serial Data SI/SIO0 Input & Output (for Dual output mode) Serial Data Output (for 1 x I/O)/ Serial Data SO/SIO1 Input & Output (for Dual output mode) SCLK Clock Input Hold, to pause the device without HOLD# deselecting the device WP# Write Protection VCC + 3.3V Power Supply GND Ground 8-LAND USON (2x3mm) 1 2 3 4 CS# SO/SIO1 WP# GND VCC HOLD# SCLK SI/SIO0 8 7 6 5 8-PIN TSSOP (173mil) CS# SO/SIO1 WP# GND 1 2 3 4 8 7 6 5 VCC HOLD# SCLK SI/SIO0 8 7 6 5 VCC HOLD# SCLK SI/SIO0 8-PIN SOP (150mil) CS# SO/SIO1 WP# GND P/N: PM1752 1 2 3 4 6 REV. 1.5, June 02, 2016 MX25V1006E BLOCK DIAGRAM X-Decoder Address Generator Memory Array Page Buffer SI/SIO0 Data Register Y-Decoder SO/SIO1 CS#, WP#, HOLD# SCLK SRAM Buffer Mode Logic State Machine Sense Amplifier HV Generator Clock Generator Output Buffer P/N: PM1752 7 REV. 1.5, June 02, 2016 MX25V1006E DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC powerup and power-down or from system noise. * Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. * Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion - Sector Erase (SE) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion * Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change. * Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data change. * Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from Deep Power-down mode command (RDP) and Read Electronic Signature command (RES). Table 1. Protected Area Sizes BP1 0 0 1 1 P/N: PM1752 Status bit BP0 0 1 0 1 Protect level 1Mb 0 (none) 1 (1 block) 2 (2 blocks) 3 (All) None Block 1 All All 8 REV. 1.5, June 02, 2016 MX25V1006E HOLD FEATURE HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low(if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1. SI/SIO0 SO/SIO1 (internal) SO/SIO1 (External) Don't care Valid Data Valid Data High_Z Bit 6 Bit 5 Bit 6 SO/SIO1 (internal) SO/SIO1 (External) High_Z Bit 7 Bit 5 SI/SIO0 HOLD# SCLK Valid Data Bit 6 Bit 7 CS# Don't care Bit 7 HOLD# SCLK CS# Figure 1. Hold Condition Operation Don't care Valid Data Bit 7 Bit 7 Valid Data Bit 6 High_Z Don't care Bit 5 Bit 6 Bit 5 Valid Data Bit 4 High_Z Bit 3 Bit 4 Bit 3 During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will keep high impedance until Hold# pin goes high and SCLK goes low. The Serial Data Input (SI) is don't care if both Serial Clock (SCLK) and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin goes high. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. P/N: PM1752 9 REV. 1.5, June 02, 2016 MX25V1006E Table 2. COMMAND DEFINITION RDID (Read Identification) 9F (hex) RDSR (Read Status Register) 05 (hex) WRSR (Write Status Register) 01 (hex) outputs sets the (WEL) resets the (WEL) manufacturer write enable write enable latch bit ID and 2-byte latch bit device ID to read out the status register to write new n bytes read out values to the until CS# goes status register high COMMAND WREN WRDI (byte) (Write Enable) (Write Disable) 1st 2nd 3rd 4th 5th Action 06 (hex) 04 (hex) COMMAND (byte) Fast Read (Fast Read Data) DREAD (Dual Output mode) 1st 0B (hex) 3B (hex) 2nd 3rd 4th 5th Action 2nd 3rd 4th 5th Action 20 (hex) AD1 AD1 AD1 AD2 AD2 AD2 AD3 AD3 AD3 x n bytes read out n bytes read out to erase the until CS# goes until CS# goes selected sector high high DP COMMAND (Deep Power(byte) down) 1st SE BE (Sector Erase) (Block Erase) B9 (hex) enters deep power down mode RDP (Release from Deep Powerdown) AB (hex) release from deep power down mode 52 or D8 (hex) READ (Read Data) 03 (hex) AD1 AD2 AD3 CE (Chip Erase) PP (Page Program) 60 or C7 (hex) 02 (hex) AD1 AD2 AD3 to erase the selected block AD1 AD2 AD3 to erase the whole chip to program the selected page REMS RES (Read (Read Electronic Electronic ID) Manufacturer & Device ID) AB (hex) 90 (hex) x x x x x ADD(1) to read out Output the 1-byte Device manufacturer ID and device ID ID (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. (2) It is not recommended to adopt any other code which is not in the command definition table above. P/N: PM1752 10 REV. 1.5, June 02, 2016 MX25V1006E MEMORY ORGANIZATION Table 3. Memory Organization Block 1 0 P/N: PM1752 Sector 31 : 16 15 : 3 2 1 0 Address Range 01F000h 01FFFFh : : 010000h 010FFFh 00F000h 00FFFFh : : 003000h 003FFFh 002000h 002FFFh 001000h 001FFFh 000000h 000FFFh 11 REV. 1.5, June 02, 2016 MX25V1006E DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure the device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. The CS# falling time needs to follow tCHCL spec. (Please refer to Table 6. AC CHARACTERISTICS) 3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge. The CS# rising time needs to follow tCLCH spec. (Please refer to Table 6. AC CHARACTERISTICS) 4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 2. 5. For the following instructions: RDID, RDSR, READ, FAST_READ, DREAD, RES and REMS the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, and Erase. Figure 2. Serial Modes Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master: -CPOL=1 for SCLK high while idle, -CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1752 12 REV. 1.5, June 02, 2016 MX25V1006E COMMAND DESCRIPTION (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low sending WREN instruction code CS# goes high. (see Figure 11) (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low sending WRDI instruction code CS# goes high. (see Figure 12) The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE) instruction completion - Chip Erase (CE) instruction completion (3) Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID and Device ID are listed as Table of ID Definitions. The sequence of issuing RDID instruction is: CS# goes lowsending RDID instruction code24-bits ID data out on SOto end RDID operation can use CS# to high at any time during data out. (see Figure. 13) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. P/N: PM1752 13 REV. 1.5, June 02, 2016 MX25V1006E (4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes lowsending RDSR instruction codeStatus Register data out on SO (see Figure. 14) The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. BP1, BP0 bits. The Block Protect (BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed) SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only. Status Register bit7 bit6 bit5 bit4 SRWD (status register write protect) 0 0 0 1=status register write disable bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) (Note 1) (Note 1) bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation Notes: 1. See the table "Protected Area Sizes". P/N: PM1752 14 REV. 1.5, June 02, 2016 MX25V1006E (5) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP1, BP0) bits to define the protected area of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low sending WRSR instruction code Status Register data on SI CS# goes high. (see Figure 15) The WRSR instruction has no effect on b6, b5, b4, b1, b0 of the status register. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Table 4. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP1 bits can be changed. WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be programmed or erased. The SRWD, BP0-BP1 of status register bits cannot be changed. WP#=0, SRWD bit=1 The protected area cannot be programmed or erased. Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1. As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM). When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM) Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP1, BP0 and hardware protected mode by the WP# to against data modification. Note: to exit the hardware protected mode, it requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP1, BP0. P/N: PM1752 15 REV. 1.5, June 02, 2016 MX25V1006E (6) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low sending READ instruction code 3-byte address on SI data out on SO to end READ operation can use CS# to high at any time during data out. (see Figure. 16) (7) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low sending FAST_READ instruction code 3-byte address on SI 1-dummy byte address on SIdata out on SO to end FAST_READ operation can use CS# to high at any time during data out. (see Figure. 17) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (8) Dual Output Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits(interleave on 1I/2O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit. The sequence is shown as Figure 18. While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. The DREAD only performs read operation. Program/Erase /Read ID/Read status....operations do not support DREAD throughputs. (9) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. P/N: PM1752 16 REV. 1.5, June 02, 2016 MX25V1006E Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes low sending SE instruction code 3-byte address on SI CS# goes high. (see Figure 20) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page. (10) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing BE instruction is: CS# goes low sending BE instruction code 3-byte address on SI CS# goes high. (see Figure 21) The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page. (11) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence of issuing CE instruction is: CS# goes low sending CE instruction code CS# goes high. (see Figure 22) The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP1, BP0 all set to "0". (12) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The last address byte (the 8 least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instrucP/N: PM1752 17 REV. 1.5, June 02, 2016 MX25V1006E tion will be rejected and not executed. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. There will be no effort on the other data bytes of the same page. The sequence of issuing PP instruction is: CS# goes low sending PP instruction code 3-byte address on SI at least 1-byte on data on SI CS# goes high. (see Figure 19) The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Page Program (PP) instruction will not be executed. (13) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low sending DP instruction code CS# goes high. (see Figure 23) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. (14) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as Table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress. The sequence is shown as Figure 24 and Figure 25. P/N: PM1752 18 REV. 1.5, June 02, 2016 MX25V1006E The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be received, be decoded, and be executed instruction. The RDP instruction is for releasing from Deep Power Down Mode. (15) Read Electronic Manufacturer ID & Device ID (REMS) The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (A7-A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 26. The Device ID values are listed in Table of ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table of ID Definitions RDID Command manufacturer ID C2 memory type 20 electronic ID 10 device ID 10 RES Command REMS Command P/N: PM1752 manufacturer ID C2 19 memory density 11 REV. 1.5, June 02, 2016 MX25V1006E POWER-ON STATE The device is at the states as below when power-up: - Standby mode (please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level (Please refer to the figure of "power-up timing"): - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal Power-On Reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the time delay: tVSL after VCC reached VCC minimum level. Please refer to the figure of "power-up timing". The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uF) P/N: PM1752 20 REV. 1.5, June 02, 2016 MX25V1006E ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature -40C to 85C Storage Temperature -65C to 150C Applied Input Voltage -0.5V to VCC+0.5V Applied Output Voltage -0.5V to VCC+0.5V VCC to Ground Potential -0.5V to VCC+0.5V NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot to VCC+1.0V to VCC or -0.5V to GND for period up to 20ns. Figure 4. Maximum Positive Overshoot Waveform Figure 3. Maximum Negative Overshoot Waveform 20ns 20ns 20ns 0V Vcc + 1.0V -0.5V Vcc 20ns 20ns 20ns CAPACITANCE TA = 25C, f = 1.0 MHz SYMBOL PARAMETER CIN COUT P/N: PM1752 MIN. TYP. MAX. UNIT Input Capacitance 6 pF VIN = 0V Output Capacitance 8 pF VOUT = 0V 21 CONDITIONS REV. 1.5, June 02, 2016 MX25V1006E Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing reference level 0.8VCC 0.2VCC 0.7VCC 0.3VCC Output timing reference level AC Measurement Level 0.5VCC Note: Input pulse rise and fall time are <5ns Figure 6. OUTPUT LOADING 25K ohm DEVICE UNDER TEST CL +2.5V 25K ohm CL=30pF or 15pF Including jig capacitance P/N: PM1752 22 REV. 1.5, June 02, 2016 MX25V1006E Table 5. DC CHARACTERISTICS Symbol Parameter Notes ILI Input Load Current 1 ILO Output Leakage Current 1 ISB1 VCC Standby Current 1 ISB2 Deep Power-down Current ICC1 VCC Read ICC2 ICC3 ICC4 ICC5 VIL VIH VOL VOH VWI VCC Program Current (PP) VCC Write Status Register (WRSR) Current VCC Sector Erase Current (SE) VCC Chip Erase Current (CE) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Low VCC Write Inhibit Voltage 1 1 1 1 3 Min. Typ. Units Test Conditions VCC = VCC Max 0.02 2 uA VIN = VCC or GND VCC = VCC Max 0.02 2 uA VOUT = VCC or GND VIN = VCC or GND 13 25 uA CS#=VCC VIN = VCC or GND 0.8 10 uA CS#=VCC f=75MHz fT=70MHz (Dual Output) 3.5 12 mA SCLK=0.1VCC/0.9VCC, SO=Open f=66MHz 10 mA SCLK=0.1VCC/0.9VCC, SO=Open f=33MHz 1.5 4 mA SCLK=0.1VCC/0.9VCC, SO=Open Program in Progress 13 20 mA CS#=VCC Program status register in 2.1 15 mA progress CS#=VCC Erase in Progress 9 15 mA CS#=VCC Erase in Progress 15 20 mA CS#=VCC -0.5 0.3VCC V 0.7VCC VCC+0.4 V 0.4 V IOL = 1.6mA VCC-0.2 V IOH = -100uA 1.5 Max. 2.3 V Notes : 1. Typical values at VCC = 3.3V, T = 25C. These currents are valid for all product versions (package and speeds). 2. Typical value is calculated by simulation. 3. Not 100% tested. P/N: PM1752 23 REV. 1.5, June 02, 2016 MX25V1006E Table 6. AC CHARACTERISTICS Symbol Alt. fSCLK fC fRSCLK fTSCLK fR fT tCH(1) tCLH tCL(1) tCLL tCLCH(2) tCHCL(2) tSLCH tCSS tCHSL tDVCH tDSU tCHDX tDH tCHSH tSHCH tSHSL tCSH tSHQZ(2) tDIS tCLQV tV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX(2) tHLQZ(2) tWHSL(4) tSHWL(4) tDP(2) tHO tRES1(2) tRES2(2) tW tBP tPP tSE tBE tCE tLZ tHZ Parameter Clock Frequency for the following instructions: FAST_READ, PP, SE, BE, CE, DP, RES, RDP, WREN, WRDI, RDID, RDSR, WRSR Clock Frequency for READ instructions Clock Frequency for DREAD instructions @33MHz Clock High Time @75MHz @33MHz Clock Low Time @75MHz Clock Rise Time (3) (peak to peak) Clock Fall Time (3) (peak to peak) CS# Active Setup Time (relative to SCLK) CS# Not Active Hold Time (relative to SCLK) Data In Setup Time Data In Hold Time CS# Active Hold Time (relative to SCLK) CS# Not Active Setup Time (relative to SCLK) Read CS# Deselect Time Write Output Disable Time 30pF Clock Low to Output Valid 15pF Output Hold Time HOLD# Active Setup Time (relative to SCLK) HOLD# Active Hold Time (relative to SCLK) HOLD# Not Active Setup Time (relative to SCLK) HOLD# Not Active Hold Time (relative to SCLK) HOLD# to Output Low-Z HOLD# to Output High-Z Write Protect Setup Time Write Protect Hold Time CS# High to Deep Power-down Mode CS# High to Standby Mode without Electronic Signature Read CS# High to Standby Mode with Electronic Signature Read Write Status Register Cycle Time Byte-Program Page Program Cycle Time Sector Erase Cycle Time Block Erase Cycle Time Chip Erase Cycle Time Min. Typ. Max. Unit DC 75 MHz DC DC 13 6 13 6 0.1 0.1 7 7 2 5 7 7 15 40 33 70 10 MHz MHz ns ns ns ns V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us 8.8 us 8.8 us 40 50 1 200 1 2 ms us ms ms s s 6 8 6 0 5 5 5 5 6 6 20 100 5 9 0.6 40 0.4 0.8 Notes: 1. tCH + tCL must be greater than or equal to 1/f (fC or fR). 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 5. Test condition is shown as Figure 5. 6. The CS# rising time needs to follow tCLCH spec and CS# falling time needs to follow tCHCL spec. P/N: PM1752 24 REV. 1.5, June 02, 2016 MX25V1006E Table 7. Power-Up Timing Symbol tVSL(1) Parameter VCC(min) to CS# low Min. 200 Max. Unit us Note: 1. The parameter is characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1752 25 REV. 1.5, June 02, 2016 MX25V1006E Timing Analysis Figure 7. Serial Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO Figure 8. Output Timing CS# tCH SCLK tCLQV tCL tCLQV tSHQZ tCLQX LSB SO SI P/N: PM1752 ADDR.LSB IN 26 REV. 1.5, June 02, 2016 MX25V1006E Figure 9. Hold Timing CS# tHLCH tCHHL tHHCH SCLK tCHHH tHLQZ tHHQX SO HOLD# * SI is "don't care" during HOLD operation. Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01 SI SO P/N: PM1752 High-Z 27 REV. 1.5, June 02, 2016 MX25V1006E Figure 11. Write Enable (WREN) Sequence (Command 06) CS# 1 0 2 3 4 5 6 7 SCLK Command SI 06 High-Z SO Figure 12. Write Disable (WRDI) Sequence (Command 04) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 04 High-Z SO Figure 13. Read Identification (RDID) Sequence (Command 9F) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Command SI 9F Manufacturer Identification SO High-Z 7 6 5 3 MSB P/N: PM1752 2 1 Device Identification 0 15 14 13 3 2 1 0 MSB 28 REV. 1.5, June 02, 2016 MX25V1006E Figure 14. Read Status Register (RDSR) Sequence (Command 05) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command 05 SI Status Register Out High-Z SO 7 6 5 4 3 2 1 Status Register Out 0 7 6 5 4 3 2 1 7 0 MSB MSB Figure 15. Write Status Register (WRSR) Sequence (Command 01) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command SI Status Register In 01 7 5 4 3 2 1 0 MSB High-Z SO 6 Figure 16. Read Data Bytes (READ) Sequence (Command 03) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK command SI 03 24-Bit Address 23 22 21 3 2 1 0 MSB Data Out 1 High-Z 7 SO 6 5 4 3 2 Data Out 2 1 0 7 MSB P/N: PM1752 29 REV. 1.5, June 02, 2016 MX25V1006E Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24 BIT ADDRESS 23 22 21 0B 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte 7 SI 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 7 SO 6 5 4 3 2 1 7 0 6 5 4 3 2 1 MSB MSB 0 7 MSB Figure 18. Dual Output Read Mode Sequence (Command 3B) CS# 0 1 2 3 4 5 6 7 8 9 10 11 39 40 41 42 43 30 31 32 SCLK 8 Bit Instruction SI/SO0 SO/SO1 P/N: PM1752 3B(hex) 24 BIT Address address bit23, bit22, bit21...bit0 High Impedance 8 dummy cycle dummy Data Output data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... 30 REV. 1.5, June 02, 2016 MX25V1006E Figure 19. Page Program (PP) Sequence (Command 02) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 1 0 7 6 5 3 2 1 0 2079 2 2078 3 2077 23 22 21 02 SI Data Byte 1 2076 24-Bit Address 2075 Command 4 1 0 MSB MSB 2074 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 CS# SCLK Data Byte 2 SI 7 6 MSB P/N: PM1752 5 4 3 2 Data Byte 3 1 0 7 6 5 4 MSB 3 2 Data Byte 256 1 0 7 6 5 4 3 2 MSB 31 REV. 1.5, June 02, 2016 MX25V1006E Figure 20. Sector Erase (SE) Sequence (Command 20) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK 24 Bit Address Command SI 23 22 20 2 1 0 MSB Note: SE command is 20(hex). Figure 21. Block Erase (BE) Sequence (Command 52 or D8) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Command SI 24 Bit Address 23 22 52 or D8 2 1 0 MSB Note: BE command is 52 or D8(hex). P/N: PM1752 32 REV. 1.5, June 02, 2016 MX25V1006E Figure 22. Chip Erase (CE) Sequence (Command 60 or C7) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 60 or C7 Note: CE command is 60(hex) or C7(hex). Figure 23. Deep Power-down (DP) Sequence (Command B9) CS# 0 1 2 3 4 5 6 tDP 7 SCLK Command B9 SI Stand-by Mode Deep Power-down Mode Figure 24. Read Electronic Signature (RES) Sequence (Command AB) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCLK Command SI AB tRES2 3 Dummy Bytes 23 22 21 3 2 1 0 MSB Electronic Signature Out High-Z 7 SO 6 5 4 3 2 1 0 MSB Deep Power-down Mode P/N: PM1752 33 Stand-by Mode REV. 1.5, June 02, 2016 MX25V1006E Figure 25. Release from Deep Power-down (RDP) Sequence (Command AB) CS# 0 1 2 3 4 5 6 tRES1 7 SCLK Command SI AB High-Z SO Stand-by Mode Deep Power-down Mode Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90) CS# 0 1 2 3 4 5 6 7 8 9 10 SCLK Command SI 2 Dummy Bytes 15 14 13 90 3 2 1 0 High-Z SO CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1) SI 7 6 5 4 3 2 1 0 Manufacturer ID SO X 7 6 5 4 3 2 1 Device ID 0 7 6 5 4 3 2 MSB MSB 1 0 7 MSB Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first P/N: PM1752 34 REV. 1.5, June 02, 2016 MX25V1006E Figure 27. Power-up Timing VCC VCC(max) Chip Selection is Not Allowed VCC(min) tVSL Device is fully accessible time P/N: PM1752 35 REV. 1.5, June 02, 2016 MX25V1006E RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure 28 and Figure 29 are for the supply voltages and the control signals at device powerup and power-down. If the timing in the figures is ignored, the device will not operate correctly. During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL. Figure 28. AC Timing at Device Power-Up VCC VCC(min) GND tVR tSHSL CS# tSLCH tCHSL tSHCH tCHSH SCLK tDVCH tCHCL tCHDX LSB IN MSB IN SI High Impedance SO Symbol tVR tCLCH Parameter VCC Rise Time Notes 1 Min. Max. 500000 Unit us/V Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1752 36 REV. 1.5, June 02, 2016 MX25V1006E Figure 29. Power-Down Sequence During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation. VCC CS# SCLK P/N: PM1752 37 REV. 1.5, June 02, 2016 MX25V1006E ERASE AND PROGRAMMING PERFORMANCE Parameter Write Status Register Cycle Time Sector erase Time Block erase Time Chip Erase Time Byte Program Time (via page program command) Page Program Time Erase/Program Cycle Min. Typ. (1) 5 40 0.4 0.8 9 0.6 Max. (2) 40 200 1 2 50 1 100,000 Unit ms ms s s us ms cycles Notes: 1. Typical program and erase time assumes the following conditions: 25C, 2.5V, and checker board pattern. 2. Under worst conditions of 85C and 2.35V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 4. Erase/Program cycles comply with JEDEC: JESD47 & JESD22-A117 standard. DATA RETENTION Parameter Condition Min. Data retention 55C 20 Max. Unit years LATCH-UP CHARACTERISTICS Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 2.5V, one pin at a time. P/N: PM1752 38 Min. -1.0V -1.0V -100mA Max. 2 VCCmax VCC + 1.0V +100mA REV. 1.5, June 02, 2016 MX25V1006E ORDERING INFORMATION Please contact Macronix regional sales for the latest product selection and available form factors. Clock Part No. Temperature Package (MHz) MX25V1006EZUI-13G 75 -40 to 85C 8-USON (2x3mm) MX25V1006EOI-13G 75 -40 to 85C 8-TSSOP (173mil) MX25V1006EMI-13G 75 -40 to 85C 8-SOP (150mil) P/N: PM1752 39 Remark REV. 1.5, June 02, 2016 MX25V1006E PART NAME DESCRIPTION MX 25 V 1006E ZU I 13 G OPTION: G: RoHS compliant and Halogen-free SPEED: 13: 75MHz TEMPERATURE RANGE: I: Industrial (-40C to 85C) PACKAGE: ZU: 2x3mm 8-USON O: 173mil 8-TSSOP M: 150mil 8-SOP DENSITY & MODE: 1006E: 1Mb TYPE: V: 2.5V DEVICE: 25: Serial Flash P/N: PM1752 40 REV. 1.5, June 02, 2016 MX25V1006E PACKAGE INFORMATION P/N: PM1752 41 REV. 1.5, June 02, 2016 MX25V1006E P/N: PM1752 42 REV. 1.5, June 02, 2016 MX25V1006E P/N: PM1752 43 REV. 1.5, June 02, 2016 MX25V1006E REVISION HISTORY Revision No. Description 1.0 1. Removed "Advanced Information" 1.1 1. Added 150mil 8-SOP package solution 1.2 1. Removed "Advanced Information" status of MX25V1006EMI-13G 1.3 1. Updated parameters for DC/AC Characteristics 2. Updated Erase and Programming Performance 1.4 1. Updated parameters for DC Characteristics 2. Modified HOLD feature descriptions. Page P4 P5,6,39, P40,43 P39 P4,23,24 P4,38 P4,23 P9 Date OCT/28/2011 MAY/16/2013 1.5 P36 P39 JUN/02/2016 P/N: PM1752 1. Updated tVR values 2. Added a statement for product ordering information 44 JUN/17/2013 NOV/12/2013 MAR/26/2015 REV. 1.5, June 02, 2016 MX25V1006E Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it's suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright(c) Macronix International Co., Ltd. 2011-2016. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix's Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 45