. tol PRELIMINARY in 27960KX BURST ACCESS 1M (128K x 8) CHMOS EPROM m Synchronous 4-Byte Data Burst Access @ Asynch Microcontroller Reset Function m Simple Interface to the 80960KA/KB ~ Outputs to Known State with High Z 7 vie ewer State Date tee Out @ CHMOS* III-E for High Performance and Low Power SOOCOK AKG orang Zo HE 125 mA Active, 30 mAStandby TTL Compatible inputs m@ 1 Mbit Density Configures as 128K x 8 Intels 27960KX is a 5V only, 1,048,576 bit, Erasable Programmable Read Only Memory, organized as 128K words of 8 bits. The 27960KX provides a simple synchronous burst interface to the 80960KA/KB bus. Internally the 27960KX is organized in 4 byte blocks, in which each byte is accessed sequentially. The internal state machine is factory configured to generate either 1 or 2 wait-states between the address and first data byte. High performance outputs provide zero wait-state data to data accesses at clock frequencies up to 25 MHz. An asynchronous. microcontroller RESET feature puts the outputs in the high impedance state and takes the internal state machine to a known state where a new burst access can begin. The 27960KxX is available in 44 lead PLCC package, providing optimum cost effectiveness. The 27960KX is manufactured on Intels 1 micron CHMOS III-E technology. The Quick-Pulse Programming algorithm provides fast, reliable Programming with throughput under 17 seconds for optimized equipment. *CHMOS is a patented process of Intel Corporation. X PREDECODER AgmAig Yi M BOO, YNIOAYre ARRAY CLK MAay4w MZ-IrOPE SENSE Y DECODER 290237-1 Figure 1. 27960KX Burst EPROM Block Diagram September 1991 4-40 Order Number: 290237-006intel. 27960KX PRELIMINARY 27960KX BURST EPROM EPROMs are established as the preferred code stor-__ age device in embedded applications. The non-vola- tile, flexible, reliable, cost effective EPROM makes a product easier to design, manufacture and service. Until recently, however, EPROMs could not match the performance needs of high-end systems. The 27960KX was designed to support the 80960KA/KB embedded processor. It utilizes the burst interface to offer near zero-wait state performance without the high cost normally associated with this performance. In embedded designs, board space and cost must be kept at a minimum without impacting perform- ance and reliability. The 27960KX removes the need for expensive high-speed shadow RAM backed up by slow EPROM or ROM for non-volatile code stor- age. Code optimization concerns are reduced with off-chip code fetches no longer crippling to sys- tem performance. FONTs can be run directly out of these EPROMs at the same performance as high- speed DRAMs. With the 27960KX, the EPROM is the ideal code or FONT storage device for your 80960KA/KB system. Architecture The 27960KX provides a simple, synchronous burst interface to the 80960KA/KB's bus. Internally, the 27960KX is organized in 4 byte blocks each byte is accessed Seaver ae burst access begins on the first clock pulse after CS is asserted. The address of the four byte block is latched by the rising edge of ALE. After a preset number of wait-states (1 or 2), data is output one byte at a time on each subse- quent clock cycie. A burst access is terminated on the rising edge of CLOCK if BLAST is asserted. High performance outputs provide zero wait-state data to data accesses at clock frequencies up to 25 MHz. Extra power and ground pins dedicated to the out- puts reduce the effects of fast output switching on device performance. The 27960KX delivers 4 bytes of data in 8 clock cycles at 25 MHz and 4 bytes of data in 7 clock cycles at 20 MHz. In a 32-bit configuration, this translates into a read bandwidth of 50 Mbytes/sec and 45 Mbytes/sec respectively. Performance capa- bility of the 27960KX in different 8O960KA/KB sys- tems is given in Table 1. cs ADDRESS 27960KX BURST EPROM 128K x 8 290237-2 Figure 2. 27960KX Burst EPROM Signal Set27960KX PRELIMINARY 6 5 4 3 2 1 4443 42 4140 Og C47 39 Ag Vss2 8 SBRIAs Voor] 8 37B Ay, | N27960Kx i. ae 44 LEAD PLCC 2 Vss3 412 34D, ee tee EN Vgs4 15 31D Vecs 1416 304, 0,517 29F Ay 18 19 20 21 22 23 2425 26 27 28 o Mm BBS > > > beter sy had 290237-3 PIN DESCRIPTIONS Figure 3. 27960KX 44-Lead PLCC Pinout Symbol Pin Function Ao-Ai6: 23-39 ADDRESS INPUTS: During a burst operation, Ap through A1 provide the base address pointing to a block of four consecutive bytes. Ao and A; select the first byte of the burst access. The 27960KX latches valid addresses in the first clock cycle. An internal address generator increments addresses Ao and A, for subsequent bytes of the burst. Do~D7: 18, 17, 14, 13, 11, 10, 7,6 DATA INPUTS/OUTPUTS ALE 42 ADDRESS LATCH ENABLE: Indicates the transfer of a physical address. ALE is an active low signal used to latch the addresses from the processor. Addresses are latched onthe rising edge of ALE. Valid addresses must be Present at or before ALE becomes valid, CHIP SELECT: Master device enable. When asserted (active low) data can be written to and read from the device. In read mode, CS enables the state machine and the I/O circuitry. , NOTES: 1. The address decode path is independent of CS, ie., X and Y decoding is always powered up. 2. For programming, CS should remain low for the entire cycle. Program and verify functions are done one byte at a time. 3. CS going high does not terminate a concurrent burst cycle. 4. CS must be deasserted between bursts. BURST LAST: Terminates a concurrent burst data cycle at the rising edge of the CLK. It must be asserted by the fourth data byte. 22 RESET: Resets the state machine into a known state, tri-states the outputs. The duration of RESET should be 10 CLK cycles minimum. At least 5 clock cycles are required after deassertion of RESET before beginning the next cycle. Reset will abort a concurrent bus cycle. . 4-42intal. 27960KX PRELIMINARY PIN DESCRIPTIONS (Continued) Symbol Pin Function PGM 43 PROGRAM-PULSE CONTROL INPUT Vpp 2 PROGRAMMING POWER SUPPLY Vpp Vss 5, 8, 12, GROUND 15, 19, 21 Voc 9, 16, 20, 44 | SUPPLY VOLTAGE INPUT Table 1. Performance Capability ADDR | Apo |} WS | WS - - - |- DATA; - - - Doo | Dox | Doz | Dos CLK | Cy/ Col] Cg] Cy C5l Cel C7 20 MHz 1 WS NON-BUFFERED : 4 ADDR | Ago | WS - - - - YRS DATA | - - Doo | Do1 | Doz | Dos - CLK | Cy Co Cg | C4 Cs5| Cel] C7 ADDR | Ago | WS - - - - |RS DATA] - | = | Doo | Dor} Do2|Do3} - CLK | Cy] Co] Cg}Ca Cs| Cel C7 25/20 MHz 2 WS NON-BUFFERED : 4 WORDS/8 CLOCK CYCLES 50/40 MBYTES/SEC WORDS/7 CLOCK CYCLES 16 MHz 1 WS BUFFERED : 4 WORDS/7 CLOCK CYCLES RS! Agx | WS | WS | - : : - | RS foo [- - Dio | Dy | Daa | Dig Cg | C1 | Co | Cg [Cy [C5 | Ce] C7] Ce 45 MBYTES/SEC Aoi | WS | - - - - | RS } Ags | WS - - | Dio | Dyq | Dy2 | Dig Cy| Co} Cg] Cy Cs5| Cel Cr 36 MBYTES/SEC Ao |wS |- |- |- |- [RS | Aog | WS : - | Dio | Day | O12} Dag Ci} Co] Cg] Cy | C5/Cg | Cr INTERFACE EXAMPLE Overview The following design offers a simple interface to the 80960KA/KBs bus. A non-buffered 27960KX burst EPROM system is shown in Figure 4. Since the 27960KX is capable of driving a 120 pF load, large, non-buffered systems can be implemented by stacking up to 2 banks of 4 EPROMs, giving a memory size of 256K x 32. The input capacitive load seen on the address lines (due to the EPROM only) is 24 pF for a 128K x 32 system (shown) and 48 pF for a 256K x 32 system. The EPROM is specified at 4 pF for input capaci- tance and 12 pF typical for output capacitance. Larger systems can be implemented with buffers. Chip Select Logic High order address lines are decoded to provide CS. Qualification with other signals is not required. The . chip setect logic can be implemented with standard asynchronous decoders, PALs or PLD's (like Intels 85C960). 4-4327960KX PRELIMINARY 27960KX does not require address latches ADDRESS LATCHES LABIA) ) ADDRESS TO NON-BURST MODE MEMORY te * SEE NOTE ts LaD(35:0) tan (18:2) | cs ts ts as Aon Aig ry) Bom Atg 7 , Aon Ais Ao-Aig aos 17 7 7 17 nG _ _ ale ae ALE ale % 858960 27960KXx 27960Kx 27960Kx 27960Kx = 128K x 8 128K x8 128K x 8 128K x 8 yy fom! cs _ 80960KK LAD(3:0) ADo-an, BLAST Blast BLAST BLAST BLAST ine a 3 0S 2 s a5 Fi cuK cuk cL LK v/R wit RESET - RESET DERESET | Restt ere DEN aK 8 8 8 8 READY my Dp-0, Og-D15 Oe-O25 Daq-05, Gaa DATA RESET cu A < 32 7 cLK2 CLK2(50 MHz) clock CLK(25 MHz) GENERATOR ESET RESET 290237-6 NOTE: Figure 4. 128K x 32 Burst EPROM System Waveforms Figure 5 shows the timing waveforms of 27960KX reads in a 32-bit system. CS setup time CS setup time is the time between CS asserted and the first rising CLK edge of CLK (during the address cycle). Since a memory access begins on the first CLK rising edge after CS asserted, a minimum CS setup time of 5 ns (tsyoy) at 25 MHz is required. With the 80960KA/KBs maximum valid address de- lay of 18 ns at 25 MHz, 13 ns remains for CS decod- ing logic. 4-44 CS Deassert between bursts After every EPROM read (one to four words) CS must be deasserted. Reset and RESET The 27960KX uses RESET. The 80960 KA/KB RESET signal must be inverted for. the 27960KX. Clock Phase The initial rising edge of CLK and CLK2 must.be in phase with as small a skew as possible.M4 : intel. 27 960KX PRELIMINARY A WS Do D o 0 Re A ws oO Dd 0 0 Rc CLK 0 1 2 3 4 5 6 7 8 3 10 1t 12 13 14 CLK ADDR 00 10 XX me rnS W UT sf \ IN JL, DATA CRE RRR XK KR RRR 5 BLAST LL LS 4 290237-9 NOTES: 1. 1-0-0-0 Burst Read > 1 indicates the number of wait states to access the first word 0s indicate the number of wait states for subsequent data words (0 in this case) 2. 27960KX latches addresses on the rising edge of ALE: it has an internal address generator which increments ad- dresses for subsequent words of the burst. , Figure 5. Two Cycles of a 27960KX 1 Wait State, 4-Byte Read (1-0-0-0 Burst Read) in a 32-Bit System 27960KX DEVICE NAMES The device names on the 27960KX were derived as mnemonics that correspond to the number of wait states and expected operating frequency for the de- vice. For example, the 25 MHz, 2 wait state 27960KX is named 27960K2-25. AC TIMING DERIVATIONS The AC timings for the 27960KX were generated specifically to meet the requirements of the 80960KA/KB microprocessor. In each case the ap- plicable 80960KA/KB clock frequency and AC tim- ing were taken together with an address buffer delay (if needed) and a 4 ns positive clock skew or a 2 ns negative clock skew (see Figure 6A). guardband to 4-45 generate the 27960KX AC timing. Worst case tim- ings were always assumed. The example below shows how the 27960K1-20 tavcoh timing was de- rived. @20 MHz the clock cycle is ~ 50 ns. tg of the 80960KA/KB is 2-20 ns. 4 ns clock skew guardband. 27960K1-20 tavcoh = 50 ns 20 ns 4ns = 26ns On timings such as this, where the EPROM is faster than the microprocessor, we specified the EPROM's timing leaving the excess time as system guard- band.intel. 27960KX PRELIMINARY CLK2 (to 80960) 4ns 2ns| CLK 200237-11 NOTE: The 27960KX allows a positive clock skew (CLK2 leading CLK) of up to 4 ns anda negative clock skew (CLK2 lagging CLK) of up to 2 ns. The larger positive clock skew takes into account longer trace lengths and heavier loading on the 1x clock trace. : Figure GA. Definition of Positive and Negative Clock Skew 50 MHz 80960KB CLOCK CLK2 > rr Combinatorial PAL Driver / 16L8=7 747244 CLK . . 27960KX 27960KX 27960KX 27960KX 29023712" 7 NOTE: , CLK and CLK2 are generated by the same PAL. This minimizes skew between CLK and CLK2. Both PAL outputs are.ted to a 74F244 driver. The EPROMs should be as close to the clock driver as possible. _ Figure 6B. Example Clock Circuit with Minimum Skew 4-4627960KX PRELIMINARY 100 MHz osc NOTE: possible. cP CET This clock generation circuit uses a 100 MHz Qscillator. The EPROMs should be as close to the NAND drivers as 74481804 NAND DRIVERS 74ACT163 290237-20 Figure 6C. Example Clock Circuit Using a 100 MHz Oscillator Decoders are needed for the systems address (chip select) decoding. For the 27960KXs timings we as- sumed a 5-10 ns chip select decoder for 16 MHz and 20 MHz frequencies and a 5-9 ns decoder for 25 MHz systems. The example below shows how the 27960K2-25 tsvch timing was derived. @25 MHz the clock cycle is ~ 40 ns. tg of the 80960KA/KB is 2-18 ns. Decoder = 9 ns 4 ns clock skew guardband 27960K2-25 tsvch = 40 ns 18 ns 9ns 4ns 9ns SYSTEM BUFFERING CONSIDERATIONS For many large system applications buffering may be required between the microprocessor and memo- ry devices. The 20 MHz 2 WS and 16 MHz 27960KX AC timings take this into account. For ap- plications at these frequencies not requiring buffer- ing these devices will provide an additional 5-10 ns of system guardband. The list below shows the buffers used in generating these timings: Input Output Buffer Buffer 20 MHz 9ns 5ns 16 MHz 10 ns 7ns The 20 MHz buffers are slightly faster in keeping with the increased sensitivity for higher perform- ance. We chose the above buffers because of their wide availability. Significantly faster buffers are avail- able for applications requiring them. The example below shows tchqv for the 27960K2-20. @20 MHz the clock cycle is ~ 50 ns. tio of the 80960KA/KB is 3 ns. Output buffer for 20 MHz = 5 ns. 4 ns clock skew guardband 27960K2-20 tchqv = 50 ns 5ns 3ns 4ns = 38ns 4-47ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains preliminary infor- mation on new products in production. The specifica- Read Operating Temperature...... 0C to + 70C(8) tions are subject to change without notice. Verity with Case Temperature under Bias . . 10C to + 80C(8) your local Intel Sales office that you have the latest data sheet before finalizing a design. Storage Temperature .......... ~ 65C to + 125C *WARNING. Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the All input or Output Voltages... .. 0.6V to +6.5V(4) with Respect to Ground Voltage on Ag.............00. 0.6V to + 13.0V(4) Operating Conditions is not recommended and ex- with Respect to Ground tended exposure beyond the Operating Conditions Vpp Supply Voltage........... 0.6V to + 14.0V(4) may affect device reliability. with Respect to Ground Vcc Supply Voltage ........... 0.6V to +7.0V(4) with Respect to Ground DC CHARACTERISTICS: READ OPERATION OC < Ta < +70C, Voc = 5V + 10%, TTL Inputs Symbol Parameter Notes Min Max | Unit Test Condition Tn Input Load Current 1 pA | Vin = 5.5V lLo Output Leakage Current 10 BA | Vout = 5.5V Ipp Vpp Load Current Read 10 HLA | Vpp = 0 to Voc, PGM = Viy Isp Voc Standby | Switching] 2 45 mA | CS = Vin, f = 25 MHz Stable 2 30 | mA|CS = Vin loc Vcc Active Current 1,3,7 125 | mA |CS = Vi_,f = 25 MHz, lovt = OMA Vit Input Low Voltage 4 -0.5 0.8 v Vin Input High Voltage 2.0 Voco+1}] V VoL Output Low Voltage 0.45 V |lot = 2.1mA Vou Output High Voltage 5 Voc 0.8 V jlon = 100 pA 2.4 V | low = 400 pA los Output Short Circuit 6 100 | mA NOTES: 1. Maximum current is with outputs unloaded. 2. log standby current assumes no output loading, i.e., oy = lol = 0 mA. 3. Ic is the sum of current through Vcoc3 + Voca and does not include the current through Vcc; and Voce. Voc1 and Vcc2 supply power to the output drivers. Voc3 and Vcc, supply power to the rest of the device.) 4. Minimum DC voltage on input and output pins is 0.5V. During transitions, this level may undershoot to 2.0V for periods less than 20 ns. 5. Maximum DC voltage on input and output pins is Voc + 0.5V which may overshoot to Vcc + 2.0V for periods less than 20 ns. 6. One output shorted for no more than one second. log is sampled but not 100% tested. 7. Iog max measured with a 10.11 wF capacitor between Vcc and Vgs. 8. This specification defines commercial product operating temperatures. 4-48intel 27960KX PRELIMINARY EXPLANATION OF AC SYMBOLS The fifth character represents the signal level indi- cated for the fourth character. The list below shows The nomenclature used for timing parameters are as character representations. per IEEE STD 662-1980 IEEE Standard Terminology A: Address R: Reset for Semiconductor Memory. B: BLAST Q: Data Each timing symbol has five characters. The first is r rock High Level s: cs always a t (for time). The second character repre- - Logic Ig eve t ime sents a signal name, e.g., (CLK, ALE, etc.). The third L: ALE/Logic Low Level Vv: Valid character represents the signals level (high or low) -P: ~-Vpp Programming Voltage 2: Tri-state level for the signal indicated by the second character. The | X: No longer a valid driven logic level fourth character represents a signal name.at which a transition occurs marking the end of the time interval being specified. AC CHARACTERISTICS: READ OPERATION 0C < Ta < +70C, Vcc = 5V 410% 27960K2-25 | 27960K1-20 | 27960K2-20 | 27960K1-16 Versions 25 MHz 20 MHz- 20 MHz 16MHZ | 2 Wait States | 1 Wait State | 2 Wait States | 1 Wait State No| Symbol Characteristic Notes| Min | Max | Min | Max | Min | Max | Min | Max 1 |tavcgH | Address Valid to : CLK High CLKO}| 12 18 10 15 ns 2 |taviy | Address Valid : to ALE High 10 10 10 10 ns nl 3 |tiutH |ALE Low to ALE High 12 12 12 12 ns 4 |tuyax | ALE High to Address Invalid 8 8 8 8 ns 5 |tsvcy | CS Valid to CLK High 1,5 5 8 7 8 ns 6 |teyHsx | CLK High to CS 2 0 0 0 0 ns Invatid 7 |tcHay | CLK High to Data Valid 7 33 43 38 45 | ns tcHax | CLK High to Data Invalid 7 7 7 7 ns 9 |tcHaz | CLK High to Data High-Z| 6 30 35 35 35 | ns 10 |tgyvcH | BLAST Valid to CLK High 15 15 15 15 ns 41 |tcHpx | CLK High to BLAST invalid 3 5 35 5 45 5 45 5 45 ns NOTES: 1. Valid signal level is meant to be either a logic high or logic iow. 2. tcynsxThe subscript N represents the number of wait states for this parameter. CS can be de-asserted (high) after the number of wait states (N) has expired. The EPROM will continue to burst out data for the current cycle. 3. BLAST must be returned high before the next rising clock edge. 4. The sum of tcHav + tavcn + NCLK will not equal actual tavay if independent test conditions are used to obtain taycn and tcHay (N = number of wait states). 5. CS must be deasserted after every burst read (see Figure 7). 6. Sampled, not 100% tested. The transition is measured +500 mV from steady state voitage. 7. For capacitive loads above 120 pF, tcuay can be derated by 1 ns/20 pF. 4-4927960KX PRELIMINARY 290237 -13 WT XC LL 04 XX X05K X KOK XX 07 { 04 BY KLAN 1@ } ws , ; 11" Om = a 8 IZ Is 5 8 Figure 7. 27960KX 1 WS AC Read Waveforms 4-50intel . 27960KX PRELIMINARY AC CONDITIONS OF TEST Input Rise and Fall Times (10% t0 90%)... 6. cece cece eee ee 4ns Input Pulse Levels ................46 0.45V to 2.4V Input Timing Reference Level................ 1.5V Output Timing Reference Level ...... 0.8V and 2.0V Table 2. Mode Table MODE CS | PGM | BLAST | ALE | RESET | Ag Veep | Voc | OUTPUT Read Vir | Vin Vin | Vip) Vin | Xt4) Veco | Voc Dout Standby (6) Vin X X X Vin X Voc) | Voc | . High Z Program Vir} Viv Vin | Vin@ | Vin Xx (3) (3) Din Program Verify Vir} Vin Vin") Vin Vin x (3) (3) Dout Program Inhibit Vin xX xX x Vin xX (3) (3) High Z 1D Byte 0: Manufacturer | Vic | Vin Vin) | Vip?) Vin Vio) | Vcc | Voc 89H ID Byte 1: Part (27960) Vir | Vin Vin) | Vip) Vin Vip(?) Voc Voc EOH ID Byte 2: KX Vir | Vin Vin) | Vip Vin Vip) Voc Voc 00B ID Byte 3: 1 Wait-State Vic | Vin Vin 1 Vin) Vin Vin) | Voc Voc 01B 2 Wait-States 10B Reset Xx Xx X xX Vit Xx Voc | Voc High Z NOTES: 1. Vix until data terminated at which time BLAST must go to VL. 2. Need to toggle from Vi} to Vi_ to Vizq to latch address. 3. See DC Programming Characteristics for Voc, Vip and Vpp voltages. 4. X can be Vi, or Vin. : / i 5. Vpp = Vcc to meet standby current specification. Vog > Vpp > Vj, will cause a slight increase in standby current. 6. The device must be in the idle state (by asserting RESET or using BLAST) before going into standby. 4-51intel. 27960KX PRELIMINARY CAPACITANCE(1) Ty = 25C, # = 1.0 MHz Symbol Parameter Typ Max Unit Condition Cin Input Capacitance 4 6 pF Vin =O0V Cout Output Capacitance 12 15 pF Vout =0V Cvypp Vpp Capacitance 40 45 pF Vin =OV NOTE: 1. Sampled, not 100% tested AC INPUT/OUTPUT REFERENCE WAVEFORMS AC TESTING LOAD CIRCUIT Vou 2.1V INPUT Vou SEE 7802 TIMING PARAMETER UNDER y TEST OH CL=120 pF M oureur L 7 290237-~15 Vou For tcHaz CL = 5 pF and Ry = 4050 " -990237-14 C,_ includes jig capacitance AC test inputs are driven at 2.4V (Vou) for a logic 1 and 0.45V (VQ) for a logic 0. Input timing begins at 1.5V.. Output timing ends at Vjq (2.0V) and Vj, (0.8V) Input Rise and fall times (10% to 90%) < 4.0 ns CLOCK CHARACTERISTICS Versions 25 MHz 20 MHz 16 MHz Units Symbol Parameter Min Max Min Max Min Max CLK Period 40 50 62.5 ns Ts Rise Time 10 10 10 ns T4 Fall Time 10 10 10 ns To Low Time 7 8 11 ns T3 High Time 7 8 11 ns Max CLK Rise Time during Programming is 100 ns CLOCK WAVEFORM CLK f+ te 290237-16 4-52intel. 27960KX PRELIMINARY Program/Program Verify Initially, and after each erasure, all bits of the EPROM are in the 1s state. Data is introduced by selectively programming 0's into the desired bit locations. Although only 0s can be programmed, both 1s and 0s can be present in the data word. Ultraviolet erasure is the only way to change Q's to 1's. Program mode is entered when Vpp is raised to 12.75V. Program/Verify operation is synchronous with the clock and can only be initiated following an idle state. Program and Program Verify take place in 3 clock cycles. In the first clock cycle, addresses and data are input and programming occurs. Pro- gram Verify follows in the second clock cycle and the third clock cycle terminates synchronous Pro- gram/Verify operation, returning the state machine to the idle state with outputs at high impedance. As in the Read mode, AzAi point to a four byte block in the memory array. During Programming the internal address increment circuitry is disabled and the programmer must supply Ag and A, to point to an individual byte within the four byte block that is to be programmed. Only one byte is programmed in each 3 cycle program/Verify sequence. Program inhibit Program Inhibit mode allows parallel programming and verification of multiple devices with different data. With Vpp at 12.75V, a Program/Verify se- quence is initiated for any device that receives a val- id ALE pulse and rising clock edge while CS is as- serted. A PGM pulse programs data in the first cycle of the sequence and data for Program Verify is out- put in the second cycle. The Program/Verify se- quence is inhibited on any devices for which CS is not asserted during the first (ALE) cycle. Data will not be programmed and the outputs will remain in their high impedance state. inteligent Identifier Mode The devices manufacturer, product type, and con- figuration are stored in a four byte block that can be _ synchronous accessed by using the inteligent identifier mode. The programmer can verify the device identifier and choose the programming algorithm that corresponds to the Intel 27960KX. The intgligent Identifier can also be used to verify that the product is configured with the desired Read mode options for wait states. Intgligent Identifier mode is entered when Ag (pin 32) is raised to its high voltage (V}) level. The inter- nal state machine is then set for intgligent Identifier Read operation. Reading the Identifier is similar to a Read operation 6n a on wait state configured prod- uct. Up to four bytes can be read in a single burst access. intgligent Identifier read is terminated by a T input, returning the state ma- chine to the idle state with outputs at high imped- ance. The four byte block code for the intgligent Identifier code is located at address 00H through 03H and is encoded as follows: MEANING (A1, Ao} DATA Intel ID Byte 00 89h -27960 Byte 01 E0h KX Byte 10 00b 1 wait state Byte 11 O1b 2 wait states Byte 11 10b RESET MODE Due to the synchronous nature of the 27960KX, the various operating modes must be initiated from a known idle state. During normal operation, the inter- nal state machine returns to an idle state at the ter- mination of a bus access (after BLAST is asserted). During initial device power up, the state machine is in an indeterminant state. The reset mode is provid- _@d to force operation in to the idle state. Reset mode 4-53 is entered when the RESET pin is asserted. Output pins are asynchronously set to the high impedance state and address latches are put into the flow through mode. A reset is successfully completed and the state machine set in an idle state in the cycle after RESET has been asserted for a minimum of 10 clock cycles and deasserted for five clock cy- cles.intel. 27960KX PRELIMINARY ADDRESS = FIRST LOCATION Vpp = 12.75 Vor = 6.25V PROGRAM ONE 100 ys PULSE INCREMENT X INCREMENT ADDRESS DEVICE FAILED DEVICE PASSED 290237-17 Figure 8. Quick-Pulse Programming Algorithm 4-54intel. 27960KX PRELIMINARY QUICK-PULSE PROGRAMMING - ALGORITHM The Quick-Pulse Programming algorithm programs Intels 27960KX. Developed to substantially reduce programming throughput time, this algorithm allows optimized equipment to program a 27960KX in un- der 17 seconds. Actual programming time depends on the programmer used. The Quick-Pulse Programming algorithm uses a 100 js pulse followed by a byte verfication to deter- mine when the. addressed byte is correctly pro- grammed. The algorithm terminates if 25 100us pulses fail to program a byte. Figure 8 shows the 27960KX Quick-Pulse Programming algorithm flow- chart. The entire program-pulse, byte-verify sequence is performed with Vcc = 6.25V and Vpp = 12.75V. The programming equipment must establish Vcc be- fore applying voltages to any other pins. When pro- gramming is complete, alt bytes should be compared to the original data with Voc = 5.0V and Vpp = 12.75V. D.C. PROGRAMMING CHARACTERISTICS T, = 25C +5C Symbol Parameter Notes Min Max Unit | Test Condition lu Input Load Current 10 PA | Vin = Vin or Vir lec Voc Program Current 1 125 mA | CS=Vi Ipp Vpp Program Current 1 50 mA | CS = Vit VIL input Low Voltage ~ 0.5 0.8 Vv Vin Input High Voltage 2.0 Voct+ 0.5 Vv VoL Output Low Voltage (Verify) 0.40 Vv | top = 2.1mA Vou Output High Voitage (Verify) Voc 0.8 , Vv lon = 400 pA Vio Ag inteligent Identifier Voltage 11.6 12.5 v Voc Supply Voltage (Program) 6.0 6.5 Vv Vpp Program Voltage 12.5 13.0 Vv NOTES: 1. The maximum current value is with outputs unioaded. 2. Vcc must be applied simultaneously or before Vpp and remove simultaneously or after Vpp. 3. During programming clock levels are Vjy and VL. 4-55intel 27960KX PRELIMINARY AC PROGRAMMING, RESET AND ID CHARACTERISTICS T, = 25C + 5C No Symbol Parameter Notes Min Max Units 1 tavPL Address Valid to PGM Low 2 ps 2 tCHAX CLK High to Address Invalid 50 ns 3 tLLCH ALE Low to CLK High 1 50 ns 4 tCHLH CLK High to ALE High 2 50 ns 5 tsvCH CS Valid to CLK High 50 ns 6 tcHsx CLK High to CS Invatid 3 ns 7 tcHav CLK High to Dour Valid 100 ns 8 tcHax CLK High to Dour Invalid 0 ns 9 tBVCH BLAST Valid to CLK High 50 ns 10 tcHBx CLK High to BLAST Invalid 4 50 ns 11 toveL DATA Valid to PGM Low 2 ps 12 tPLPH PGM Program Pulse Width 95 105 ps 13 tpHax PGM High to Din Invalid 2 ps 14 tcLeL CLK Low to PGM Low 50 ns 15 tazcH Din in Tri-State to CLK High 2 ps 16 tycs Voc Program Voltage to CLK High 2 pS 17 tyes Vpp Program Voltage to CLK High 7 2 ps 18 tagHCH Ag Vip Voltage to CLK High 2 ys 19 tCHAgX CLK High to AQ not Vip Voltage 2 ps 20 tRVCH RESET Valid to CLK High 6 50 ns 21 tCHCL CLK High to CLK Low 5 100 ns 22 tCLCH CLK Low to CLK High 5 100 ns NOTES: . tt CS is low, ALE can go low no sooner than the falling edge of the previous CLK. . ALE must return high prior to the next rising edge of clock. . CS must remain low until after the rising edge CLK1. . BLAST must return high prior to the next rising edge of CLK. . Max CLK rise/fall time is 100 ns. . RESET must be held low for 10 cycles and high for 5 cycles before performing a read. . Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. NOOewon = 4-56PRELIMINARY 27960KX intel. 8t-LEz062 1@ Wod Hl, W Hla p 1 Mm + HI, viva NIO VLV0 av W t ssaudqv yaqv 0 SsaudaVv OW a, UH | 5 , Figure 9. 27960KX Programming Waveforms 4-5727960KX PRELIMINARY ADDR DATA a w pod} OF _ 290237-19 Figure 10. 27960KX RESET and ID Waveforms 4-58