4
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
Flash Write Operation Status Detection
The SST34HF16x1C/D/S provide one hardware and two
software m eans to d etect th e completion of a Write (Pro-
gram or Erase) cycle, in order to optimize the system
Write cycle time. The hardware detection uses the
Ready/Busy# (RY/BY#) pin. The software detection
includes two status bits: Data# Polling (DQ7) and Toggle
Bit (DQ6). The End-of-Write detection mode is enabled
after the rising edge of WE#, which initiates the internal
Prog ram or Erase ope ra tion.
The actual completion of the nonvolatile write is asynchro-
nous with the system; theref ore, either a Ready /B usy# (R Y/
BY#), Data# P olling (DQ7) or Toggle Bit (DQ6) read ma y be
simultan eous with the comp letion o f the Wri te cy cle. If this
occurs, the system may possibly get an erroneous result,
i.e., valid data may appear to conflict with either DQ7 or
DQ6. In order to prevent spurious rejection, if an erroneous
result occurs, the software routine should include a loop to
read the accessed location an additional two (2) times. If
both reads are valid, then the device has completed the
Write cy cle, ot herwi se the reje ction i s va lid.
Ready/ Busy# (RY/BY#)
The SST34HF16x1C/D/S include a Ready/Busy# (RY/
BY#) output signal. R Y/BY# is an open drain output pin that
indicates whether an Erase or Program operation is in
progress. S ince RY/BY# is an open drain output, it allows
several devices to be tied in parallel to VDD via an exter nal
pull-up resistor. After the rising edge of the final WE# pulse
in the command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an
Erase or P rogram opera tion i s in pr ogress. Wh en RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
Byt e/W ord (CI OF)
The device includes a CIOF pin to control whether the
de vi ce da ta I /O pi ns oper at e x8 o r x16. If the CIOF pin is at
logic “1” (VIH) the device is in x16 data configuration: all
data I/0 pi ns DQ0-DQ15 are active and con t rol le d by BEF#
and OE#.
If the CIOF pin is at logi c “0”, the device is in x8 data config-
uration: only data I/O pins DQ0-DQ7 are active and con-
trolled by BEF# and OE#. The remaining data pins DQ8-
DQ14 are at Hi-Z, while pin DQ15 is used as the address
input A-1 for the Least Significant Bit of the address bus.
Flash Data# Polling (DQ7)
When the de vices are in an internal Program operation, any
attempt to read DQ7 will produce the complement of the
true da ta. Once the Program operation i s completed, DQ7
will produce true data. During internal Erase operation, an y
attempt to read DQ7 will produce a ‘0’. Once the internal
Erase operation is completed, DQ 7 wi ll produce a ‘1’. The
Data# Polling is valid after the rising edge of f ourth WE# (or
BEF#) p u lse for Program ope ration . For Sector -, B lock-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or BEF#) pulse . See Figure 11 for Data# P oll-
ing (DQ7) timing diagram and Figure 23 f or a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 wil l pr od uc e a lt ernat in g “1 ” s
and “0”s, i.e., togg li ng between 1 and 0. Wh en t he inte rnal
Program or Erase op eration is compl eted, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is v alid after the rising edge of the f ourth
WE# (or BEF#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the
rising edge of sixth WE# (or BEF#) pulse. DQ6 w ill be set to
“1” if a Read operation is attempted on an Erase-sus-
pended Se ctor/Blo ck. If Program ope ration is initiate d in a
sector/b loc k not selected in Erase-Suspend mode, DQ6 will
toggle.
An addi tio na l To ggl e B i t is available on DQ 2, which can be
used in conjunction with DQ6 to ch eck w het he r a pa rticular
sector is being actively erased or erase-suspended. Tab le 1
shows detailed status bit inf ormation. The Toggle Bit (DQ2)
is valid after the rising edge of the last WE# (or BEF#)
pulse of a Write operation. See Figure 12 for Toggle Bit tim-
ing diag ram an d Figu re 23 f or a fl owc hart.
Note: DQ7, DQ6, and DQ2 require a valid address when reading
status inf ormation.
TABLE 1: WRITE OPERATION STATUS
Status DQ7DQ6DQ2RY/BY#
Normal
Operation Standard
Program DQ7# Toggle No Toggle 0
Standard
Erase 0 Toggle Toggle 0
Erase-
Suspend
Mode
Read From
Erase
Suspended
Sector/Block
1 1 Toggle 1
Read From
Non-Erase
Suspended
Sector/Block
Data Data Data 1
Program DQ7# Toggle N/A 0
T1.0 1252