©2004 Silicon Storage T echnology, Inc.
S71252-00-000 3/04
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation.
CSF and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Advance Information
FEATURES:
Flash Organization: 1M x16 or 2M x8
Dual-Bank Architecture for Concurrent
Read/W rite Ope rat ion
16 Mbit: 12 Mbit + 4 Mbit
(P)SRAM Organization:
2 Mbit: 128K x16 or 256K x8
4 Mbit: 256K x16 or 512K x8
8 Mbit: 512K x16 or 1024K x8
Single 2.7-3.3V Read and Write Operations
Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
Low Power Consumption:
Active Current: 25 mA (typical)
Standby Current: 20 µA (typical)
Hardware Sector Protection (WP#)
Protects 4 outer most sectors (4 KWord) in the
larger bank by holding WP# low and unprotects
by holding WP# high
Hardware Reset Pin (RST#)
Resets the internal state machine to reading
data array
Byte Selection for Flash (CIOF pin)
Selects 8-bit or 16-bit mode
Sector-Erase Capability
Uniform 2 KWord sectors
Block-Erase Capability
Uniform 32 KWord blocks
Read Access Time
Flash: 70 ns
(P)SRAM: 70 ns
Erase-Suspend / Erase-Resume Capabilities
Security ID Feature
SST: 128 bits
User: 128 bits
Latched Address and Data
Fast Erase and Word-/Byte-Program (typical):
Sector-Erase Time: 18 ms
Block-Erase Time: 18 ms
Chip-Erase Time: 35 ms
Word-Program Time: 7 µs
Automatic Write Timing
Internal VPP Generation
End-of-Write Detection
Toggle Bit
Data# Polling
Ready/Busy# pin
CMOS I/O Compatibility
JEDEC Standard Command Set
Packages Available
56-ball LFBGA (8mm x 10mm)
62-ball LFBGA (8mm x 10mm)
PRODUCT DESCRIPTION
The SST34HF16x1C/D/S ComboMemory devices inte-
grate either a 1M x16 or 2M x8 CMOS flash memory bank
with eit her a 12 8K x 16/ 256K x8, 25 6K x 16/ 512 x8, or 512 K
x16/1024K x8 CMOS SRAM or pseud o SRAM (PSRAM)
memory bank in a multi-chip package (MCP). These
devices are fabricated using SST’s proprietary, high-perfor-
mance CMOS SuperFlash technology incorporating the
split-gate cell design and thick-oxide tunneling injector to
attain better reliability and manufacturability compared with
alternate approaches. The SST34HF16x1C/D/S devices
are ideal for applications such as cellular phones, GPS
devices, PDAs, and other portable electronic devices in a
low power and small form f actor system.
The SST34HF16x1C/D/S feature dual flash memory bank
arch itecture a llowi ng f or concurr ent oper ations between the
two flash memory banks and the (P)SRAM. The devices
can read data from either bank while an Erase or Program
operation is in progr ess in the opposite bank. The two flash
memory banks are partitioned into 12 Mbit and 4 Mbit with
bottom sector protection options for storing boot code , pro-
gram code, configuration/parameter data and user data.
The S upe r Flas h te ch no logy pr ovid es fi xed Erase an d P r o-
gram times, in depen dent o f the num ber of Erase/ Pro gram
cycles that have occurred. Therefore, the system software
or hardware does not ha v e to be modified or de-rated as is
nec essary with al tern ativ e flas h techno logies , whose E rase
and Pr ogram tim es inc rease with accumul ated Erase/Pr o-
gram cycles. The SST34HF16x1C/D/S devices offer a
guaranteed endurance of 10,000 cycles. Data retention is
rated at greater than 100 years. With high performance
Word-Program, the flash memory banks provide a typical
Word-Program time of 7 µsec. The entire flash memory
bank can be erased and progr ammed w ord-b y-word in typ-
icall y 4 secon ds for the SS T34HF16x1C /D/S, w hen usin g
interface features such as Toggle Bit, Data# Polling, or RY/
BY# to indicate the completion of Program operation. To
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
SST34HF168116Mb CSF (x8/x16) + 2/4/8 Mb SRAM (x16) MCP ComboMemory
2
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
protect against inadvertent flash write, the
SST34HF16x1C/D/S devices contain on-chip hardware
and softw are data protection schemes.
The flas h and (P)SRAM operate as two independent mem-
or y banks wi th respec tive bank enable signa ls. The mem-
ory bank selection is done b y two bank enab le signals. The
(P)SRAM bank enable signals, BES1# and BES2, select
the (P)SRAM bank (BES1# and BES2 are NC for
SST34HF1601C). The flash memory bank enable signal,
BEF#, has to be used with Softw are Data Protection (SDP)
command sequence when cont rolling the Erase and Pro-
gram operations in the flash memory bank. The memory
banks are superimposed in the same memory address
space where they share common address lines, data lines,
WE# and OE# which minimize power consumption and
area.
Designed, manufactured, and tested for applications requir-
ing low power and small for m factor, the SST34HF16x1C/
D/S are offered in both commercial and e xtended temper a-
tures and a small footprint package to meet board space
constraint requirements. See Figures 3 and 4 for pin
assignments.
Device Operatio n
The SST34HF16x1C/D/S uses BES1#, BES2 and BEF#
to control operation of either the flash or the (P)SRAM
memory bank. When BEF# is low, the flash bank is acti-
v ated f o r Read , Prog ram or Era se oper atio n. When BES1#
is low , and BES2 is high the (P)SRAM is activ ated f or Read
and Write operation. BEF# and BES1# cannot be at low
le v el, an d BES2 can not be at high le v el at th e same tim e. If
all bank enable signals are asserted, bus contention
will result and the device may suffer permane nt dam-
age. All address , data, and control lines ar e shared by flash
and (P)SRAM memory banks which minimizes power con-
sumption and loading. The device goes into standby when
BEF# and BES1# bank enables are raised to VIHC (Log ic
High) or when BEF# is high and BES2 is low .
Concurrent Read/Write Operation
Dual bank architecture of SST34HF16x1C/D/S devices
allows the Concurrent Read/Write operation whereby the
user can r ead from one ban k while programm ing or eras-
ing in the other bank. This operation can be used when the
user n eeds to read syste m cod e in one ba nk whil e upda t-
ing data in the other bank. See Figures 1 and 2 for dual-
bank memory organization.
Note: For the purposes of this tabl e, write means to Block-, Sector,
or Chip-Erase, or Word-/Byte-Program as applicable to the
appropriate bank.
Flash Read Operation
The Read operation of the SST34HF16x1C/D/S is con-
trolle d by BEF# and OE#, bo th have to be low for the sys-
tem to obtain data from the outputs. BEF# is used for
device selection. When BEF# is high, the chip is dese-
lected and only standby power is consumed. OE# is the
output control and is used to gate data from the output pins.
The data b us is in high impedance state when either BEF#
or OE# is high. Refer to the Read cycle timing diagram for
further details (Figure 8).
CONCURRENT READ/WRITE STATES
Flash
(P)SRAMBank 1 Bank 2
Read Write No Operation
Write Read No Operation
Write No Op eration Read
No Operation Write Read
Write No Op eration Write
No Operation Write Write
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
3
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
Flash Word-/Byte-Program Operation
These devices are programmed on a word-by-word or
byte-by-by te basis depending on the state of the CIOF pin.
Before programming, one must ensure that the sector
which is being prog rammed is fully erased.
The Progr am operation is accomplished in three steps:
1. Software Data Protection is initiated using the
three-byte load sequence.
2. Word address and word data are loaded.
During the Word-Program operation, the
addresses are latched on the falling edge of either
BEF# or WE#, whichever occurs last. The data is
latch ed on t he r i si ng edg e of either BE F# or W E# ,
whichever occurs first.
3. The internal Program operation is initiated after
the r isin g ed ge o f th e fourth WE# or BE F#, wh ic h-
ever occurs first. The Program operation, once ini-
tiated, will be completed typically within 7 µs.
See Fi gures 9 and 10 for WE# and B E F # control led Pro-
gram operation timing diagrams and Figure 22 for flow-
charts. Dur ing th e Pro gram operatio n, the on ly valid rea ds
are Data# Polling and Toggle Bit. During the internal Pro-
gr am ope rat ion , the host is fr ee to p erform a ddit ion al t asks .
Any comman ds issued dur ing an inter nal Pro gram ope ra-
tion are ignored.
Flash Sector- (Block-) Erase Operation
These devices offer both Sector-Erase and Block-Erase
operations . These oper ations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis.
The sector architectur e is based on a unif orm sector size of
2 KWord. The Block-Erase mode is based on a uniform
block size of 32 KWord. The Sector -Erase operation is initi-
ated by executing a six-byte command sequence with a
Sector -Erase com mand (30 H) and s ector addr ess (S A) in
the last b us cycle. The Bloc k-Erase operation is initiated b y
executing a six-byte command sequence with Block-Erase
command (50H) and block address (BA) in the last bus
cycl e. The sec tor or block addr ess is latch ed on th e falling
edge of the sixth WE# pul se, whi le the co mmand (30 H or
50H) is latche d on t he r isin g edge of the sixth WE# p uls e.
The internal Erase operation begins after the sixth WE#
pulse. Any com mands is sued dur ing the Block- or Sec tor-
Erase operation are ignored except Erase-Suspend and
Erase-Resume. See Figures 14 and 15 for timing wave-
forms.
Flash Chip-Erase Operation
The SST3 4HF16x 1C/D/S provide a Chip-E rase operation ,
which allows the us er to erase all sec tors/blocks to the “1”
state. This is useful when the device must be quickly
erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
BEF#, whichever occur s first. During th e Erase ope ration,
the only valid read is Toggle Bits or Data# Polling. See
Table 7 for the command sequence, Figure 13 for timing
diagram, and Figure 26 for the flowchar t. Any commands
issued d uring t he Ch ip -Erase op e r at ion are ign o red . Wh en
WP# is low, any attempt to Chip-Erase will be ignored.
Flash Erase-Suspend/-Resume Operations
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memor y loca tion, or program dat a into any
sector /block that i s not sus pended for an Eras e operation .
The operation is e xecuted by issuing a one-byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode within 20 µs after
the Erase-Suspend command had been issued. Valid data
can be read from any sector or block that is not suspended
from an Erase operation. Reading at address location
within er ase-suspended sectors/blocks will output DQ2 tog-
gling and DQ6 at “1”. While in Erase-Suspend mode, a
Word-/Byte-Program operation is allowed except for the
sector or block selected for Erase-Suspend. To resume
Sector-Erase or Block-Erase operation which has been
suspended, the system must issue an Erase-Resume
command. The oper ation is ex ecuted b y issuing a one-byte
comm and se quence wi th Eras e Resum e comm and (3 0H)
at any address in the one-b yte sequence.
4
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
Flash Write Operation Status Detection
The SST34HF16x1C/D/S provide one hardware and two
software m eans to d etect th e completion of a Write (Pro-
gram or Erase) cycle, in order to optimize the system
Write cycle time. The hardware detection uses the
Ready/Busy# (RY/BY#) pin. The software detection
includes two status bits: Data# Polling (DQ7) and Toggle
Bit (DQ6). The End-of-Write detection mode is enabled
after the rising edge of WE#, which initiates the internal
Prog ram or Erase ope ra tion.
The actual completion of the nonvolatile write is asynchro-
nous with the system; theref ore, either a Ready /B usy# (R Y/
BY#), Data# P olling (DQ7) or Toggle Bit (DQ6) read ma y be
simultan eous with the comp letion o f the Wri te cy cle. If this
occurs, the system may possibly get an erroneous result,
i.e., valid data may appear to conflict with either DQ7 or
DQ6. In order to prevent spurious rejection, if an erroneous
result occurs, the software routine should include a loop to
read the accessed location an additional two (2) times. If
both reads are valid, then the device has completed the
Write cy cle, ot herwi se the reje ction i s va lid.
Ready/ Busy# (RY/BY#)
The SST34HF16x1C/D/S include a Ready/Busy# (RY/
BY#) output signal. R Y/BY# is an open drain output pin that
indicates whether an Erase or Program operation is in
progress. S ince RY/BY# is an open drain output, it allows
several devices to be tied in parallel to VDD via an exter nal
pull-up resistor. After the rising edge of the final WE# pulse
in the command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an
Erase or P rogram opera tion i s in pr ogress. Wh en RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
Byt e/W ord (CI OF)
The device includes a CIOF pin to control whether the
de vi ce da ta I /O pi ns oper at e x8 o r x16. If the CIOF pin is at
logic “1” (VIH) the device is in x16 data configuration: all
data I/0 pi ns DQ0-DQ15 are active and con t rol le d by BEF#
and OE#.
If the CIOF pin is at logi c “0”, the device is in x8 data config-
uration: only data I/O pins DQ0-DQ7 are active and con-
trolled by BEF# and OE#. The remaining data pins DQ8-
DQ14 are at Hi-Z, while pin DQ15 is used as the address
input A-1 for the Least Significant Bit of the address bus.
Flash Data# Polling (DQ7)
When the de vices are in an internal Program operation, any
attempt to read DQ7 will produce the complement of the
true da ta. Once the Program operation i s completed, DQ7
will produce true data. During internal Erase operation, an y
attempt to read DQ7 will produce a ‘0’. Once the internal
Erase operation is completed, DQ 7 wi ll produce a ‘1’. The
Data# Polling is valid after the rising edge of f ourth WE# (or
BEF#) p u lse for Program ope ration . For Sector -, B lock-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or BEF#) pulse . See Figure 11 for Data# P oll-
ing (DQ7) timing diagram and Figure 23 f or a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 wil l pr od uc e a lt ernat in g “1 s
and “0”s, i.e., togg li ng between 1 and 0. Wh en t he inte rnal
Program or Erase op eration is compl eted, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is v alid after the rising edge of the f ourth
WE# (or BEF#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the
rising edge of sixth WE# (or BEF#) pulse. DQ6 w ill be set to
“1” if a Read operation is attempted on an Erase-sus-
pended Se ctor/Blo ck. If Program ope ration is initiate d in a
sector/b loc k not selected in Erase-Suspend mode, DQ6 will
toggle.
An addi tio na l To ggl e B i t is available on DQ 2, which can be
used in conjunction with DQ6 to ch eck w het he r a pa rticular
sector is being actively erased or erase-suspended. Tab le 1
shows detailed status bit inf ormation. The Toggle Bit (DQ2)
is valid after the rising edge of the last WE# (or BEF#)
pulse of a Write operation. See Figure 12 for Toggle Bit tim-
ing diag ram an d Figu re 23 f or a fl owc hart.
Note: DQ7, DQ6, and DQ2 require a valid address when reading
status inf ormation.
TABLE 1: WRITE OPERATION STATUS
Status DQ7DQ6DQ2RY/BY#
Normal
Operation Standard
Program DQ7# Toggle No Toggle 0
Standard
Erase 0 Toggle Toggle 0
Erase-
Suspend
Mode
Read From
Erase
Suspended
Sector/Block
1 1 Toggle 1
Read From
Non-Erase
Suspended
Sector/Block
Data Data Data 1
Program DQ7# Toggle N/A 0
T1.0 1252
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
5
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
Data Protection
The SST3 4HF1 6x 1C/D/S provide both har d ware an d so ft-
ware features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit M ode: Forcing OE# low, BEF# high, or WE#
high will in hi bit t he Write operation . T hi s prevents inadvert-
ent w rites durin g pow er-u p or po wer- dow n.
Hardware Block Protection
The SST34HF16x1C/D/S pr ovide a hardware b lock pr otec-
tion which protects the outermost 8 KWord in Bank 1. The
block is protected when WP# is held low. See Figures 1
and 2 f o r Bloc k-Pr otec tion lo cation.
A user can disable block protection by driving WP# high
thus allowing erase or program of data into the protected
sectors. WP# must be held high prior to issuing the write
command and remain stable until after the entire Write
operation has completed.
Hardware Reset (RST# )
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode (see Figure 19). When no internal
Program/Erase operation is in progress, a minimum period
of TRHR is required after RST# is driven high before a valid
Read can take place (see Figu re 18).
The Erase oper ation that has been interrupted needs to be
reinitiated after the dev ice resumes normal operation mode
to ensure data integrity. See Figures 1 8 and 19 for timing
diagrams.
Software Data Protection (SDP)
The SST34HF16x1C/D/S provide the JEDEC standard
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program opera-
tion req ui res th e in cl us i on o f the th re e-byte se qu enc e. Th e
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
po w e r-d own. Any Er as e ope r at i on req ui re s th e in cl usi o n of
six-byte sequence. The SST34HF16x1C/D/S are shipped
with the Software Data Protection permanently enabled.
See Table 7 f or the spec ific softw are command codes. Dur-
ing SDP command sequence, inv alid commands will abort
the device to Read mode within TRC. The contents of DQ15-
DQ8 are “Don’t Care” during any SDP command
sequence.
Security ID
The SST34HF16x1C/D/S devices offer a 256-bit Security
ID spac e. The Secur e ID spa ce is divid ed into two 128-bi t
segments—one factory programmed segment and one
user programmed segment. The first segment is pro-
grammed and locked at SST with a unique, 128-bit num-
ber. The user segment is left un-programmed for the
customer to program as desired. To program the user seg-
ment of the S ecur ity ID, the user must use the Sec ur ity ID
Word-Program command. End-of-Write status is checked
by reading the toggle bits. Data# Polling is not used for
Security ID End-of-Write detection. Once programming is
complete , the Sec ID should be locked using the User-Sec-
ID-Program-Lock-Out. This disables any future corruption
of this space. Note that regardless of whether or not the
Sec ID is locked, neither Sec ID segment can be erased.
The Secure ID space can be queried by ex ecuting a three-
byte command sequence with Query-Sec-ID command
(88H) at ad dress 5555H in th e last byte sequenc e. To exit
this mode, the Exit-Sec-ID command should be executed.
Refer to Tab le 7 for more details.
6
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
Product Identifica tion
The Product Identification mode identifies the de vice as the
SST34HF16x1C/D/S and manufacturer as SST. This
mode may be accessed by software operations only. The
hardware de vice ID Read operation, which is typically used
by programmers cannot be used on this de vice because of
the shar ed lines be tween flash and (P)SRA M in the mult i-
chip package. There fore, appl icatio n of high volt age to pi n
A9 may damage this device. Users may use the software
Product Identification operation to identify the part (i.e.,
using t he device I D) whe n usi ng mult ip le ma nufact urers in
the same socket. For details, see Tables 4 and 7 for soft-
ware operation, Figure 16 for the Software ID Entry and
Read timing diagram and Figure 24 for the ID Entry com-
mand sequence flowchart.
Note: BK = Bank Address (A19-A18)
Product Identification Mode Exit
In order to return to the standard Read mode, the Software
Produc t Ident ificati on mode must be exited. Exit is acco m-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command ma y also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit
command is ignored during an internal Program or Erase
operatio n. See Ta ble 7 for software co mmand code s, Fig-
ure 17 f or timing wav ef orm and Figure 24 f or a flowchart.
(P)SRAM Operation
With BES1# low, BES2 and BEF# high, the
SST34HF16x1C/D/S operate as either 128K x16, 256K
x16, or 5 12 K x1 6 CMOS (P)S RA M, wi th f ul ly s ta tic ope ra-
tion requiring no external clocks or timing strobes. The
SST34HF16x1C/D/S (P)SRAM is mapped into the first 512
KWord address space. When BES1#, BEF # are high an d
BES2 is low, all memory banks are deselected and the
device enters standby. Read and Write cycle times are
equal. The control si gnals UBS# and LBS# provide access
to the upper data byte and lower data byte (UBS# and
LBS# si gna ls ar e NC for SST341 6x 1S pa rts) . See Table 4
f or x16 (P)S RAM Read and Write data byte contr ol modes
of operation. See Table 5 for x8 SRAM Read and Write
data byte control modes of operation.
(P)SRAM Read
The (P)SRAM Read operatio n of the SST34HF16x1C/D/S
is cont r olled by OE # an d B ES1# , bo th h ave to be low with
WE# and BES2 high f or the system to obtain data from the
outputs. BES1# and BES2 are used for (P)SRAM bank
selection. OE# is the output control and is used to gate
data from the output pins. The data bus is in high imped-
ance state when OE# is high. Refer to the Read cycle tim-
ing diag ram, Figur e 5, f or further det ails .
(P)SRAM Write
The (P)SRAM Write operation of the SST34HF16x1C/D/S
is controlled by WE# and BES1#, both have to be low,
BES2 must be high for the system to write to the (P)SRAM.
Duri ng the Word-Writ e operation, the ad dresses and data
are referenced to the rising edge of either BES1#, WE#, or
the falling edge of BES2 whichever occurs first. The write
time is measured from the last falling edge of BES#1 or
WE# or the r ising ed ge of BES2 to th e first ris ing edge of
BES1#, or WE# or the falling e dge of BES2. R efer to the
Write cycle timing diagrams, Figures 6 and 7, for further
details.
TABLE 2: PRODUCT IDENTIFICATION
ADDRESS DATA
Manufacturer’s ID BK000 0H 00BFH
Device ID
SST34HF16x1C/D/S BK0001H 734BH
T2.0 1252
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
7
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
1252 B1.0
SuperFlash Memory
(Bank 1)
I/O Buffers
SuperFlash Memory
(Bank 2)
2 / 4 / 8 Mbit
SRAM or PSRAM
AMS1- A0
SA5
DQ15/A-1 - DQ0
Notes: 1. AMS = Most significant address
2. For LS package only: WE# = WEF# and/or WES#
OE# = OEF# and/or OES#
3. For SST34FH16x1S, LBS# and UBS# are No Connect.
4. For SST34HF1601C, BES1#, BES2, SA, LBS#, and UBS# are No Connect
5. Additional Address for x8 SRAM
Control
Logic
RST#
BEF#
WP#
LBS#3
UBS#3
WE#2
OE#2
BES1#4
BES24
RY/BY#
Address
Buffers
Address
Buffers
FUNCTIONAL BLOCK DIAGRAM
8
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 1: SST34HF16X1C/D, CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION
FFFFFH
F8000H Block 31
F7FFFH
F0000H Block 30
EFFFFH
E8000H Block 29
E7FFFH
E0000H Block 28
DFFFFH
D8000H Block 27
D7FFFH
D0000H Block 26
CFFFFH
C8000H Block 25
C7FFFH
C0000H Block 24
Bank 2
BFFFFH
B8000H Block 23
B7FFFH
B0000H Block 22
AFFFFH
A8000H Block 21
A7FFFH
A0000H Block 20
9FFFFH
98000H Block 19
97FFFH
90000H Block 18
8FFFFH
88000H Block 17
87FFFH
80000H Block 16
7FFFFH
78000H Block 15
77FFFH
70000H Block 14
6FFFFH
68000H Block 13
67FFFH
60000H Block 12
5FFFFH
58000H Block 11
57FFFH
50000H Block 10
4FFFFH
48000H Block 9
47FFFH
40000H Block 8
3FFFFH
38000H Block 7
37FFFH
30000H Block 6
2FFFFH
28000H Block 5
27FFFH
20000H Block 4
1FFFFH
18000H Block 3
17FFFH
10000H Block 2
0FFFFH
08000H Block 1
07FFFH
02000H
01FFFH
00000H
Block 0
Bank 1
Bottom Sector Protection; 32 KWord Blocks; 2 KWord Sectors
8 KWord Sector Protection
(4-2 KWord Sectors)
1252 F01.0
Note: The address input range in x16 mode (BYTE#=VIH) is A19-A0
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
9
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 2: SST34HF16X1S, 2M X8 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION
1FFFFFH
1F0000H Block 31
1EFFFFH
1E0000H Block 30
1DFFFFH
1D0000H Block 29
1CFFFFH
1C0000H Block 28
1BFFFFH
1B0000H Block 27
1AFFFFH
1A0000H Block 26
19FFFFH
190000H Block 25
18FFFFH
180000H Block 24
Bank 2
17FFFFH
170000H Block 23
16FFFFH
160000H Block 22
15FFFFH
150000H Block 21
14FFFFH
140000H Block 20
13FFFFH
130000H Block 19
12FFFFH
120000H Block 18
11FFFFH
110000H Block 17
10FFFFH
100000H Block 16
0FFFFFH
0F0000H Block 15
0EFFFFH
0E0000H Block 14
0DFFFFH
0D0000H Block 13
0CFFFFH
0C0000H Block 12
0BFFFFH
0B0000H Block 11
0AFFFFH
0A0000H Block 10
09FFFFH
090000H Block 9
08FFFFH
080000H Block 8
07FFFFH
070000H Block 7
06FFFFH
060000H Block 6
05FFFFH
050000H Block 5
04FFFFH
040000H Block 4
03FFFFH
030000H Block 3
02FFFFH
020000H Block 2
01FFFFH
010000H Block 1
00FFFFH
004000H
003FFFH
000000H
Block 0
Bank 1
Bottom Sector Protection; 64 KByte Blocks; 4 KByte Sectors
16 KByte Sector Protection
(4-4 KByte Sectors)
1252 F01b.0
Note: The address input range in x8 mode (BYTE#=VIL) is A19-A-1
10
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 3: PIN ASSIGNMENTS FOR 56- BALL LFBGA (8MM X 10MM)
FIGURE 4: PIN ASSIGNMENTS FOR 62- BALL LFBGA (8MM X 10MM)
1252 56-lfbga P1a.0
A11
A8
WE#
WP#
LBS#
A7
A15
A12
A19
BES2
RST#
UBS#
A6
A3
NC
A13
A9
NC
RY/BY#
A18
A5
A2
NC
A14
A10
A17
A4
A1
A16
NC
DQ6
DQ1
VSS
A0
CIOF
NOTE*
DQ13
DQ4
DQ3
DQ9
OE#
BEF#
VSS
DQ7
DQ12
VDDS
VDDF
DQ10
DQ0
BES1#
DQ14
DQ5
NC
DQ11
DQ2
DQ8
A B C D E F G H
8
7
6
5
4
3
2
1
TOP VIEW (balls facing down)
Note* = DQ15/A-1
1252 56-lfbga P1b.0
A11
A8
WE#
WP#
NC
A7
A15
A12
A19
BES2
RST#
NC
A6
A3
NC
A13
A9
NC
RY/BY#
A18
A5
A2
NC
A14
A10
A17
A4
A1
A16
SA
DQ6
DQ1
VSS
A0
CIOF
NOTE*
DQ13
DQ4
DQ3
DQ9
OE#
BEF#
VSS
DQ7
DQ12
VDDS
VDDF
DQ10
DQ0
BES1#
DQ14
DQ5
NC
DQ11
DQ2
DQ8
A B C D E F G H
8
7
6
5
4
3
2
1
TOP VIEW (balls facing down)
Note* = DQ15/A-1
SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D SST34HF1621S / SST34HF1 641 S
Note: 1. F or SST34HF1601C, VDDS, SA, BES2, and BES1# are No Connect.
1252 62-lfbga P2.0
NC
NC
NC
A16
WEF#
VSSS
WP#
LBS#
A18
NC
A11
A8
RY/BY#
RST#
NC
UBS#
A17
A5
A15
A10
A19
OES#
A7
A4
A14
A9
DQ11
A6
A0
A13
DQ15
DQ13
DQ12
DQ9
A3
BEF#
A12
WES#
DQ6
BES2
DQ10
DQ8
A2
VSSF
VSSF
DQ14
DQ4
VDDS
DQ2
DQ0
A1
OEF#
NC
DQ7
DQ5
VDDF
DQ3
DQ1
BES1#
NC
NC
NC
A B C D E F G H J K
8
7
6
5
4
3
2
1
TOP VIEW (balls facing down)
Note: 1. For SST34HF1601C , VSSS, VDDS, WES#, BES2, OES#, UBS#, LBS#, and BES1# are No Connect .
SST34HF16x1C/D
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
11
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
TABLE 3: PIN DESCRIPTION
Symbol Pin Name Functions
AMS1 to A0Address Inputs To provide flash address, A19-A0.
To provi de (P)SRAM add res s , A MS-A0
SA SRAM x8 Address To provide additional address for x8 SRAM
DQ14-DQ0Data Inputs/Outputs To output data during Read cycles and receive input data during Write cycles.
Data is internally latch ed during a flash Erase/ Program cycle . The outpu ts are in
tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.
DQ15/A-1 Data Inpu t/O utp ut
and LBS Address DQ15 is used as data I/O pin when in x16 mode (CIOF = “1”)
A-1 is used as the LBS address pin when in x8 mode (CIOF = “0”)
BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low
BES1# (P)SRAM Memory Bank Enable To activate the (P)SRAM memory bank when BES1# is low
BES2 (P)SRAM Memory Bank Enable To activate the (P)SRAM memory bank when BES2 is high
OEF#2Output Enable To gate the data output buffers for Flash2 only
OES#2Output Enable To gate the data output buffers for SRAM2 only
WEF#2Write Enable To control the Write operations for Flash2 only
WES#2Write Enable To control the Write operations for SRAM2 only
OE# Output Enable To gate the data output buffers
WE# Write Enable To control the Write operations
CIOF Byte Selection for Flash When low, select Byte mode. When high, select Word mode.
UBS# Upper Byte Control ((P)SRAM) To enable DQ15-DQ8
LBS# Lower Byte Control ((P)SRAM) To enable DQ7-DQ0
WP# Write Prot ect To protect an d unprotect the bottom 8 KW ord (4 secto rs) from Eras e or Program
operation
RST# Reset To Reset and return the device to Read mode
RY/BY# Ready/Busy# To output the status of a Program or Erase Operation
RY/BY# is a open dr ai n outpu t, so a 10K - 100K pull-up resistor i s requi red to
allow RY/BY# to transition high indicating the device is ready to read.
VSSF2Ground Flash2 only
VSSS2Ground SRAM2 only
VSS Ground
VDDFPower Supply (Flash) 2.7-3.3V Power Supply to Flash only
VDDSPower Supply ((P)SRAM) 2.7-3.3V Power Supply to (P)SRAM only
NC No Connection Unconnected pins
T3.0 1252
1. AMS = Most Significant Address
AMS = A16 for SST34HF1621C/D/S, A17 for SST34HF1641C /D/S, and A18 f or SST34HF1681C/D/S
2. LS package only
12
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
TABLE 4: OPERATIONAL MODES SELECTION FOR X16 (P)SRAM
Mode BEF#1BES1#1,2 BES21,2 OE#2,3 WE#2,3 LBS#2UBS#2
DQ15-8
DQ7-0 CIOF = VIH CIOF = VIL
Full Standby VIH VIH X X X X X HIGH-Z HIGH-Z HIGH-Z
XV
IL XXXX
Output Disable VIH VIL VIH VIH VIH X X HIGH-Z HIGH-Z HIGH-Z
VIL VIH XXV
IH VIH
VIL VIH XV
IH VIH X X HIGH-Z HIGH-Z HIGH-Z
XV
IL
Flash Read VIL VIH XV
IL VIH XXD
OUT DOUT DQ14-8 = HIGH-Z
DQ15 = A-1
XV
IL
Flash Write VIL VIH X VIH VIL XXD
IN DIN DQ14-8 = HIGH-Z
DQ15 = A-1
XV
IL
Flash Erase VIL VIH XV
IH VIL XX X X X
XV
IL
(P)SRAM Read VIH V
IL VIH VIL VIH VIL V
IL DOUT DOUT DOUT
VIH VIL HIGH-Z DOUT DOUT
VIL VIH DOUT HIGH-Z HIGH-Z
(P)SRAM W r ite VIH VIL VIH XV
IL VIL VIL DIN DIN DIN
VIH VIL HIGH-Z DIN DIN
VIL VIH DIN HIGH-Z HIGH-Z
Product
Identification4VIL VIH V
IL V
IL VIH X X Manufact urer’s ID5
Device ID5
T4.0 1252
1. Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time
2. X can be VIL or VIH, but no other value.
3. OE# = OEF# and OES#
WE# = WEF# and WES# for LS package only
4. Software mode only
5. With A19-A18 = VIL;SST Manuf act urer’s ID = BFH, is read wit h A0=0,
SST34HF16x1C/D/S Device ID = 734BH, is read with A0=1
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
13
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
TABLE 5: OPERATIONAL MODES SELECTION FOR X8 SRAM
Mode BEF#1BES1#1,2 BES21,2 OE#2WE#2SA2
DQ15-8
DQ7-0 CIOF = VIH CIOF = VIL
Full Standby VIH VIH X X X X HIGH-Z HIGH-Z HIGH-Z
XV
IL XXX
Output Disable VIH VIL VIH VIH VIH X HIGH-Z HIGH-Z HIGH-Z
VIL VIH XXV
IH
VIL VIH XV
IH VIH X HIGH-Z HIGH-Z HIGH-Z
XV
IL
Flash Read VIL VIH XV
IL VIH XD
OUT DOUT DQ14-8 = HIGH-Z
DQ15 = A-1
XV
IL
Flash Write VIL VIH X VIH VIL XD
IN DIN DQ14-8 = HIGH-Z
DQ15 = A-1
XV
IL
Flash Erase VIL VIH XV
IH VIL XX X X
XV
IL
SRAM Read VIH V
IL VIH VIL VIH SA DOUT HIGH-Z HIGH-Z
SRAM Writ e VIH VIL VIH XV
IL SA DIN HIGH-Z HIGH-Z
Product
Identification3VIL VIH V
IL V
IL VIH X Manufacturer’s ID 4
Devi ce ID4Manufacturer’s ID4
De vice ID4
T5.0 1252
1. Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time
2. X can be VIL or VIH, but no other value.
3. Software mode only
4. With A19-A18 = VIL;SST Manuf act urer’s ID = BFH, is read wit h A0=0,
SST34HF16x1C/D/S Device ID = 734BH, is read with A0=1, for x8 A-1 will not be part of the Device ID
TABLE 6: OPERATIONAL MODES SELECTION FOR 0 MBIT SRAM: SST3 4HF1601C
Mode BEF# OE#1,2
1. X can be VIL or VIH, but no other value.
2. OE# = OEF#, WE# = WEF#
WE#1,2
DQ15-8
DQ7-0 CIOF = VIH CIOF = VIL
Full Standby VIH X X HIGH-Z HIGH-Z HIGH-Z
XX
Output Disable VIH VIH VIH HIGH-Z HIGH-Z HIGH-Z
XX
VIL VIH VIH HIGH-Z HIGH-Z HIGH-Z
Flash Read VIL VIL VIH DOUT DOUT DQ14-8 = HIGH-Z
DQ15 = A-1
Flash Write VIL VIH VIL DIN DIN DQ14-8 = HIGH-Z
DQ15 = A-1
Flash Erase VIL VIH VIL XXX
Product
Identification3
3. Software mode only
VIL VIL VIH Manufacturer’s ID4
Device ID4
4. With A19-A18 = VIL;SST Manuf act urer’s ID = BFH, is read wit h A0=0,
SST34HF1601C Device ID = 734BH, is read with A0=1, for x8 A-1 will not be part of the De vice ID
Manufacturer’s ID4
Device ID4
T6.0 1252
14
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
TABLE 7: SOFTWARE COMMAND SEQUENCE
Command
Sequence 1st Bus
Write Cycle 2nd Bus
Write Cycle 3rd Bus
Write Cycle 4th Bus
Write Cycle 5th Bus
Write Cycle 6th Bus
Write Cycle
Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2
Word-/Byte-Program 5555H AAH 2AAAH 55H 5555H A0H WA3Data
Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX430H
Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX450H
Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Erase-Suspend XXXXH B0H
Erase-Resume XXXXH 30H
Query Sec ID 55555H AAH 2AAAH 55H 5555H 88H
User Security ID
Word-/Byte-Program 5555H AAH 2AAAH 55H 5555H A5H SIWA6Data
User Security ID
Program Lock-out75555H AAH 2AAAH 55H 5555H 85H XXH 0000H
Softw are ID Entry85555H AAH 2AAAH 55H BKX9
5555H 90H
Softw are ID Exit/
Sec ID Exit10,11 5555H AAH 2AAAH 55H 5555H F0H
Softw are ID Exit/
Sec ID Exit10,11 XXH F0H
T7.0 1252
1. Address format A14-A0 (Hex) , Addresses A19-A15 can be VIL or VIH, b ut no other value , f or th e command seque nce wh en in x16 mode.
When in x8 mode, Addresses A19-A15, Address A-1 and DQ14-DQ8 can be VIL or VIH, but no other value, for the command sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence
3. WA = Program word/byte address
4. SAX for Sector-Erase; uses A19-A10 address lines
BAX for Block-Erase; uses A19-A15 address lines
5. F or SST34HF16x1C/D/S,
SST ID is read with A3 = 0 (Address range = 00000H to 00007H),
User ID is read with A3 = 1 (Address range = 00010H to 00017H).
Lock Status is read wi th A7-A0 = 000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. SIWA = User Security ID Program word/byte address
For SST34HF16x1C/D/S, valid W ord-Addresses for User Sec ID are from 00010H-00017H.
All 4 cycles of User Security ID Word-Program and Program Lock-out must be completed before going back to Read-Array mode.
7. The User Security ID Program Lock-out command must be executed in x16 mode (BYTE#=VIH).
8. The device does not remain in Software Product Identification mode if powered down.
9. A19 and A18 = VIL
10. Both Software ID Exi t operations are equivalent
11. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the
User Sec ID mode again (the programmed “0” bits cannot be re versed to “1”).
For SST34HF16x1C/D/S, valid W ord-Addresses for User Sec ID are from 00010H-00017H.
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
15
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may caus e per manent d amage to the device. This is a stres s rating only and funct ional operatio n
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V
Pac kage Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Output Short Circuit Cur rent2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. VDD = VDDF and VDDS
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range Ambient Temp VDD
Commercial 0°C to +70°C 2.7-3.3V
Extended -20°C to +85°C 2.7-3.3V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 20 and 21
16
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
TABLE 8: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V)
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDD1Active VDD Current Address input = VILT/VIHT, at f=1/TRC Min,
VDD=VDD Max, all DQs open
Read OE#=VIL, WE#=VIH
Flash 35 mA BEF#=VIL, BES1#=VIH, or BES2=VIL
(P)SRAM 30 mA BEF#=VIH, BES1#=VIL , BES2=VIH
Concurrent Operation 60 mA BEF#=VIH, BES1#=VIL , BES2=VIH
Write2WE#=VIL
Flash 40 mA BEF#=VIL, BES1#=VIH, or BES2=VIL, OE#=VIH
(P)SRAM 30 mA BEF#=VIH, BES1#=VIL , BES2=VIH
ISB Standby VDD Current SRAM
PSRAM 30
85 µA
µA VDD = VDD Max, BEF#=BES1#=VIHC, BES2=VILC
IRT Reset VDD Current 30 µA RST#=GND
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILIW Input Leakage Current
on WP# pin and RST# pin 10 µA WP#=GND to VDD, VDD=VDD Max
RST#=GND to VDD, VDD=VDD Max
ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max
VIH Input High Voltage 0.7 VDD VV
DD=VDD Max
VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Ma x
VOLF Flash Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOHF Flash Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
VOLS (P)SRAM Output Low Voltage 0.4 V IOL =1 mA , VDD=VDD Min
VOHS (P)SRAM Output High Voltage 2.2 V IOH =-500 µA, VDD=VDD Min
T8.0 1252
1. Address input = VILT/VIHT, VDD=VDD Max (See Figure 20)
2. IDD active while Erase or Program is in progress.
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
17
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol Parameter Minimum Units
TPU-READ1Power-up to Read Operation 100 µs
TPU-WRITE1Power-up to Write Operation 100 µs
T9.0 1252
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter Description Test Condition Maximum
CI/O1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
I/O Pin Capacitance VI/O = 0V 20 pF
CIN1Input Capacitance VIN = 0V 16 pF
T10.0 1252
TABLE 11: FLASH RELIABILITY CHARACTERISTICS
Symbol Parameter Minimum Specification Units Test Method
NEND1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Endurance 10,000 Cycles JEDEC Standard A117
TDR1Data Retention 100 Years JEDEC Standard A103
ILTH1Latch Up 100 + IDD mA JEDEC Standard 78
T11.0 1252
18
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
AC CHARACTERISTICS
TABLE 12: (P)SRAM READ CYCLE TIMING PARAMETERS
Min Max Units
TRCS Read Cycl e Time 70 ns
TAAS Address Access Time 70 ns
TBES Bank Enable Access Time 70 ns
TOES Output Enable Access Time 35 ns
TBYES UBS#, LBS# Access Time 70 ns
TBLZS1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
BES# to Active Output 0 ns
TOLZS1Output Enable to Active Output 0 ns
TBYLZS1UBS#, LBS# to Active Out put 0 ns
TBHZS1BES# to High-Z Output 25 ns
TOHZS1Output Disable to High-Z Output 25 ns
TBYHZS1U BS#, LBS# to High-Z Output 35 ns
TOHS Output Hold from Address Change 10 ns
T12.0 1252
TABLE 13: (P)SRAM WRITE CYCLE TIMING PARAMETERS
Symbol Parameter Min Max Units
TWCS Write Cycle Time 70 ns
TBWS Bank Enable to End-of-Write 60 ns
TAWS Address Valid to End-of-Write 60 ns
TASTS Address Set-up Time 0 ns
TWPS Write Pulse Width 60 ns
TWRS Write Recovery Time 0 ns
TBYWS UBS#, LBS# to En d-of-Write 60 ns
TODWS Output Disable from WE# Low 30 ns
TOEWS Output Enable from WE# High 0 ns
TDSS Data Set-up Time 30 ns
TDHS Data Hold from Write Time 0 ns
T13.0 1252
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
19
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
TABLE 14: FLASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.3V
Symbol Parameter Min Max Units
TRC Read Cycle Time 70 ns
TCE Chip Enable Access Time 70 ns
TAA Address Access Time 70 ns
TOE Output Enable Access Time 35 ns
TCLZ1BEF# Low to Active Output 0 ns
TOLZ1OE# Low to Active Output 0 ns
TCHZ1BEF# High to High-Z Output 20 ns
TOHZ1OE# High to Hi gh-Z Output 20 ns
TOH1Output Hold from Address Change 0 ns
TRP1RST# Pulse Width 500 ns
TRHR1RST# High Before R ead 50 ns
TRY1,2 RST# Pin Low to Re ad 20 µs
T14.0 1252
1. This parameter is measured only for initial qualification and after the design or pr ocess change that could affect this parameter.
2. This parameter appl ies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase.
TABLE 15: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol Parameter Min Max Units
TBP Word-Program Time 10 µs
TAS Address Setup Time 0 ns
TAH Address Hold Time 40 ns
TCS WE# and BEF# Setup Time 0 ns
TCH WE# and BEF# Hold Time 0 ns
TOES OE# Hi gh Setup Ti me 0 ns
TOEH OE# High Hold Time 10 ns
TCP BEF# Pulse Width 40 ns
TWP WE# Pulse Width 40 ns
TWPH1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
WE# Pulse Width High 30 ns
TCPH1 BEF# Pulse Width High 30 ns
TDS Data Setup Time 30 ns
TDH1Data Hold Time 0 ns
TIDA1Software ID Access and Exit Time 150 ns
TES Erase-Sus pe nd Lat enc y 20 µs
TBY1,2
2. This parameter appl ies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.
RY/BY# Delay Time 90 ns
TBR1Bus# Recovery Time s
TSE Sector-Erase 25 ms
TBE Block-Erase 25 ms
TSCE Chip-Erase 50 ms
T15.0 125 2
20
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 5: (P)SRAM READ CYCLE TIMING DIAGRAM
FIGURE 6: (P)SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
ADDRESSES AMSS-0
DQ15-0
UBS#, LBS#
OE#
BES1#
BES2
TRCS
TAAS
TBES
TOES
TBLZS
TOLZS
TBYES
TBYLZS TBYHZS
DATA VALID
TOHZS
TBHZS
TOHS
1252 F04.0
TBES
Note: AMSS = Most Si gnificant Address
AMSS = A16 for SST34HF1621C/S, A17 for SST34HF1641C/D/S, and A18 for SST34HF1681D
For SST34HF16x1S, LBS# and UBS# are No Connect and in x8 mode, the additional SRAM address is SA
TAWS
ADDRESSES AMSS3-0
BES1#
BES2
WE#
UBS#, LBS#
TWPS TWRS
TWCS
TASTS
TBWS
TBWS
TBYWS
TODWS TOEWS
TDSS TDHS
1252 F05.0
NOTE 2
NOTE 2
DQ15-8, DQ7-0 VALID DATA IN
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will remain at high impedance.
If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance.
Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant SRAM Address
AMSS = A16 for SST34HF1621C/S, A17 for SST34HF1641C/D/S, and A18 for SST34HF1681D
For SST34HF16x1S, LBS# and UBS# are No Connect and in x8 mode, the additional SRAM address is SA
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
21
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 7: (P)SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1 X16 (P)SRAM ONLY
ADDRESSES AMSS3-0
WE#
BES1#
BES2
TBWS
TBWS
TAWS
TWCS
TWPS TWRS
TASTS TBYWS
DQ15-8, DQ7-0 VALID DATA IN
NOTE 2 NOTE 2
TDSS TDHS
UBS#, LBS#
1252 F06.0
Note: 1. If OE# is High duri ng the Write cycle, the outputs will remain at high impedance.
2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant SRAM Address
AMSS = A16 for SST34HF1621C, A17 for SST34HF164 1C/D, and A18 for SST34HF1681D
22
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 8: FLASH READ CYCLE TIMING DIAGRAM FOR WORD MODE
(FOR BYTE MODE A-1 = ADDRESS INPUT)
FIGURE 9: FLASH WE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM FOR WORD MODE
(FOR BYTE MODE A-1 = ADDRESS INPUT)
1252 F07.0
ADDRESS A19-0
DQ15-0
WE#
OE#
BEF#
TCE
TRC TAA
TOE
TOLZ
VIH
HIGH-Z TCLZ TOH
TCHZ
HIGH-Z
DATA VALIDDATA VALID
TOHZ
1252 F08.0
ADDRESS A19-0
DQ15-0
TDH
T
WPH
TDS
TWP
TAH
TAS
TCH
TCS TBY
BEF#
RY/BY#
5555 2AAA 5555 ADDR
XXAA XX55 XXA0 DATA
WORD
(ADDR/DATA)
OE#
WE#
TBR
TBP
Note: X can be VIL or VIH, but no other value.
VALID
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
23
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 10: FLASH BEF# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM FOR WORD MODE
(FOR BYTE MODE A-1 = ADDRESS INPUT)
FIGURE 11: FLASH DATA# POLLING TIMING DIAGRAM FOR WORD MODE
(FOR BYTE MODE A-1 = ADDRESS INPUT)
VALID
1252 F09.0
ADDRESS A19-0
DQ15-0
TDH
T
CPH
TDS
TCP
TAH
TAS
TCH
TCS
WE#
5555 2AAA 5555 ADDR
XXAA XX55 XXA0 DATA
WORD
(ADDR/DATA)
OE#
BEF#
TBP
TBY
RY/BY# TBR
Note: X can be VIL or VIH, but no other value.
1252 F10.0
ADDRESS A19-0
DQ7DATA DATA# DATA# DATA
WE#
OE#
BEF#
TOEH
TOE
TCE
TOES
RY/BY#
TBY
24
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 12: FLASH TOGGLE BIT TIMING DIAGRAM FOR WORD MODE
(FOR BYTE MODE A-1 = DONT CARE)
FIGURE 13: FLASH WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM FOR WORD MODE
(FOR BYTE MODE A-1 = DONT CARE)
1252 F11.0
ADDRESS A19-0
DQ6
WE#
OE#
BEF#
TOE
TOEH
TCE
TWO READ CYCLES
WITH SAME OUTPUTS
VALID DATA
TBR
VALID
TBR
1252 F12.0
ADDRESS A19-0
DQ15-0
WE#
5555 2AAA 2AAA5555 5555
XX55 XX10XX55XXAA XX80 XXAA
5555
OE#
BEF#
SIX-BYTE CODE FOR CHIP-ERASE
TSCE
TWP
TBY
RY/BY#
Note: This device also supports BEF# controlled Chip-Er ase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 15.)
X can be VIL or VIH, but no other value.
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
25
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 14: FLASH WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM FOR WORD MODE
(FOR BYTE MODE A-1 = DONT CARE)
FIGURE 15: FLASH WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM FOR WORD MODE
(FOR BYTE MODE A-1 = DONT CARE)
1252 F13.0
ADDRESS A19-0
DQ15-0
WE#
5555 2AAA 2AAA5555 5555
XX55 XX50XX55XXAA XX80 XXAA
BAX
OE#
BEF#
SIX-BYTE CODE FOR BLOCK-ERASE
TWP
TBY
RY/BY#
VALID
TBR
TBE
Note: This device also supports BEF# controlled Block-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 15.)
BAX = Block Address
X can be VIL or VIH, but no other value.
1252 F14.0
ADDRESS A19-0
DQ15-0
WE#
5555 2AAA 2AAA5555 5555
XX55 XX30XX55XXAA XX80 XXAA
SAX
OE#
BEF#
SIX-BYTE CODE FOR SECTOR-ERASE
TWP
TBY
RY/BY#
VALID
TBR
TSE
Note: This device also suppor t s BEF# cont rolled Secto r-Erase operation.
The WE# and BEF# signals are interchangeable as long as minim um timings are meet. (See Table 15.)
SAX = Sector Address
X can be VIL or VIH, but no other value.
26
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 16: FLASH SOFTWARE ID ENTRY AND READ FOR WORD MODE
(FOR BYTE MODE A-1 = 0)
FIGURE 17: FLASH SOFTWARE ID EXIT FOR WORD MODE
(FOR BYTE MODE A-1 = 0)
1252 F15.0
ADDRESS A14-0
TIDA
DQ15-0
WE#
5555 2AAA 5555 0000 0001
OE#
BEF#
Three-Byte Sequence For Software ID Entry
TWP
TWPH TAA
00BF Device ID
XX55XXAA XX90
Note: X can be VIL or VIH, b ut no other value .
Devi ce ID - 734BH for SST34HF16x1C/DS
1252 F16.0
ADDRESS A14-0
DQ15-0
TIDA
TWP
TWHP
WE#
5555 2AAA 5555
Three-Byte Sequence for Software ID Exit and Reset
OE#
BEF#
XXAA XX55 XXF0
Note: X can be VIL or VIH, but no other value
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
27
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 18: RST# TIMING (WHEN NO INTERNAL OPERATION IS IN PROGRESS)
FIGURE 19: RST# TIMING (DURING SECTOR- OR BLOCK-ERASE OPERATION)
1252 F17.0
RY/BY#
0V
RST#
BEF#/OE#
TRP
TRHR
1252 F18.0
RY/BY#
BEF#
OE#
TRP
TRY
TBR
RST#
28
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 20: AC I NPUT/OUTPUT REFERENCE WAVEFORMS
FIGURE 21: A TEST LOAD EXAMPLE
1252 F19.0
REFERENCE POINTS OUTPUTINPUT VIT
VIHT
VILT
VOT
A C test inputs are driven at VIHT (0.9 VDD) for a l ogic “1” and VILT (0.1 VDD) fo r a logic “0 ”. Measurem ent ref e rence point s
f or inputs and outputs are VIT (0.5 VDD) and V OT (0.5 VDD). Input rise and f all times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
1252 F20.0
TO TESTER
TO DUT
CL
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
29
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 22: WORD-PROGRAM ALGORITHM
1252 F21.0
Start
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XXA0H
Address: 5555H
Load Word
Address/Word
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
Note: X can be VIL or VIH, but no other value.
30
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 23: WAIT OPTIONS
1252 F22.0
Wait TBP,
TSCE, TSE
or TBE
Program/Erase
Initiated
Internal Timer Toggle Bit
Ye s
Ye s
No
No
Program/Erase
Completed
Does DQ6
match?
Read same
word
Data# Polling
Program/Erase
Completed
Program/Erase
Completed
Read word
Is DQ7 =
true data?
Read DQ7
Program/Erase
Initiated
Program/Erase
Initiated
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
31
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 24: SOFTWARE PRODUCT ID COMMAND FLOWCHARTS
1252 F23.0
Load data: XXAAH
Address: 5555H
Software Product ID Entry
Command Sequence
Load data: XX55H
Address: 2AAAH
Load data: XX90H
Address: 5555H
Wait TIDA
Read Software ID
Load data: XXAAH
Address: 5555H
Software ID Exit
Command Sequence
Load data: XX55H
Address: 2AAAH
Load data: XXF0H
Address: 5555H
Wait TIDA
Return to normal
operation
Note: X can be VIL or VIH, but no other value.
32
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 25: SOFTWARE SEC ID COMMAND FLOWCHARTS
1252 F24.0
Sec ID Exit
Command Sequence
Load data: XXF0H
Address: XXH
Return to normal
operation
Wait TIDA
X can be VIL or VIH, but no other value
Load data: XXAAH
Address: 5555H
Sec ID Query Entry
Command Sequence
Load data: XX55H
Address: 2AAAH
Load data: XX88H
Address: 5555H
Wait TIDA
Read Sec ID
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XXF0H
Address: 5555H
Wait TIDA
Return to normal
operation
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
33
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
FIGURE 26: ERASE COMMAND SEQUENCE
1252 F25.0
Load data: XXAAH
Address: 5555H
Chip-Erase
Command Sequence
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XXAAH
Address: 5555H
Wait TSCE
Chip erased
to FFFFH
Load data: XXAAH
Address: 5555H
Sector-Erase
Command Sequence
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX30H
Address: SAX
Load data: XXAAH
Address: 5555H
Wait TSE
Sector erased
to FFFFH
Load data: XXAAH
Address: 5555H
Block-Erase
Command Sequence
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX50H
Address: BAX
Load data: XXAAH
Address: 5555H
Wait TBE
Block erased
to FFFFH
Note: X can be VIL or VIH, but no other value.
34
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
PRODUCT ORDERING INFORMATION
Package Attribute
E = non-Pb
Package Modifier
P = 56 balls
S = 62 balls
Pac kage Type
L1 = LFB GA (8mm x 10 mm x 1.4 mm, 0.45 mm ball siz e)
L = LFBGA (8mm x 10mm x 1.4mm, 0.40mm ball size)
B1 = TFBGA (8mm x 10mm x 1.2mm, 0.45mm ball size)
Temperature Range
C = Commercial = 0°C to +70°C
E = Extended = -20°C to +85°C
Minimum Endurance
4 =10,00 0 cycles
Read Access Speed
70 = 70 ns
Version
C = x16 Mbit SRAM
D = x16 Mbit PSRAM
S = x8 Mbit SRAM
Bank Split
1 = 12 Mbit + 4 Mbit
SRAM Density
0 = No SRAM
2 = 2 Mbit
4 = 4 Mbit
8 = 8 Mbit
Flash Density
16 = 16 Mbit
Voltage
H = 2.7-3.3V
Product Series
34 = Concurrent SuperFlash + SRAM ComboMemory
Device Speed Suffix1 Suffix2
SST34HF16x1X-XXX -XX-XXXX
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
35
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
Valid combinations for SST34HF1601C
SST34HF1601C-70-4C-L1P SST34HF1601C-70-4C-LS SST34HF1601C-70-4C-B1P
SST34HF1601C-70-4C-L1PE SST34HF1601C-70-4C-LSE SST34HF1601C-70-4C-B1PE
SST34HF1601C-70-4E-L1P SST34HF1601C-70-4E-LS SST34HF1601C-70-4E-B1P
SST34HF1601C-70-4E-L1PE SST34HF1601C-70-4E-LSE SST34HF1601C-70-4E-B1PE
Valid combinations for SST34HF1621C
SST34HF1621C-70-4C-L1P SST34HF1621C-70-4C-LS
SST34HF1621C-70-4C-L1PE SST34HF1621C-70-4C-LSE
SST34HF1621C-70-4E-L1P SST34HF1621C-70-4E-LS
SST34HF1621C-70-4E-L1PE SST34HF1621C-70-4E-LSE
Valid combinations for SST34HF1621S
SST34HF1621S-70-4C-L1P
SST34HF1621S-70-4C-L1PE
SST34HF1621S-70-4E-L1P
SST34HF1621S-70-4E-L1PE
Valid combinations for SST34HF1641C
SST34HF1641C-70-4C-L1P SST34HF1641C-70-4C-LS
SST34HF1641C-70-4C-L1PE SST34HF1641C-70-4C-LSE
SST34HF1641C-70-4E-L1P SST34HF1641C-70-4E-LS
SST34HF1641C-70-4E-L1PE SST34HF1641C-70-4E-LSE
Valid combinations for SST34HF1641D
SST34HF1641D-70-4C-L1P SST34HF1641D-70-4C-LS
SST34HF1641D-70-4C-L1PE SST34HF1641D-70-4C-LSE
SST34HF1641D-70-4E-L1P SST34HF1641D-70-4E-LS
SST34HF1641D-70-4E-L1PE SST34HF1641D-70-4E-LSE
Valid combinations for SST34HF1641S
SST34HF1641S-70-4C-L1P
SST34HF1641S-70-4C-L1PE
SST34HF1641S-70-4E-L1P
SST34HF1641S-70-4E-L1PE
Valid combinations for SST34HF1681D
SST34HF1681D-70-4C-L1P SST34HF1681D-70-4C-LS
SST34HF1681D-70-4C-L1PE SST34HF1681D-70-4C-LSE
SST34HF1681D-70-4E-L1P SST34HF1681D-70-4E-LS
SST34HF1681D-70-4E-L1PE SST34HF1681D-70-4E-LSE
Note: Va lid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm av ailability of valid combinations and to determine availability of new combinations.
36
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
PACKAGING DIAGRAMS
56-BALL LOW-PROFILE, FINE-PITCH B ALL GRID ARRAY (LFBGA) 8MM X 10MM
SST PACKAGE CODE: L1P
A1 CORNER
H G F E D C B A
A B C D E F G H
BOTTOM VIEW
TOP VIEW
SIDE VIEW
8
7
6
5
4
3
2
1
SEATING PLANE 0.35 ± 0.05
1.30 ± 0.10
0.12
8.00 ± 0.20
0.45 ± 0.05
(56X)
A1 CORNER
10.00 ± 0.20
0.80
5.60
0.80
5.60
56-lfbga-L1P-8x10-450mic-3
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,
this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. The actual shape of the corners may be slightly different than as portrayed in the drawing.
8
7
6
5
4
3
2
1
1mm
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
37
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
62-BALL LOW-PROFILE, FINE-PITCH B ALL GRID ARRAY (LFBGA) 8MM X 10MM
SST PACKAGE CODE: LS
A1 CORNER
K J H G F E D C B A
A B C D E F G H J K
BOTTOM VIEW
TOP VIEW
8
7
6
5
4
3
2
1
8.00 ± 0.20
0.40 ± 0.05
(62X)
A1 CORNER
10.00 ± 0.20
0.80
5.60
0.80
7.20
62-lfbga-LS-8x10-400mic-3
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,
this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. The actual shape of the corners may be slightly different than as portrayed in the drawing.
8
7
6
5
4
3
2
1
1mm
SIDE VIEW
SEATING PLANE 0.32 ± 0.05
1.30 ± 0.10
0.12
38
Advance Information
16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1601C / SST34HF1621C / SST34HF1641C
SST34HF1641D / SST34HF1681D / SST34HF1621S / SST34HF1641S
©2004 Silicon Storage Technology, Inc. S71252-00-000 3/04
56-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM X 10MM
SST PACKAGE CODE: B1P
TABLE 16: REVISION HISTORY
Number Description Date
00 Initial Release Mar 2004
1.2 max
H G F E D C B A
A B C D E F G H
BOTTOM VIEWTOP VIEW
SIDE VIEW
8
7
6
5
4
3
2
1
SEATING PLANE
0.35 ± 0.05
0.12
8.00 ± 0.20
0.45 ± 0.05
(56X)
10.00 ± 0.20
0.80
5.60
0.80
5.60
56-tfbga-B1P-8x10-450mic-1
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm)
8
7
6
5
4
3
2
1
1mm
A1 CORNER A1 CORNER
Silicon Stor age Technology, Inc. • 1171 Sonor a Court • Sunnyvale , CA 940 86 • Telephone 408-73 5-91 10 • Fax 408-735-90 36
www.SuperFlash.com or www.sst.com