May 2000
DESCRIPTION
The TS8388BFS is a monolithic 8–bit analog–to–digital converter, designed for digitizing wide bandwidth analog signals at very high sampling
rates of up to 1 GSPS.
The TS8388BFS is using an innovative architecture, including an on chip Sample and Hold (S/H), and is fabricated with an advanced high
speed bipolar process (B6HF from Siemens).
The on–chip S/H has a 2 GHz full power input bandwidth, providing excellent dynamic performance in undersampling applications (High IF
digitizing).
MAIN FEATURES
§ 8-bit resolution.
§ ADC gain adjust.
§ 1.5 GHz full power input bandwidth.
§ 1 GSPS (min) sampling rate.
§ SINAD = 44.3 dB (7.2 Effective Bits) SFDR = 58 dBc
@ FS = 1 GSPS, FIN = 20 MHz :
§ SINAD = 42.9 dB (7.0 Effective Bits) SFDR = 52 dBc
@ FS = 1 GSPS, FIN = 500 MHz :
§ SINAD = 40.3dB (6.8 Effective Bits) SFDR = 50 dBc
@ FS = 1 GSPS, FIN = 1000 MHz (-3 dB FS)
§ 2-tone IMD : -52dBc (489 MHz, 490 MHz) @ 1GSPS.
§ DNL = 0.4 LSB INL = 0.7 LSB.
§ Low Bit Error Rate (10-13 ) @ 1 GSPS
§ Very low input capacitance : 3 pF
§ 500 mVpp differential or single-ended analog inputs.
§ Differential or single-ended 50 Ω ECL compatible
clock inputs.
§ ECL or LVDS/HSTL output compatibility.
§ Data ready output with asynchronous reset.
§ Gray or Binary selectable output data ; NRZ output mode.
§ Power consumption : 3.6 W @ Tj = 70°C
3.8 W @ Tj =125°C
§ CQFP package enhanced with heat spreader : Rthjc = 4.75°C/W
§ Dual power supply : ± 5 V
§ Radiation tolerance oriented design
(150 Krad (Si) measured).
APPLICATIONS
§ Digital Sampling Oscilloscopes.
§ Satellite receiver.
§ Electronic countermeasures / Electronic warfare.
§ Direct RF down – conversion.
SCREENING
§ TCS standard screening level
§ Mil-PRF-38535, QML level Q for package version.
§ Space screening according to ESA/SCC 9000.
§ Temperature range : -55°C < Tc ; Tj < +125°C
FS Suffix
Rth CQFP 68
Ceramic Quad Flat Pack
1/ Die form : JTS8388B
2/ Evaluation board : TSEV8388BF
3/ Dmux TS81102G0 : companion device available
TS8388BFS
1 GSPS 8-BIT A/D CONVERTER
TS8388BFS
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TABLE OF CONTENTS
1. SIMPLIFIED BLOCK DIAGRAM....................................................................................................................................3
2. FUNCTIONAL DESCRIPTION.........................................................................................................................................3
3. SPECIFICATIONS..............................................................................................................................................................4
3.1. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW).......................................................................................................................4
3.2. RECOMMENDED CONDITIONS OF USE......................................................................................................................................................4
3.3. ELECTRICAL OPERATING CHARACTERISTICS..............................................................................................................................5
3.4. TIMING DIAGRAMS ................................................................................................................................................................................9
3.5. EXPLANATION OF TEST LEVELS...................................................................................................................................................10
3.6. WAFER SCREENING.......................................................................................................................................................................10
3.7. FUNCTIONS DESCRIPTION............................................................................................................................................................11
3.8. DIGITAL OUTPUT CODING.............................................................................................................................................................11
4. PACKAGE DESCRIPTION. ............................................................................................................................................12
4.1. TS8388BFS PIN DESCRIPTION......................................................................................................................................................12
4.2. TS8388BFS PINOUT........................................................................................................................................................................13
4.3. OUTLINE DIMENSIONS – 68 PINS CQFP.........................................................................................................................................14
4.4. THERMAL CHARACTERISTICS......................................................................................................................................................15
5. TYPICAL CHARACTERIZATION RESULTS.............................................................................................................16
5.1. STATIC LINEARITY – FS = 50 MSPS / FIN = 10 MHZ......................................................................................................................16
5.2. EFFECTIVE NUMBER OF BITS VERSUS POWER SUPPLIES VARIATION ...................................................................................17
5.3. TYPICAL FFT RESULTS..................................................................................................................................................................18
5.4. SPURIOUS FREE DYNAMIC RANGE VERSUS INPUT AMPLITUDE..............................................................................................19
5.5. DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY...........................................................................................20
5.6. EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY................................................................................20
5.7. SFDR VERSUS SAMPLING FREQUENCY......................................................................................................................................21
5.8. TS8388BFS ADC PERFORMANCES VERSUS JUNCTION TEMPERATURE .................................................................................22
5.9. TYPICAL FULL POWER INPUT BANDWIDTH.................................................................................................................................23
5.10. ADC STEP RESPONSE...............................................................................................................................................................24
6. DEFINITION OF TERMS................................................................................................................................................25
7. APPLYING THE TS8388BFS...........................................................................................................................................27
7.1. TIMING INFORMATIONS.................................................................................................................................................................27
7.2. PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND..........................................................................28
7.3. ANALOG INPUTS (VIN) (VINB)........................................................................................................................................................29
7.4. CLOCK INPUTS (CLK) (CLKB).........................................................................................................................................................30
7.5. CLOCK SIGNAL DUTY CYCLE ADJUST .........................................................................................................................................31
7.6. NOISE IMMUNITY INFORMATIONS................................................................................................................................................31
7.7. DIGITAL OUTPUTS..........................................................................................................................................................................32
7.8. OUT OF RANGE BIT........................................................................................................................................................................35
7.9. GRAY OR BINARY OUTPUT DATA FORMAT SELECT...................................................................................................................35
7.10. DIODE PIN 49..............................................................................................................................................................................35
7.11. ADC GAIN CONTROL PIN 60......................................................................................................................................................36
8. EQUIVALENT INPUT / OUTPUT SCHEMATICS.......................................................................................................37
8.1. EQUIVALENT ANALOG INPUT CIRCUIT AND ESD PROTECTIONS..............................................................................................37
8.2. EQUIVALENT ANALOG CLOCK INPUT CIRCUIT AND ESD PROTECTIONS.................................................................................37
8.3. EQUIVALENT DATA OUTPUT BUFFER CIRCUIT AND ESD PROTECTIONS................................................................................38
8.4. ADC GAIN ADJUST EQUIVALENT INPUT CIRCUITS AND ESD PROTECTIONS ..........................................................................38
8.5. GORB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS............................................................................................39
8.6. DRRB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS............................................................................................39
9. TSEV8388BF : CHIP EVALUATION BOARD (SEE SEPARATE TSEV8388BF SPECIFICATION)....................40
10. ORDERING INFORMATION......................................................................................................................................41
10.1. PACKAGE DEVICE ...........................................................................................................................................................................41
10.2. EVALUATION BOARD .......................................................................................................................................................................41
TS8388BFS
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1. SIMPLIFIED BLOCK DIAGRAM
G=2 T/H G=1 T/H G=1
CLOCK
BUFFER
RESISTOR
CHAIN
ANALOG
ENCODING
BLOCK
INTERPOLATION
STAGES
REGENERATION
LATCHES
ERROR CORRECTION &
DECODE LOGIC
OUTPUT LATCHES &
BUFFERS
4
4 5
4 5
8
8
VIN,VINB
CLK, CLKB
GAIN
DRRB DR,DRB GORB DATA,DATAB OR,ORB
MASTER/SLAVE TRACK & HOLD AMPLIFIER
2. FUNCTIONAL DESCRIPTION
The TS8388BFS is an 8 bit 1GSPS ADC based on an advanced high speed bipolar technology (B6HF from SIEMENS) featuring a cutoff
frequency of 25 GHz.
The TS8388BFS includes a front-end master/slave Track and Hold stage (S/H), followed by an analog encoding stage and interpolation
circuitry.
Successive banks of latches are regenerating the analog residues into logical data before entering an error correction circuitry and a
resynchronization stage followed by 75 Ω differential output buffers.
The TS8388BFS works in fully differential mode from analog inputs up to digital outputs.
The TS8388BFS features a full power input bandwidth of 1.5 GHz.
Control pin GORB is provided to select either Gray or Binary data output format.
Gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8388BFS.
The TS8388BFS uses only vertical isolated NPN transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation
tolerance (no performance drift measured at 150kRad total dose).
TS8388BFS
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3. SPECIFICATIONS
3.1. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW)
Parameter Symbol Comments Value Unit
Positive supply voltage VCC GND to 6 V
Digital negative supply
voltage DVEE GND to -5.7 V
Digital positive supply
voltage VPLUSD GND-0.3 to 2.8 V
Negative supply voltage VEE GND to -6 V
Maximum difference
between negative supply
voltages
DVEE to VEE 0.3 V
Analog input voltages VIN or VINB -1 to +1 V
Maximum difference
between VIN and VINB
VIN - VINB -2 to +2 V
Digital input voltage VDGORB -0.3 to VCC +0.3 V
Digital input voltage VDDRRB VEE -0.3 to +0.9 V
Digital output voltage Vo VPLUSD-3 to VPLUSD -0.5 V
Clock input voltage VCLK or VCLKB -3 to +1.5 V
Maximum difference
between VCLK and VCLKB
VCLK - VCLKB -2 to +2 V
Maximum junction
temperature Tj+145 oC
Storage temperature Tstg -65 to +150 oC
Lead temperature
(soldering 10s) Tleads +300 oC
Notes : Absolute maximum ratings are limiting values (referenced to GND=0V), to be applied individually, while other parameters are within
specified operating conditions. Long exposure to maximum rating may affect device reliability.
The use of a thermal heat sink is mandatory (see Thermal characteristics page 19).
3.2. RECOMMENDED CONDITIONS OF USE
Parameter Symbol Comments Min. Typ. Max. Unit
Positive supply voltage VCC 4.75 +5 5.25 V
Positive digital supply voltage VPLUSD ECL output compatibility GND V
VPLUSD LVDS output compatibility +1.4 +2.4 +2.6 V
Negative supply voltages VEE, DVEE -5.25 -5.0 -4.75 V
Differential analog input voltage
(Full Scale) VIN, VINB
VIN -VINB
50 Ω differential or single-ended ±113
450
±125
500
±137
550
mV
mVpp
Clock input power level PCLK PCLKB 50 Ω single–ended clock input 3 4 10 dBm
Operating temperature range TJCivil : “C” grade
Industrial : “V” grade
Military : “M” grade
0 < Tc < 70
-40 < Tc < 85
-55 < Tc ; Tj < +125
oC
TS8388BFS
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3.3. ELECTRICAL OPERATING CHARACTERISTICS
VEE = DVEE = -5 V ; VCC = +5 V ; VIN -VINB = 500 mVpp Full Scale differential input ;
Digital outputs 75 or 50 Ω differentially terminated ;
Tj (typical) = 70°C. Full temperature range : -55°C < Tc ; Tj < +125°C
Parameter Symb Temp Test
level Min Typ Max Unit
POWER REQUIREMENTS
Positive supply voltage Analog
Digital (ECL)
Digital (LVDS)
VCC
VPLUSD
VPLUSD
II,IV 4.75
1.4
5
0
2.4
5.25
2.6
V
V
V
Positive supply current Analog
Digital ICC
IPLUSD
II, IV 400
120 425
130 mA
mA
Negative supply voltage VEE Full IV -5.25 -5 -4.75 V
Negative supply current Analog
Digital AIEE
DIEE II,IV 170
140 185
160 mA
mA
Nominal power dissipation PD Full II
IV 3.6
3.8 3.7
3.9 W
W
Power supply rejection ratio (note 2) PSRR IV +/- 0.5 mV/V
RESOLUTION 8bits
ANALOG INPUTS
Full Scale Input Voltage range (differential mode)
( 0 Volt common mode voltage ) VIN
VINB
Full IV -125
-125 125
125 mV
mV
Full Scale Input Voltage range (single–ended input option )
(see Application Notes) VIN
VINB
Full IV -250 0250 mV
mV
Analog input capacitance CIN Full IV 33.5 pF
Input bias current IIN Full IV 10 20 µA
Input Resistance RIN Full IV 0.5 1MΩ
Full Power input Bandwidth FPBW Full IV 1.3 1.5 GHz
Small Signal input Bandwidth (10 % full scale) SSBW Full IV 1.5 1.7 GHz
CLOCK INPUTS
Logic compatibility for clock inputs (note 10 )
(see Application Notes) ECL or specified clock input
power level in dBm
ECL Clock inputs voltages (VCLK or VCLKB) : Full IV
• Logic “0” voltage VIL -1.5 V
• Logic “1” voltage VIH -1.1 V
• Logic “0” current IIL 5µA
• Logic “1” current IIH 5µA
Clock input power level into 50 Ω termination DBm into 50 Ω
Clock input power level Full IV -2 4 10 dBm
Clock input capacitance CCLK Full IV 33.5 pF
TS8388BFS
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Preliminary Beta Site
Parameter Symb Temp Test
level Min Typ Max Unit
DIGITAL OUTPUTS (notes 1,6)
Single ended or differential input mode, 50 % clock duty cycle (CLK,CLKB), Binary output data format,
Tj (typical) = 70°C. Full temperature range :-55°C < Tc ; Tj < +125°C.
Logic compatibility for digital outputs
( Depending on the value of VPLUSD )
(see Application Notes)
ECL or LVDS
Differential output voltage swings ( assuming VPLUSD = 0V) :
75 Ω open transmission lines ( ECL levels )
75 Ω differentially terminated
50 Ω differentially terminated
Full IV 1.50
0.70
0.54
1.620
0.825
0.660
V
V
V
Output levels ( assuming VPLUSD = 0V)
75 Ω open transmission lines (note 6) 25°CIV
• Logic “0” voltage VOL -1.62 -1.54 V
• Logic “1” voltage VOH -0.88 -0.8 V
Output levels ( assuming VPLUSD = 0V)
75 Ω differentially terminated (note 6) 25°CIV
• Logic “0” voltage VOL -1.41 -1.34 V
• Logic “1” voltage VOH -1.07 -1 V
Output levels ( assuming VPLUSD = 0V)
50 Ω differentially terminated (note 6) 25°CII
• Logic “0” voltage VOL -1.35 -1.28 V
• Logic “1” voltage VOH -1.09 -1.02 V
Output level drift with temperature Full IV 1.6 mV/°C
DC ACCURACY
Single ended or differential input mode, 50 % clock duty cycle (CLK,CLKB), Binary output data format,
Tj (typical) = 70°C. Full temperature range :-55°C < Tc ; Tj < +125°C.
Differential non linearity (notes 2,3) DNL Full I
VI 0.4
0.5 0.5
0.6 LSB
LSB
Integral non linearity (notes 2,3) INL Full I
VI 0.7
0.9 1
1.2 LSB
LSB
No missing codes (note 3) Full Guaranteed over specified temperature range
Gain error Full I
VI -10
-11 -2
-2 6
7% FS
% FS
Input offset voltage Full I
VI -26
-30 -5
-5 14
17 mV
mV
Gain error drift
Offset error drift Full
Full IV
IV 100
40
125
50
150
60
ppm/°C
ppm/°C
TS8388BFS
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Parameter Symb Temp Test
level Min Typ Max Unit
TRANSIENT PERFORMANCE
Bit Error Rate (notes 2, 4)
FS = 1 GSPS Fin = 62.5 MHz BER Full IV 1E-12 Error/
sample
ADC settling time (note 2)
VIn -VinB = 400 mVpp TS IV 0.5 ns
Overvoltage recovery time (note 2) ORT IV 0.5 ns
AC PERFORMANCE
Single ended or differential input and clock mode, 50 % clock duty cycle (CLK,CLKB), Binary output data format,
Tj. = 70°C, unless otherwise specified.
Signal to Noise and Distortion ratio (note 2) SINAD Full IV
FS = 1 GSPS Fin = 20 MHz 42 44 dB
FS = 1 GSPS Fin = 500 MHz 41 43 dB
FS = 1 GSPS Fin = 1000 MHz (-1dB Fs) 38 40 dB
Effective Number Of bits ENOB Full IV
FS = 1 GSPS Fin = 20 MHz 7.0 7.2 Bits
FS = 1 GSPS Fin = 500 MHz 6.6 6.8 Bits
FS = 1 GSPS Fin = 1000 MHz (-1dBFs) 6.2 6.4 Bits
Signal to Noise Ratio (note 2) SNR Full IV
FS = 1 GSPS Fin = 20 MHz 42 45 dB
FS = 1 GSPS Fin = 500 MHz 41 44 dB
FS = 1 GSPS Fin = 1000 MHz (-1dBFs) 41 44 dB
Total Harmonic Distortion (note 2) THD Full IV
FS = 1 GSPS Fin = 20 MHz 50 54 dB
FS = 1 GSPS Fin = 500 MHz 46 50 dB
FS = 1 GSPS Fin = 1000 MHz (-1dBFs) 42 46 dB
Spurious Free Dynamic Range (note 2) SFDR Full IV
FS = 1 GSPS Fin = 20 MHz - 52 - 57 dBc
FS = 1 GSPS Fin = 500 MHz - 47 - 52 dBc
FS = 1 GSPS Fin = 1000 MHz (-1dBFs) - 42 - 47 dBc
FS = 1 GSPS Fin = 1000 MHz (-3dBFs) - 45 - 50 dBc
Two-tone inter-modulation distortion (note 2) IMD Full IV
FIN1 = 489 MHz @ FS = 1 GSPS - 47 - 52 dBc
FIN2 = 490 MHz @ FS = 1 GSPS
TS8388BFS
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Preliminary Beta Site
Parameter Symb Temp Test
level Min Typ Max Unit
SWITCHING PERFORMANCE AND CHARACTERISTICS – See Timing Diagrams Figure 1, Figure 2
Maximum clock frequency FSFull 11.4 GSPS
Minimum clock frequency FSFull IV 10 MSPS
Minimum Clock pulse width (high) TC1 Full IV 0.280 0.500 50 ns
Minimum Clock pulse width (low) TC2 Full IV 0.350 0.500 50 ns
Aperture delay (Note 2) TA Full IV 100 +250 400 ps
Aperture uncertainty (Notes 2, 5) Jitter 25oCIV 0.4 0.6 ps (rms)
Data output delay (Notes 2, 10, 11, 12) TOD Full IV 1150 1360 1660 ps
Output rise/fall time for DATA (20 % – 80 %)
(note 11)TR/TF Full IV 250 350 550 ps
Output rise/fall time for DATA READY
(20 % – 80 % ) (note 11)
TR/TF Full IV 250 350 550 ps
Data ready output delay (Notes 2,10, 11, 12) TDR Full IV 1110 1320 1620 ps
Data ready reset delay TRDR Full IV 720 1000 ps
TOD-TODR
(notes 9, 13)
TOD-
TDR Full IV 40 40 40 ps
TC1+TDR-TOD
See Timing Diagram (Note 2) @ 1Gsps
TD1 Full IV 460 460 460 ps
Data pipeline delay TPD Full IV 4clock
cycles
Note 1 : Differential output buffers are internally loaded by 75 Ω resistors. Buffer bias current = 11 mA.
Note 2 : See definition of terms
Note 3 : Histogram testing based on sampling of a 10 MHz sinewave at 50 MSPS.
Note 4 : Output error amplitude < ± 4 LSB around worst code.
Note 5 : Maximum jitter value obtained for single–ended clock input on the JTS8388B die (chip on board) : 200 fs.
(500 fs expected on TS8388BFS)
Note 6 : Digital output back termination options depicted in Application Notes figures 3,4,5 .
Note 7 : With a typical value of TD = 465 ps, at 1 GSPS, the timing safety margin for the data storing using the ECLinPS 10E452 output
registers from Motorola is of ± 315 ps, equally shared before and after the rising edge of the Data Ready signals (DR, DRB).
Note 8 : The clock inputs may be indifferently entered in differential or single–ended, using ECL levels or 4 dBm typical power level into the
50 Ω termination resistor of the inphase clock input.
(4 dBm into 50 Ω clock input correspond to 10 dBm power level for the clock generator.)
Note 9 : At 1GSPS, 50/50 clock duty cycle, TC2 = 500 ps (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate.
Note 10 : Specified loading conditions for digital outputs :
- 50 Ω or 75 Ω controlled impedance traces properly 50 / 75 Ω terminated, or unterminated 75 Ω controlled impedance traces.
- Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola.( e.g. : 10E452 ) ( Typical input parasitic
capacitance of 1.5 pF including package and ESD protections. )
Note 11 : Termination load parasitic capacitance derating values :
- 50 Ω or 75 Ω controlled impedance traces properly 50 / 75 Ω terminated : 60 ps / pF or 75 ps per additionnal ECLinPS load.
- Unterminated ( source terminated ) 75 Ω controlled impedance lines : 100 ps / pF or 150 ps per additionnal ECLinPS termination
load.
Note 12 :apply proper 50 / 75 impedance traces propagation time derating values : 6 ps / mm (155 ps/inch) for TSEV8388BF Evaluation Board.
Note 13 : Values for TOD and TDR track each other over temperature, ( 1 % variation for TOD - TDR per 100 oC. temperature variation ).
Therefore TOD - TDR variation over temperature is negligible. Moreover, the internal ( onchip ) and package skews between each
Data TODs and TDR effect can be considered as negligible.Consequently, minimum values for TOD and TDR are never more than
100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes about TOD - TDR variation
over temperature in section 7).
TS8388BFS
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Preliminary Beta Site
3.4. TIMING DIAGRAMS
TC1 TC2
TA= 250 ps TBC
XX
N+1
XN+2
X
N+3
N
Figure 1 : TS8388B TIMING DIAGRAM ( 1 GSPS CLOCK RATE )
Data Ready Reset , Clock held at LOW level
DIGITAL
OUTPUTS
(VIN, VINB )
Data Ready
(DR, DRB)
(CLK, CLKB)
X
N+5
TD1=TC1+TDR-TOD
= TC1-40 ps = 460 ps
ps
DATA
N-4 DATA
N-3 DATA N
DATA
N-1
DATA
N-2
TC=1000 ps
XX
N+4
TOD = 1360 ps
1360 ps
DRRB
1ns (min)
TDR = 1320 ps
TPD: 4.0 Clock periods
1000 ps
TRDR = 920 ps
N-1
TD2 = TC2+TOD-TDR
= TC2+40ps = 540 ps
TDR = 1320 ps
DATA
N-5 DATA
N+1
TC1 TC2
TA= 250ps TBC
XX
N+1
XN+2
XN+3
N
Figure 2 : TS8388B TIMING DIAGRAM ( 1 GSPS CLOCK RATE )
Data Ready Reset , Clock held at HIGH level
DIGITAL
OUTPUTS
(VIN, VINB )
Data Ready
(DR, DRB)
(CLK, CLKB)
XN+5
TD1=TC1+TDR-TOD
= TC1-40 ps = 460 ps
DATA
N-4 DATA
N-3 DATA N
DATA
N-1
DATA
N-2
TC = 1000 ps
X
X
N+4
TOD = 1360 ps
1360 ps
DRRB 1ns (min)
TDR = 1320 ps
TPD: 4.0 Clock periods
1000 ps
TRDR = 920ps
N-1
TD2 = TC2+TOD-TDR
= TC2+40ps = 540 ps
TDR = 1120 ps
DATA
N-5 DATA
N+1
TS8388BFS
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Preliminary Beta Site
3.5. EXPLANATION OF TEST LEVELS
D100 % wafer tested at +25°C (1)
I100% production tested at +25°C (1) (for packaged device).
II 100 % production tested at +25°C (1), and sample tested at specified temperatures
III Sample tested only at specified temperatures
IV Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at
specified temperature).
VParameter is a typical value only
VI 100 % production tested over specified temperature range.
Only MIN and MAX values are guaranteed (typical values are issuing from characterization results).
(1) Unless otherwise specified, all tests are pulsed tests : therefore Tj = Tc = Ta,
where Tj ,Tc and Ta are junction, case and ambient temperature respectively.
3.6. WAFER SCREENING
Parameter Temperature JTS8388B chip Unit
Min Max
DC Accuracy @ 50 MSPS / 10 MHz
25°C (2)
DNL 0.6 LSB
INL 0.8 LSB
No missing codes Guaranteed
AC Performance
50MSPS / 25MHz 25°C (2)
SNR 45 dB
ENOB 7.1 bit
(2) Unless otherwise specified, all tests are pulsed tests : therefore Tj = Tc = Ta,
where Tj ,Tc and Ta are junction, case and ambient temperature respectively.
TS8388BFS
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Preliminary Beta Site
3.7. FUNCTIONS DESCRIPTION
Name Function
VCC Positive power supply
VEE Analog negative power supply
VPLUSD Digital positive power supply
GND Ground
VIN, VINB Differential analog inputs
CLK, CLKB Differential clock inputs
<D0:D7>
<D0B:D7B> Differential output data port
DR ; DRB Differential data ready outputs
OR ; ORB Out of range outputs
GAIN ADC gain adjust
GORB Gray or Binary digital output select
DIOD/DRRB Die junction temp. measurement/
asynchronous data ready reset
VPLUSD = +0 V (ECL)
VPLUSD=+2.4V (LVDS)
VIN
VINB
CLK
CLKB
D0 → → D7
D0B →→ D7B
DR
16
VEE=-5V
VCC = +5 V
TS8388B
ORB
GND
GORB
GAIN
OR
DVEE=-5V
DIOD/
DRRB
DRB
3.8. DIGITAL OUTPUT CODING
NRZ (Non Return to Zero) mode, ideal coding : does not include gain, offset, and linearity voltage errors.
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