1998 Integrated Dev ic e Tec hnology , Inc .
◆High-performance embedded 64-bi t microprocessor
-64-bi t integer operations
-64-bi t registers
-100MHz, 133MHz, 150 MHz, 180MHz, and 200MHz
operat ion frequencies
◆High-performance DSP capability
-100 Million Integer Multiply-Accumulate Operations/sec
@ 200 MHz
-67 MFlops floating point operations @ 200MHz
◆High-performance microprocessor
-100 M Mul-Add/second at 200MHz
-67 MFLOP/s at 200MHz
->500,000 dhrystone (2.1)/sec capability at 200MHz
(265 dhrystone MIPS)
◆High level of integration
-64-bi t, 200 MHz integer CPU
-67MFlops single-precision floating-point unit
-8KB instruction cache; 8KB data cache
-Integ er multiply unit with 100M Mul -Add/sec
◆Low-power operation
-Active power management powers-down inactive units
-Standby mode
◆Upwardly software compatible with IDT RIS Control ler
Family
◆Large, eff icient on-chip caches
-Separate 8kB Instruction and 8kB Data caches
-Over 2400MB/sec bandwidth from internal caches
-2-set associative
-Write-back and write-through support
-Cache locking to facilitate deterministic response
◆Bus compatible with RC4000 family
-System interface provides bandwidth up t o 800 MB/S
-Direct interface to 32-bit w ide or 64-bit wide systems
-Synchroni zed to external reference clock for multi-master
operation
◆Improved real-time support
-Fast interrupt decode
-Optional cache locking
August 1998
DSC3149/2
The IDT logo is a registered trademark and ORION, RC4600, RC4650, RV4650, RC4700, RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
200 MIP S 64 -bit ORI ON C PU
64-bit register file
64-bit adder
Store A ligner
Logic Unit
Load aligner
High-Performance
Integer Multiply
Pipeline Control
FP register file
FP Add/Sub/ Cvt/
Pack/Unpack
FP Multiply
Pipeline Control
67MFL OPS Sin gle -Preci sion F PA
Div/Sqrt
32-/64-bit
Synchronized
System Interface
Address Translation/
Cache Attribute Control
Exception Management
Functions
System Control Coprocessor
Data Cache
Da ta Cac h e
Instruction Bus
Control Bus
Data Bus
Set A
(Lockable)
Set B
Instr uct ion Cac h e
Set B
Instruction Cache
Set A
(Lockable)
!
!!
!
"
""
"
#
##
#
The IDT79RC4650 is a low-cost member of the IDT Micropro-
cessor family, targeted to a variety of performance hungry
embedded applicati ons. The RC4650 continues the IDT tradition of
high-performance through high-speed pipelines, high-bandwidth
caches and bus i nterface, 64-bit architecture, and careful attention
to efficient control. The RC4650 reduces the cost of this perfor-
mance relative to the RC4700, by removing functional units that
are frequent ly unneeded for many embedded applications, such as
double-precision floating point arithmetic and a TLB.
The RC4650 adds features relative to the RC4700, reflective of
its target applications. These features enable system cost reduc-
tion (e.g. optional 32-bit system interface) as well as higher perfor-
mance for certain types of systems (e.g. cache locking, improved
real-time support, integer DSP capability).
The RC4650 supports a wide variety of embedded processor-
based applications, such as consumer game systems, multi-media
functions, internetworking equipment, switching equipment, and
printing systems. Upwardly software-compatible with the RC3000
family, and bus- and upwardly software-compatible with the IDT
RC4000/RC5000 family, the RC4650 will serve in many of the
same applicati ons, but, in addition supports other appli cati ons such
as those requiring integer DSP funct ions.
The RC4650 brings 64-bit performance levels to lower cost
systems. High performance is preserved by retaining large on- chip
caches that are two-way set associative, a streamlined high-speed
pipeline, high-bandwidth, 64-bit execution, and facilities such as
early restart for data cache misses. These techniques combine to
allow the system designer 3GB/sec aggregate bandwidth, 800 MB/
sec bus bandwidth, 265 Dhrystone MIPS, 67 MFlops, and 100 M
Multiply-add/second.
The RC4650 provides complete upward application-software
compatibility with the IDT79RC3000™ and IDT79RC4700™ fa milie s
of microprocessors.An array of development tools facilitates the
rapid development of RC4650-based systems, enabling a wide
variety of customers to take advantage of the high-performance
capabilities of the processor while maintai ning short time to market
goals.
The 64-bit computing capability of the RC4650 enables a wide
variety of capabilities previously limited by the lower bandwidth and
bit-manipulation rates inherent in 32-bit architectures. For example,
the RC4650 can perform loads and stores from cached memory at
the rate of 8-bytes every clock cycle, doubling the bandwidth of an
equivalent 32-bit processor. This capability, coupled with the high
clock rate for the RC4650 pipeline, enables new levels of perfor-
mance to be obtained from embedded systems.
This data sheet provides an overview of the features and architec-
ture of the RC4650 CPU. A more detailed description of the
processor is available in the IDT79RC4650 Processor Hardware
User’s Manual, available from IDT. Further information on develop-
ment support, applications notes, and complementary products are
also available fr om your local IDT sales representative.
The RC4650 family br ings a high- level of integration des igned for
high-performance computing. The key elements of the RC4650 are
briefly described below. A more detailed description of each of these
subsystems is available in the User’s Manual .
The RC4650 uses a 5-stage pipeline similar t o the IDT79RC3000
and the IDT79RC4700. The simplicity of this pipeline allows the
RC4650 to be lower cost and lower power than super- scalar or super-
pipelined processors. Unlike superscalar processors, applications
that have large data dependencies or that require a great deal of
load/stores can still achieve performance close to the peak
performance of the processor. Figure 2 shows the RC4650 pi peline.
The RC4650 implements the MIPS-III I nstruction Set Architecture
and is upwardly compatible with applications that run on the earlier
generation parts. The RC4650 includes the same additions to the
instruction set found in the RC4700 family of microprocessors,
targeted at improving performance and capability while maintaining
binary compatibility with ear lier RC3000 processors.
General Purpose Registers
63 0 Multiply/Divid e Reg is t e r s
0630
r1 HI (Accumulate HI)
r2 63 0
• LO (A ccumulate LO)
•
•Program Counter
• 63 310
r29 PC
Figure 1: CPU Regist ers
The extensions result in better code density, greater multi-
processing support, improved performance for commonly used
code sequences in operating system kernels, and fa ster execution
of floating-point intensive applications. All resource dependencies
are made transparent to the programmer, insuring transportability
among implementations of the M IPS instruction set architecture. In
addition, M IPS-III specifies new instructions defined to take advan-
tage of the 64-bit architecture of the processor.
Finall y, the RC4650 also implements additional instructions, which
are considered extensions to the MIPS-III architect ure. These instruc-
tions improve the multiply and multiply-add throughput of the CPU,
making it well suited to a wide variety of imaging and DSP applica-
tions. These extensions, whi c h use opcodes allocated by MIPS Tech-
nologies for this purpose, are supported by a wide variety of
development tools.
I01I 2I 1R 2R 1A 2A 1D 2D 1W 2W
I11I 2I 1R 2R 1A 2A 1D 2D 1W 2W
I21I 2I 1R 2R 1A 2A 1D 2D 1W •••
I31I 2I 1R 2R 1A 2A 1D •••
I41I 2I 1R 2R 1A •••
one cycle
! " !
#!$"% ! !&& !!
2A-2D Data cache access and load align
1D Data virtual- to-physical address translation
1D-2D Virtual-to-physical address trans lation
2R Register file r ead
2R Bypass calculation
2R Instruction decode
2R Branch address calculation
1A Issue or slip decision
1A-2A I nteger add, logical, shift
1A Data virt ual address calculation
2A Store align
1A Branch decision
2W Register file w rite
Figure 2: RC4650 Pi peline
The MIPS integer unit implements a load/store ar chitecture with
single cycle ALU operations (logical, shift, add, sub) and autono-
mous multiply/divide unit. The 64-bit register resources include: 32
general-purpose orthogonal integer registers, the HI/LO result
registers for the integer multiply/divide unit, and the program
counter. In addition, the on-chip floating-point co-processor adds
32 floating-point registers, and a floating-point control/status
register.
The RC4650 has thirty-two general-purpose 64-bit registers.
These regi sters are used for scalar int eger operations and address
calculation. The register file consists of two read ports and one
write port and i s full y bypassed to minimize operation latency in the
pipeli ne. Figure 1 illustrates the RC4650 Regist er File.
The RC4650 ALU consists of the integer adder and logic unit.
The adder performs address calculations in addition to arithmetic
operations, and the logic unit performs all logical and shift opera-
tions. Each of these units is highly optimized and can perform an
operation in a si ngle pipeline cycle.
The RC4650 uses a dedicated integer multiply/divide unit, opti-
mized for high-speed multiply and multiply-accumulate operation.
Table 1 shows the performance, expressed in terms of pipeline
clocks, achieved by the RC4650 integer multiply unit.
The MIPS-II I archit ecture defines that the results of a mul tiply or
divide oper ation are placed in t he H I and LO registers. The values
can then be transferred to the general purpose register file using
the MFHI /MFLO instructions.
'$ & '$!&
( ! % $! !
MULT/U, MAD/U 16 bit 3 2 0
32 bit 4 3 0
MUL 16 bit 3 2 1
32 bit 4 3 2
DMULT,
DMULTU any 6 5 0
DIV, DIVU any 36 36 0
DDIV, DDIVU any 68 68 0
Table 1: RC4650 In teger Multip ly Operati on
The RC4650 adds a new multiply instruction, “MUL”, which can
specify that the multiply results bypass the “Lo” register and are
placed immediately in the pr imary regi ster fi le. By avoidi ng the explicit
“Move-from-Lo” instruction required when using “Lo”, throughput of
multiply-intensive operat ions is inc reased.
An additional enhancement offered by the RC4650 is an atomic
“multiply-add” operation, MAD, used to perform multiply-accumulate
operations. This instruction multiplies two numbers and adds the
product to the current contents of the HI and LO registers. This oper-
ation is used in numerous DSP algorithms, and allow s the RC4650 to
cost reduce system s requiring a mix of DSP and contr ol functions.
Finally, aggressive implementation techniques feature low latency
for these operations along with pipelining to allow new operations to
be issued before a previous one has fully completed. Table 1 also
shows the repeat rate (peak issue rate), latency, and number of
processor stalls required for the various operations. The RC4650
performs automatic operand size detection to determine the size of
the operand, and im plements hardware interlocks to prevent overrun,
allowing this high-performance to be achieved with simple program-
ming.
The RC4650 incorporates an entire single-precision floating-point
co-processor on chip, including a floating-point register file and
execution units. The floating-point co-processor forms a “seamless”
interface with the integer unit, decoding and execut ing instructions in
parallel with the integer unit.
The RC4650’s floating- point unit directly implements single-preci-
sion floating-point operations. This enables the RC4650 to perform
functins such as graphics rendiering, without requiring extensive die
are or power consumption.
The RC4650 does not directly implement the double-precision
operations found in the RC4700. However, to maintain software
compatibility, the RC4650 will signal a trap when a double-precision
operation is initiated, allowing the requested function to be emulated
in software. Alternatively, the system architect could use a software
library emulation of double-precision functions, selected at compile
time, to elim inate the overhead associated with trap and emulation.
The RC4650 floating-point execution units perform single preci-
sion arithmetic, as specified in the I EEE Standard 754. The execution
unit is broken into a separate multiply unit and a combined add/
convert/divide/square r oot uni t. Overlap of m ult ipl ies and add/ subtr act
is supported. The multiplier is partially pipelined, allowing a new
multiply to begin every 6 cycl es.
As in the IDT79RC4700, the RC4650 maintains fully precise
floating-point exceptions while allowing both overlapped and pipe-
lined operations. Precise exceptions are extremely important in
mission-critical environments, such as ADA, and highly desirable for
debugging in any environm ent.
The floating-point unit’s operation set includes floating-point
add, subtract, multiply, divide, square root, conversion between
fixed-point and floating-point format, conversion among floating-
point for mats, and floating- point compare. These operations compl y
with IEEE Standard 754. Double precision operations are not
directly supported; attempts to execute double-precision floating
point operations, or refer directly to double-precision registers,
result in the RC4650 signalling a “trap” to the CPU, enabling
emulation of the requested function.
Table 2: gives the lat encies of some of the float ing- point instruc-
tions in internal processor cycles.
The floating-point register file is made up of thirty-two 32-bit
regi ster s. These registers are used as source or target regi ster s for
the singl e-precision operations.
References to these registers as 64-bit registers (as supported
in the RC4700) will cause a trap to be signalled.
The floating-point control register space contains two registers;
one for determining configuration and revision information for the
coprocessor and one for control and status information. Thes e are
primarily involved with diagnostic software, exception handling,
state saving and restoring, and contr ol of rounding modes.
'$!
! %
ADD 4
SUB 4
MUL 8
DIV 32
SQRT 31
CMP 3
FIX 4
FLOAT 6
ABS 1
MOV 1
NEG 1
LWC1 2
SWC1 1
Table 2: Floating-Point Operation
!
!!
!
"
""
"
#
##
#$
$$
$%
%%
%
The system control co-processor in the MIPS architecture is
responsible for the virtual to physical address translation and cache
protocols, the exception control system, and the diagnostics capa-
bility of the processor. In the MIPS architecture, the system control
co-processor (and thus the kernel software) is implementation depen-
dent.
In the RC4650, significant changes in CP0—relative to the
RC4700—have been implemented. These changes are designed to
simplify memory management, facilitate debug, and speed real-time
processing.
!
!!
!
"
""
"
The RC4650 incorporates all system control co-processor (CP0)
registers on-chip. These registers provide the path through which the
virtual memory system’s address translation is controlled, exceptions
are handled, and operating modes are controlled (kernel vs. user
mode, interrupts enabled or disabled, cache features). In addit ion, the
RC4650 includes registers to implement a real-time cycle counting
facility, which aids in cache diagnostic testing, assists in data error
detection, and facilitates software debug. Alternatively, this timer can
be used as the operating system reference timer, and can signal a
periodic interrupt.
Table 3 shows the CP0 registers of the RC4650.
)* )!* +
0 IBase Instruction address space base
1 IBound Instruction addres s space bound
2 DBase Data address space bas e
3 DBound Data addres s space bound
4-7, 10, 20-
25, 29, 31 — Not used
8 BadVAddr Virtual address on address exceptions
9 Count Count s every other cycle
11 Compare Generate interrupt when Count = Com-
pare
12 S tatus Miscellaneous control/status
13 Cause Exception/Interrupt informat ion
14 EPC Exception PC
15 PRId Processor ID
16 Conf ig Cache and system attributes
17 CAlg Cache att ributes for the eight 512MB
regions of the virtual address space
18 IWatch Instruction breakpoint virtual addres s
Table 3: RC4650 CPO Registers
&
&&
&
"
""
"
The RC4650 supports two modes of operation: user mode and
kernel mode. Ker nel mode operation is t ypicall y used for excepti on
handling and operating system kernel functions, including CP0
management and access to IO devices. In kernel mode, software
has access to the entire address space and all of the co-processor
0 registers, and can select whether to enable co-processor 1
accesses. The processor enters kernel mode at reset, and when-
ever an except ion is recognized.
User mode is typically used for applications programs. User
mode accesses are li mited to a subset of the virtual address space
and can be inhibited from accessing CP0 funct ions.
19 DWatch Data breakpoint virtual address
26 ECC Used in cache diagnostics
27 CacheErr Cache diagnostics
28 T agLo Cache index
30 ErrorEPC CacheErr or exception PC
0xFFFFFFFF
0xC0000000
Kernel virtual address space
(kseg2)
Unmapped, 1.0 GB
0xBFFFFFFF
0xA0000000
Uncached kernel physical address space
(kseg1)
Unmapped, 0.5GB
0x9FFFFFFF
0x80000000
Cached kerne l physical address space
(kseg0)
Unmapped, 0.5GB
0x7FFFFFF
0x00000000
User virtual address space
(useg)
Mapped, 2.0GB
Figure 3: Kernel/User Mode Vi rtual Addressing (32-bit mode)
)* )!* +
Table 3: RC4650 CPO Registers
'
''
'
(
((
(
The 4GB virtual address space of the RC4650 is shown in Figure
3. The 4 GB address space is divided into addresses accessible in
either kernel or user mode (kuseg), and addresses only accessible in
kernel mode (kseg2:0).
The RC4650 supports the use of multiple user tasks sharing
common virtual addresses, but mapped to separate physical
addresses. This facility is implemented via the “base-bounds” regis-
ters contained in CP0.
When a user vi rtual address is asserted (load, store, or inst ruction
fetch), the RC4650 compar es the virtual address with the contents of
the appropriate “bounds” register (instruction or data). If the virtual
address is “in bounds” , the value of the corresponding “base” register
is added to the virtual address to form the physical address for that
reference. If the address is not within bounds, an exception is
signalled.
This facility enables multiple user processes in a single physical
memory without the use of a TLB. This type of operation is further
supported by a number of development tools for the RC4650,
including real-time operating systems and “position independent
code.”
Kernel mode addresses do not use the base- bounds r egist ers, but
rather undergo a fi xed virtual- to-physical address translation.
)
))
) !
!!
!
To facilitate software debug, the RC4650 adds a pair of “watch”
registers to CP0. When enabled, these registers will cause the CPU
to take an exception when a “watched” address is appropriately
accessed.
'
''
'
The RC4650 also adds the capability to speed interrupt exception
decoding. Unlike the RC4700, which utili zes a single common excep-
tion vector for all exception types (including interrupts), the RC4650
allows kernel software to enable a separate interrupt exception
vector. When enabled, this vector location speeds interrupt
processing by allowing software to avoid decoding interrupts from
general purpose excepti ons.
(
((
(
"
""
"
To keep the RC4650’s high-performance pipeline full and oper-
ating effi ciently, the RC4650 incorporates on-chi p inst ruction and data
caches that can each be accessed in a single proc essor cycle. Each
cache has its own 64-bit data path and can be accessed in parallel.
The cache subsystem provides the integer and floating-point units
with an aggregate bandwidth of over 2400 MB per second at a pipe-
line clock frequency of 200MHz. The cache subsystem is similar in
construction to that found in the RC4700, although some changes
have been implemented. Table 6 is an overview of the caches found
on the RC4650.
(
((
(
The RC4650 incorporates a two-way set associative on-chip
instruction cache. This virtually indexed, physically tagged cache is
8KB in size and is parity protected.
Because the cache is virtually indexed, the virtual-to-physical
address translation occurs in parallel with the cache access, thus
further increasing performance by allowing these two operations to
occur simultaneously. The tag hol ds a 20-bit physi cal address and
valid bi t, and is parity protected.
The instruction cache is 64-bits wide, and can be refilled or
accessed in a single processor cycle. Instruction fetches require
only 32 bits per cycle, for a peak instruction bandwidth of 800MB/
sec at 200MHz. Sequential accesses take advantage of the 64-bit
fetch to reduce power dissipation, and cache miss refill, can write
64 bits- per-cycle to minim ize the cache miss penalty. The line size
is eight instructions (32 bytes) to maximize perf ormance.
In addition, the contents of one set of the instruction cache (set
“A”) can be “ locked” by setting a bit in a CP0 register. Locking the
set prevents its contents from being overwritten by a subsequent
cache miss; refill occurs then only i nto “set B”.
This operation effectively “locks” time-critical code into one 4kB
set, whil e allowing the other set to ser vice ot her instruction str eam s
in a nor mal f ashion. Thus, the benefits of cached performance are
achieved, w hile deterministic real-ti me response is preserved.
(
((
(
For fast, single cycle data access, the RC4650 includes an 8KB
on-chip data cache that is tw o-way set associ ative with a f ixed 32-
byte (eight words) line size. Table 4 lists the RC4650 cache
attributes.
The data cache is protected with byte parity and its tag is
protected with a single parity bit. It is virtually indexed and physically
tagged to allow simultaneous address translation and data cache
access
"!! !!
(
8KB 8KB
',!(!
2-way set asso cia -
tive 2-way set associa-
tive
(
32B 32B
&-
vAddr11..0 vAddr11..0
!,
pAddr31..12 pAddr31..12
. $ %
n.a. writeback /writethru
!
&
read sub-block order read sub-block order
write sequential write sequenti al
/ !
! !
entire line first word
0!%
per-word per-byte
! " 1,
set A set A
Table 4: RC4650 Cache Attributes
RC4650
Memory I/O
Controller
Control
Address
SCSI ENET
32 or 64
9
Boot
ROM DRAM
(80ns)
32 or 64
2
11
Figure 4: Typical RC4650 System Architect ure
2
The normal write policy is w riteback, which means that a store
to a cache li ne does not i mmediately cause memory to be updated.
This increases system performance by reducing bus traffic and
eliminating the bottleneck of waiting for each store operation to
finish before issuing a subsequent memory operation. Software
can however select write-through for certain address ranges, using
the CAlg register in CP0. Cache protocols supported for the data
cache are:
Uncached. Addresses in a memory area indicated as
uncached will not be read from the cache. Stores to such
addresses will be written directly to main memory, without
changing cache contents.
◆Writeback. Loads and inst ruction fetches will first search
the cache, reading mai n m emory only if the desired data is
not cache r esident . On data store operations, t he cache is
first searched to see if the target address is cache resident .
If it is resident, the cache contents will be updated, and the
cache line mar ked for later writeback. If the cache lookup
misses, the target line is first br ought into the cache before
the cache is updated.
◆W r ite-through with wri te al locate. Loads and instruction
fetches will first search the cache, reading main memory
only if the desired data is not cache resident. On data store
operations, the cache is fir st searched to see if the target
address is cache resident. If it is resident, the cache con-
tents will be updated and main memory w ill also be written;
the state of the “writeback” bit of the c ache line will be
unchanged. If the cache lookup misses, the tar get line is
first brought into the cache bef ore the cache is updated.
◆W rite-t hrough without writ e-all ocate. Loads and instruc-
tion fetches w ill first search the cache, reading mai n mem-
ory only if t he desired data is not cache resident . On data
store operations, the cache is first searched to see i f the
target address is cache resident. If it is resident, the cache
contents will be updated, and the cache line marked for
later w riteback. If the cache lookup misses, then only main
memory is written.
Associated with the Data Cache is the store buffer. When the
RC4650 executes a Store instruction, this single-entry buffer gets
written with the store data while the tag comparison is performed. If
the tag matches, then the data is written into the Data Cache in the
next cycle that the Data Cache is not accessed (the next non-load
cycle). The store buffer allows the RC4650 to execute a store every
processor cycle and to perform back-to-back stores without penalty.
*
**
*
)
))
)+
++
++
++
+
Writes to external memory, whether cache miss writebacks or
stores to unc ached or write-through addresses, use the on-chip write
buffer. The write buffer holds up to four address and data pairs. The
entire buffer is used for a data cache writeback and allows the
processor to proceed in parallel w ith memory update.
!
!!
!
"
""
"
+
++
+
The RC4650 supports a 64-bit system interface that is bus
compatible with the RC4700 system interface. In addition, the
RC4650 supports a 32-bit system interface mode, allowing the CPU
to interf ace directly with a lower cost memory system.
The interface consists of a 64-bit Address/Data bus with 8 check
bits and a 9-bit com mand bus protected with parity. In addition, there
are 8 handshake signals and 6 interrupt inputs. The interface has a
simple timing specification and is capable of transferring data
between the pr ocessor and memory at a peak r ate of 800MB/sec.
Figure 4 shows a typical system using the RC4650. In this
example two banks of DRAMs are used to supply and accept data
with a DDxxDD data pattern.
The RC4650 clocking interface allows the C PU to be easily mated
with external reference clocks. The CPU input clock is the bus r efer-
ence clock, and can be between 25 and 100MHz (somewhat depen-
dent on maximum pipeline speed for the CPU).
An on-chip phase-locked-loop generates the pipeline clock from
the system interface clock by multiplying it up an amount selected at
system reset. Supported multipliers are values 2 through 8 i nclusive,
allowing systems to implement pipeline clocks at significantly higher
frequency than the system interface clock.
MasterClock
SysAD Addr Data0 Data1 Data2 Data3
SysCmd Read CData CData CData CEOD
ValidOut
ValidIn
RdRdy
WrRdy
Release
Figure 5: RC4650 Block Read Request (64-bit interface option)
!
!!
!
"
""
"
,
,,
,
The 64-bit System Address Data (SysAD) bus is used to
transfer addresses and data between the RC4650 and the rest of
the system. It i s protected w ith an 8-bit parity check bus, SysA DC.
When initialized for 32-bit operation, SysAD can be viewed as a
32-bi t multiplexed bus, w it h 4 parity check bits.
The system interface is configurable to allow easier interfacing
to memory and I/O systems of varying frequencies. The bus
frequency and reference timing of the R C4650 are tak en from the
input clock. The rate at which the CPU transmi ts dat a to the system
interface is pr ogrammable via boot ti me mode control bit s. The r ate
at which the processor receives data is fully controlled by the
external device. Therefore, either a low cost interface requiring no
read or write buffering or a faster, high performance interface can
be designed to com municate with the RC 4650. Again, the system
designer has the flexibility to make these price/performance trade-
offs.
!
!!
!
"
""
"
""
""""
""
,
,,
,
The RC4650 interfac e has a 9-bit System Command (SysCmd)
bus. The command bus indicates whether the SysAD bus carries
an address or data. If the SysAD carries an address, then the
SysCmd bus al so indi cates what type of transaction is to t ake place
(for example, a read or write). If the SysAD carries data, then the
SysCmd bus also gives information about the data (for example,
this i s the last data word transmitted, or the cache state of this data
line is clean exclusive). The SysCmd bus is bidirectional to suppor t
both processor requests and external requests to the RC4650.
Processor requests are initiated by the RC4650 and r esponded to
by an external device. External requests are issued by an external
device and require the RC4650 to respond.
The RC4650 supports singl e datum (one to eight byte) and 8-word
block transfers on the SysAD bus. In the case of a single-datum
transfer, the low-order 3 address bits gives the byte address of the
transfer, and the SysCmd bus indicates the number of bytes being
transferred. The choice of 32- or 64-bit wide system i nterface dictates
whether a cache line block transaction requires 4 double word data
cycles or 8 single word cycles, and whether a single datum transfer
larger than 4 bytes needs to be broken into two smaller transfers.
-
--
-
(
((
(.
..
.
!
!!
!
There are six handshake s ignals on the system interface. Two of
these signals, RdRdy* and WrRdy*, are used by an external device to
indicate to the RC4650 whether it can accept a new read or write
transaction. The RC4650 samples these signals before deasserting
the address on read and write requests.
ExtRqst* and Release* are used to transfer control of the SysAD
and SysCmd buses between the processor and an external device.
When an external device needs to control the interface, it asserts
ExtRqst*. The R C4650 responds by asser ting Release* to release the
system int erface to slave state.
ValidOut* and ValidIn* are used by the RC4650 and the external
device respectively to i ndicat e that there is a valid command or data
on the SysAD and SysCmd buses. The RC4650 asserts ValidOut*
when it is dr iving these buses with a valid com mand or data, and t he
external device dr ives ValidIn* when it has control of the buses and is
driving a valid comm and or data.
MasterClock
SysAD Addr Data0 Data1 Data2 Data3
SysCmd
ValidOut
ValidIn
RdRdy
WrRdy
Release
Write CData CData CData CEOD
Figure 6: RC4650 Block Write Request (64-bit system interface)
/
//
/
!
!!
!
"
""
"
+
++
+
The RC4650 requires a non-overlapping system interface,
compatible with the RC4700. This means that only one processor
request may be outstanding at a time and that the request must be
serviced by an external device before the RC4650 issues another
request. The RC4650 can issue read and write requests to an
external device, and an external device can issue read and write
request s to the RC 4650.
The RC4650 asserts ValidOut* and simultaneously drives the
address and r ead command on the SysAD and SysCmd buses. If
the system interface has RdRdy* or Read transactions asserted,
then the processor tristates its drivers and releases the system
interface to slave state by as serting Release*. The external device
can then begin sending the data to the RC4650.
Figur e 5 shows a processor block r ead request and t he external
agent read response. The read latency is 4 cycles (ValidOut* to
ValidIn*), and the response data pattern is DDxxDD. Figure 6
shows a pr ocessor block write.
*
**
*
*
**
*
The RC4700 and the RC4650 implement additional w rite proto-
cols designed to improve performance. This implementation
doubles t he effective write bandwidth. The wr ite re-issue has a high
repeat rate of 2 cycles per write. A write issues if WrRdy is
asserted 2 cycles earlier and is still asserted at the issue cycle. If it
is not still asserted, the last write re-issues again. Pipelined writes
have the same 2-cycle per write repeat rate, but can issue one
more write after WrRdy de-asserts. They still follow the issue rule
as R4x00 mode for other writes.
0
00
0
The RC4650 responds to requests issued by an external
device. The requests can take several forms. An external device
may need to supply data in response to an RC4650 read request
or it may need to gain control over the system interface bus to
access other resources whic h may be on that bus.
The following is a list of the supported external requests:
◆Read Response
◆Null
,
,,
,
1"
1"1"
1"
&
&&
&
Fundamental oper ational modes for the processor are ini ti alized
by the boot-time mode control interface. The boot-time mode
control interface is a serial interface operating at a very low
fr equency (MasterClock divided by 256). The low-frequency opera-
tion allows the initialization information to be kept in a low-cost
EPROM; alternatively the twenty -or-so bits could be generated by
the system interface ASIC or a si mple PAL.
To initialize all fundamental, operational modes, immediately
after the VCCOK signal is asserted, the pr ocessor reads a ser ial bit
stream of 256 bits. After initialization is complete, the processor
continues to dr ive the serial clock output, but no further initiali zati on
bits are read.
,
,,
,
1"
1"1"
1"
The boot-ti me serial mode stream is defi ned in Table 5. Bit 0 is the
bit presented to the processor when VCCOK is asserted; bit 255 i s t he
last.
2
22
2
"
""
"
CP0 is also used to control the power management for the
RC4650. This is the standby m ode and it can be used to reduce the
power consumption of the internal core of the CPU. The standby
mode is entered by executing the WAIT instruction with the SysAD
bus idle and i s exited by any interrupt.
!
!!
!
)
))
)
&
&&
&
The RC4650 provides a means to reduce the amount of power
consumed by the internal core when the CPU would otherwise not be
performing any useful operations. This is known as “Standby Mode.”
!
!!
!
)
))
)
Executing the WAIT instruction enables interrupts and enters
Standby mode. When the WAIT inst ruction finishes the W pipe-stage,
if the SysAd bus is currently idle, the internal clocks will shut down,
thus freezing the pipeline. The PLL, internal timer, and some of the
input pins (Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*) will
continue to run. If the conditions are not correct when the WAIT
instruction finishes the W pipe-stage (i.e. the SysAd bus is not idle),
the WAI T is treated as a N OP.
Once the CPU is in Standby Mode, any interrupt, including the
internally generated timer interrupt, will cause the CPU to exit
Standby Mode.
The RC4650 utilizes special packaging techniques to improve
the thermal properties of high-speed processors. The RC4650 is
packaged using cavity down packaging in a 208-pin MQ UAD.
The RC4650 utilizes the MQUAD package (the “MS” package),
which i s an all-alumi num package with the die at tached t o a nor mal
copper lead frame mounted to the aluminum casing. Due to the
heat-spreading effect of the aluminum, the MQUAD package
allows for an efficient thermal transfer between the die and the
case. The aluminum offers less internal resistance from one end of
the package to the other, reducing the temperature gradient across
the package and t herefor e pr esenting a great er area for convecti on
/&
$
0 Res erved (must be zero)
4..1 Writeback data rate:
64-bit 32-bit
0 → D0 → W
1 → DDx 1 → WWx
2 → DDxx 2 → WWxx
3 → DxDx 3 → WxWx
4 → DDxxx 4 → WWxxx
5 → DDxxx x 5 → WWxxxx
6 → DxxDx x 6 → WxxWxx
7 → DDxxx xxx 7 → WWxxxxxx
8 → DxxxD xxx 8 → WxxxWxxx
9-15 reserved 9-15 reserved
7. .5 Clock multi p lie r:
0 → 2
1 → 3
2 → 4
3 → 5
4 → 6
5 → 7
6 → 8
7 reserved
80 → Lit tle endian
1 → Big endian
10..9 00 → RC4000 compatible
01 → reserved
10 → pipelined writes
11 → write re-issue
11 Disable t he t i me r interru pt on Int[5]
12 0 → 64-bit system interface
1 → 32-bit syste m interface
14..13 Output driver strength:
10 → 100% strength (fastest)
11 → 83% strength
00 → 67% strength
01 → 50% strength (slow est)
255..15 Must be zero
Table 5: Boot-time mode stream
and conduction to the PCB for a given temperature. Even nominal
amounts of airflow will dramatically reduce the junction temperature
of the die, r esult ing in cooler operation.
The RC4650 is guaranteed in a case temperature range of 0° to
+85° C. The type of package, speed (power) of the device, and
airflow conditions affect the equivalent ambient temperature condi-
tions that wi ll meet thi s specification.
The equivalent allowable ambient temperature, TA, can be calcu-
lated using the thermal resistance from case to ambient (∅CA) of the
given package. The following equation relates ambient and case
temperatures:
TA = T C - P * ∅CA
where P is the m aximum power consum ption at hot t emperature,
calculated by using the maximum I CC specif ication for the device.
Typical values f or ∅CA at various airflows are shown in Table 6.
Note that the RC4650 implements advanced power management
to substantially reduce the average power dissipation of the device.
This operation is described in the IDT79RC4640 and IDT79RC4650
RISC Processor Hardware User’s M anual.
(
((
(
!
!!
!
")
")")
")
3
33
34
44
445
4545
456
66
6
AC Electrical Characteristics:
- In System Interface Parameters tables (RC4650 and RV4650),
Data Setup and D ata Hold minimums changed.
(
((
(
(
((
( 344
344344
34476
7676
76
Features:
- A dded 150 MHz operation frequency.
- Upgraded spec to “f inal .”
(
((
(
(
((
( 344
344344
34486
8686
86
- A dded 200 MHz operation frequency.
(
((
(
344
344344
3448
88
8
Features:
- Changed dhrystone/sec reference
Power Consumption ( RV4650):
- Upgraded System Condition Icc active parameters
C l o ck Para met e rs:
- Changed MasterClock per iod to 200MHz
∅
3
45*6 2
208 MQUAD 21 13 10 9 8 7
Table 6: Thermal Resistance (∅CA) at Various Airflows
The following is a list of interface, interrupt, and miscellaneous pins available on the RC4650. Pins marked with one asterisk are active
when low.
0 )!* %$
$
System interface:
ExtRqst* Input External reques t
Signals that the system int erface needs to submit an external request.
Release* Output Release interface
Signals that the processor is releasing the system interface to s l ave state
RdRdy* Input Read Ready
Signals that an ext er nal agent can now accept a proces sor read.
WrRdy* I nput Wr ite Ready
Signals that an ext er nal agent can now accept a proces sor write reques t.
ValidIn* Input Valid Input
Signals that an external agent is now driving a v alid address or data on the Sy sAD bus and a valid c om -
mand or data identifier on t he SysCmd bus .
ValidOut* Output Valid output
Signals t hat the processor is now driving a valid addres s or data on the SysAD bus and a valid command
or data identifier on t he SysCmd bus.
SysAD(63:0) Input/Output Syst em address/data bus
A 64-bit address and data bus for communicatio n between the processor and an external agent.
SysADC(7:0) Input/Output System addres s/data check bus
An 8-bit bus containing parity chec k bits for the SysAD bus during data bus cycles.
SysCmd(8:0) Input/Output System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an external agent.
SysCmdP Input/Output Reserved system command/data identifier bus parit y
For the RC4650 this signal is unused on input and zero on output.
Clock/control interface:
MasterClock Input Master clock
Master clock input used as the sys t em i nterface referenc e cloc k. A ll output timings are relat iv e t o this input
clock. Pipeline operation frequency is derived by mult iply ing this clock up by the factor selected during
boot initialization.
VCCP Input Quiet VCC for PLL
Quiet V CC for the internal phase locked loop.
VSSP Input Quiet VSS for PLL
Quiet V SS for the internal phase locked loop.
Int erru pt in te rfa c e :
Int*(5:0) Input Interrupt
Six general processor interrupts, bit-wise ORed with bit s 5:0 of the int erru pt register.
NMI* Input Non-m askab le interrupt
Non-m askab le interrupt, ORed with bit 6 of the interrupt register.
!
!!
!
"#
"# "#
"#
$
$$
$
(1)
NOTES TO ABSOLUTE MAXIMUM RATING TABLE:
1. Stresses greater than those listed under ABSOLUTE M AXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at t hes e or any other condit i ons abov e tho se indi cated in th e operat ional sectio ns of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affec t reliab ility.
2. VIN mini mum = –2.0 V for pulse wi dth less than 15n s. VIN should not exc eed VCC +0.5 Volts.
3. When VIN < 0V or VIN > V CC
4. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds .
$
$$
$
Initi a lization interfa c e :
VCCOk Input VCC is OK
When asserted, this signal indicates to the RC4650 that the power supply has been above Vcc minimum
for m ore than 100 milliseconds and will r emain stable. The assertion of VCCOk initiates the reading of the
boot-time mode control serial s tream.
ColdReset* Input Cold reset
This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted syn-
chronously wi th MasterCloc k .
Reset* Input Reset
This s ignal must be asserted for any reset sequence. It may be asserted synchronously or asynchro-
nously for a cold reset, or synchronously to init iate a warm reset . Reset must be de-asserted synchro-
nously with MasterClock.
ModeClock Output Boot mode clock
Serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six.
ModeIn Input Boot mode data in
Serial boot- mode data input.
%* !,
78
±
9 8
78
±
9 8
78
±
9 :
** ! ** ! &!
VTERM Terminal Voltage wit h respect to GND –0.5(2) to +7.0 –0.5(2) to +4.6 –0.5 (2) to +4 .6 V
TCOperating Temperature(case) 0 to +85 0 to +85 -40 to +85 °C
TBIAS Case Temperature Under Bias –55 to +125 –55 to +125 –55 to +125 °C
TSTG Storage Temperature –55 to +125 –55 to +125 –55 to +125 °C
IIN DC Input Current 20 (3) 20(3) 20(3) mA
IOUT DC Output Current 50 (4) 50(4) 50(4) mA
;!& *$! ;) 8
8
8
Commercial 0°C to +85°C (Case) 0V 5. 0V±5% 3.3V±5%
Indus trial -40 + 85 °C (Case) 0V N/A 3.3V±5%
0 )!* %$ $
%
% %
%
$%
$%$%
$%
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(VCC = 5.0±5%, TCASE = 0°C to + 8 5 °C)
*
* *
*
%
%%
%
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&'()&'()
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0!!* /<( /<( &
/** /!-** /** /!-**
VOL — 0.1V — 0.1V |IOUT|= 20uA
VOH VCC - 0.1V — VCC - 0.1V —
VOL — 0.4V — 0.4V |IOUT|= 4mA
VOH 2.4V — 2.4V —
VIL –0.5V 0.2VCC –0.5V 0.2VCC —
VIH 2.0V VCC + 0.5V 2.0V VCC + 0.5V —
IIN —±10uA — ±10uA 0 ≤ VIN ≤ VCC
CIN — 10pF — 10pF —
COUT — 10pF — 10pF —
I/OLEAK — 20uA — 20uA Input/Output Leakage
0!!* /<( /<( &
%$ !
(9)
/!- %$ !
(9)
/!-
System
Condition: 100/50MHz 133/44MHz —
ICC standby — 75 mAb—100 mA
bCL = 0pF(8)
— 150 mAb—200 mA
bCL = 50pF
active,
64-bit bus
option
700 mAb900 mAb900 mAb950 mA bCL = 0pF
No SysAd activity(8)
800 mAb1000 mAb1000 mAb1100 mAbCL = 50pF
R4x00 compatible writes,
TC = 25oC
800 mAb1200 mAa1000 mAb1350 mAaCL = 50pF
Pipelined writes or write re-
issue,
TC = 25oC(8)
a. These are the specifications IDT tests to insure compliance.
b. T hese are not tested. They are the result s of engineering analysis and are provided f or reference onl y.
%
% %
%
$
$$
$
%
%%
%
&'()
&'()&'()
&'()
(VCC=5.0V ± 5%; TCASE = 0°C to +85 °C)
.
..
.
"
""
"
9
99
9:;5
:;5:;5
:;5$
$$
$
NOTES TO RC4650/RV4650 AC/DC ELECTRI CAL CHARACTE RIS TI C TABLES:
5. Operation of the RC4650/RV4650 is only guaranteed with the Phase Loc k Loop enabled.
6. Timings are measured f rom 1.5V of the cloc k to 1.5V of the signa l.
7. Capacitiv e load f or all outpu t timin gs is 50pF.
8. Guaranteed by design.
9. Typica l integer instruction mix and cache miss rates.
+
++
+
%
%%
%
&'()
&'()&'()
&'()
(6)
0!!* %* &
/<(
/<( :
/ /!- / /!-
Pipeline clock frequency PClk 50 100 50 133 MHz
MasterClock HIGH tMCHIGH Transition ≤ tMCRise/Fall 4—3—ns
MasterClock LOW tMCLOW Transition ≤ tMCRise/Fall 4—3—ns
MasterCloc k Frequency(5) —— 25502567MHz
MasterClock Period tMCP — 20401540ns
Clock Jit ter for MasterClock tJitterIn(8) ——±250 — ±250 ps
MasterClock Ri se Time tMCRise(8) — —5—4ns
MasterClock Fall Time tMCFall(8) — —5—4ns
ModeClock Period tModeCKP(8) — — 256*
tMCP
— 256*
tMCP
ns
0!!* %* &
/<(
/<( :
/ /!- / /!-
Data Output(7) tDM= Min
tDO = Max mode14..13 = 10 (fastest) 1.0(8) 91.0
(8) 9ns
mode14..13 = 01 (slowest) 2.0(8) 12 2.0 12 ns
Data Output Hold tDOH* mode14..13 = 10 (fastest) 1.0 — 1.0 — ns
Data Setup tDS trise = 5ns
tfall = 5ns 5.5 — 4.5 — ns
Data Hold tDH 2 — 1.5 — ns
* 25pf loading on ext ernal output signals, f astest settings
,
,,
,
- +
- +- +
- +
%
%%
%
&'
&'&'
&'(
((
()
))
)
0!!* %* &
/<(
/<( :
/ /!- / /!-
Mode Data Setup tDS — 3 — 3 — Master Clock Cycle
Mode Data Hold tDH — 0 — 0 — Master Clock Cycle
%
%%
%
.
..
.
$
$$
$
&'()
&'()&'()
&'()
(VCC = 3.3±5%, TCASE = 0°C to +85°C)
0!!* 8 /<( 8 /<( &
/** /!-** /** /!-**
VOL — 0.1V — 0.1V |IOUT|= 20uA
VOH VCC - 0.1V — VCC - 0.1V —
VOL — 0.4V — 0.4V |IOUT|= 4mA
VOH 2.4V — 2.4V —
VIL –0.5V 0.2VCC –0.5V 0.2VCC —
VIH 0.7VCC VCC + 0.5V 0.7VCC VCC + 0.5V —
IIN —±10uA — ±10uA 0 ≤ VIN ≤ VCC
CIN — 10pF — 10pF —
COUT — 10pF — 10pF —
I/OLEAK — 20uA — 20uA Input/Out put
Leakage
0!!* 8 /<( 8 2/<( 8 /<( &
/** /!-** /** /!-** /** /!-**
VOL — 0.1V — 0.1V — 0.1V |IOUT|= 20uA
VOH VCC - 0.1V — VCC - 0.1V — V CC - 0.1V —
VOL — 0.4V — 0.4V — 0.4V |IOUT|= 4mA
VOH 2.4V — 2.4V — 2.4V —
VIL –0.5V 0.2VCC –0.5V 0.2VCC –0.5V 0.2VCC —
VIH 0.7VCC VCC + 0.5V 0.7VCC VCC + 0.5V 0.7VCC VCC + 0.5V —
IIN —±10uA — ±10uA — ±10uA 0 ≤ VIN ≤ VCC
CIN — 10pF — 10pF — 10pF —
COUT — 10pF — 10pF — 10pF —
I/OLEAK — 20uA — 20uA — 20uA Input/O utput
Leakage
2
*
* *
*
%&'()
%&'()%&'()
%&'()
0!!* 8 /<( 8 /<( &
%$ !
(9)
/!- %$ !
(9)
/!-
System Condition 100/50MHz 133/67MHz —
ICC
standby — 50 mAb— 60 mAbCL = 0pF (8)
— 100 mAb— 110 mAbCL = 50pF
active,
64-bit bus
option
475 mAb600 mAb625 m Ab700 m AbCL = 0pF , No SysAd
activity(8)
550 mAb675 mAb700 m Ab800 m AbCL = 50pF R4x00
|compat ible writes
TC = 25oC
550 mAb800 mAa700 m Ab900 m AaCL = 50pF Pipelined
writes or Write re-issue,
TC = 25oC(8)
a. These are the specifi cations IDT tests to insure compliance.
b. These are not tested. They are the result of engineering analysi s and are provided for reference only.
0!!* 8 /<( 8 2 /<( 8 /<( &
%$ !
(9)
/!- %$ !
(9)
/!- %$ !
(9)
/!-
System Condit ion 150/ 75MHz 180/60MHz 200/67MHz —
ICC
standby — 60mAb— 60mAb— 60mAbCL = 0pF (8)
— 110mAb— 110mAb— 110mAbCL = 50pF
active,
64-bit bus
option
700 mAb800mAb855 mAb900mAb925mAb1000mAbCL = 0pF, No SysAd
activity(8)
850mAb900mAb930mAb1000mAb1000mAb1100mAbCL = 50pF R4x00
|compatible wri tes
TC = 25oC
850mAb1000mAa930mAb1200mAa1000mAb1300mAaCL = 50pF Pipelined
writes or Write re-issue,
TC = 25oC(8)
a. These are t he specifications IDT tests to insur e compliance.
b. These are not tested. They are the resu lt of engineering analysis and are provided for reference only.
%
% %
%
.
..
.
$%&'()
$%&'() $%&'()
$%&'()
(VCC=3.3V ± 5%; TCASE = 0°C to +85°C)
/
//
/
%
%%
%
&'
&'&'
&'(
((
()
))
)
0!!* %* &
8
/<( 8
/<( :
/ /!- / /!-
Pipeline cl ock
Frequency PClk 50 100 50 133 MHz
MasterClock HIGH tMCHIGH Transition ≤ tMCRise/Fall 4— 3 — ns
MasterClock LOW tMCLOW Transition ≤ tMCRise/Fall 4— 3 — ns
MasterClock
Frequency(5) ——25502567MHz
MasterClock Period tMCP —20401540ns
C loc k Ji tt er for
MasterClock tJitterIn(1) ——±250 — ±250 ps
MasterClock Rise Time tMCRise(1) ——5—4ns
MasterClock Fall Time t MCFall(1) ——5—4ns
ModeCloc k Period tModeCKP(1) — — 256*
tMCP
— 256*
tMCP
ns
0!!*
8
/<( 8
2/<( 8
/<( :
/ /!- / /!- / /!-
Pipeline clock
Frequency 50 150 50 180 50 200 MHz
MasterClock HIGH 3 — 3 — 3 — ns
MasterClock LOW 3 — 3 — 3 — ns
MasterClock
Frequency(5) 25 75 25 90 25 100 MHz
MasterClock Period 13. 3 40 11.1 40 10 4 0 ns
Clock Ji t ter for
MasterClock —±250 — ±250 — ±250 ps
MasterClock Rise Ti m e — 4 — 4 — 4 ns
MasterClock Fall Time — 4 — 4 — 4 ns
ModeClock Period — 256*
tMCP
— 256*
tMCP
— 256*
tMCP
ns
+
+ +
+
%
%%
%
&'()
&'()&'()
&'()
(6)
,-
,- ,-
,-
+
++
+
%&'()
%&'()%&'()
%&'()
0!!* %* &
8
/<( 8
/<( :
/ /!- / /!-
Data Output(7) tDM= Min
tDO = Max mode14..13 = 10 (fastest) 1. 0(1) 91.0
(1) 9ns
mode14..13 = 01 (slowest) 2.0(1) 10 2.0(1) 10 ns
Data Output Hold tDOH* mode14..13 = 10 (fastest) 1.0 — 1.0 — ns
Data Set up tDS trise = 5ns
tfall = 5ns 6—6—ns
Data Hol d tDH 3—3—ns
* 25pf loading on external output signals, fastest s ettings.
0!!* %* &
8
/<( 8
2/<( 8
/<( :
/ /!- / /!- / /!-
Data Output(7) tDM= Min
tDO = Max mode14..13 = 10 (f astest) 1.0(1) 91.0
(1) 91.0
(1) 9ns
mode14..13 = 01 (slowest) 2.0(1) 12 2.0(1) 12 2.0(1) 12 ns
Data Output Hold tDOH* mode14..13 = 10 (fastest) 1.0 — 1.0 — 1.0 — ns
Data Setup tDS trise = 5ns
tfall = 5ns 6—6—6—ns
Data Hold tDH 3—3—3—ns
* 25pf loading on ex ternal output signals, fastest settings.
0!!* %*
&
8
/<( 8
/<( :
/ /!- / /!-
Mode Data Setup tDS — 3 — 3 — Master Clock Cycle
Mode Data Hold tDH — 0 — 0 — Master Clock Cycle
0!!* %*
8
/<( 8
2 /<( 8
/<( :
/ /!- / /!- / /!-
Mode Data Setup tDS 3 — 3 — 3 — Master Clock Cycle
Mode Data Hold tDH 0 — 0 — 0 — Master Clock Cycle
+
+ +
+
% 0)1- "2
% 0)1- "2% 0)1- "2
% 0)1- "23
33
3
104
105
1208 156
157
53
52
MS208
Top View
&'() "
&'() "&'() "
&'() "2
22
23
33
3
/$
/$/$
/$
-4
-4 -4
-4
0 + 0 + 0 + 0 +
1 N.C. 53 N.C. 105 N.C. 157 N.C.
2 N.C. 54 N.C. 106 N.C. 158 N.C.
3 N.C. 55 N.C. 107 N.C. 159 SysAD59
4 N.C. 56 N.C. 108 N.C. 160 ColdReset*
5 N.C. 57 SysCmd2 109 N.C. 161 SysAD28
6 N.C. 58 SysAD36 110 N.C. 162 VCC
7 N.C. 59 SysAD4 111 N.C. 163 VSS
8 N.C. 60 SysCmd1 112 N.C. 164 SysAD60
9N.C. 61V
SS 113 N.C. 165 Reset*
10 SysAD11 62 VCC 114 SysAD52 166 SysAD29
11 VSS 63 SysAD35 115 ExtRqst* 167 SysAD61
12 VCC 64 SysAD3 116 VCC 168 SysAD30
13 SysCmd8 65 SysCmd0 117 VSS 169 VCC
14 SysAD42 66 SysAD34 118 SysAD21 170 VSS
15 SysAD10 67 VSS 119 SysAD53 171 SysAD62
16 SysCmd7 68 VCC 120 RdRdy* 172 SysAD31
17 VSS 69 SysAD2 121 Modein 173 SysAD63
18 VCC 70 Int5* 122 SysAD22 174 VCC
19 SysAD41 71 SysAD33 123 SysAD54 175 VSS
20 SysAD9 72 SysAD1 124 VCC 176 VCCOK
21 SysCmd6 73 VSS 125 VSS 177 SysADC3
22 SysAD40 74 VCC 126 Release* 178 SysADC7
23 VSS 75 Int4* 127 SysAD23 179 N.C.
24 VCC 76 SysAD32 128 SysAD55 180 N.C.
25 SysAD8 77 SysAD0 129 NMI* 181 N.C.
26 SysCmd5 78 Int3* 130 VCC 182 N.C.
27 SysADC4 79 VSS 131 VSS 183 N.C.
28 SysADC0 80 VCC 132 SysADC2 184 N.C.
29 VSS 81 Int2* 133 SysADC6 185 VCCP
30 VCC 82 SysAD16 134 SysAD24 186 VSSP
31 SysCmd4 83 SysAD48 135 VCC 187 MasterClock
32 SysAD39 84 Int1* 136 VSS 188 VCC
33 SysAD7 85 VSS 137 SysAD56 189 VSS
34 SysCmd3 86 VCC 138 SysAD25 190 SysADC5
35 VSS 87 SysAD17 139 SysAD57 191 SysADC1
36 VCC 88 SysAD49 140 VCC 192 VCC
*N.C. pins should be left floating for maximum flexibility and compatibility with future designs.
37 SysAD38 89 Int0* 141 VSS 193 VSS
38 SysAD6 90 SysAD18 142 N.C 194 SysAD47
39 ModeClock 91 VSS 143 SysAD26 195 SysAD15
40 WrRdy* 92 VCC 144 SysAD58 196 SysAD46
41 SysAD37 93 SysAD50 145 N.C. 197 VCC
42 SysAD5 94 ValidIn* 146 VCC 198 VSS
43 VSS 95 SysAD19 147 VSS 199 SysAD14
44 VCC 96 SysAD51 148 SysAD27 200 SysAD45
45 N.C. 97 VSS 149 N.C. 201 SysAD13
46 N.C. 98 VCC 150 N.C. 202 SysAD44
47 N.C. 99 ValidOut* 151 N.C. 203 VSS
48 N.C. 100 SysAD20 152 N.C. 204 VCC
49 N.C. 101 N.C. 153 N.C. 205 SysAD12
50 N.C. 102 N.C. 154 N.C. 206 SysCmdP
51 N.C. 103 N.C. 155 N.C. 207 SysAD43
52 N.C. 104 N.C. 156 N.C. 208 N.C.
0 + 0 + 0 + 0 +
Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet, to improve design or performance and to supply the best product possible
Integr ated Device Technology, Inc.
2975 Stender Way, Santa Clara, CA 95054-3090 Telephone: (408) 727-6116 Fax (408) 492-8674
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IDT 79 YY XXXX 999 A A
__________ ______ ____ _____ _____
Operating Device Speed Package Temp range/
Voltage Type Process
Blank
MS
100
133
4650
R
RV
Commercial
208-Pin MQUAD
100 MHz PClk
133 MHz PClk
64-bit RI SC Microprocessor for
Embedded Systems
5.0+/-5%
3.3+/-5%
'
''
'
")
")")
")
6
66
6
IDT79RC4650 - 100, 133 MQUAD package, Commercial Tem perature
150 MHz PClk
150
IDT79RV4650 -100,133, 150, 180, 200 MQUAD package, Commercial Temperature
(0°C to +85°C Case)
IIndustrial
(-40° to =85°C Case)
IDT79RV4650 -100, 133 MQUAD package, Indust rial Temperature
180 180 MHz PClk
200 200 MHz PClk
