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FEATURES
RGY PACKAGE
(TOPVIEW)
2
A1 19 SDA
3
RESET 18 SCL
4
INT0 17 INT
5
SD0 16 SC3
6
SC0 15 SD3
7
INT1 14 INT3
8
SD1 13 SC2
9
SC1 12 SD2
1
10
A0
GND
20
11
INT2 VCC
20
6 8 9 10
1
2
3
4
5
15
14
13
12
11
INT2
SD2
SD1
SC1
GND
19
RESET
INT0
SD0
SC0
INT1
INT
SC3
SD3
INT3
SC2
RGW PACKAGE
(TOPVIEW)
18 17 16
7
SDA
SCL
A1
A0
VCC
DGV, DW, OR PW PACKAGE
(TOPVIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
A0
A1
RESET
INT0
SD0
SC0
INT1
SD1
SC1
GND
VCC
SDA
SCL
INT
SC3
SD3
INT3
SC2
SD2
INT2
DESCRIPTION/ORDERING INFORMATION
PCA9545A4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
•1-of-4 Bidirectional Translating Switches •No Glitch on Power Up•I
2
C Bus and SMBus Compatible •Supports Hot Insertion•Four Active-Low Interrupt Inputs •Low Standby Current•Active-Low Interrupt Output •Operating Power-Supply Voltage Range of2.3 V to 5.5 V•Active-Low Reset Input
•5.5-V Tolerant Inputs•Two Address Pins, Allowing up to FourDevices on the I
2
C Bus •0 to 400-kHz Clock Frequency•Channel Selection Via I
2
C Bus, In Any •Latch-Up Performance Exceeds 100 mA PerCombination JESD 78•Power Up With All Switch Channels •ESD Protection Exceeds JESD 22Deselected
– 2000-V Human-Body Model (A114-A)•Low R
ON
Switches
– 200-V Machine Model (A115-A)•Allows Voltage-Level Translation Between
– 1000-V Charged-Device Model (C101)1.8-V, 2.5-V, 3.3-V, and 5-V Buses
The PCA9545A is a quad bidirectional translating switch controlled via the I
2
C bus. The SCL/SDA upstream pairfans out to four downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels canbe selected, determined by the contents of the programmable control register. Four interrupt inputs ( INT3– INT0),one for each of the downstream pairs, are provided. One interrupt ( INT) output acts as an AND of the fourinterrupt inputs.
An active-low reset ( RESET) input allows the PCA9545A to recover from a situation in which one of thedownstream I
2
C buses is stuck in a low state. Pulling RESET low resets the I
2
C state machine and causes allthe channels to be deselected, as does the internal power-on reset function.
The pass gates of the switches are constructed such that the V
CC
pin can be used to limit the maximum highvoltage, which will be passed by the PCA9545A. This allows the use of different bus voltages on each pair, sothat 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts, without any additional protection. Externalpullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5.5-V tolerant.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
GQN OR ZQN PACKAGE
(TOP VIEW)
1 2 3 4
A
B
C
D
E
PCA9545A
4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RGW Reel of 3000 PCA9545ARGWR PD545AQFN – RGY Reel of 1000 PCA9545ARGYR PD545ATube of 25 PCA9545ADW
PCA9545ASOIC – DW Reel of 2000 PCA9545ADWRReel of 250 PCA9545ADWT PCA9545APCA9545APW PD545ATube of 70
PCA9545APWE4–40 °C to 85 °C PCA9545APWR PD545ATSSOP – PW Reel of 2000
PCA9545APWRE4
PCA9545APWT PD545AReel of 250
PCA9545APWTE4Reel of 2000 PCA9545ADGVRTVSOP – DGV PD545AReel of 250 PCA9545ADGVTVFBGA – GQN Reel of 1000 PCA9545AGQNR PD545AVFBGA – ZQN (Pb-free) Reel of 1000 PCA9545AZQNR PD545A
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
TERMINAL ASSIGNMENTS
1 2 3 4
AA1 A0 V
CC
SDA
BINT0 INT RESET SCL
CSC0 SD0 SD3 SC3
DSD1 SC2 INT1 INT3
EGND SC1 INT2 SD2
2
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PCA9545A4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
TERMINAL FUNCTIONS
NO.
NAME DESCRIPTIONDGV, DW, PW, GQN ANDRGWAND RGY ZQN
1 19 A2 A0 Address input 0. Connect directly to V
CC
or ground.2 20 A1 A1 Address input 1. Connect directly to V
CC
or ground.Active-low reset input. Connect to V
CC
through a pullup3 1 B3 RESET
resistor, if not used.Active-low interrupt input 0. Connect to V
CC
through a4 2 B1 INT0
pullup resistor.5 3 C2 SD0 Serial data 0. Connect to V
CC
through a pullup resistor.6 4 C1 SC0 Serial clock 0. Connect to V
CC
through a pullup resistor.Active-low interrupt input 1. Connect to V
CC
through a7 5 D3 INT1
pullup resistor.8 6 D1 SD1 Serial data 1. Connect to V
CC
through a pullup resistor.9 7 E2 SC1 Serial clock 1. Connect to V
CC
through a pullup resistor.10 8 E1 GND Ground
Active-low interrupt input 2. Connect to V
CC
through a11 9 E3 INT2
pullup resistor.12 10 E4 SD2 Serial data 2. Connect to V
CC
through a pullup resistor.13 11 D2 SC2 Serial clock 2. Connect to V
CC
through a pullup resistor.Active-low interrupt input 3. Connect to V
CC
through a14 12 D4 INT3
pullup resistor.15 13 C3 SD3 Serial data 3. Connect to V
CC
through a pullup resistor.16 14 C4 SC3 Serial clock 3. Connect to V
CC
through a pullup resistor.Active-low interrupt output. Connect to V
CC
through a pullup17 15 B2 INT
resistor.18 16 B4 SCL Serial clock line. Connect to V
CC
through a pullup resistor.19 17 A4 SDA Serial data line. Connect to V
CC
through a pullup resistor.20 18 A3 V
CC
Supply power
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Switch Control Logic
I2C Bus Control
Interrupt Logic
Input Filter
Power-on Reset
PCA9545A
SC0
A1
A0
INT
INT0
SDA
SCL
GND
SD3
SD2
SD1
SD0
SC3
SC2
SC1 9
13
16
5
8
12
15
6
10
20
3
19
18
4
17
2
1
7
11
14
INT1
INT2
INT3
Pin numbers shown are for DGV, DW, PW, and RGY packages.
Output
Filter
VCC
RESET
PCA9545A
4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
BLOCK DIAGRAM
4
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Device Address
1 1 1 0A10 A0
Slave Address
R/W
Fixed Hardware
Selectable
Control Register
Interrupt Bits
(Read Only) Channel-Selection Bits
(Read/Write)
Channel 0
Channel 1
Channel 2
Channel 3
INT0
INT1
INT2
INT3
INT3 INT2 INT1 INT0 B3 B2 B1 B0
7 6 54 3 2 1 0
Control Register Definition
PCA9545A4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
Following a start condition, the bus master must output the address of the slave it is accessing. The address ofthe PCA9545A is shown in Figure 1 . To conserve power, no internal pullup resistors are incorporated on thehardware-selectable address pins, and they must be pulled high or low.
Figure 1. PCA9545A Address
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,while a logic 0 selects a write operation.
Following the successful acknowledgment of the slave address, the bus master sends a byte to the PCA9545A,which is stored in the control register (see Figure 2 ). If multiple bytes are received by the PCA9545A, it savesthe last byte received. This register can be written and read via the I
2
C bus.
Figure 2. Control Register
One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register(see Table 1 ). After the PCA9545A has been addressed, the control register is written. The four LSBs of thecontrol byte are used to determine which channel or channels are to be selected. When a channel is selected,the channel becomes active after a stop condition has been placed on the I
2
C bus. This ensures that allSCn/SDn lines are in a high state when the channel is made active, so that no false conditions are generated atthe time of connection. A stop condition must occur always right after the acknowledge cycle.
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Interrupt Handling
PCA9545A
4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status)
(1)
INT3 INT2 INT1 INT0 D3 B2 B1 B0 COMMAND
0 Channel 0 disabledXXXXXXX
1 Channel 0 enabled0 Channel 1 disabledXXXXXX X1 Channel 1 enabled0 Channel 2 disabledXXXXX XX1 Channel 2 enabled0 Channel 3 disabledXXXX XXX1 Channel 3 enabledNo channel selected,000000X0
power-up/reset default state
(1) Several channels can be enabled at the same time. For example, B3 = 0, B2 = 1, B1 = 1, B0 = 0 means that channels 0 and 3 aredisabled, and channels 1 are 2 and enabled. Care should be taken not to exceed the maximum bus capacity.
The PCA9545A provides four interrupt inputs (one for each channel) and one open-drain interrupt output (seeTable 2 ). When an interrupt is generated by any device, it is detected by the PCA9545A and the interrupt outputis driven low. The channel does not need to be active for detection of the interrupt. A bit also is set in the controlregister.
Bits 4–7 of the control register correspond to channels 0–3 of the PCA9545A, respectively. Therefore, if aninterrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into thecontrol register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The master then can address the PCA9545A and readthe contents of the control register to determine which channel contains the device generating the interrupt. Themaster then can reconfigure the PCA9545A to select this channel and locate the device generating the interruptand clear it.
It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master toensure that all devices on a channel are interrogated for an interrupt.
The interrupt inputs can be used as general-purpose inputs if the interrupt function is not required.
If unused, interrupt input(s) must be connected to V
CC
.
Table 2. Control Register Read (Interrupt)
(1)
INT3 INT2 INT1 INT0 D3 B2 B1 B0 COMMAND
0 No interrupt on channel 0XXX XXXX1 Interrupt on channel 00 No interrupt on channel 1XX XXXXX1 Interrupt on channel 10 No interrupt on channel 2X X X X X X X1 Interrupt on channel 20 No interrupt on channel 3XXXXXXX1 Interrupt on channel 3
(1) Several interrupts can be active at the same time. For example, INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0 means that there is no interrupton channels 0 and 3, and there is interrupt on channels 1 and 2.
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RESET Input
Power-On Reset
Voltage Translation
2
Maximum
Typical
Minimum
VCC (V)
4.543.532.5 5 5.5
1
5
4.5
4
3.5
3
2.5
2
1.5
Vpass (V)
I
2
C Interface
PCA9545A4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
The RESET input can be used to recover the PCA9545A from a bus-fault condition. The registers and the I
2
Cstate machine within this device initialize to their default states if this signal is asserted low for a minimum of t
WL
.All channels also are deselected in this case. RESET must be connected to V
CC
through a pullup resistor.
When power is applied to V
CC
, an internal power-on reset holds the PCA9545A in a reset condition until V
CC
hasreached V
POR
. At this point, the reset condition is released and the PCA9545A registers and I
2
C state machineare initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, V
CC
mustbe lowered below 0.2 V to reset the device.
The pass-gate transistors of the PCA9545A are constructed such that the V
CC
voltage can be used to limit themaximum voltage that is passed from one I
2
C bus to another.
Figure 3 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated usingdata specified in the electrical characteristics section of this data sheet). In order for the PCA9545A to act as avoltage translator, the V
pass
voltage must be equal to or lower than the lowest bus voltage. For example, if themain bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, V
pass
must be equal to or below 2.7V to effectively clamp the downstream bus voltages. As shown in Figure 3 , V
pass
(max) is at 2.7 V when thePCA9545A supply voltage is 3.5 V or lower, so the PCA9545A supply voltage could be set to 3.3 V. Pullupresistors then can be used to bring the bus voltages to their appropriate levels (see Figure 13 ).
Figure 3. V
pass
Voltage vs V
CC
The I
2
C bus is for two-way two-line communication between different ICs or modules. The two lines are a serialdata line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullupresistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is notbusy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the highperiod of the clock pulse, as changes in the data line at this time are interpreted as control signals (seeFigure 4 ).
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SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
SDA
SCL
Start Condition
S
Stop Condition
P
SCL
Master
Transmitter/
Receiver Slave
Receiver Slave
Transmitter/
Receiver Master
Transmitter
Master
Transmitter/
Receiver
I2C
Multiplexer
Slave
SDA
PCA9545A
4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
Figure 4. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line whilethe clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock ishigh is defined as the stop condition (P) (see Figure 5 ).
Figure 5. Definition of Start and Stop Conditions
A device generating a message is a transmitter; a device receiving a message is the receiver. The device thatcontrols the message is the master, and the devices that are controlled by the master are the slaves (seeFigure 6 ).
Figure 6. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver isnot limited. Each byte of eight bits is followed by one acknowlege (ACK) bit. The transmitter must release theSDA line before the receiver can send an ACK bit.
When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a mastermust generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. Thedevice that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stablelow during the high pulse of the ACK-related clock period (see Figure 7 ). Setup and hold times must be takeninto account.
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Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for ACK
NACK
ACK
A AS 1 1 1 0 0 A1 A0 0
Start Condition
SDA
R/W ACK From Slave ACK From Slave
P
B0B1B2B3XXXX
Stop Condition
Slave Address Control Register
ANA
S 1 1 10 0 A1 A0 1
SDA INT0INT3 INT2 INT1 P
B3 B2 B1 B0
Start Condition R/W ACK From Slave NACK From Master Stop Condition
Slave Address Control Register
PCA9545A4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
Figure 7. Acknowledgment on the I
2
C Bus
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) afterthe last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA linehigh. In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Data is transmitted to the PCA9545A control register using the write mode shown in Figure 8 .
Figure 8. Write Control Register
Data is read from the PCA9545A control register using the read mode shown in Figure 9 .
Figure 9. Read Control Register
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
PCA9545A
4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 7 VV
I
Input voltage range
(2)
–0.5 7 VI
I
Input current ±20 mAI
O
Output current ±25 mAContinuous current through V
CC
±100 mAContinuous current through GND ±100 mADGV package 92DW package 58GQN/ZQN package 78θ
JA
Package thermal impedance
(3)
°C/WPW package 83RGW package TBDRGY package 47P
tot
Total power dissipation 400 mWT
stg
Storage temperature range –65 150 °CT
A
Operating free-air temperature range –40 85 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNIT
V
CC
Supply voltage 2.3 5.5 VSCL, SDA 0.7 ×V
CC
6V
IH
High-level input voltage VA1, A0, INT3– INT0, RESET 0.7 ×V
CC
V
CC
+ 0.5SCL, SDA –0.5 0.3 ×V
CCV
IL
Low-level input voltage VA1, A0, INT3– INT0, RESET –0.5 0.3 ×V
CC
T
A
Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
10
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Electrical Characteristics
PCA9545A4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
V
POR
Power-on reset voltage
(2)
No load, V
I
= V
CC
or GND V
POR
1.6 2.1 V5 V 3.64.5 V to 5.5 V 2.6 4.53.3 V 1.9V
pass
Switch output voltage V
SWin
= V
CC
, I
SWout
= –100 µA V3 V to 3.6 V 1.6 2.82.5 V 1.52.3 V to 2.7 V 1.1 2I
OH
INT V
O
= V
CC
2.3 V to 5.5 V 10 µAV
OL
= 0.4 V 3 7SCL, SDAI
OL
V
OL
= 0.6 V 2.3 V to 5.5 V 6 10 mAINT V
OL
= 0.4 V 3SCL, SDA ±1SC3–SC0, SD3–SD0 ±1I
I
A1, A0 V
I
= V
CC
or GND 2.3 V to 5.5 V ±1µAINT3– INT0 ±1RESET ±15.5 V 3 12Operating mode f
SCL
= 100 kHz V
I
= V
CC
or GND, I
O
= 0 3.6 V 3 112.7 V 3 105.5 V 0.3 1I
CC
Low inputs V
I
= GND, I
O
= 0 3.6 V 0.1 1 µA2.7 V 0.1 1Standby mode
5.5 V 0.3 1High inputs V
I
= V
CC
, I
O
= 0 3.6 V 0.1 12.7 V 0.1 1One INT3– INT0 input at 0.6 V,
8 15Other inputs at V
CC
or GNDINT3– INT0
One INT3– INT0 input at V
CC
– 0.6 V,
8 15Other inputs at V
CC
or GNDSupply-current
∆I
CC
2.3 V to 5.5 V µAchange
SCL or SDA input at 0.6 V,
8 15Other inputs at V
CC
or GNDSCL, SDA
SCL or SDA input at V
CC
– 0.6 V,
8 15Other inputs at V
CC
or GNDA1, A0 4.5 6C
i
INT3– INT0 V
I
= V
CC
or GND 2.3 V to 5.5 V 4.5 6 pFRESET 4.5 5.5SCL, SDA 15 19C
io(OFF)
(3)
V
I
= V
CC
or GND, Switch OFF 2.3 V to 5.5 V pFSC3–SC0, SD3–SD0 6 84.5 V to 5.5 V 4 9 16V
O
= 0.4 V, I
O
= 15 mAR
ON
Switch on-state resistance 3 V to 3.6 V 5 11 20 ΩV
O
= 0.4 V, I
O
= 10 mA 2.3 V to 2.7 V 7 16 45
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V V
CC
), T
A
= 25 °C.(2) The power-on reset circuit resets the I
2
C bus logic with V
CC
< V
POR
. V
CC
must be lowered to 0.2 V to reset the device.(3) C
io(ON)
depends on the device capacitance and load that is downstream from the device.
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I
2
C Interface Timing Requirements
Switching Characteristics
PCA9545A
4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10 )
STANDARD MODE FAST MODEI
2
C BUS I
2
C BUS
UNITMIN MAX MIN MAX
f
scl
I
2
C clock frequency 0 100 0 400 kHzt
sch
I
2
C clock high time 4 0.6 µst
scl
I
2
C clock low time 4.7 1.3 µst
sp
I
2
C spike time 50 50 nst
sds
I
2
C serial-data setup time 250 100 nst
sdh
I
2
C serial-data hold time 0
(1)
0
(1)
µst
icr
I
2
C input rise time 1000 20 + 0.1C
b
(2)
300 nst
icf
I
2
C input fall time 300 20 + 0.1C
b
(2)
300 nst
ocf
I
2
C output fall time 10-pF to 400-pF bus 300 20 + 0.1C
b
(2)
300 nst
buf
I
2
C bus free time between stop and start 4.7 1.3 µst
sts
I
2
C start or repeated start condition setup 4.7 0.6 µst
sth
I
2
C start or repeated start condition hold 4 0.6 µst
sps
I
2
C stop condition setup 4 0.6 µsSCL low to SDA output lowt
vdL(Data)
Valid-data time (high to low)
(3)
1 1 µsvalid
SCL low to SDA output hight
vdH(Data)
Valid-data time (low to high)
(3)
0.6 0.6 µsvalid
ACK signal from SCL lowt
vd(ack)
Valid-data time of ACK condition 1 1 µsto SDA output lowC
b
I
2
C bus capacitive load 400 400 pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the V
IH
min of the SCL signal), in orderto bridge the undefined region of the falling edge of SCL.(2) C
b
= total bus capacitance of one bus line in pF(3) Data taken using a 1-k Ωpullup resistor and 50-pF load (see Figure 10 )
over recommended operating free-air temperature range, C
L
≤100 pF (unless otherwise noted) (see Figure 12 )
FROM TOPARAMETER MIN MAX UNIT(INPUT) (OUTPUT)
R
ON
= 20 Ω, C
L
= 15 pF 0.3t
pd
(1)
Propagation delay time SDA or SCL SDn or SCn nsR
ON
= 20 Ω, C
L
= 50 pF 1t
iv
Interrupt valid time
(2)
INTn INT 4 µst
ir
Interrupt reset delay time
(2)
INTn INT 2 µs
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified loadcapacitance, when driven by an ideal voltage source (zero output impedance).(2) Data taken using a 4.7-k Ωpullup resistor and 100-pF load (see Figure 12 )
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Interrupt and Reset Timing Requirements
PCA9545A4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 12 )
PARAMETER MIN MAX UNIT
t
PWRL
Low-level pulse duration rejection of INTn inputs 1 µst
PWRH
High-level pulse duration rejection of INTn inputs 0.5 µst
WL
Pulse duration, RESET low 6 nst
rst
(1)
RESET time (SDA clear) 500 nst
REC(STA)
Recovery time from RESET to start 0 ns
(1) t
rst
is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,signaling a stop condition. It must be a minimum of t
WL
.
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PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
VCC
CL = 50 pF
(See Note A)
tbuf
ticr
tsth tsds
tsdh
ticf
ticr
tscl tsch
tsts
tvd(ACK)
or tvdL
tvdH
0.3 × VCC
Stop
Condition
tsps
Repeat
Start
Condition
Start or Repeat
Start Condition
SCL
SDA
Start
Condition
(S)
Address
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
Two Bytes for Complete
Device Programming
I2C PORT LOAD CONFIGURATION
VOLTAGE WAVEFORMS
ticf
Stop
Condition
(P)
tsp
DUT SDn, SCn
0.7 × VCC
0.3 × VCC
0.7 × VCC
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Address
Bit 1
Address
Bit 6 ACK
(A)
BYTE DESCRIPTION
I2C address + R/W
Control register data
1
2
PCA9545A
4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
A. C
L
includes probe and jig capacitance.B. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z
O
= 50 Ω,t
r
/t
f
= 30 ns.C. The outputs are measured one at a time, with one transition per measurement.
Figure 10. I
2
C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms
14
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SCL
SDA
LEDx
RESET
30%
50%
50%
LED OFF
Start ACK or Read Cycle
trst
tWL
tREC
trst
RL = 4.7 kΩ
VCC
CL = 100 pF
(See Note A)
INTERRUPT LOAD CONFIGURATION
DUT INT
0.5 × VCC
INTn
(input)
VOLTAGE WAVEFORMS (tiv)
tiv
VOLTAGE WAVEFORMS (tir)
INT
(output) 0.5 × VCC
INTn
(input)
INT
(output)
0.5 × VCC
0.5 × VCC
tir
PCA9545A4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 11. Reset Timing
A. C
L
includes probe and jig capacitance.B. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z
O
= 50 Ω,t
r
/t
f
= 30 ns.
Figure 12. Interrupt Load Circuit and Voltage Waveforms
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APPLICATION INFORMATION
PCA9545A
SD1
SDA
SCL
SDA Channel 0
Channel 1
Channel 2
Channel 3
See Note A
I2C/SMBus
Master SCL INT
RESET
INT1
SC1
SD2
SC2
SD3
SC3
INT2
INT3
SD0
INT0
SC0
VCC = 2.7 V to 5.5 V VCC = 3.3 V VCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
See Note A
See Note A
See Note A
19
18
17
3
20
5
6
4
8
9
7
12
13
11
15
16
14
2
1
10
A1
A0
GND
PCA9545A
4-CHANNEL I
2
C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
Figure 13 shows an application in which the PCA9545A can be used.
A. If the device generating the interrupt has an open-drain output structure or can be 3-stated, a pullup resistor isrequired. If the device generating the interrupt has a totem-pole output structure and cannot be 3-stated, a pullupresistor is not required. The interrupt inputs should not be left floating.B. Pin numbers shown are for DGV, DW, PW, and RGY packages.
Figure 13. Typical Application
16
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PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCA9545ADGVR OBSOLETE TVSOP DGV 20 TBD Call TI Call TI
PCA9545ADGVRG4 OBSOLETE TVSOP DGV 20 TBD Call TI Call TI
PCA9545ADW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9545ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9545ADWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9545ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9545AGQNR OBSOLETE BGA
MICROSTAR
JUNIOR
GQN 20 TBD Call TI Call TI
PCA9545APW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9545APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9545APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9545APWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9545APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9545APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9545APWT ACTIVE TSSOP PW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9545APWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9545APWTG4 ACTIVE TSSOP PW 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9545ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCA9545ARGYRG4 ACTIVE VQFN RGY 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PCA9545AZQNR ACTIVE BGA
MICROSTAR
JUNIOR
ZQN 20 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCA9545ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
PCA9545APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PCA9545APWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PCA9545ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
PCA9545AZQNR BGA MI
CROSTA
R JUNI
OR
ZQN 20 1000 330.0 12.4 3.3 4.3 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCA9545ADWR SOIC DW 20 2000 367.0 367.0 45.0
PCA9545APWR TSSOP PW 20 2000 367.0 367.0 38.0
PCA9545APWT TSSOP PW 20 250 367.0 367.0 38.0
PCA9545ARGYR VQFN RGY 20 3000 367.0 367.0 35.0
PCA9545AZQNR BGA MICROSTAR
JUNIOR ZQN 20 1000 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
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