REJ03C0368-0100, Rev.1.00, 2009.05.07
Page 1 of 16
R1WV6416R Series
64Mb Advanced LPSRAM (4M word x 16bit / 8M word x 8bit)
REJ03C0368-0100
Rev.1.00
2009.05.07
Description
The R1WV6416R Series is a family of low voltage 64-Mbit static RAMs organized as 4,194,30 4-word by
16-bit, fabricated by Renesas’s high -performance 0.15um CMOS an d TFT technologies.
The R1WV6416R Series is suitable for memo ry applications where a simple interfacing, battery operating
and battery backup are the important design obje ctives.
The R1WV6416R Series is provided in 4 8-pin thin small outline package [TSOP (I): 12mm x 20mm with
pin pitch of 0.5mm], 52-pin micro thin small outline package [µTSOP (II): 10.79mm x 10.49mm with pin pitch
of 0.4mm] and 48-ball fine pitch ball grid array [f-BGA] package. It gives the best solution for compaction of
mounting area as well as flexibility of wiring pattern of printed circuit boards.
Features
• Single 2.7~ 3.6V power sup ply
• Small stand-by current: 8 µA (3.0V, typical)
• No clocks, No refresh
• All inputs and outputs are TTL compatible.
• Easy memory expansion by CS1#, CS2, LB# and UB#
• Common Data I/O
• Three-state outputs: OR-tie Capability
• OE# prevents data contention on the I/O bus
Ordering Information
Type No. Access time Package
R1WV6416RSA-5S% 55 ns
R1WV6416RSA-7S% 70 ns
12mm x 20mm 48-pin plastic TSOP (I)
(normal-bend type) (48P 3R)
R1WV6416RSD-5S% 55 ns
R1WV6416RSD-7S% 70 ns 350 mil 52-pin plastic μ-TSOP (II)
(normal-bend type) (52PTG)
R1WV6416RBG-5S% 55 ns
R1WV6416RBG-7S% 70 ns f-BGA 0.75mm pitch 48-ball
% - Temperature version; see table below
% Temperature Range
R 0 ~ +70 °C
I -40 ~ +85 °C
R1WV6416R Series
REJ03C0368-0100, Rev.1.00, 2009.05.07
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Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
A15
A14
A13
A12
A11
A10
A9
A8
A19
CS1#
WE#
NC
NC
Vcc
CS2
A21
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
A
16
BYTE#
UB#
Vss
LB#
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
NC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
NC
A0
52-pin
μ
TSOP (II)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
CS2
A21
UB#
LB#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A
16
BYTE#
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
CS1#
A0
48-pin TSOP (I)
LB#
DQ15
DQ13
Vss
Vcc
DQ10
DQ8
A18
A
B
C
D
E
F
G
H
1 2 3 4 5 6
OE#
UB#
DQ14
DQ12
DQ11
DQ9
A19
A8
A0
A3
A5
A17
A1
A4
A6
A7
A16
A15
A13
A10
A2
CS1#
DQ1
DQ3
DQ4
DQ6
WE#
A11
CS2
DQ0
DQ2
Vcc
Vss
DQ5
DQ7
A20
A14
A12
A9
A21
48-pin
f
-BGA (TOP VIEW)
R1WV6416R Series
REJ03C0368-0100, Rev.1.00, 2009.05.07
Page 3 of 16
Pin Description
Pin name Function
Vcc Power supply
Vss Ground
A0 to A21 Address input (word mode)
A-1 to A21 Address input (byte mode)
DQ0 to DQ15 Data input/output
CS1# Chip select 1
CS2 Chip select 2
WE# Write enable
OE# Output enable
LB# Lower byte enable
UB# Upper byte enable
BYTE# Byte control mode enable
NC Non connection
Note: BYTE# pin is supported for 48-pin TS OP (I) and 52-pin µTSOP (II) packages.
R1WV6416R Series
REJ03C0368-0100, Rev.1.00, 2009.05.07
Page 4 of 16
Block Diagram
Note: BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages.
A
0
CS1#
A
1
CS2
LB#
UB#
WE#
OE#
A21
BYTE#
DQ0
DQ1
DQ7
DQ8
DQ9
DQ15
/ A -1
Vcc
Vss
COLUMN DECODER
X
8 / x16
CONTROL
ADDRESS
BUFFER
ROW
DECODER
MEMORY ARRAY
2M-word x16-bit
or
4M-word x 8-bit
SENSE / WRITE AMPLIFIER
CLOCK
GENERATOR
BUFFER
DQ
SELECTOR
BUFFER
DQ
DAT
A
32Mb SRAM #1
32Mb SRAM #2
R1WV6416R Series
REJ03C0368-0100, Rev.1.00, 2009.05.07
Page 5 of 16
Operation Table
CS1# CS2 BYTE# LB# UB# WE# OE# DQ0~7 DQ8~14 DQ15 Operation
H X X X X X X High-Z High-Z High-Z Stand-by
X L X X X X X High-Z High-Z High-Z Stand-by
X X H H H X X High-Z High-Z High-Z Stand-by
L H H L H L X Din High-Z High-Z Write in lower byte
L H H L H H L Dout High-Z High-Z Read in lower byte
L H H L H H H High-Z High-Z High-Z Output disable
L H H H L L X High-Z Din Din Write in upper byte
L H H H L H L High-Z Dout Dout Read in upper byte
L H H H L H H High-Z High-Z High-Z Output disable
L H H L L L X Din Din Din Word write
L H H L L H L Dout Dout Dout Word read
L H H L L H H High-Z High-Z High-Z Output disable
L H L L L L X Din High-Z A-1 Byte write
L H L L L H L Dout High-Z A-1 Byte read
L H L L L H H High-Z High-Z A-1 Output disable
Note1. H: VIH L:V
IL X: V
IH or VIL
2. BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages.
3. When apply BYTE# =“L”, please ass ign L B #=UB#=“L”.
Absolute Maximum Ratings
Parameter Symbol Value unit
Power supply voltage relativ e to Vss Vcc -0.5 to +4.6 V
Terminal voltage on any pin relative to Vss VT -0.5*1 to Vcc+0.3*2 V
Power dissipation PT 0.7 W
R ver. 0 to +70 °C
Operation temperature Topr*3 I ver. -40 to +85 °C
Storage temperature range Tstg -65 to 150 °C
R ver. 0 to +70 °C
Storage temperature range under bias Tbias*3 I ver. -40 to +85 °C
Note 1. –2.0V in case of AC (Pulse width ≤30ns)
2. Maximum voltage is +4.6V.
3. Ambient temperature range depends on R/I-version. Please see table on page 1.
R1WV6416R Series
REJ03C0368-0100, Rev.1.00, 2009.05.07
Page 6 of 16
Recommended Operating Conditions
Parameter Symbol Min. Typ. Max. Unit Note
Vcc 2.7 3.0 3.6 V Supply voltage Vss 0 0 0 V
Input high voltage VIH 2.4 -
Vcc+0.2 V
Input low voltage VIL -0.2 - 0.4 V 1
R ver. 0 - +70 °C 2
Ambient temperature range I ver. Ta -40 - +85 °C 2
Note 1. –2.0V in case of AC (Pulse width ≤ 30ns)
2. Ambient temperature range depends on R/I-version. Please see table on page 1.
DC Characteristics
Parameter Symbol Min. Typ. Max. Unit Test conditions*3
Input leakage current | ILI | - - 1 μA Vin = Vss to Vcc
Output leakage current
| ILO | - - 1 μA
BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
CS1# =VIH or CS2 =VIL or
OE# =VIH or WE# =VIL or
LB# = UB# =VIH, VI/O =Vss to Vcc
ICC1 - 45*1 60 mA
Min. cycle, duty =100%, II/O = 0mA
BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
CS1# =VIL, CS2 =VIH, Others = VIH/VIL
Average operating curre nt
ICC2 - 5*1 10 mA
Cycle =1μs, dut y =100%, II/O = 0mA
BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V,
VIH ≥ VCC-0.2V, VIL ≤ 0.2V
Standby current ISB - 0.1*1 0.3 mA
BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
CS2 =VIL
- 8*1 24 μA ~+25°C
- 14*2 48 μA ~+40°C
- - 100 μA ~+70°C
Standby current
ISB1
- - 160 μA ~+85°C
Vin ≥ 0V
BYTE# ≥ Vcc -0.2V or
BYTE# ≤ 0.2V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ VCC-0.2V,
CS2 ≥ VCC-0.2V or
(3) LB# = UB# ≥ VCC-0.2V,
CS1# ≤ 0.2V,
CS2 ≥ VCC-0.2V
Output high voltage VOH 2.4 - - V BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
IOH = -0.5mA
Output low voltage VOL - - 0.4 V
BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
IOL = 2mA
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. Typical parameter indicates the value for the center of distribution at 3.0V (T a= 40ºC), and not 1 00% tested.
3. BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages.
R1WV6416R Series
REJ03C0368-0100, Rev.1.00, 2009.05.07
Page 7 of 16
Capacitance
(Ta =25°C, f =1MHz)
Parameter Symbol Min. Typ. Max. Unit Test conditions Note
Input capacitance C in - - 20 pF Vin =0V 1
Input / output capacitance C I/O - - 20 pF V
I/O =0V 1
Note1.This parameter is sampled and not 1 00% tested.
AC Characteristics
Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = 0 ~ +70°C / -40 ~ +85°C*1)
• Input pulse levels: VIL = 0.4V, VIH = 2.4V
• Input rise and fall time: 5ns
• Input and output timing reference level: 1.4V
• Output load: See figures (Including scope and jig)
Note1. Ambient temperature range depends on R/I-version. Please see table on page 1.
DQ
1.4V
RL = 500 ohm
CL = 30 pF
R1WV6416R Series
REJ03C0368-0100, Rev.1.00, 2009.05.07
Page 8 of 16
Read Cycle
R1WV6416R**-5S R1WV6416R**-7S
Parameter Symbol
Min. Max. Min. Max. Unit Note
Read cycle time tRC 55 - 70 - ns
Address access time tAA - 55 - 70 ns
tACS1 - 55 - 70 ns
Chip select access time tACS2 - 55 - 70 ns
Output enable to output valid tOE - 25 - 35 ns
Output hold from address change tOH 10 - 10 - ns
LB#, UB# access time tBA - 55 - 70 ns
tCLZ1 10 - 10 - ns 2,3
Chip select to output in low-Z tCLZ2 10 - 10 - ns 2,3
LB#, UB# enable to low-Z tBLZ 5 - 5 - ns 2,3
Output enable to output in lo w-Z tOLZ 5 - 5 - ns 2,3
tCHZ1 0 20 0 25 ns 1,2,3
Chip deselect to output in high-Z tCHZ2 0 20 0 25 ns 1,2,3
LB#, UB# disable to high-Z tBHZ 0 20 0 25 ns 1,2,3
Output disable to output in high-Z tOHZ 0 20 0 25 ns 1,2,3
R1WV6416R Series
REJ03C0368-0100, Rev.1.00, 2009.05.07
Page 9 of 16
Write Cycle
R1WV6416R**-5S R1WV6416R**-7S
Parameter Symbol
Min. Max. Min. Max. Unit Note
Write cycle time tWC 55 - 70 - ns
Address valid to end of write tAW 50 - 65 - ns
Chip select to end of write tCW 50 - 65 - ns 5
Write pulse width tWP 40 - 55 - ns 4
LB#, UB# valid to end of write tBW 50 - 65 - ns
Address setup time tAS 0 - 0 - ns 6
Write recovery time tWR 0 - 0 - ns 7
Data to write time overlap tDW 25 - 35 - ns
Data hold from write time tDH 0 - 0 - ns
Output enable from end of write tOW 5 - 5 - ns 2
Output disable to output in high-Z tOHZ 0 20 0 25 ns 1,2
Write to output in high-Z tWHZ 0 20 0 25 ns 1,2
Note1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit
conditions and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and
from device to device.
4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write begins at the latest transition among CS1# go in g low, CS2 g oin g high, W E# goin g low and LB# going
low or UB# going low .
A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB#
going high or UB# goi ng high. tWP is measured from the beginning of write to the end of write.
5. tCW is measured from the later of CS1# going lo w or CS2 going high to end of write.
6. tAS is measured the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1# or W E# going high or CS2 going low to the end of write cycle.
R1WV6416R Series
REJ03C0368-0100, Rev.1.00, 2009.05.07
Page 10 of 16
BYTE# Timing Conditions
R1WV6416R**-5S R1WV6416R**-7S
Parameter Symbol
Min. Max. Min. Max. Unit Note
Byte setup time tBS 5 - 5 - ms
Byte recovery time tBR 5 - 5 - ms
BYTE# Timing Waveforms
CS2
CS1#
BYTE#
tBS tBR
R1WV6416R Series
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Page 11 of 16
Timing Waveforms
Read Cycle*1
Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V
tAA
tBLZ
CS2
CS1#
OE#
A0~21
A -1~21
LB#,UB#
WE#
DQ0~15
DQ0~7
VIH
VIL
tOH
tBA
tBHZ
tCLZ1
tACS1
tCLZ2
tACS2
tOE
tOLZ
tCHZ1
tCHZ2
tOHZ
Valid Data
High impedance
WE# = “H” level
(Word Mode)
(Byte Mode)
tRC
(Word Mode)
(Byte Mode)
R1WV6416R Series
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Page 12 of 16
Write Cycle (1)*1 (WE# CLOCK)
Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V
CS2
CS1#
OE#
A0~21
A -1~21
LB#,UB#
WE#
DQ0~15
DQ0~7
tOH
tBW
tCW
tCW
tOW tOHZ
(Word Mode)
(Byte Mode)
tWC
(Word Mode)
(Byte Mode)
tAW
tAS tWP tWR
tDW tDH
tWHZ
Valid Data
tOLZ
R1WV6416R Series
REJ03C0368-0100, Rev.1.00, 2009.05.07
Page 13 of 16
Write Cycle (2)*1 (CS1#, CS2 CLOCK)
Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V
CS2
CS1#
OE#
A0~21
A -1~21
LB#,UB#
WE#
DQ0~15
DQ0~7
VIH
VIL
tBW
tCW
tCW
OE# = “H” level
(Word Mode)
(Byte Mode)
tWC
(Word Mode)
(Byte Mode) tAW
Valid Data
tAS tWR
tWR
tDW tDH
tAS
tWP
R1WV6416R Series
REJ03C0368-0100, Rev.1.00, 2009.05.07
Page 14 of 16
Write Cycle (3)*1 (LB#, UB# CLOCK)
Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V
CS2
CS1#
OE#
A0~21
A -1~21
LB#,UB#
WE#
DQ0~15
DQ0~7
VIH
VIL
tBW
tCW
tCW
OE# = “H” level
(Word Mode)
(Byte Mode)
tWC
(Word Mode)
(Byte Mode)
Valid Data
tAW
tAS
tWP
tWR
tDW tDH
R1WV6416R Series
REJ03C0368-0100, Rev.1.00, 2009.05.07
Page 15 of 16
Low Vcc Data Retention Characteristics
Parameter Symbol Min. Typ Max. Unit Test conditions*3,4
VCC for data retention VDR 2.0 - 3.6 V
Vin ≥ 0V
BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ VCC-0.2V,
CS2 ≥ VCC-0.2V or
(3) LB# = UB# ≥ VCC-0.2V,
CS1# ≤ 0.2V,
CS2 ≥ VCC-0.2V
- 8*1 24 μA ~+25°C
- 14*2 48 μA ~+40°C
- - 100 μA ~+70°C
Data retention current ICCDR
- - 160 μA ~+85°C
Vin ≥ 0V
BYTE# ≥ Vcc -0.2V or
BYTE# ≤0.2V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ VCC-0.2V,
CS2 ≥ VCC-0.2V or
(3) LB# = UB# ≥ VCC-0.2V,
CS1# ≤ 0.2V,
CS2 ≥ VCC-0.2V
Chip select to data retention
time tCDR 0 - - ns
Operation recovery time tR 5 - - ms
See retention waveform.
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. Typical parameter indic ates the value for the center of distribution at 3.0V (Ta= 40ºC), and not 100% tested.
3. BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages.
4. CS2 also controls address buffer, WE# buffer ,CS1# buffer ,OE# buffer ,LB# ,UB# buffer and Din buffer. If
CS2 controls data retention mode, Vin levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high
impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or0V ≤ CS2 ≤ 0.2V.
The other input levels (addres s, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state.
R1WV6416R Series
REJ03C0368-0100, Rev.1.00, 2009.05.07
Page 16 of 16
Low Vcc Data Retentio n Timing Waveforms*1
Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V
CS2
CS1#
LB#, UB#
Vcc
Vcc
Vcc
(1) CS1# Controlled
(2) CS2 Controlled
(3) LB#, UB# Controlled
tCDR t
R
2.7V 2.7V
2.2V 2.2V
V
DR
tCDR t
R
2.7V 2.7V
2.2V 2.2V
V
DR
tCDR t
R
2.7V 2.7V
0.6V 0.6V
V
DR
CS1# ≥Vcc - 0.2V
0V ≤CS2 ≤0.2V
LB#
,
UB# ≥Vcc - 0.2V
Revision History R1WV6416R Data Sheet
Contents pf Revision
Rev. Date Page Description
0.01 Mar.24, 2008 - Initial issue: Prelimi nary Data Sheet
1.00 May 07, 2009 - Finalized
5 Operation Table corrected
6 Error corrected: ISB Test condition CS2=VIH->VIL
To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although t he old company name remains in t his docum ent, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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9. Although Renesas Electronics endeavors to improve the qu ality and reliability of its products, semiconductor products have
specific chara cterist ics such as the o ccurren ce of failure at a certai n rate an d malfunct ion s under certai n u se cond ition s. Further,
Renesas Electronics p roducts are not subject to radiation resistance design . Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but no t limited to redundancy, fire
control and malfunction prevention, approp riate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
10. Please cont act a Renesas Elect roni cs sales office for details as to environmental matters su ch as the environ mental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with
applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas
Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electro nics” as used in this document means Renesas Ele ct r onics Corporation and also includes its majority-
owned subsid iaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.