1 Introduction
1.1 FEATURES
1.2 APPLICATIONS
Contents
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
– Individual Channel-Specific Power•14-Bit 85-MSPS High-Performance Single ADC
Measurements•At f
IN
= 140 MHz, SNR ≥71 dBFS,
– A Dedicated Final AGCSFDR ≥79 dBc
•Test Bus to Monitor Data at Different Stages of•At f
IN
= 70 MHz, SNR ≥73 dBFS,
the DDC Signal PathSFDR ≥85 dBc
•3.3-V Analog Supplies, 1.5-V Digital Core•Independent Clocks for ADC and DDC With
Supply, 3.3-V Digital I/O SupplyBuilt-In FIFO
•484-Ball Plastic BGA (23 mm ×23 mm) With•Programmable Closed-Loop VGA Control With
1,0-mm Pitch6-Bit Outputs for ADC
•Power Dissipation (Eight Active DDC•Received Total Wideband Power (RTWP)
Channels): 2.3 WMeasurement for the Composite Power AcrossCarriers With Programmable Time Window forMeasurement
•8 UMTS Digital Downconverter (DDC)
•Wireless Base Station ReceiverChannels or 16 CDMA/TD-SCDMA DDC
•Multi-Carrier Digital ReceiverChannels With Programmable 18-Bit Filter
•UMTS (8 Carriers-1 Sector)Coefficients
•CDMA (16 Carriers-1 Sector)•Each DDC Channel Provides:
•TD-SCDMA (16 Carriers-1 Sector)– Real or Complex DDC Inputs– UMTS Mode Rx Filtering: 6-Stage CIC (m =
•Digital Radio Receivers1 or 2), up to 40-Tap CFIR, up to 64-Tap
•Wideband ReceiversPFIR
•Software Radios– CDMA Mode Rx Filtering: 6-Stage CIC (m =
•Wireless Local Loop1 or 2), up to 64-Tap CFIR, up to 64-TapPFIR
•Intelligent Antenna Systems
1 Introduction ............................................... 14.5 Factory Test and No-Connect Signals .............. 151.1 FEATURES ........................................... 14.6 Power and Ground Signals .......................... 151.2 APPLICATIONS ...................................... 14.7 Digital Supply Monitoring ............................ 162 General Description ..................................... 34.8 JTAG ................................................ 163 SPECIFICATIONS ........................................ 44.9 AFE8405 and AFE8406 PCB Design Compatibility .163.1 PACKAGE ORDERING INFORMATION ............. 45 Typical Characteristics ................................ 173.2 ABSOLUTE MAXIMUM RATINGS ................... 46 ANALOG-TO-DIGITAL CONVERTERS .............. 243.3 RECOMMENDED OPERATING CONDITIONS ...... 46.1 ADC Operation ...................................... 243.4 THERMAL CHARACTERISTICS ..................... 56.2 ADC Input Configuration ............................ 243.5 POWER DISSIPATION ............................... 56.3 ADC Input Voltage Overstress ...................... 283.6 ANALOG ELECTRICAL CHARACTERISTICS ....... 66.4 ADC Reference Circuit .............................. 283.7 DIGITAL CHIP DC CHARACTERISTICS ............ 86.5 ADC Clock Input ..................................... 283.8 DIGITAL CHIP AC TIMING CHARACTERISTICS ... 97 RECEIVE DIGITAL SIGNAL PROCESSING ........ 304 AFE8405 PINS ........................................... 10 7.1 Receive Input Interface .............................. 304.1 Analog Section Signals .............................. 10 7.2 DDC Organization ................................... 434.2 Digital Receive Section Signals ..................... 11 8 AFE8405 GENERAL CONTROL ...................... 738.1 Microprocessor Interface Control Data, Address,4.3 Microprocessor Signals ............................. 14
and Strobes ......................................... 734.4 JTAG Signals ........................................ 15
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this document.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
8.2 Synchronization Signals ............................. 76 8.4 AFE8405 Programming ............................. 778.3 Interrupt Handling ................................... 77
2Contents Submit Documentation Feedback
2 General Description
B0104-02
refpa
refma
Internal
Reference
S&H
14-Bit
Pipelined
ADCCore
Dual14-Bit85-MSPS ADC
Digital
Error
Correction
Output
Control
TimingCircuitry
inpa
inma
clkpa
clkma
trst_n
tck
tdi
tms
JTAG tdo
rx_synca– drx_sync
reset_n
16 6
ControlandSync
d(15:0)
a(5:0)
rd_n
wr_n
ce_n
interrrupt
rx_sysnc_out
da(13:0)
clkouta
16
16
DigitalReceive
DataPorts
dvga_a
dvga_b dvga_d
dvga_c
rxin_a
adcclk_a
adcclk_b
rxin_b
rxin_c
adcclk_c
rxin_d
adcclk_d
ReceiveInput
Interface
Power
Measurements
andWideband
AGC
6 6 6 6
rxclk
DDC0
2CDMA2000-1X,
2 TD-SCMA or1UMTS
DDC2
2CDMA2000-1X,
2 TD-SCMA or1UMTS
DDC3
2CDMA2000-1X,
2 TD-SCMA or1UMTS
DDC4
2CDMA2000-1X,
2 TD-SCMA or1UMTS
DDC5
2CDMA2000-1X,
2 TD-SCMA or1UMTS
DDC6
2CDMA2000-1X,
2 TD-SCMA or1UMTS
DDC7
2CDMA2000-1X,
2 TD-SCMA or1UMTS
DDC1
2CDMA2000-1X,
2 TD-SCMA or1UMTS
I
I
I
I
I
I
I
I
Q
Q
Q
Q
Q
Q
Q
Q
sync
sync
sync
sync
sync
sync
sync
sync
Output
Format
Parallel
or
Serial
32
8
rxout_X_X
rx_sync_out_X
rxclk_out
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
The AFE8405 is a multichannel communications signal processor that provides analog-to-digitalconversion and digital downconversion optimized for cellular base transceiver systems. The devicesupports UMTS, CDMA-1X, and TD-SCDMA air-interface cellular standards.
The AFE8405 provides up to 8 UMTS digital downconverter channels (DDC), 16 CDMA DDCs or 16TD-SCDMA DDCs. The DDC channels are independent and operate simultaneously.
The AFE8405 DDCs have three input ports; one is hardwired to the internal 14-bit analog-to-digitalconverter (rxin_a) and two are 16-bit digital inputs (rxin_c, rxin_d). Each DDC channel can beprogrammed to accept data from any one of the three input ports; rxin_b is not used.
Figure 2-1. Functional Block Diagram
Submit Documentation Feedback General Description 3
3 SPECIFICATIONS
3.1 PACKAGE ORDERING INFORMATION
3.2 ABSOLUTE MAXIMUM RATINGS
(1)
3.3 RECOMMENDED OPERATING CONDITIONS
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
SPECIFIED TRANSPORTPACKAGE PACKAGE ORDERINGPRODUCT PACKAGE–LEADS TEMPERATURE MEDIA,DESIGNATOR MARKING NUMBERRANGE QUANTITY
AFE8405 Plastic BGA–484 ZDQ –40 °C to 85 °C AFE8405I AFE8405IZDQ Tray, 60
UNIT
Analog Chip
AVDD Analog supply voltage –0.3 V to 3.7 VDRVDD I/O ring supply voltage –0.3 V to 3.7 VGround difference DRVSS to AVSS –0.1 V to 0.1 VAnalog input voltage –0.15 V to 3.6 VDigital input voltage –0.3 V to DRVDD + 0.3 V
Digital Chip
VDDS Pad ring supply voltage –0.3 V to 3.7 VDVDD Core supply voltage –0.3 V to 1.8 VDigital input voltage –0.3 V to VDDS + 0.3 V
Entire Chip
Clamp current for an input or output –20 mA to 20 mAT
STG
Storage temperature –65 °Cto 140 °CT
J
Junction temperature 105 °CLead soldering temperature (10 seconds) 300 °CESD classification (tested to EIA/JESD22-A114-B) Class 2
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
MIN NOM MAX UNIT
Analog Chip
AVDD Analog supply voltage 3 3.3 3.6 VDRVDD I/O ring supply voltage 3 3.3 3.6 VV
ID
Differential input voltage range 2.3 VVCM Common-mode input voltage 1.5 1.6 VDifferential clock inputs 3 V
PP
Clock input duty cycle 50%
Digital Chip
VDDS I/O ring supply voltage 3 3.6 VDVDD Core supply voltage 1.425 1.575 VSupply voltage difference, VDDS – DVDD 2 V
Entire Chip
T
A
Temperature ambient, no air flow –40 85 °CT
J
(1)
Junction temperature 105 °C
(1) Thermal management is required for full-rate operation. The circuit is designed for junction temperatures up to 125 °C. Sustainedoperation at elevated temperatures reduces long-term reliability. Lifetime calculations based on maximum junction temperature of105 °C.
SPECIFICATIONS 4Submit Documentation Feedback
3.4 THERMAL CHARACTERISTICS
3.5 POWER DISSIPATION
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
THERMAL CONDUCTIVITY
(1)
MIN TYP MAX UNIT
Theta junction-to-ambient (0 LFPM) 14 °C/WTheta junction-to-ambient (100 LFPM) 13 °C/WR
θJA
Theta junction-to-ambient (250 LFPM) 12.2 °C/WTheta junction-to-ambient (500 LFPM) 11.6 °C/WR
θJC
Theta junction-to-case 2.8 °C/W
(1) Air flow reduces R
θJA
and is highly recommended.
Typical values at T
A
= 25 °C, UMTS mode, sampling rate = 61.44 MSPS, and rxclk = 122.88 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
AVDD
Analog supply current Six active DDC channels 123 mAI
DRVDD
Analog I/O supply current 21.5 mAI
DVDD
Digital core supply current 959 mAI
VDDS
Digital I/O supply current
(1)
100 mAAnalog power dissipation 477 mWDigital power dissipation
(2)
1.439 WTotal power dissipation
(2)
1.9 WI
AVDD
Analog supply current Eight active DDC channels 123 mAI
DRVDD
Analog I/O supply current 21.5 mAI
DVDD
Digital core supply current 1.198 AI
VDDS
Digital I/O supply current
(1)
115 mAAnalog power dissipation 477 mWDigital power dissipation
(2)
1.797 WTotal power dissipation
(2)
2.3 W
(1) Current consumption on the digital I/O supply is primarily due to the external loads and follows C ×V×F. Internal loads are estimated at2 pF per terminal. Data outputs transition once every four clocks, whereas clock outputs transition every cycle. In general,I
VDDS
=Σ(DataPad/4) ×C×V×F + ΣClockPad ×C×V×F.(2) Excluding current consumption from the digital I/O supply, which is dependent on external loads
Submit Documentation Feedback SPECIFICATIONS 5
3.6 ANALOG ELECTRICAL CHARACTERISTICS
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
Typical values at T
A
= 25 °C, minimum and maximum values over temperature range of T
A
= –40 °C to 85 °C, sampling rate =80 MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3 V, –1-dBFS differential input, internal reference, and 3-VPPdifferential clock (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 14 Bits
Analog Inputs
V
ID
Differential input voltage range 2.3 V
PP
C
ID
Differential input capacitance 3.2 pFI
IC
Common-mode input current 2 mA per input, 4 mA total 4 mAAnalog input bandwidth Source impedance = 50 Ω750 MHz
Conversion Characteristics
f
rxclk
= 1 ×f
ADC
ch_rate_sel = rate_sel = 8500
f
rxclk
= 2 ×f
ADC
ch_rate_sel = rate_sel = 8001f
ADC
ADC clock rate (f
clkpa
= f
clkma
= f
ADC
) MSPSf
rxclk
= 4 ×f
ADC
ch_rate_sel = rate_sel = 4010
f
rxclk
= 8 ×f
ADC
ch_rate_sel = rate_sel = 2011Data latency – ADC input to FIFO input 16.5 Clock
Cycles
Internal Reference Voltages
refma Lower reference voltages 1 Vrefpa Upper reference voltages 2.15 VReference error ±3.5 % of FScma 1.55Common-mode output voltages V±0.05
Dynamic DC Characteristics and Accuracy
No missing codes testedDNL Differential linearity error f
IN
= 1 MHz ±0.65 LSBsINL Integral linearity error f
IN
= 1 MHz ±4 LSBsOffset error ±4 mVOffset temperature coefficient 7 µV/ °CGain error ±0.5 % of FSGain temperature coefficient 0.0015 Δ%/ °C
Dynamic AC Characteristics
f
IN
= 10 MHz, T
A
= 25 °C 74.5f
IN
= 30 MHz 74f
IN
= 50 MHz 73.5f
IN
= 70 MHz, T
A
= 25 °C 73.5SNR Signal-to-noise ratio f
IN
= 70 MHz, T
A
=25 °C to 85 °C 70 73 dBFSf
IN
= 70 MHz, T
A
–40 °C 69 73f
IN
= 130 MHz 71.5f
IN
= 170 MHz 70.5f
IN
= 230 MHz 69RMS output noise INPA and INMA tied to CMA 1.1 LSBs
SPECIFICATIONS 6Submit Documentation Feedback
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
ANALOG ELECTRICAL CHARACTERISTICS (continued)
Typical values at T
A
= 25 °C, minimum and maximum values over temperature range of T
A
= –40 °C to 85 °C, sampling rate =80 MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3 V, –1-dBFS differential input, internal reference, and 3-VPPdifferential clock (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Dynamic AC Characteristics (Continued)
f
IN
= 10 MHz, T
A
= 25 °C 84f
IN
= 30 MHz 83.5f
IN
= 50 MHz 84f
IN
= 70 MHz, T
A
= 25 °C 85SFDR Spurious free dynamic range dBcf
IN
= 70 MHz, T
A
= –40 °C to 85 °C 77 82f
IN
= 130 MHz 81f
IN
= 170 MHz 76f
IN
= 230 MHz 68.5f
IN
= 10 MHz, T
A
= 25 °C 95.8f
IN
= 30 MHz 95f
IN
= 50 MHz 97.5HD2 Second harmonic f
IN
= 70 MHz, T
A
= 25 °C 95 dBcf
IN
= 130 MHz 81.5f
IN
= 170 MHz 76f
IN
= 230 MHz 68.5f
IN
= 10 MHz, T
A
= 25 °C 84f
IN
= 30 MHz 83.5f
IN
= 50 MHz 82.5HD3 Third harmonic f
IN
= 70 MHz, T
A
= 25 °C 85 dBcf
IN
= 130 MHz 92f
IN
= 170 MHz 79f
IN
= 230 MHz 83f
IN
= 10 MHz, T
A
= 25 °C 95.5Worst harmonic/spur other than HD2 or HD3 dBcf
IN
= 70 MHz, T
A
= 25 °C 95f
IN
= 10 MHz, T
A
= 25 °C 74f
IN
= 30 MHz 73.5f
IN
= 50 MHz 73.5f
IN
= 70 MHz, T
A
= 25 °C 73SINAD Signal-to-noise plus distortion f
IN
= 70 MHz, T
A
= 25 °C to 85 °C 70 72 dBFSf
IN
= 70 MHz, T
A
= –40 °C 69 72f
IN
= 130 MHz 71f
IN
= 170 MHz 69f
IN
= 230 MHz 66f
IN
= 10 MHz, T
A
= 25 °C 82.5f
IN
= 30 MHz 82f
IN
= 50 MHz 82THD Total harmonic distortion f
IN
= 70 MHz, T
A
= 25 °C 83.5 dBcf
IN
= 130 MHz 80f
IN
= 170 MHz 74f
IN
= 230 MHz 68Channel-to-channel crosstalk f
IN
= 225 MHz 95 dBc
Submit Documentation Feedback SPECIFICATIONS 7
3.7 DIGITAL CHIP DC CHARACTERISTICS
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
T
A
= –40 °C to 85 °C (unless otherwise noted)
VDDS = 3 V to 3.6 VPARAMETER
(1) (2) (3)
TEST CONDITIONS UNITMIN TYP MAX
V
IL
Voltage input, low 0.8 VV
IH
Voltage input, high 2 VV
OL
Voltage output, low
(4)
I
OL
= 2 mA 0.5 VV
OH
Voltage output high
(4)
I
OH
= –2 mA 2.4 VDDS V|I
PU
| Pullup current ( tdi, tms, trst_n, ce_n, wr_n, rd_n, V
IN
= 0 V, nominal 20 A 5 35 µAreset_n )
(4)
|I
PD
| Pulldown current (all other inputs and bidirectionals)
(4)
V
IN
= VDDS, nominal 20 µA 5 35 µA|I
IN
| Leakage current
(4)
V
IN
= 0V or VDDS, outputs in 20 µAhigh-impedance stateQuiescent supply current, IDVDD or IVDDS
(4)
V
IN
= 0 for pads with pulldowns,I
DDQ
8 mAV
IN
= VDDS for inputs with pullupsC
IN
Capacitance for inputs
(5)
5 pFC
BI
Capacitance for bidirectionals
(5)
5 pF
(1) Voltages are measured at low speed. Output voltages are measured with the indicated current load.(2) Currents are measured at nominal voltages, high temperature.(3) reset_n and interrupt have no timing specifications because they are asynchronous signals.die_id pins fa002_out, fa002_clk, and fa002_scan are not specified and are for factory use only.fuse pin fuse_out is not specified and is for factory use only.test pins zero, scanen, testmode0 and testmode1 are not specified and are for factory use only.(4) Each part is tested at high temperature for the given specification. Lots are sample tested at –40 °C.(5) Controlled by design and process and not directly tested.
SPECIFICATIONS 8Submit Documentation Feedback
3.8 DIGITAL CHIP AC TIMING CHARACTERISTICS
(1)
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
T
A
= –40 °C to 85 °C (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
f
CK
Clock frequency ( adcclk_a/b/c/d, rxclk)
(2)
160 MHzt
CKL
Clock low period (below V
IL
) ( adcclk_a/b/c/d, rxclk)
(2)
2 nst
CKH
Clock high period (above V
IH
) ( adcclk_a/b/c/d, rxclk)
(2)
2 nst
RF
Clock rise and fall times (V
IL
to V
IH
) ( adcclk_a/b/c/d, rxclk)
(3)
2 nsInput setup ( rx_sync[a–d]) before rxclk rises
(2)
2t
SU
Input setup ( rxin_a/b/c/d_[0-15] ) before rxclk rises (ADC FIFO blocks bypassed)
(2)
2 nsInput setup ( rxin_a/b/c/d_[0-15] ) before adcclk_a/b/c/d rises (ADC FIFO blocks enabled)
(2)
2Input hold ( rx_sync[a–d]) after rxclk rises
(2)
1t
HD
Input hold ( rxin_a/b/c/d_[0-15] ) after rxclk rises (adc fifo blocks bypassed)
(2)
2.5 nsInput hold ( rxin_ a/b/c/d_[0-15] ) after adcclk_a/b/c/d rises (adc fifo blocks enabled)
(2)
1Data output delay ( rx_sync_out_[0-7], rxout_[0-7]_a/b/c/d, rxclk_out, rx_sync_out,t
DLY
7 nsdvga_[a-d]_[5-0]) after rxclk rises.
(2)
Data output hold (rx_sync_out_[0-7], rxout_[0-7]_a/b/c/d, rxclk_out, rx_sync_out,t
OHD
0.5 nsdvga_[a-d]_[5-0]) after rxclk rises.
(2)
f
JCK
JTAG clock frequency ( tck)
(2)
40 MHzt
JCKL
JTAG clock low period (below V
IL
) ( tck)
(2)
10 nst
JCKH
JTAG clock high period (above V
IH
) ( tck)
(2)
10 nst
JSU
JTAG input ( tdi or tms) setup before tck goes high
(2)
2 nst
JHD
JTAG input ( tdi or tms) hold time after tck goes high
(2)
10 nst
JDLY
JTAG output ( tdo) delay from falling edge of tck.
(2)
10 nsControl setup during reads or writest
CSU
3 pin mode: a[5:0] valid before rd_n, wr_n or ce_n falling edge 6 ns2 pin mode: a[5:0] and wr_n valid before ce_n falling edge
(2)
Control setup during writest
EWCSU
3 pin mode: d[15:0] valid before wr_n and ce_n rising edge 10 ns2 pin mode: d[15:0] valid before ce_n rising edge
(2)
Control hold during writes.t
CHD
3 pin mode: a[5:0] and d[15:0] valid after wr_n and ce_n rise 6 ns2 pin mode: a[5:0], d[15:0] and wr_n valid after ce_n rise
(2)
t
CSPW
Control strobe ( ce_n and wr_n low) pulse duration during write.
(2)
25 nst
CDLY
Control output delay ce_n and rd_n low and a[5:0] stable to d[15:0] during read.
(2)
25 nst
REC
Control recovery time between reads or writes.
(2)
6 nst
HIZ
Control end of read to Hi-Z. rd_n and ce_n rise to d[15:0] 3-state
(4)
10 nst
COH
Control read d[15:0] output hold time 1 ns
(1) Timing is measured from the respective clock at VDDS/2 to input or output at VDDS/2. Output loading is a 50- Ωtransmission line whosedelay is calibrated out.(2) Each part is tested at 90 °C case temperature for the given specification. Lots are sample tested at –40 °C.(3) Recommended practice(4) Controlled by design and process and not directly tested.
Submit Documentation Feedback SPECIFICATIONS 9
4 AFE8405 PINS
4.1 Analog Section Signals
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
Signal Name Ball Type Description
inpa F3 Input ADCA analog positive inputinma F4 Input ADCA analog negative inputNC V4 —NC V3 —
clkpa H1 Input ADCA clock positive inputclkma J1 Input ADCA clock negative inputNC R1 —NC T1 —
refpa L3 Input ADCA positive reference input. connect 0.1 µF to AVSS.refma K3 Input ADCA negative reference input; connect 0.1 µF to AVSS.NC P3 —NC N3 —
cma H3 Output ADCA common-mode output referenceNC T3 —
iref M3 Input Current set; connect 56 k Ωto AVSS
clkouta n/a Output ADCA output clock; internally connected to adcclkada(13:0) n/a Output ADCA output data; internally connected to rxin_a_15:2fuse_sel H5 Input Connect to AVSS; factory use onlypwdn L9 Input Connect to AVDD, ADCA output enable; AVDD = enabled, AVSS = disabledGND N9 Inputovra G6 Output ADCA over range indicator bitNC N8 —
pin_configure T5 Input Connect to AVDD, factory use onlydll_disable N10 Input Connect to AVDD, factory use onlyAVDD M9 Inputext_ref M10 Input Connect to AVSS, AVDD = external reference, AVSS = internal reference
AFE8405 PINS10 Submit Documentation Feedback
4.2 Digital Receive Section Signals
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
Signal Name Ball Type Description
rxclk R22 Input Receive digital section clock input
adcclk_a n/a Input rxin_a_x input clock; connected to ADCA output clockadcclk_b n/a Input Not used, not connected internallyadcclk_c AA11 Input rxin_c_x input clockadcclk_d AB11 Input rxin_d_x input clock
rxin_c_ovr AB6 Input ADC overflow/overrange bit for rxin_crxin_d_ovr V12 Input ADC overflow/overrange bit for rxin_d
dvga_a_5 D7 Output Digital VGA control output for ADC0 MSBdvga_a_4 D8 Output Digital VGA control output for ADC0dvga_a_3 C7 Output Digital VGA control output for ADC0dvga_a_2 B7 Output Digital VGA control output for ADC0dvga_a_1 A7 Output Digital VGA control output for ADC0dvga_a_0 C8 Output Digital VGA control output for ADC0 LSB
dvga_b_5 B8 Output Not useddvga_b_4 A8 Output Not useddvga_b_3 D9 Output Not useddvga_b_2 D10 Output Not useddvga_b_1 C9 Output Not useddvga_b_0 B9 Output Not used
dvga_c_5 AA15 Output Digital VGA control output for rxin_c MSB, test bus bit 1dvga_c_4 AB15 Output Digital VGA control output for rxin_c, test bus bit 0dvga_c_3 V16 Output Digital VGA control output for rxin_c, test bus bit 19dvga_c_2 W16 Output Digital VGA control output for rxin_c, test bus bit 18dvga_c_1 Y16 Output Digital VGA control output for rxin_c, test bus CLKdvga_c_0 AA16 Output Digital VGA control output for rxin_c LSB, test bus SYNC
dvga_d_5 AB16 Output Digital VGA control output for rxin_d MSB, test bus AFLAGdvga_d_4 V17 Output Digital VGA control output for rxin_ddvga_d_3 W17 Output Digital VGA control output for rxin_ddvga_d_2 AA17 Output Digital VGA control output for rxin_ddvga_d_1 AB17 Output Digital VGA control output for rxin_ddvga_d_0 V18 Output Digital VGA control Output for rxin_d LSB
rxin_c_15 Y7 Input/output Receive input data bus c bit 15 (MSB), test bus bit 17rxin_c_14 AA7 Input/output Receive input data bus c bit 14, test bus bit 16rxin_c_13 AB7 Input/output Receive input data bus c bit 13, test bus bit 15rxin_c_12 Y8 Input/output Receive input data bus c bit 12, test bus bit 14rxin_c_11 V10 Input/output Receive input data bus c bit 11, test bus bit 13rxin_c_10 AA8 Input/output Receive input data bus c bit 10, test bus bit 12rxin_c_9 AB8 Input/output Receive input data bus c bit 9, test bus bit 11rxin_c_8 W9 Input/output Receive input data bus c bit 8, test bus bit 10rxin_c_7 Y9 Input/output Receive input data bus c bit 7, test bus bit 9rxin_c_6 AA9 Input/output Receive input data bus c bit 6, test bus bit 8rxin_c_5 AB9 Input/output Receive input data bus c bit 5, test bus bit 7rxin_c_4 W10 Input/output Receive input data bus c bit 4, test bus bit 6rxin_c_3 Y10 Input/output Receive input data bus c bit 3, test bus bit 5
Submit Documentation Feedback AFE8405 PINS 11
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
Signal Name Ball Type Description
rxin_c_2 AA10 Input/output Receive input data bus c bit 2, test bus bit 4rxin_c_1 AB10 Input/output Receive input data bus c bit 1, test bus bit 3rxin_c_0 W11 Input/output Receive input data bus c bit 0 (LSB), test bus bit 2
rxin_d_15 W12 Input/output Receive input data bus d bit 15 (MSB), test bus bit 35rxin_d_14 Y12 Input/output Receive input data bus d bit 14, test bus bit 34rxin_d_13 AA12 Input/output Receive input data bus d bit 13, test bus bit 33rxin_d_12 AB12 Input/output Receive input data bus d bit 12, test bus bit 32rxin_d_11 V13 Input/output Receive input data bus d bit 11, test bus bit 31rxin_d_10 W13 Input/output Receive input data bus d bit 10, test bus bit 30rxin_d_9 Y13 Input/output Receive input data bus d bit 9, test bus bit 29rxin_d_8 AA13 Input/output Receive input data bus d bit 8, test bus bit 28rxin_d_7 AB13 Input/output Receive input data bus d bit 7, test bus bit 27rxin_d_6 V14 Input/output Receive input data bus d bit 6, test bus bit 26rxin_d_5 W14 Input/output Receive input data bus d bit 5, test bus bit 25rxin_d_4 AA14 Input/output Receive input data bus d bit 4, test bus bit 24rxin_d_3 AB14 Input/output Receive input data bus d bit 3, test bus bit 23rxin_d_2 V15 Input/output Receive input data bus d bit 2, test bus bit 22rxin_d_1 W15 Input/output Receive input data bus d bit 1, test bus bit 21rxin_d_0 Y15 Input/output Receive input data bus d bit 0 (LSB), test bus bit 20
rx_synca P21 Input Receive sync inputrx_syncb P22 Input Receive sync inputrx_syncc N20 Input Receive sync inputrx_syncd N21 Input Receive sync input
rx_sync_out E22 Output Receive general purpose output syncrxclk_out E21 Output Receive clock output
rx_sync_out_7 A20 Output Receive serial interface frame strobe for rxout_7_xrx_sync_out_6 C19 Output Receive serial interface frame strobe for rxout_6_x, frame strobe (rx_sync_out signal) forparallel interfacerx_sync_out_5 C17 Output Receive serial interface frame strobe for rxout_5_xrx_sync_out_4 C16 Output Receive serial interface frame strobe for rxout_4_xrx_sync_out_3 D15 Output Receive serial interface frame strobe for rxout_3_xrx_sync_out_2 B13 Output Receive serial interface frame strobe for rxout_2_xrx_sync_out_1 C12 Output Receive serial interface frame strobe for rxout_1_xrx_sync_out_0 A10 Output Receive serial interface frame strobe for rxout_0_x
rxout_7_a D20 Output DDC 7 serial out data. CDMA A: I data UMTS: Imsb DDC parallel interface I(12)rxout_7_b C21 Output DDC 7 serial out data. CDMA B: I data UMTS: Imsb – 1 DDC parallel interface I(13)rxout_7_c B20 Output DDC 7 serial out data. CDMA A: Q data UMTS: Qmsb DDC parallel interface I(14)rxout_7_d C20 Output DDC 7 serial out data. CDMA B: Q data UMTS: Qmsb – 1 DDC parallel interface I(15)
rxout_6_a A19 Output DDC 6 serial out data. CDMA A: I data UMTS: Imsb DDC parallel interface I(8)rxout_6_b B19 Output DDC 6 serial out data. CDMA B: I data UMTS: Imsb – 1 DDC parallel interface I(9)rxout_6_c A18 Output DDC 6 serial out data. CDMA A: Q data UMTS: Qmsb DDC parallel interface I(10)rxout_6_d B18 Output DDC 6 serial out data. CDMA B: Q data UMTS: Qmsb – 1 DDC parallel interface I(11)
rxout_5_a D18 Output DDC 5 serial out data. CDMA A: I data UMTS: Imsbparallel interface I(4)rxout_5_b B17 Output DDC 5 serial out data. CDMA B: I data UMTS: Imsb – 1 parallel interface I(5)rxout_5_c D17 Output DDC 5 serial out data. CDMA A: Q data UMTS: Qmsb parallel interface I(6)rxout_5_d A17 Output DDC 5 serial out data. CDMA B: Q data UMTS: Qmsb – 1parallel interface I(7)
AFE8405 PINS12 Submit Documentation Feedback
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
Signal Name Ball Type Description
rxout_4_a A16 Output DDC 4 serial out data. CDMA A: I data UMTS: Imsb parallel interface I(0)rxout_4_b B16 Output DDC 4 serial out data. CDMA B: I data UMTS: Imsb – 1 parallel interface I(1)rxout_4_c D16 Output DDC 4 serial out data. CDMA A: Q data UMTS: Qmsb parallel interface I(2)rxout_4_d A15 Output DDC 4 serial out data. CDMA B: Q data UMTS: Qmsb – 1 parallel interface I(3)
rxout_3_a B15 Output DDC 3 serial out data. CDMA A: I data UMTS: Imsb parallel interface Q(12)rxout_3_b C15 Output DDC 3 serial out data. CDMA B: I data UMTS: Imsb – 1 parallel interface Q(13)rxout_3_c A14 Output DDC 3 serial out data. CDMA A: Q data UMTS: Qmsb parallel interface Q(14)rxout_3_d B14 Output DDC 3 serial out data. CDMA B: Q data UMTS: Qmsb – 1 parallel interface Q(15)
rxout_2_a D14 Output DDC 2 serial out data. CDMA A: I data UMTS: Imsb parallel interface Q(8)rxout_2_b A13 Output DDC 2 serial out data. CDMA B: I data UMTS: Imsb – 1 parallel interface Q(9)rxout_2_c C13 Output DDC 2 serial out data. CDMA A: Q data UMTS: Qmsb parallel interface Q(10)rxout_2_d D13 Output DDC 2 serial out data. CDMA B: Q data UMTS: Qmsb – 1 parallel interface Q(11)
rxout_1_a A12 Output DDC 1 serial out data. CDMA A: I data UMTS: Imsb parallel interface Q(4)rxout_1_b B12 Output DDC 1 serial out data. CDMA B: I data UMTS: Imsb – 1 parallel interface Q(5)rxout_1_c D12 Output DDC 1 serial out data. CDMA A: Q data UMTS: Qmsb parallel interface Q(6)rxout_1_d A11 Output DDC 1 serial out data. CDMA B: Q data UMTS: Qmsb – 1 parallel interface Q(7)
rxout_0_a B11 Output DDC 0 serial out data. CDMA A: I data UMTS: Imsb parallel interface Q(0)rxout_0_b C11 Output DDC 0 serial out data. CDMA B: I data UMTS: Imsb – 1 parallel interface Q(1)rxout_0_c B10 Output DDC 0 serial out data. CDMA A: Q data UMTS: Qmsb parallel interface Q(2)rxout_0_d A9 Output DDC 0 serial out data. CDMA B: Q data UMTS: Qmsb – 1 parallel interface Q(3)
Submit Documentation Feedback AFE8405 PINS 13
4.3 Microprocessor Signals
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
Signal Name Ball Type Description
d0 Y22 Input/output MPU register interface data bus bit 0 (LSB)d1 Y21 Input/output MPU register interface data busd2 AB20 Input/output MPU register interface data busd3 AA20 Input/output MPU register interface data busd4 Y20 Input/output MPU register interface data busd5 W20 Input/output MPU register interface data busd6 V20 Input/output MPU register interface data busd7 AB19 Input/output MPU register interface data busd8 AA19 Input/output MPU register interface data busd9 Y19 Input/output MPU register interface data busd10 W19 Input/output MPU register interface data busd11 V19 Input/output MPU register interface data busd12 AB18 Input/output MPU register interface data busd13 AA18 Input/output MPU register interface data busd14 Y18 Input/output MPU register interface data busd15 W18 Input/output MPU register interface data bus bit 15 (MSB)
a0 T20 Input MPU register interface address bus bit 0 (LSB)a1 U22 Input MPU register interface address busa2 U21 Input MPU register interface address busa3 W22 Input MPU register interface address busa4 V21 Input MPU register interface address busa5 W21 Input MPU register interface address bus bit 5 (MSB)
rd_n T22 Input MPU register interface read – active lowwr_n R20 Input MPU register interface write – active lowce_n T21 Input MPU register interface chip enable – active low
reset_n R21 Input Chip reset – active lowinterrupt M21 Output Chip interrupt
AFE8405 PINS14 Submit Documentation Feedback
4.4 JTAG Signals
4.5 Factory Test and No-Connect Signals
4.6 Power and Ground Signals
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
Signal Name Ball Type Description
tdi K22 Input JTAG test data intms K21 Input JTAG test mode selecttrst_n J22 Input JTAG test resetNote: the trst_n pin should be asserted low after power up to insure the JTAG logic isproperly initialized.tck L20 Input JTAG test clocktdo L21 Output JTAG test data out
Signal Name Ball Type Description
testmode0 G21 Input Do not connect; internal pulldowntestmode1 G22 Input Do not connect; internal pulldownscanen H21 Input Do not connect; internal pulldownfa002_scan J20 Input Do not connect; internal pulldownfa002_clk H22 Input Do not connect; internal pulldownfa002_out J21 Output Do not connectzero H20 Input Do not connect; internal pulldownfuse_out F20 Output Do not connectfuse_ena D21 Input Do not connect; internal pulldownfuse_bias F21 Input Do not connect; internal pulldown
Signal Name Ball Description
AVDD H4, J3, L1, L2, M1, M2, M9, N1, N2, R3, T4 Analog power (3.3 V)DRVDD H6, H7, J8, K8, L8, P8, R8, T6, T7 Analog I/O power (3.3 V)AVSS A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C1, C2, Analog groundC3, C4, C5, D1, D2, D3, D4, D5, E1, E2, E3, E4,E5, F1, F2, F5, F6, F7, F8, F9, G1, G2, G3, G4,G5, G7, G8, G9, H2, J2, J4, J5, J6, K1, K2, K4, K5,K6, L4, L5, L6, L7, M4, M5, M6, M7, N4, N5, N6,N7, N9, P1, P2, P4, P5, P6, R2, R4, R5, R6, T2,U1, U2, U3, U4, U5, U6, U7, U8, U9, V1, V2, V5,V6, V7, V8, W1, W2, W3, W4, W5, Y1, Y2, Y3, Y4,AA1, AA2, AA3, AA4, AB1, AB2, AB3, AB4DRVSS H8, H9, J7, J9, K7, K9, M8, P7, P9, R7, R9, T8, T9 Analog I/O groundVDDS B6, B21, D6, D11, D19, D22, E10, E11, E12, E13, Digital I/O power (3.3 V), also called VpadE14, E15, E16, E17, E18, E19, K20, M20, P20,U11, U12, U13, U14, U15, U16, U17, U18, U19,V11, W7, AA6, AA21DVDD F22, G10, G19, H10, H19, J10, J19, K10, K19, L10, Digital core power (1.5 V), also called VcoreL19, M19, N19, P10, P19, R10, R19, V22DVSS A6, A21, A22, B22, C6, C10, C14, C18, C22, E6, Digital groundE7, E8, E9, E20, F10, F11, F12, F13, F14, F15,F16, F17, F18, F19, G11, G12, G13, G14, G15,G16, G17, G18, G20, H11, H12, H13, H14, H15,H16, H17, H18, J11, J12, J13, J14, J15, J16, J17,J18, K11, K12, K13, K14, K15, K16, K17, K18, L11,L12, L13, L14, L15, L16, L17, L18, M11, M12, M13,M14, M15, M16, M17, M18, N11, N12, N13, N14,N15, N16, N17, N18, N22, P11, P12, P13, P14,P15, P16, P17, P18, R11, R12, R13, R14, R15,R16, R17, R18, T10, T11, T12, T13, T14, T15, T16,T17, T18, T19, U10, U20, V9, W6, W8, Y5, Y6,Y11, Y14, Y17, AA5, AA22, AB5, AB21, AB22
Submit Documentation Feedback AFE8405 PINS 15
4.7 Digital Supply Monitoring
4.8 JTAG
4.9 AFE8405 and AFE8406 PCB Design Compatibility
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
Signal Name Ball Description
dvddmon L22 It is recommended that this pin be brought to a probe point for monitoring and debugging purposes.dvssmon M22 It is recommended that this pin be brought to a probe point for monitoring and debugging purposes.
The JTAG standard for boundary scan testing is implemented for board testing purposes. Internal scantest is not supported. Five device pins are dedicated for JTAG support: tdi, tdo, tms, tck, and trst_n. TheJTAG bsdl configuration file is available at www.ti.com .
NOTEThe trst_n pin should be asserted after power up to insure the JTAG logic is properlyinitialized.
The AFE8406 is 14-bit, 85-MSPS, dual-ADC, 8-channel wideband receiver. AFE8405 has a pin- andsoftware-compatible upgrade to AFE8406 for diversity applications. Attention must be paid to theconfiguration of pins L9, M9, and N9 for PCB design to support AFE8405 and AFE8406 compatibility.
The ADC power-management system is configured by pins L9, M9, and N9. AFE8405/8406 signal namesof pin L9, M9 and N9 are shown in the following table.BALL NO. AFE8405 SIGNAL NAME AFE8406 SIGNAL NAME COMMENT
AFE8405 ADCA output enable: AVDD =L9 pwdn oea
enable; AVSS = disableM9 AVDD pwdnN9 GND oeb
The AFE8406 has two ADCs (ADCA and ADCB). Their ADC output and power on/off states areconfigured by pins L9, M9, and N9 as shown in following table.AFE8406
M9 L9 N9 Out A Out B ADC A ADC B
0 0 0 Off Off On On0 0 1 Off On On On0 1 0 On Off On On0 1 1 On On On On1 0 0 Off Off Off Off1 0 1 Off On Off On1 1 0 On Off On Off1 1 1 On On On On
The AFE8405 has one ADC (ADCA). Its output and power on/off states are configured by pin L9. Whenthe ADC is enabled, the configuration corresponds to the AFE8406 configuration with (M9, L9, N9) = (1, 1,0), which is ADCA on and ADCB off.
The AFE8405 L9, M9, and N9 configuration is recommended for new designs using AFE8405. For currentAFE8406 users who would like to use AFE8405 on an AFE8406 PCB for single-ADC applications, if L9,M9, and N9 are in a state where ADCB is is not powered down, device functionality and performance isnot affected, but this state results in higher power dissipation.
16 AFE8405 PINS Submit Documentation Feedback
5 Typical Characteristics
Digital Output Codes
−1.00
−0.75
−0.50
−0.25
0.00
0.25
0.50
0.75
1.00
0 2048 4096 6144 8192 10240 12288 14336 16384
DNL − Differential Nonlinearity Error − LSB
G001
Digital Output Codes
−3.0
−2.5
−2.0
−1.5
−1.0
−0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 2048 4096 6144 8192 10240 12288 14336 16384
INL − Integral Nonlinearity Error − LSB
G002
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
DIFFERENTIAL NONLINEARITY ERROR (DNL)
Figure 5-1.INTEGRAL NONLINEARITY ERROR (INL)
Figure 5-2.
Submit Documentation Feedback Typical Characteristics 17
f − Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0.00 0.25 0.50 0.75 1.00 1.25
fS = 80 MSPS
fIN = 10.1 MHz
SFDR = 83.69 dBc
SINAD = 74.19 dBFS
SNR = 74.81 dBFS
THD = 81.56 dBc
Amplitude − dBFS
G003
f − Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0.00 0.25 0.50 0.75 1.00 1.25
fS = 80 MSPS
fIN = 30.1 MHz
SFDR = 83.04 dBc
SINAD = 74.36 dBFS
SNR = 74.95 dBFS
THD = 81.99 dBc
Amplitude − dBFS
G004
f − Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0.00 0.25 0.50 0.75 1.00 1.25
fS = 80 MSPS
fIN = 50.1 MHz
SFDR = 83.10 dBc
SINAD = 73.70 dBFS
SNR = 74.33 dBFS
THD = 80.99 dBc
Amplitude − dBFS
G005
f − Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0.00 0.25 0.50 0.75 1.00 1.25
fS = 80 MSPS
fIN = 70.1 MHz
SFDR = 87.54 dBc
SINAD = 73.50 dBFS
SNR = 73.66 dBFS
THD = 85.66 dBc
Amplitude − dBFS
G006
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE
Figure 5-3. Figure 5-4.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE
Figure 5-5. Figure 5-6.
Typical Characteristics18 Submit Documentation Feedback
f − Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0.00 0.25 0.50 0.75 1.00 1.25
fS = 80 MSPS
fIN = 90.1 MHz
SFDR = 83.93 dBc
SINAD = 72.96 dBFS
SNR = 73.3 dBFS
THD = 82.54 dBc
Amplitude − dBFS
G007
f − Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0.00 0.25 0.50 0.75 1.00 1.25
fS = 80 MSPS
fIN = 130.1 MHz
SFDR = 80.69 dBc
SINAD = 72.02 dBFS
SNR = 72.6 dBFS
THD = 79.65 dBc
Amplitude − dBFS
G008
f − Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0.00 0.25 0.50 0.75 1.00 1.25
fS = 80 MSPS
fIN = 170.1 MHz
SFDR = 78 dBc
SINAD = 70.41 dBFS
SNR = 71.55 dBFS
THD = 75.55 dBc
Amplitude − dBFS
G009
f − Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0.00 0.25 0.50 0.75 1.00 1.25
fS = 80 MSPS
fIN = 230.1 MHz
SFDR = 71.47 dBc
SINAD = 68.43 dBFS
SNR = 70.53 dBFS
THD = 70.92 dBc
Amplitude − dBFS
G010
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE
Figure 5-7. Figure 5-8.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE
Figure 5-9. Figure 5-10.
Submit Documentation Feedback Typical Characteristics 19
f − Frequency − MHz
−140
−120
−100
−80
−60
−40
−20
0
0.00 0.25 0.50 0.75 1.00 1.25
fS = 80 MSPS
fIN1 = 70.15 MHz, –7 dBFS
fIN2 = 70.25 MHz, –7 dBFS
IMD3 = −85 dBFS
Amplitude − dBFS
G011
f − Frequency − MHz
−140
−120
−100
−80
−60
−40
−20
0
0.00 0.25 0.50 0.75 1.00 1.25
fS = 80 MSPS
fIN1 = 150.13 MHz, –7 dBFS
fIN2 = 150.23 MHz, –7 dBFS
IMD3 = −87 dBFS
Amplitude − dBFS
G012
Input Amplitude − dBFS
−20
0
20
40
60
80
100
120
−90 −80 −70 −60 −50 −40 −30 −20 −10 0
fS = 80 MSPS
fIN = 69.5 MHz
AC Performance − dB
G013
SFDR (dBc)
SFDR (dBFS)
SNR (dBc)
SNR (dBFS)
Input Amplitude − dBFS
−20
0
20
40
60
80
100
120
−90 −80 −70 −60 −50 −40 −30 −20 −10 0
fS = 80 MSPS
fIN = 150.5 MHz
AC Performance − dB
G014
SFDR (dBc)
SFDR (dBFS)
SNR (dBc)
SNR (dBFS)
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE
Figure 5-11. Figure 5-12.
AC PERFORMANCE AC PERFORMANCEvs vsINPUT AMPLITUDE INPUT AMPLITUDE
Figure 5-13. Figure 5-14.
Typical Characteristics20 Submit Documentation Feedback
f − Frequency − MHz
−140
−120
−100
−80
−60
−40
−20
0
−4 −3 −2 −1 0 1 2 3 4
fDATA = 61.44 MSPS
IF = 70 MHz, 0 dBm
DDC Rate = 122.88 MSPS
Normalized Amplitude − dB
G015
f − Frequency − MHz
−140
−120
−100
−80
−60
−40
−20
0
−4 −3 −2 −1 0 1 2 3 4
fDATA = 61.44 MSPS
IF = 140 MHz, 0 dBm
DDC Rate = 122.88 MSPS
Normalized Amplitude − dB
G016
f − Frequency − MHz
−120
−100
−80
−60
−40
−20
0
−1.5 −1.0 −0.5 0.0 0.5 1.0 1.5
fDATA = 78.6432 MSPS
IF = 70 MHz, 0 dBm
DDC Rate = 78.6432 MSPS
Normalized Amplitude − dB
G017
f − Frequency − MHz
−120
−100
−80
−60
−40
−20
0
−1.5 −1.0 −0.5 0.0 0.5 1.0 1.5
fDATA = 78.6432 MSPS
IF = 140 MHz, 0 dBm
DDC Rate = 78.6432 MSPS
Normalized Amplitude − dB
G018
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
DDC PERFORMANCE WITH WCDMA CARRIER DDC PERFORMANCE WITH WCDMA CARRIER
Figure 5-15. Figure 5-16.
DDC Performance With CDMA2000 Carrier DDC Performance With CDMA2000 Carrier
Figure 5-17. Figure 5-18.
A
Submit Documentation Feedback Typical Characteristics 21
f − Frequency − MHz
−100
−80
−60
−40
−20
0
−4 −3 −2 −1 0 1 2 3 4
P − Power − dBm
G020
f − Frequency − MHz
−140
−120
−100
−80
−60
−40
−20
0
0 5 10 15 20 25 30
Normalized Amplitude − dB
ADC OUTPUT DDC OUTPUT
f − Frequency − MHz
−100
−80
−60
−40
−20
0
−1.5 −1.0 −0.5 0.0 0.5 1.0 1.5
P − Power − dBm
G022
f − Frequency − MHz
−140
−120
−100
−80
−60
−40
−20
0
0 5 10 15 20 25 30
Normalized Amplitude − dB
ADC OUTPUT DDC OUTPUT
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
DDC Performance (WCDMA Carrier With Tone Blocker)f
DATA
= 61.44 MSPS, DDC rate = 122.88 MSPS, WCDMA carrier at 70 MHz and –71 dBFS, tone blocker at 73 MHz and–1 dBFS.
Figure 5-19.
DDC Performance (CDMA Carrier With Two-Tone Blocker)f
DATA
= 78.6432 MSPS, DDC rate = 78.6432 MSPS, CDMA2000 carrier at 70 MHz and –84 dBFS, tone 1 at 70.9 MHz and–12 dBFS, tone 2 at 71.7 MHz and –12 dBFS.
Figure 5-20.
22 Typical Characteristics Submit Documentation Feedback
20 40 60 80
75 74
74
74
73
73
73
73
72
72
72
72
71
71
71
71
70
69
100 120
f -InputFrequency-MHz
IN
f -SamplingFrequency-MHz
S
SNR-dBc
140 160 180 200 220
40
50
60
70
80
90
100
69 70 71 72 73 74 75
M0048-03
M0049-03
20
68 72 76 80 84 88
40 60 80
90
90
88
88
88
88
88 86
86
86
86
86
84
84
84
84
84
84
82
82
82
82
82
80
80
80
80
80
78
78
78
76
76
76
74
74
74
72
72
72
70
70
100 120 140 160 180 200 220
40
50
60
70
80
90
100
f -InputFrequency-MHz
IN
SFDR-dBc
f -SamplingFrequency-MHz
S
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
Typical values are at T
A
= 25 °C, differential input amplitude = –1 dBFS, test bus output
Figure 5-21.
Figure 5-22.
Submit Documentation Feedback Typical Characteristics 23
6 ANALOG-TO-DIGITAL CONVERTERS
B0105-02
refpa
refma
Internal
Reference
S&H
14-Bit
Pipelined
ADCCore
Dual14-Bit85-MSPS ADC
Digital
Error
Correction
Output
Control
TimingCircuitry
inpa
inma
clkpa
clkma
da(13:0)
ovra
clkouta
6.1 ADC Operation
6.2 ADC Input Configuration
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
The AFE8405 includes a high-performance, single-channel, 14-bit, 85-MSPS analog-to-digital converter(ADC). To provide a complete solution, the ADC channel includes a high-bandwidth linearsample-and-hold stage (S & H) and internal reference. An internal reference is provided, simplifying systemdesign requirements, yet an external reference can be used optionally to suit the accuracy and low-driftrequirements of the application.
Figure 6-1. ADC Block Diagram
The ADC digital output data and output clocks are connected directly to the rxin_a port of the AFE8405digital section. The ovra output connects directly to the AFE8405 digital section and also to a packageball. The ADC outputs can be accessed through the test bus in decimate-by-32 ×mode only.
The conversion process is initiated by a falling edge of the external input clocks. Once the signal iscaptured by the input S & H, the input sample is sequentially converted by a series of small resolutionstages, with the outputs combined in a digital correction logic block. Both the rising and the falling clockedges are used to propagate the sample through the pipeline every half clock cycle. This process resultsin data latency of 16.5 clock cycles, after which the output data is available as a 14-bit parallel word,coded in binary 2s-complement format to the AFE8405 receive section.
The analog input for the ADC consists of a differential sample-and-hold architecture implemented using aswitched-capacitor technique shown in Figure 6-2 .
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Figure 6-2. Analog Input Stage
This differential input topology produces a high level of ac performance for high sampling rates. It alsoresults in a high usable input bandwidth, especially important for high intermediate-frequency (IF) orundersampling applications. The ADC requires each of the analog inputs (inp, inm) to be externally biasedaround the common-mode level of the internal circuitry (cmx). For a full-scale differential input, each of thedifferential lines of the input signal swings symmetrically between cm + 0.575 V and cm – 0.575 V. Thismeans that each input is driven with a signal of up to cm ±0.575 V, so that each input has a maximumdifferential signal of 1.15 V
PP
for a total differential input signal swing of 2.3 V
PP
. The maximum swing isdetermined by the two reference voltages, the top reference (refpa) and the bottom reference (refma).
The ADC obtains optimum performance when the analog inputs are driven differentially. The circuit shownin Figure 6-3 shows one possible configuration using an RF transformer.
Submit Documentation Feedback ANALOG-TO-DIGITAL CONVERTERS 25
S0176-06
0.1 Fm
AC
Signal
Source
R0
50 W
10 W
inp
inm cm
AFE8405
ADT1-1WT
1:1
Z0
50 W
100nF
25 W
25 W100nF
25 W
25 W
20 )400mA fs(in MSPS)
125 MSPS
(6-1)
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
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Figure 6-3. Transformer Input to Convert Single-Ended Signal to Differential Signal
The single-ended signal is fed to the primary winding of an RF transformer. Because the input signal mustbe biased around the common-mode voltage of the internal circuitry, the common-mode voltage (V
CM
)from the ADC is connected to the center-tap of the secondary winding. To ensure a steady low-noise V
CMreference, best performance is obtained when the common-mode output is filtered to ground with a 10- Ωseries resistor and parallel 0.1- µF and 0.001- µF low-inductance capacitors.
Output V
CM
is designed to drive the ADC input directly. When providing a custom common-mode level, beaware that the input structure of the ADC sinks a common-mode current in the order of 200 µA (100 µAper input). Equation 6-1 describes the dependency of the common-mode current and the samplingfrequency:
This equation helps to design the output capability and impedance of the driving circuit accordingly.
When it is necessary to buffer or apply a gain to the incoming analog signal, it is possible to combinesingle-ended operational amplifiers with an RF transformer, or to use a differential input/output amplifierwithout a transformer, to drive the input of the AFE8405 ADC. Texas Instruments offers a wide selection ofsingle-ended operational amplifiers (including the THS3201, THS3202, OPA847, and OPA695) that canbe selected depending on the application. An RF gain block amplifier, such as Texas InstrumentsTHS9001, can also be used with an RF transformer for high-input-frequency applications. TheTHS4503/6/9 are recommended differential input/output amplifiers. Table 6-1 lists the recommendedamplifiers.
Table 6-1. Recommended Amplifiers to Drive the Input of the AFE8405
INPUT SIGNAL FREQUENCY RECOMMENDED AMPLIFIER TYPE OF AMPLIFIER USE WITH TRANSFORMER?
DC to 20 MHz THS4503/6/9 Differential in/out amplifier NoDC to 50 MHz OPA847 Operational amplifier Yes10 MHz to 120 MHz OPA695 Operational amplifier YesTHS3201 Operational amplifier YesTHS3202 Operational amplifier YesOver 100 MHz THS9001 RF gain block Yes
ANALOG-TO-DIGITAL CONVERTERS26 Submit Documentation Feedback
S0177-05
RT
100 W
+
–
OPA695
imm
imp
5V
cm
R1
400 W
0.1 Fm
AFE8405
CIN
RIN
0.1 Fm1:1
–5V
R2
57.5 W
VIN
AV=8V/V
(18dB)
RS
100 W
1000pF
10 W
RIN
S0178-02
VOCM
inm
3.3V
5V
10 Fm0.1 Fm
THS4503
RT
RS
AFE8405
14-Bit/85-MSPS
RGRF
RIN
RIN
1 Fm
10 Fm0.1 Fm
–5V
RGRF
10 W
0.1 Fm
inp
cm
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
When using single-ended operational amplifiers (such as the THS3201, THS3202, OPA847, or OPA695)to provide gain, a three-amplifier circuit is recommended with one amplifier driving the primary of an RFtransformer and one amplifier in each of the legs of the secondary driving the two differential inputs of theADC. These three amplifier circuits minimize even-order harmonics. For high-frequency inputs, an RF gainblock amplifier can be used to drive a transformer primary; in this case, the transformer secondaryconnections can drive the input of the ADC directly, as shown in Figure 6-3 , or with the addition of thefilter circuit shown in Figure 6-4 .
Figure 6-4 illustrates how R
IN
and C
IN
can be placed to isolate the signal source from the switching inputsof the ADC and to implement a low-pass RC filter to limit the input noise in the ADC. It is recommendedthat these components be included in the AFE8405 circuit layout when any of the amplifier circuitsdiscussed previously are used. The components allow fine-tuning of the circuit performance. Anymismatch between the differential lines of the ADC input produces a degradation in performance at highinput frequencies, mainly characterized by an increase in the even-order harmonics. In this case, specialcare should be taken to keep as much electrical symmetry as possible between both inputs.
Another possible configuration for lower-frequency signals is the use of differential input/output amplifiersthat can simplify the driver circuit for applications requiring dc coupling of the input. Flexible in theirconfigurations (see Figure 6-5 ), such amplifiers can be used for single-ended-to-differential conversionand signal amplification.
Figure 6-4. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
Figure 6-5. Using the THS4503 With the AFE8405
Submit Documentation Feedback ANALOG-TO-DIGITAL CONVERTERS 27
6.3 ADC Input Voltage Overstress
6.4 ADC Reference Circuit
S0179-01
20 W
refp
29
refm
30
iref
31
1 Fm
1 Fm
20 W
56.2kW
6.5 ADC Clock Input
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
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The AFE8405 ADC can handle absolute maximum voltages of 3.6 V dc on the input pins inp and inm. Fordc inputs between 3.6 V and 3.8 V, a 25- Ωresistor is required in series with the input pins. For inputsabove 3.8 V, the device can handle only transients, which must have less than 5% duty cycle ofoverstress. The input pins connect internally to an ESD diode to AVDD, as well as a switched capacitorcircuit. The sampling capacitor of the switched capacitor circuit connects to the input pins through a switchin the sample phase. In this phase, an input larger than 2.65 V would cause the switched capacitor circuitto present an equivalent load of a forward biased diode to 2.65 V in series with a 60- Ωimpedance. Also,beyond the voltage on AVDD, the ESD diode to AVDD starts to become forward biased.
In the phase where the sampling switch is off, the diode loading from the input switched capacitor circuit isdisconnected from the pin, while the ESD loading to AVDD is still present.
CAUTIONA violation of any of the previously stated conditions could damage the device (orreduce its lifetime) either due to electromigration or gate oxide integrity. Care shouldbe taken not to expose the device to input overvoltage for extended periods of time,as it may degrade device reliability.
The AFE8405 ADC has built-in internal reference generation, requiring no external circuitry on the printedcircuit board (PCB). For optimum performance, it is best to connect both refp and refm to ground with a1- µF decoupling capacitor in series with a 20- Ωresistor, as shown in the Figure 6-6 . In addition, anexternal 56.2-k Ωresistor should be connected from iref to AVSS to set the proper current for the operationof the ADC, as shown in Figure 6-6 . No capacitor should be connected between these pins; only the56.2-k Ωresistor should be used.
Figure 6-6. REFP, REFM, and IREF Connections for Optimum Performance
The AFE8405 ADC clock input can be driven with either a differential clock signal or a single-ended clockinput, with little or no difference in performance between the configurations. The common-mode voltage ofthe clock inputs is set internally to cm using internal 5-k Ωresistors that connect clkp and clkm to cm, asshown in Figure 6-7 .
ANALOG-TO-DIGITAL CONVERTERS28 Submit Documentation Feedback
S0180-01
cm
5kW
clkp
5kW
cm
clkm
6pF
3pF3pF
S0168-15
clkp
AFE8405
clkm
SquareWaveor
SineWave
0.01 Fm
0.01 Fm
S0167-11
clkp
AFE8405
clkm
DifferentialSquareWaveor
SineWave
(3V )
P-P
0.01 Fm
0.01 Fm
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
Figure 6-7. Clock Inputs
When driven with a single-ended CMOS clock input, it is best to connect clkm to ground with a 0.01- µFcapacitor, while clkp is ac-coupled with a 0.01- µF capacitor to the clock source, as shown in Figure 6-8 .
Figure 6-8. AC-Coupled, Single-Ended Clock Input
The ADC clock input can also be driven differentially, reducing susceptibility to common-mode noise. Inthis case, it is best to connect both clock inputs to the differential input clock signal with 0.01- µFcapacitors, as shown in Figure 6-9 .
Figure 6-9. AC-Coupled, Differential Clock Input
For high-input-frequency sampling, it is recommended to use a clock source with low jitter. Additionally,the internal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a50% duty cycle should be provided.
Bandpass filtering of the source can help produce a 50% duty-cycle clock and reduce the effect of jitter.When using a sinusoidal clock, the clock jitter further improves as the amplitude is increased. In thatsense, using a differential clock allows for the use of larger amplitudes without exceeding the supply railsand absolute maximum ratings of the ADC clock input.
Submit Documentation Feedback ANALOG-TO-DIGITAL CONVERTERS 29
7 RECEIVE DIGITAL SIGNAL PROCESSING
7.1 Receive Input Interface
B0106-01
FIFO
16
rxin_a(1) 16
DualRealor
SingleComplex
PowerMeter
DualRealor
SingleComplex
AGC
DualRealor
SingleComplex
AGC
DualRealor
SingleComplex
PowerMeter
FIFO
16
rxin_b(2) 16
FIFO
16
rxin_c 16
FIFO
16
rxin_d 16
dvga_c
dvga_d
dvga_a
dvga_b
6
6
6
6
18
rx_distribution
BustoDDC
Channels
TestandNoise
Signal
Generator
TestandNoise
Signal
Generator
16
16
16
16
To Testbus
TestBusSelect
andDecimation
Testbus
Sources
1to64
Sample
Delay
Line
1to64
Sample
Delay
Line
1to64
Sample
Delay
Line
1to64
Sample
Delay
Line
delay_a 18
delay_b
18
delay_c 18
delay_d
TestandNoise
Signal
Generator
TestandNoise
Signal
Generator
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
The downconversion section of the AFE8405 consists of the receive input interface, the rx_distributionbus, and eight digital downconverter blocks.
The purpose of the receive input interface is to accept signal data from three 16-bit input ports, measurethe input signal power, control the digital VGA, and distribute the data to the DDC blocks. The inputinterface also has a user-controlled test generator and noise source.
The rx_distribution bus distributes the three channels of signal data to each of the eight DDC blocks.
Each DDC block selects one of the three channels (or two for complex input data) from the rx_distributionbus and then performs downconversion tuning, programmable delay, channel filtering with decimation,power measurement, fixed gain adjust, and/or automatic gain control. Each DDC block can support oneUMTS channel, two CDMA channels, or two TD-SCDMA channels. An optional mode permits stacking twoDDC blocks in UMTS mode to provide double-length final pulse-shape filtering.
Tuned, filtered, and decimated signal data is output in bit-serial or parallel format.
(1) Hard-wired to internal ADCA(2) The rxin_b port is not used and not connected internally.
Figure 7-1. Receive Data Input Interface
The AFE8405 receive input data interface accepts data from several sources:•Signal data from the integrated 14-bit ADC (rxin_a)•Signal data presented at the two 16-bit digital data input ports (rxin_c and rxin_d)•An LFSR test signal generator allows the AFE8405 to be tested using a known repetitive datasequence.
RECEIVE DIGITAL SIGNAL PROCESSING30 Submit Documentation Feedback
7.1.1 Receive FIFO
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
For the rxin_c and rxin_d input ports, signal data can be provided in binary or 2s-complement form. Thelocation of the ADC's MSB can be programmed to allow additional AGC headroom if desired. Forexample, a 14-bit ADC may be connected with the MSBs aligned or shifited down to allow the AGCadditional gain range before clipping the signal.
Signal data can be accepted at rates up to rxclk in UMTS mode for either eight normal channels or fourdouble-length final pulse-shaping filter channels. In CDMA mode, the maximum input rate is rxclk for realinputs, or rxclk/2 for complex inputs. For maximum filter performance, higher clock rates generally allowlonger filters.
Complex signal data is input with I data driving one input port and Q data driving another. This means thatthere is only one signal data port available when using complex input mode (rxin_c and rxin_d).
Signal input data is clocked into eight-stage FIFOs using a matching external clock signal, adcclk_a/b/c/d.Signal data is clocked out of the FIFO from a gated rxclk (the AFE8405 receive section clock). The FIFOallows an arbitrary phase relationship between adcclk_a/c/d and rxclk. The frequency relationship ismandated by the programmed configuration.
The test and noise generator can supply test sequences or add noise to the input signal data. The testsequences, when combined with the checksum generators, are useful for initial board debug or power-onself-test.
For applications that require receiver desensitization, the noise generator can add noise to input datastreams.
The ADC input port, rxin_a, can be passed to the test-bus control block, decimated by 32 ×, and routeddirectly to the AFE8405 test-bus output pins. The key requirement of this function is to be able to verifiythe performance of the ADC by reconstructing the samples, while limiting the output sample rate to lessthan 5 MHz using an 85-MHz ADC sample rate.
Many other internal chip signals can be routed to the test bus for evaluation and debug purposes. Whenthe test bus is enabled, the rxin_c and rxin_d ports are driven as digital outputs.
Each of the four outputs to the DDC channels includes a 1- to 64-sample delay line.
A
PROGRAMMING
VARIABLE DESCRIPTION
ssel_ddc(2:0) Selects the sync source for the DDC data input multiplexer and mixer. This sets the sync source for DDC input clockgeneration and synchronization for all DDC channels.offset_bin_X Selects offset binary input when set, 2s complement input when cleared. X = {a, b, c, d}. Note that the internal ADCsuse 2s complement format, so offset_bin_a must be set.msb_pos_X(2:0) Identifies the connection location of the ADC’s MSB. Programmed values of {0..7} correspond to msb at {rxin_x_15..rxin_x_8}. X = {a, b, c, d}
The receive FIFO consists of an eight-stage memory and two counters generating the input write pointerand output read pointer. When the FIFO receives a sync signal, the input and output pointers areinitialized with a write-to-read pointer offset of four samples. Input samples from rxin_X (writes) areclocked with the adcclk_X input clock rising edges, and the input pointer advances on each clock risingedge. Output samples (reads) and the output pointer are clocked with the rxclk input signal rising edges,divided by the programmed sample rate loaded into the rate_sel(1:0) control register.
A
Submit Documentation Feedback RECEIVE DIGITAL SIGNAL PROCESSING 31
7.1.2 Receive Input Power Meters
B0107-01
Fromrxin_aFIFOOutput
Fromrxin_cFIFOOutput
Fromrxin_bFIFOOutput
Fromrxin_dFIFOOutput
pmeter_iq0
pmeter_iq2
pmeter_iq1
pmeter_iq3
I
I
I
I
Q
Q
Q
Q
PowerMeter0Results
PowerMeter2Results
PowerMeter1Results
PowerMeter3Results
PowerMeter0
PowerMeter2
PowerMeter1
PowerMeter3
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
PROGRAMMING
VARIABLE DESCRIPTION
adc_fifo_bypass When set, bypasses the input FIFOs and input data is latched directly using the rxclk. When cleared, input data islatched using the adcclk_a/b/c/d inputs.ssel_adc_fifo(2:0) Selects the sync source for the FIFO state machines. This sync signal initializes the FIFO input and outputpointers.rate_sel(1:0) This selects the FIFO input and output rate; {rxclk, rxclk/2, rxclk/4 or rxclk/8}. For example, with rxclk at 153.6MHz, set rate_sel to 0, 1, 2, or 3, respectively, for adcclk_a/b/c/d 153.6, 76.8, 38.4, or 19.2 MHz. Must be set thesame as DDCCONFIG1 register ch_rate_sel(1:0).adc_fifo_strap_ab When set, the rxin_a and rxin_b FIFO input and output pointers are synchronized to support complex inputsignals. (Note: rxin_b is not used.)adc_fifo_strap_cd When set, the rxin_c and rxin_d FIFO input and output pointers are synchronized to support complex inputsignals.
Figure 7-2. Receive Input Power Meters
Four receive input RMS power meters are provided by design. For real inputs, three power meters (powermeter 0/2/3) can be used to measure the RMS power of the combined carriers in each of the three inputsignals from rxin_a/c/d (the Q input is held at zero). For complex inputs from rxin_c and rxin_d, one powermeter can be use to measure the combined complex power and the other can be disabled (rxin_b is notused in the AFE8405).
RECEIVE DIGITAL SIGNAL PROCESSING32 Submit Documentation Feedback
B0108-01
21-Bit
Integration
Counter
Clear
58-Bit
Integrator
58-Bit
Register
9-Bit
SyncDelay
Counter
21-Bit
Interval
Counter
Transfer
Sync
Delay
(in8Sample
Increments)
Integration
(in8Sample
Increments)
21219
RMSPower
I
Q
33
32
16
Interval
(in8Sample
Increments)
16
32
Interrupt
T0116-01
Sync
Delay
Sync
Event
Integration Time Integration Time Integration Time
Interval Time
Interrupt Interrupt Interrupt
Interval Time
Integration
Start
Integration
Start
Integration
Start
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
Figure 7-3. Detailed Functionality of Receive Input Power Meter
Figure 7-4. Receive Input Power Meter Timing
Power is calculated by squaring each 16-bit I (I and Q for complex inputs) sample, summing, and thenintegrating the summed-squared results into a 58-bit accumulator over a programmable integration period.The integration period is programmed into the 21-bit counter, in eight-sample increments. The power readis:
Power = [(I
2
)×(N ×8 + 1)] for real inputs, where N is the integration count.Power = [(I
2
+ Q
2
)×(N ×8 + 1)] for complex inputs, where N is the integration count.
A programmable 21-bit interval counter sets the power measurement interval (how often power ismeasured) in eight-sample increments. A measurement integration period is started at the beginning ofeach interval period.
The process begins with a sync event starting the 9-bit delay counter. After (8 ×sync_delay + 2) samples,the integration interval is started. Integration continues until the integration count is met, at which point the58-bit integrator results are transferred to the read-only register and an interrupt is generated. A newmeasurement period starts at the end of the interval period.
The 21-bit counters in eight-sample increments allow up to 104.8-mS interval times at 160-MHz clock.
Submit Documentation Feedback RECEIVE DIGITAL SIGNAL PROCESSING 33
7.1.3 Receive Input AGC (RAGC)
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
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NOTEEach of the four composite RMS power meter blocks has its own delay sync, interval, andintegration period counters, as well as separate sync source registers.
PROGRAMMING
VARIABLE DESCRIPTION
recv_pmeterX(57:0) 58-bit power measurement result. X = {0, 1, 2, 3}.recv_pmeterX_sqr_sum(20:0) 21-bit integration (square and sum) period. X = {0, 1, 2, 3}.recv_pmeterX_sync_delay(8:0) Power meter delay sync period. X = {0, 1, 2, 3}.recv_pmeterX_strt_intrvl(20:0) 21-bit measurement interval. X = {0, 1, 2, 3}. The strt_intrvl value must be greater than the sqr_sumvalue.ssel_recv_pmeter_X(2:0) Sync source. X = {0, 1, 2, 3}.pmeterX_iq Selects complex power measurement input mode when set. X = {0, 1, 2, 3}.recv_pmeterX_ena Enables power meter when set. X = {0, 1, 2, 3}.
Input signals from the ADCs can be used to create a front-end composite AGC loop when combined witha digitally controlled variable-gain amplifier (DVGA) connected before the ADCs. The AGC systemoperates by integrating the square of the ADC samples over a programmable interval and applying atable-driven error signal to a loop integrator based on the squared integration output. The error table mapsthe signal power to a user-programmed error value. The loop integrator output is used to drive map tablesto control the DVGA output pins and a gain adjustment multiplier. Fast updates can be enabled if desired,to cause the loop integrator to adjust quickly to interfering signals. The ADC input signals can also bepassed through a high-pass filter to remove dc offset before squaring the input.
The programmable error table, integrator mapping tables, and clip thresholds, when combined with theuser-programmable interval timers, provide a highly flexible AGC function.
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B0109-01
FreezeControlRegisterBit
FreezeFromSyncSource
ClearControlRegisterBit
ClearSyncSource
Map
Table
MSBs
Gain
Map
Table
16
Update
Map
Table
1
08
clip_hi_thresh
clip_low_thresh
ClipDetectControls
Delay Adjust
sd_thresh
SignalDetect
ModeControls
128wx8bRAM
Update
Sync
Sync
Delay
Samples
From
ADCFIFO
IntegrateandDumpSignalPowerMeasurement
5
enable corner
no_signal
err_shift
5
32
55
6
31
16 7
{127..0}+
DVGA
Map
Table
6
Gain
Map
Table
6
Highpass
Filter X2Error
Map
Table
7
Mag Clip
Detect
clip_error 16
Signal
Level
Detect 64wx22bRAM
UpdateInterval
Loop Accumulator
toDVGA
Pins
ToDDC
Channels
acc_shift
5
Shift
and
Limit
16
Delay
acc_offset
7
Limit
{127..0}
+
16
16
Error
Shift
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
Figure 7-5. Receive Input AGC
The AGC measurement interval timer is a 24-bit timer initialized by a sync after a programmable 8-bitdelay. During the integration interval, the squared input signal is shifted by the programmed value andaccumulated. At the end of the interval time, an update pulse is generated, and the selected 7 bits of the55-bit accumulated power is upper-limit checked and transferred to the power holding register. Aprogrammable offset is applied, and the following limit check produces a 7-bit address value for the RAMerror map table. The user-programmable error map table and following gain-shift setting are used todetermine the loop error signal to be added to the 32-bit AGC loop accumulator. The error value is onlyadded to the loop accumulator once per update. The loop accumulator upper 6 MSBs are used as theaddress for the programmable DVGA map table and gain map table. The gain map table address can bedelayed from 0 to 31 clock cycles to align DVGA changes to signal level changes at the output of theAGC.
The AGC includes four sources for freezing the loop and holding the loop accumulator constant. A generalsync source can be used to control the freeze directly; when the selected sync source is high, the AGC isheld, and when low, the AGC operates. A control register bit freezes the AGC in the same fashion; whenthe bit is set, the AGC is held, and when cleared, the AGC operates. A signal level detector is providedthat can be used to freeze the AGC loop automatically in the event of input signal loss. A programmablesignal detection threshold value, number of samples below the signal detection threshold, and windowtimer are used to determine when no signal is present. Finally, a programmable number of AGC updatesafter sync can be programmed, and the AGC is held until the next sync event. Freeze holds the loopaccumulator constant, the integrate-and-dump accumulator constant, and the interval timer constant.When freeze is released, the interval timer resumes counting.
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B0110-01
17
32 hp_corner
3
Shift
and
Limit
16 16
Limit
–
+
16
17
Samples
From
ADCFIFO
Samplesto
X Block
2
hp_ena
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
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A sync event always reinitializes the integrate-and-dump interval timer and terminates the pending updateto the loop accumulator from the current integrate-and-dump measurement interval. For example, if a syncevent occurs during an integrate-and-dump interval, that interval is terminated without updating the loop,and the integrate-and-dump accumulator is cleared. After the programmed sync delay, a new intervalstarts.
The AGC includes a dual-threshold clip-detect function, using two programmable 16-bit thresholds andprogrammable counters. The clip detector causes immediate loop accumulator updates while the clipevent is active. The 16-bit clip error value is aligned at the MSBs of the loop accumulator. Clip events arequalified when a programmed number of samples are above the clip-high threshold during theprogrammable clip window time. For example, a clip event can be defined as eight samples above theclip-high threshold in a 256-sample window; the clip-high threshold, the number of samples above theclip-high threshold, and the sample window time are programmable. Once the clip event has occurred, theclip duration is controlled by the clip-low threshold value, clip-low samples value, and clip-low timer. Theclip event is cleared when the number of samples below the clip-low threshold exceeds the programmedvalue within the clip-low timer window. The clip-low threshold, number of clip-low samples, and the clip-lowwindow timer are programmable.
The AGC blocks can be paired together, rxin_a with rxin_b, and rxin_c with rxin_d, to produce a complexinput AGC mode. The clip detector output from the rxin_b/d AGCs is logically ORed with the rxin_a/c clipdetect outputs. The squared input function before the integrate-and-dump and signal-level detector isreplaced with an I
2
+ Q
2
power calculation. The accumulator MSBs from the rxin_a/c AGCs are connectedto the rxin_c/d DVGA map table and gain map table inputs. This arrangement allows the AGCs to operatein a direct-conversion receiver system by controlling the I
2
+ Q
2
complex signal level.
The high-pass filter is a 32-bit accumulator followed by an adjustable shift to control the corner frequency,a subtractor to remove the accumulated offset, and a final limiter to produce a 16-bit result. The high-passfilter function is enabled by setting hp_ena; clearing hp_ena holds the accumulator reset.
Figure 7-6. High-Pass Filter in Receive Input AGC
PROGRAMMING
VARIABLE DESCRIPTION
ragc_bypass_X Bypasses the entire receive AGC circuit when set. X = {0, 1, 2, 3}hp_ena_X Enables high pass filter when sethp_corner_X(2:0) Adjusts the corner frequency of the high-pass filterinteg_interval_X(23:0) Integrate-and-dump signal-power measurement interval in samples.acc_shift_X(4:0) Shift-down amount following the integrate-and-dump accumulator.acc_offset_X(5:0) Offset value applied to the shifted integrate-and-dump output.ragc_sync_delay_X(7:0) AGC sync delay interval, from 1 to 256 samplesssel_ragc_interval_X(2:0) Sync source selection for the interval timerssel_ragc_freeze_X(2:0) Sync source selection for AGC freeze
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7.1.4 Test and Noise Signal Generator
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
PROGRAMMING
VARIABLE DESCRIPTION
ssel_ragc_clear_X(2:0) Sync source selection for the AGC loop accumulator clearragc_freeze_X Register bit to freeze the AGC when setragc_clear_X Register bit to clear the AGC accumulator when setragc_update_X(7:0) Sets the number of updates per sync event, after which no further updates occur until the next syncevent. Program to 0x00 to update continually.sd_ena_X Enables freezing the AGC with the signal detector when setsd_thresh_X(15:0) Signal-detection threshold for AGC channel X. This 16-bit word is lined up with bits 23 down to 8 of thesquare output. The smallest signal level that can be programmed is therefore 16 LSBs on the ADCinput, and the largest is 4095 LSBs at the ADC input.sd_samples_X(15:0) The number of samples below the signal detect threshold within the signal detect sample timer windowrequired to freeze on the AGC.sd _timer_X(15:0) Window timer to qualify signal detection.clip_hi_thresh_X(15:0) Clip detector high thresholdclip_lo_thresh_X(15:0) Clip detector low thresholdclip_hi_samples_X(7:0) A clip event is detected when the number of samples above the clip-high threshold within the clip-highsample timer window exceeds this value.clip_lo_samples_X(7:0) A clip event ends when the number of samples below the clip-low threshold within the clip-low sampletimer window exceeds this value.clip_hi_timer_X(15:0) Window timer to qualify clip eventsclip_lo_timer_X(15:0) Window timer to determine when the clip event ends.clip_error_X(15:0) Error signal applied to the AGC accumulator when a clip event is active. This data is MSB aligned, andtherefore can cause immediate changes to the accumulator.ragc_error_map_X 128-word ×8-bit memory holding the log to error look up tabledvga_map_X 64-word ×6-bit memory holding the accumulator to DVGA look-up tablegain_map_X 64-word ×16-bit memory holding the accumulator to GAIN look-up table (256 decibels is unity gain).delay_adj_X(4:0) Delay between DVGA output updates and gain map updates to compensate for ADC pipeline delays,etc.err_shift_X(4:0) Error map table shift-up output before adding to loop accumulatorcomplex_01 Enables complex AGC mode on inputs rxin_a and rxin_b when setcomplex_23 Enables complex AGC mode on inputs rxin_c and rxin_d when setragc_accum_X(31:0) 32-bit read-only register holding the current contents of the loop accumulator.3-state(10:7) 3-state controls for the dvga_d/c/b/a output pins; pins are in the high-impedance state when the 3-statebits are set.ragc_mpu_ram_read When set, the receive AGC map RAMs are readable via the MPU control interface. The AFE8405 signalpath is not operational when this bit is set, it is intended for debug purposes only.
The test and noise generator can generate test signals to replace the rxin_a/b/c/d inputs as a tool fordebug, evaluation, and self-test. Checksum generators included in the individual DDC channels at theoutputs can be used in conjunction with the noise generator and the internal sync timer block to create thebuilt-in self-test function.
The test and noise signal source included in this block is a 23-bit linear feedback shift register (LFSR) witha fixed polynomial and fixed initialization state. A sync input is required to initialize the LFSR, and the syncsource is connected to the ddc_counter output signal.
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B0111-01
LFSR
0
5
22
InitializedOnSyncEvent-EachoftheFourGeneratorsHasaDifferentSeed
adcclk_X
sync lfsr(22:0)
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
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Figure 7-7. Noise Signal Generator
Receive Input Port LFSR Seed Value, MSB to LSB
rxin_a 100 0000 0000 0000 0001 0000 (0x40 0010)rxin_b 010 0110 1110 0110 1100 1110 (0x26 E6CE)rxin_c 110 1110 1010 0010 1001 1000 (0x6E A298)rxin_d 000 1011 0001 1110 1011 0111 (0x0B 1EB7)
RECEIVE DIGITAL SIGNAL PROCESSING38 Submit Documentation Feedback
B0112-01
lfsr19
lfsr16
lfsr15
lfsr14
lfsr13
lfsr12
lfsr11
lfsr22
lfsr22
lfsr22
lfsr22
lfsr22
lfsr22
lfsr20
lfsr22
lfsr18
lfsr17
lfsr16
lfsr15
lfsr14
lfsr13
lfsr12
lfsr11
lfsr10
dout9
dout15
dout14
dout13
dout12
dout11
dout10
dout8
dout7
dout6
dout5
dout4
dout3
dout2
dout1
dout0
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
The 23-bit LFSR output signal if used to create a 16-bit dout(15:0) test signal using XOR combinations ofthe LFSR bits.
Figure 7-8. Mapping of LFSR Values to Output Bits
To enable the test signal generator, the slf_tst_ena control bit is set. The rxin_a/b/c/d signals are thenreplaced by the four generator output streams. To use this test signal generator as a signal source forself-test, the user must also set the adc_fifo_bypass control bit. Setting the adc_fifo_bypass control bitcauses the adcclk_a/b/c/d input clocks to be internally replaced with rxclk/N, where N is programmed withthe rate_sel(1:0) control bits to {1, 2, 4, or 8}.
The test signal generators can also output a programmable constant value. All four test signal generatorsoutput the same programmable constant value.
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B0113-01
DatatoFIFOfor rxin_a
DatatoFIFOfor rxin_b
DatatoFIFOfor rxin_c
DatatoFIFOfor rxin_d
16
16
16
16
16
16
16
16
16
16
16
16
rxin_a
rxin_b
rxin_c
rxin_d
Testand
Noise
Generator
Testand
Noise
Generator
Testand
Noise
Generator
Testand
Noise
Generator
sync
slf_tst_ena
rduz_sens_ena
B0114-01
ToFIFOfor rxin_X
16
16
16
16
16
lfsr(15:0)
lfsr17
nz_pwr_mask(15:0)
lfsr16
rduz_sens_ena
rxin_X(15:0)
16XORs
16 ANDs
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
Figure 7-9. Block Diagram of Noise Generator Input Options
The LFSR circuits can also be used to add noise to the rxin_a/b/c/d input signals by setting therduz_sens_ena control register bit. The magnitude of the noise added can be adjusted by programmingthe nz_pwr_mask(15:0) control register. In Figure 7-10 , X = {a ,b, c, or d}.
Figure 7-10. Detail Circuit for Adding Noise Generator Signal to rxin Signal
40 RECEIVE DIGITAL SIGNAL PROCESSING Submit Documentation Feedback
7.1.5 Sample Delay Lines
7.1.6 Test Bus
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
PROGRAMMING
VARIABLE DESCRIPTION
slf_tst_ena When set, the test signal generators replace the rxin_a/b/c/d input signals with internally generatedpseudorandom sequences. The fifo_bypass bit must be set when this bit is set.rduz_sens_ena Enables the LFSR, adding noise to the ADC input data when set.nz_pwr_mask(15:0) Selects the power of the noise added to the ADC input data.adc_fifo_bypass When set, the FIFO is essentially bypassed, and the adcclk_a/b/c/d clock input ports are ignored.ddc_counter(31:0) 32-bit general-purpose counter intervalddc_counter_width(7:0) 8-bit general-purpose counter timeout pulse counterssel_ddc_counter(2:0) Sync source selection for the general purpose counterself_test_constant(17:0) 18-bit self-test constant value applied to all four rxin_a/b/c/d inputs when self_test_const_ena is set.self_test_const_ena Enables the self-test constant value for rxin_a/b/c/d
The four sample delay line blocks each consist of a 64-register memory and a state machine. The statemachine uses a counter to control the write (input) pointer, and the programmed read offset register datato create the read (output) pointer. Programming larger read offset register values increases the effectivedelay at a resolution equal to the sample rate.
The read offset registers, delay_line_X, are double-buffered. Writes to these registers may occur anytime,but the actual values used by the circuit are not updated until a delay line sync event occurs.
A
PROGRAMMING
VARIABLE DESCRIPTION
delay_line_X(5:0) Read offset into the 64-element memory for each delay line. X = {0, 1, 2, 3}.ssel_delay_line_X(2:0) Selects the sync source used to update the double-buffered delay line register.
When the test bus is enabled, the rxin_c(15:0) and rxin_d(15:0) ports become outputs, and the dvga_cand dvga_d pins are combined with the rxin_c(15:0) and rxin_d(15:0) pins to allow 36-bit wide signalsfrom the DDC channels and the receive input interface to be multiplexed to this test output port. Many ofthese sources can be decimated to reduce the output sample rates.
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B0115-02
DDC0 MUX
ddc_tst_sel(5:0)
ReceiveInterface
DDC1
DECIMATE
tst_decim17
(35:20)
(19:18)
(17:2)
(1:0)
tst_clk
tst_aflag
tst_sync
rxin_d(15:0)
rxin_c(15:0)
dvga_c(3:2)
dvga_c(5:4)
dvga_d(5)
dvga_c(0)
dvga_c(1)
Sync
pfiroutput
cfiroutput
zeros
tadjchannel A
tadjchannelB
ncosin
ncocos
cicoutput
DDC2
DDC3
DDC4
DDC5
DDC6
DDC7
MUX
tst_select(3:0)
mixeri*cos&i*sin
mixerq*cos&q*sin
ddcmuxchannel A
ddcmuxchannelB
rxin_aFIFOOutputs
tst_decim_delay
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
Figure 7-11. Test Bus Output Circuit Showing Options for Selecting Signal
PROGRAMMING
VARIABLE DESCRIPTION
ssel_tst_decim(2:0) Selects the sync source for the testbus decimatortst_decim_delay(3:0) Sets the test-bus decimator delay from synctst_decim17 Must be clearedtst_on Enables the test bus; rxin_c(15:0) and rxin_d(15:0) are changed from inputs to outputs, dvga_c(5:0) anddvga_d(5) are used as part of the test bus.tst_select(3:0) Selects the source block for the testbus output: DDC0–DDC7 or receive interface.ddc_tst_sel(5:0) Selects the signal to be output from the DDC blocktst_rate_sel(4:0) Sets the test-bus output clock period to (tst_rate_sel + 1) rxclk cycles. When the testbus source is set tothe ADC FIFO, tst_rate_sel(4:0) must be set to 0 for an output.tst_clk_pol Selects the polarity of the test clock output at dvga_c(1) when the test bus is enabled; 0 for rising edgein the center of valid data, 1 for falling edge in the center of valid data. No effect when tst_rate_sel is0 0000.
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7.2 DDC Organization
B0116-01
DDC5
DDC4
DDC3
DDC2
DDC1
4to2(Complex)or
4to1(Real)Switch
4to2(Complex)or
4to1(Real)Switch
CDMA DDC A
CDMA DDCB
Output
Interface
or1UMTSDDC
DDC0
18
18
18
18
DDC6
DDC7
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
Figure 7-12. DDC Organization for Single-Length Filter Mode
The AFE8405 provides downconversion for up to eight UMTS receive channels, 16 CDMA2000 receivechannels or 16 TD-SCDMA receive channels. Downconversion channels are organized into 8 DDC blocks.Each individual DDC block provides two CDMA2000 or two TD-SCDMA DDC channels, A and B, or oneUMTS channel.
Both CDMA DDC channels in a DDC block can be independently tuned, though they would likely be usedas diversity pairs and tuned to the same frequency. Filter coefficients are shared between the two CDMADDC channels within a block.
Two adjacent DDC blocks (for example, DDC0 and DDC1) can be strapped together to form a singleUMTS DDC channel with double-length final pulse shaping filtering. The AFE8405 can therefore providefour UMTS DDC channels with double-length final PFIR filtering as shown in the following diagram.
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B0117-01
4to2(Complex)or
4to1(Real)Switch
4to2(Complex)or
4to1(Real)Switch
4to2(Complex)or
4to1(Real)Switch
4to2(Complex)or
4to1(Real)Switch
CDMA DDC A
CDMA DDC A
CDMA DDCB
CDMA DDCB
Output
Interface
Output
Interface
or1UMTSDDC
DDC0
DDC1
DDC0PlusDDC1
DDC2PlusDDC3
DDC6PlusDDC7
DDC4PlusDDC5
18
18
18
18
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
www.ti.com
Figure 7-13. DDC Organization for Double-Length Filter Mode
PROGRAMMING
VARIABLE DESCRIPTION
ddc_ena When set, turns on the DDC.cdma_mode When set, puts the DDC block in dual-channel CDMA mode.gbl_ddc_write When set, all subsequent programming (writes only) for DDC0 and DDC1 is also written to DDC2/4/6 and DDC3/5/7.
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7.2.1 Downconverter Function Blocks
B0118-01
4to2
Select
18
18
18
18
32
16
Frequency
Phase
NCO
Delay
Adjust
Zero
Pad
SixStage
CICFilter
Dec4to32
CFIR
Filter
Decby2
PFIR
Filter
Decby1
AGC Serial
Interface
RMSPower
Measure
SerialI,Q
upto18
(25-BitsWith
AGCDisabled)
From
rx_distribution
Bus
Checksum
Generator
ParallelI,Q
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
Figure 7-14. DDC Functional Block Diagram
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7.2.2 DDC Mixer
B0119-01
4to2
Select
18
18
18
18
18
18
18
18
20 20
18
18
Demux
and
Round
Sin Cos
FromNCO
mixer_gain
From
rx_distribution
Bus
IATo
Channel
Delay
QA
QB
IB
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
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Each AFE8405 downconversion block can process two CDMA carriers or a single UMTS carrier. Signaldata is selected from one of four ports for real inputs, or two of four ports for complex inputs. Data fromthe selected port(s) is multiplied with a complex, programmable, numerically controlled oscillator (NCO)which tunes the signal of interest to baseband. The delay adjust and zero pad blocks permit adjustment ofthe delay in the end-to-end channel. Zero padding interpolates the signal to the rxclk rate. Filteringconsists of a six-stage CIC filter which decimates the tuned data by a factor from 4 to 32, a compensatingFIR filter (CFIR) which decimates by a factor of two, followed by a programmable FIR filter (PFIR) whichdoes not decimate. The output interface block can be programmed to decimate by 2 if desired.
The RMS power meter measures the power within the channel bandwidth. The AGC automatically drivesthe gain and keeps the magnitude of the signal at a user-specified level. This allows fewer bits torepresent the signal. The serial output interface formats and rounds the output data. Each of thepreviously mentioned blocks is described in greater detail in the following sections.
Figure 7-15. Mixer Functional Block Diagram
The receive mixer translates the input (from one of the input signal sources) to baseband wheresubsequent filtering is performed to isolate the signal of interest. The mixer is a complex multiplier thataccepts 18-bit I and 18-bit Q signal data from the receive input interface and 20-bit sine and cosinesequences from the NCO. The NCO generates a mixing frequency (sometimes referred to as a localoscillator, or LO) specified by the user so that the desired signal is tuned to 0 Hz.
A DDC channel can support one UMTS signal directly, or two CDMA channels at half the input rate. Whenin CDMA mode, the path selection and the mixer tuning and phase of each channel can be setindependently. The mixer output produces two complex streams; one representing the signal path for theA-side DDC, the other for the B-side. Each of these streams drives a channel delay and zero pad block.
The maximum input rate for UMTS is rxclk for either real or complex input data.
The maximum input rate in CDMA mode with real inputs is rxclk (remix_only is set, see the following).
The maximum input rate in CDMA mode with complex inputs is rxclk/2 due to sharing of multiplierresources.
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7.2.3 DDC Numerically Controlled Oscillator (NCO)
B0120-01
Reg
32
FrequencyWord 32
FrequencySync
Reg 32
ZeroPhaseSync
Clear
23
Reg
16
PhaseOffset 16
PhaseOffsetSync
23 Sin/Cos
Table
20
20
Dither
Generator
DitherSync
5
Aligned
toBottom
5Bits
Aligned
toBottom
32Bits
cos
sin
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PROGRAMMING
VARIABLE DESCRIPTION
ddcmux_sel_a(3:0) Programs the I and Q complex input data routing onto two of the four input ports for stream A of CDMA DDCddcmux_sel_b(3:0) Programs the I and Q complex input data routing onto two of the four input ports for stream B of CDMA DDCremix_only For CDMA mode only, set this bit for real input data at the rxclk rate.For complex inputs in CDMA mode, the maximum input data rate is rxclk/2, and this bit must be cleared.For CDMA mode with real inputs at the rxclk/2 rate or lower, this bit must be cleared.zero_qsample When set, the Q samples used by the mixer are always zero. This bit should be set for real only inputs in UMTSmode, or real-only inputs in CDMA mode when the input sample rate is rxclk/2 or lower.ch_rate_sel(1:0) Specifies the input channel data rate (rxclk, rxclk/2, rxclk/4, or rxclk/8 MSPS). MUST BE SET THE SAME ASREGISTER rate_sel(1:0).
mixer_gain When asserted, adds 6 dB of gain in the mixer. This gain is highly recommended.
Figure 7-16. Detailed NCO Circuit
The NCO is a digital complex oscillator that is used to translate (or downconvert) an input signal of interestto baseband. The block produces programmable complex digital sinusoids by accumulating a frequencyword which is programmed by the user. The output of the accumulator is a phase argument that indexesinto a sin/cos ROM table which produces the complex sinusoid. A phase offset can be added prior toindexing if desired for channel calibration purposes. This changes the sin/cos phase with respect to theNCOs of other channels.
A 5-bit dither generator is provided and generates a small level of digital pseudonoise that is added to thephase argument below the bottom bits and is useful for reducing NCO spurious outputs. This dithergeneration is enabled by setting the dither_ena bit; the magnitude of the dither can be reduced by settingone or both of the dither_mask bits.
A
DITHER PROGRAMMING
VARIABLE DESCRIPTION
dither_ena When set, turns dither on. Clearing turns dither off.dither_mask(1:0) Masks the MSB and MSB – 1 dither bits, respectively, when set.
The NCO spurious levels are better than –115 dBc. Added phase dither randomizes the periodic nature ofthe phase accumulation process and reduces low-level spurious energy. For some frequencies (N ×Fs/24, where N = {1, 2, ..., 23}), dither is ineffective. In these cases, an initial phase of 4 reduces NCOspurs. Figure 7-17 shows the spur level performance of the NCO without dither, with dither, and with aphase offset value.
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a) Worst Case Spectrum Without Dither
b) Spectrum With Dither (Tuned to Same Frequency
a) Plot Without Dither or Phase Initialization
b) Plot With Dither or Phase Initialization
AFE8405
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Figure 7-17. NCO SFDR - Without Dither Figure 7-18. NCO SFDR - With Dither
Figure 7-19. NCO Spectra (0 and Fs/4) - Without Dither Figure 7-20. NCO Spectra (0 and Fs/4) - With Dither oror Phase Initialization Phase Initialization
The tuning frequency is specified as a 32-bit frequency word and is programmed as two sequential 16-bitwords over the control port. The NCO frequency resolution is f
clk
/ 2
32
, where f
clk
is the ADCCLK frequency.As an example, at an input clock rate of 61.44 MHz, the frequency step size would be approximately 14mHz. The frequency word is determined by the formula:Frequency word (in decimal) = 2
32
×tuning frequency / f
clk
Note that frequency tuning words can be positive or negative valued. Specifying a positive frequencyvalue translates complex negative frequencies upwards towards 0 Hertz. Specifying a negative tuningfrequency translates complex positive frequencies downwards towards 0 Hz.
A
FREQUENCY PROGRAMMING
VARIABLE DESCRIPTION
phase_add_a(31:0) 32-bit tuning frequency word for the A-side DDC when in CDMA mode. Also for UMTS mode.phase_add_b(31:0) 32-bit tuning frequency word for the B-side DDC when in CDMA mode. Not used in UMTS mode.
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7.2.4 DDC Filtering and Decimation
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Each of the 16 CDMA DDC channels can be loaded with unique frequency values.
The phase of the NCO sin/cos output can be adjusted relative to the phase of other channel NCOs byspecifying a phase offset. The phase offset is programmed as a 16-bit word, yielding a step size of about5.5 m °. The phase offset word is determined by the formula:Phase offset word = 2
16
×offset_in_degrees / 360, orPhase offset word = 2
16
×offset_in_radians / 2 π
A
PHASE PROGRAMMING
VARIABLE DESCRIPTION
phase_offset_a(15:0) 16-bit phase offset word for the A-side DDC when in CDMA mode. Also for UMTS mode.phase_offset_b(15:0) 16-bit phase offset word for the B-side DDC when in CDMA mode. Not used in UMTS mode.
Each of the 16 CDMA DDC channels can be loaded with unique phase-offset values.
Various synchronization signals are available which are used to synchronize the NCOs of all channelswith respect to each other. Frequency sync and phase-offset sync determine when frequency and phaseoffset changes occur. For example, generating a frequency sync after programming the two frequencywords causes the NCO (or multiple NCOs) to change frequency at that time, rather than after each of thethree frequency words is programmed over the control bus. The zero-phase sync signal is used to forcethe sine and cosine oscillators to their zero-phase state. Dither sync can be used to synchronize the dithergenerators of multiple NCOs. The NCOs used in the transmit section are identical to what is described forthe receive section. Note that there is one set of syncs provided for each DDC. When one DDC is used toprocess two CDMA signals, the syncs are shared between them.
A
SYNC PROGRAMMING
VARIABLE DESCRIPTION
ssel_nco(2:0) Sync source for NCO accumulator resetssel_dither(2:0) Sync source for NCO dither resetssel_freq(2:0) Sync source for NCO frequency register loadingssel_phase(2:0) Sync source for NCO phase register loading
The purpose of the receive filter chain is to isolate the signal of interest (and reject all others) that hasbeen previously translated to baseband via the mixer and NCO. The overall decimation through the chainmust be considered. The goal, generally, is to output the isolated signal at a rate that is twice (2 ×) thesignal’s chip rate. For UMTS this would be 7.68 MSPS and for CDMA the output rate should be 2.4576MSPS. TD-SCDMA systems require the output rate be the chip rate of 1.28 MSPS. The output interface isprogrammed to decimate by 2 for the TD-SCDMA case.
Receive filtering and decimation is performed in several stages:1. Zero-padding to interpolate the input sample rate (if needed) up to the rxclk rate2. High-rate decimation (4 to 32) using a six-stage cascade-integrate-comb filter (CIC)3. Decimate-by-two compensation filtering using the programmable compensating FIR filter (CFIR)4. Pulse-shape filtering via the programmable FIR filter (PFIR) with no decimation5. Output interface, serial or parallel format, with no decimation or decimate-by-2
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B0121-01
Delay
Adjust
ZeroPad
Interpby{1,2,4,8}
PFIRFilter
NoDecimation
OutputInterface
Decby{1,2}
SixStage
CICFilter
Decby{4–32}
CFIRFilter
Decby2
From
Mixer
7.2.5 DDC Channel Delay Adjust and Zero Insertion
B0122-01
18
InputRate
SamplesFrom
Mixer
ReadOffset 3
InsertOffset
Sync(ZeroStuffMoment)
Zero
Pad
18
I
Q
DelayMemory
I:8Slots 18Bits
Q:8Slots 18Bits
´
´
18
18
18
18
I
Q
3
FullrxclkRate
Samplesto
CICFilter
Sync(OffsetRegisters)
Interpolation
(NumberofZerosStuffedBetweenSamples)
3
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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Figure 7-21. DDC Filtering Functional Block Diagram
Table 7-1 contains some examples of decimation and sample rates at the output of each block for UMTS,CDMA and TD-SCDMA standards at various supported input samples. For each example, the differentialADC clocks are provided to the AFE8405 at the input sample rate and rxclk is provided at the zero-padoutput rate.
Table 7-1. Examples of Decimation and Sample Rates
(1)
Input Zeros rxclk(MHz) and CIC CIC CFIR CFIR PFIR PFIR OutputSample Added Zero-Pad Decimation Output Decimation Output Decimation Output DecimationRate Output Rate Rate Rate Rate(MSPS) (MSPS) (MSPS) (MSPS) (MSPS)
UMTS 76.80 1 153.6 10 15.36 2 7.68 1 7.68 1
UMTS 61.44 1 122.88 8 15.36 2 7.68 1 7.68 1
CDMA 78.6432 0 78.6432 16 4.9152 2 2.4576 1 2.4576 1
CDMA 78.6432 1 157.2864 32 4.9152 2 2.4576 1 2.4576 1
CDMA 61.44 1 122.88 25 4.9152 2 2.4576 1 2.4576 1
TD-SCDMA 81.92 0 81.92 16 5.12 2 2.56 1 2.56 2
TD-SCDMA 76.80 0 76.80 15 5.12 2 2.56 1 2.56 2
TD-SCDMA 76.80 1 153.6 30 5.12 2 2.56 1 2.56 2
TD-SCDMA 61.44 1 122.88 24 5.12 2 2.56 1 2.56 2
(1) The DDC output interfaces, both serial and parallel formats, can be programmed to decimate by 2. For the TD-SCDMA examples listed,the DDC output rate is 1.28 Msps (1 ×chip rate).
Figure 7-22. DDC Delay and Zero Insertion Block
The receive-channel delay-adjust function is used to add programmable delays in the channeldownconvert path. Adjusting channel delay can be used to compensate for analog elements external tothe AFE8405 digital downconversion such as cables, splitters, analog downconverters, filters, etc.
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7.2.6 DDC CIC Filter
B0123-01
Z–1 Z–1
Z–m1 Z–m2 Z–m3 Z–m4 Z–m5 Z–m6
Z–1 Z–1 Z–1 Z–1
Shift
Decimate
by4–32
N
Round
and
Limit
24 18
Shift
0–31
18 54
24
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The delay memory block consists of an eight-register memory and a state machine. The state machineuses a counter to control the write (input) pointer, and the programmed read offset register data to createa read (output) pointer. Programming larger read offset register values increases the effective delay at aresolution equal to the input sample rate.
The zero-pad block is used in conjunction with the delay memory for delay adjustments. For example, withinput rates of rxclk/8, the zero-pad block interpolates the input data to rxclk by inserting seven zeros. Thezero-pad’s sync and insert-offset controls specify when the zeros are inserted relative to the sync signal.This permits a fine adjustment at the rxclk resolution.
The read offset register, tadf_offset_course_a/b, and the insert offset register, tadj_offset_fine_a/b, aredouble-buffered. Writes to these registers may occur anytime, but the actual values used by the circuit arenot updated until a register sync.
A
PROGRAMMING
VARIABLE DESCRIPTION
tadj_offset_coarse_a(2:0) Read offset into the eight-element memory for the UMTS or CDMA mode-A channel DDC.tadj_offset_coarse_b(2:0) Read offset into the eight-element memory for the CDMA mode-B channel DDC when in CDMA mode.tadj_offset_fine_a(2:0) Controls the zero-pad (or stuff) insert offset (fine adjust) for the UMTS or CDMA mode-A channel of theDDC.tadj_offset_fine_b(2:0) Controls the zero-pad (or stuff) insert offset (fine adjust) for the CDMA mode-B channel of the DDCwhen in CDMA mode.tadj_interp(2:0) The interpolation value (1, 2, 4, or 8). Same used for both the A and B channels when in CDMA mode.Selects the number of zeros to be inserted.ssel_tadj_fine(2:0) Selects the sync source for the fine time-adjust, zero-stuff moment. Same for A and B channels when inCDMA mode.ssel_tadj_reg(2:0) Selects the sync source used to update the double-buffer caurse- and fine-delay selection registers.Same for A and B channels when in CDMA mode.
Figure 7-23. DDC CIC Filter Block Diagram
The CIC filter provides the first stage of filtering and large-value decimation. The filter consists of sixstages and decimates over a range from 4 to 32.
I data and Q data are handled separately with two CIC filters. In addition, when in CDMA mode (twoCDMA channels processed within a single DDC), another pair of CIC filters handles the B-side channel.
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7.2.7 DDC Compensating FIR Filter (CFIR)
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The filter response is 6 ×(sin(x)/x) in character where the key attribute is that the resulting response nullssignal aliases from decimation. A consequence of this desirable behavior is that only a small portion of thepassband can be used, generally less than 25%. This means that the CIC decimation value should bechosen so that the signal exiting the CIC filter is oversampled by at least a factor of four.
The filter is equivalent to six stages of an FIR filter with uniform coefficients (six combined boxcar filterstages). Each filter would be of length N if m = 1, or 2N if m = 2.
The filter is made up of six banks of 54-bit accumulator sections followed by six banks of 24-bit subtractorsections. Each of the subtractor sections can be independently programmed with a differential delay ofeither one or two. A shift block follows the last integration stage and can shift the 54-bit accumulated datadown by 36-rcic_shift (a programmable factor from 0 to 31 bits).
The CIC filter exhibits a droop across its frequency response. The following CFIR filter compensates forthe CIC droop with a gradually rising frequency response. It is also possible to compensate for CIC droopin the PFIR filter.
The gain of the receive CIC filter is:Ncic
6
×2
(number of stages where M=2)
×2
(–36+RCIC_SHIFT)
, where RCIC_SHIFT is 0 to 31.
There is no rollover protection internal to the CIC or at the final round, so the user must ensure no sampleexceeds full scale prior to rounding. For practical purposes, this means the CIC gain can only compensatefor peak gain less than one or must be less than or equal to one. A fixed gain of 12 dB at the output of theCIC can also be programmed.
A
PROGRAMMING
VARIABLE DESCRIPTION
cic_decim(4:0) The CIC decimation ratio (4 to 32). The ratio is cic_decim + 1. This ratio applies to both A and B channels ofthe DDC block in CDMA mode.cic_scale_a(4:0) The shift value for the A channel. A value of 0 is no shift; each increment in value increases the amplitude ofthe shifter output by a factor of 2.cic_scale_b(4:0) The shift value for the B channel. A value of 0 is no shift; each increment in value increases the amplitude ofthe shifter output by a factor of 2.cic_gain_ddc When asserted, adds a gain of 12 dB at the CIC output.cic_m2_ena_a(5:0) Sets the differential delay value M for each of the CIC subtractor stages for the UMTS or CDMA mode Achannel.cic_m2_ena_b(5:0) Sets the differential delay value M for each of the CIC subtractor stages for the CDMA mode B channel.cic_bypass Bypasses the CIC filter when set, for factory use only.ssel_cic(2:0) Sets syncing (1 of 8 sources) for the CIC decimation moment.
The receive compensating FIR filter (CFIR) decimates the output of the CIC filter by a fixed factor of two.Filter coefficient size, input data size, and output data size are 18 bits. The CFIR length can beprogrammed. This permits turning off taps and saving power if shorter filters are appropriate (the CFIRpower dissipation is proportional to its length).
The filter is organized in two partial filter blocks, each containing a data RAM, a coefficient RAM, and adual multiplier; and a common state machine and output accumulator.
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B0124-01
MPUControl
Interface
Complex
Input
Samples
COEF
RAM
32x18
DATA
RAM
64x36
DATA
RAM
64x36
Reg
Complex
Output
Samples
Output
Sample
Valid
crastarttap StateMachine
Read
Pointer
Write
Pointer
WritePointer
MUX
ReadPointer
mpu
ram_read
ReadData
WriteData
COEF
RAM
32x18
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Figure 7-24. DDC CFIR Block Diagram
The maximum CFIR filter length is a function of AFE8405 rxclk clock rate, output sample rate, and thenumber of coefficient memory registers. The maximum number of taps is 64 and the minimum number is14. Lengths between these limits can be specified in increments of 2.
Subject to the above minimum and maximum values, in the general case, the number of taps available is:UMTS mode: 2 ×(rxclk କtput sample rate)CDMA mode if cic_decim is even (decimating by an odd number): 2 ×(cic_decim)CDMA mode if cic_decim is odd (decimating by an even number): 2 ×(cic_decim + 1)
Example CFIR filter lengths available based on mode and rxclk frequency:
A
Mode rxclk CIC cic_decim CFIR CFIR COMMENTS(MHz) DECIMATION MAX LENGTH MIN LENGTH
UMTS 153.6 10 9 40 14 UMTSUMTS 122.88 8 7 32 14 UMTSCDMA 157.2864 32 31 64 14 CDMA2000CDMA 122.88 25 24 48 14 CDMA2000CDMA 78.6432 16 15 32 14 CDMA2000 low-power configurationCDMA 153.6 30 29 60 14 TD-SCDMACDMA 81.92 16 15 32 14 TD-SCDMACDMA 76.8 15 14 28 14 TD-SCDMA low-power configuration
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A single set of programmed tap values is used for both the A-side and B-side DDC channels (two CDMAchannels) within a single DDC block when in CDMA mode.
After the CFIR filter performs the convolution, gain is applied at full precision, the signal is rounded, andthen hard limited. A shifter at the output of the filter then scales the data by either 2e-19 or 2e-18. Thegain through the filter is therefore:Sum(CFIR coefficients) x 2
–(18 or 19)
Coefficients are organized in two groups of 32 words, each 18 bits wide. For fully utilized filters, the 64coefficients are loaded 0 through 31 into the first RAM, and 32 through 63 into the second RAM. The16-bit MSBs and 2-bit LSBs are written into the RAMs using different page register values. Shorter filtersrequire the coefficients be loaded into the 2 RAMs equally, starting from address 0.
For example, a CFIR coefficient set for a symmetric 58-tap TD-SCDMA CFIR is:
Taps Coefficient Taps Coefficient
0 = 57 –13 15 = 42 –4,9751 = 56 –20 16 = 41 –4,6492 = 55 14 17 = 40 –2323 = 54 101 18 = 39 6,5814 = 53 184 19 = 38 11,2665 = 52 133 20 = 37 8,9176 = 51 –147 21 = 36 –1,9577 = 50 –562 22 = 35 –16,7368 = 49 –768 23 = 34 –25,4699 = 48 –364 24 = 33 –17,59910 = 47 719 25 = 32 11,56011 = 46 1,905 26 = 31 56,45512 = 45 2,126 27 = 30 102,21513 = 44 567 28 = 29 131,07114 = 43 –2,416
The first 29 coefficients are loaded into addresses 0 through 28 in the first coefficient RAM, and theremaining 29 are loaded into addresses 0 through 28 in the second coefficient RAM. Loading the 18-bitcoefficients requires 2 writes per coefficient, one for the upper 16 bits and another for the lower 2 bits.
To program this coefficient set for the DDC2 CFIR, the following control microprocessor interfacesequence would be used.
A
Step Address Data Descriptiona[5:0] d[15:0]
1 0x21 0x0480 Page register for DDC2 CFIR Coefficient RAM 0–31, LSBs.2 0x00 0x0003 Lower 2 bits of coefficient 03 0x01 0x0000 Lower 2 bits of coefficient 14 0x02 0x0002 Lower 2 bits of coefficient 25 0x03 0x0001 Lower 2 bits of coefficient 36 0x04 0x0000 Lower 2 bits of coefficient 47 0x05 0x0001 Lower 2 bits of coefficient 58 0x06 0x0001 Lower 2 bits of coefficient 69 0x07 0x0002 Lower 2 bits of coefficient 710 0x08 0x0000 Lower 2 bits of coefficient 811 0x09 0x0000 Lower 2 bits of coefficient 9
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Step Address Data Descriptiona[5:0] d[15:0]
12 0x0A 0x0003 Lower 2 bits of coefficient 1013 0x0B 0x0001 Lower 2 bits of coefficient 1114 0x0C 0x0002 Lower 2 bits of coefficient 1215 0x0D 0x0003 Lower 2 bits of coefficient 1316 0x0E 0x0000 Lower 2 bits of coefficient 1417 0x0F 0x0001 Lower 2 bits of coefficient 1518 0x10 0x0003 Lower 2 bits of coefficient 1619 0x11 0x0000 Lower 2 bits of coefficient 1720 0x12 0x0001 Lower 2 bits of coefficient 1821 0x13 0x0002 Lower 2 bits of coefficient 1922 0x14 0x0001 Lower 2 bits of coefficient 2023 0x15 0x0003 Lower 2 bits of coefficient 2124 0x16 0x0000 Lower 2 bits of coefficient 2225 0x17 0x0003 Lower 2 bits of coefficient 2326 0x18 0x0001 Lower 2 bits of coefficient 2427 0x19 0x0000 Lower 2 bits of coefficient 2528 0x1A 0x0003 Lower 2 bits of coefficient 2629 0x1B 0x0003 Lower 2 bits of coefficient 2730 0x1C 0x0003 Lower 2 bits of coefficient 2831 0x1D 0x0000 Lower 2 bits of unused coefficient RAM location32 0x1E 0x0000 Lower 2 bits of unused coefficient RAM location33 0x1F 0x0000 Lower 2 bits of unused coefficient RAM location34 0x21 0x04A0 Page register for DDC2 CFIR Coefficient RAM 32–63, LSBs.35 0x00 0x0003 Lower 2 bits of coefficient 2936 0x01 0x0003 Lower 2 bits of coefficient 3037 0x02 0x0003 Lower 2 bits of coefficient 3138 0x03 0x0000 Lower 2 bits of coefficient 3239 0x04 0x0001 Lower 2 bits of coefficient 3340 0x05 0x0003 Lower 2 bits of coefficient 3441 0x06 0x0000 Lower 2 bits of coefficient 3542 0x07 0x0003 Lower 2 bits of coefficient 3643 0x08 0x0001 Lower 2 bits of coefficient 3744 0x09 0x0002 Lower 2 bits of coefficient 3845 0x0A 0x0001 Lower 2 bits of coefficient 3946 0x0B 0x0000 Lower 2 bits of coefficient 4047 0x0C 0x0003 Lower 2 bits of coefficient 4148 0x0D 0x0001 Lower 2 bits of coefficient 4249 0x0E 0x0000 Lower 2 bits of coefficient 4350 0x0F 0x0003 Lower 2 bits of coefficient 4451 0x10 0x0002 Lower 2 bits of coefficient 4552 0x11 0x0001 Lower 2 bits of coefficient 4653 0x12 0x0003 Lower 2 bits of coefficient 4754 0x13 0x0000 Lower 2 bits of coefficient 4855 0x14 0x0000 Lower 2 bits of coefficient 4956 0x15 0x0002 Lower 2 bits of coefficient 5057 0x16 0x0001 Lower 2 bits of coefficient 5158 0x17 0x0001 Lower 2 bits of coefficient 5259 0x18 0x0000 Lower 2 bits of coefficient 53
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Step Address Data Descriptiona[5:0] d[15:0]
60 0x19 0x0001 Lower 2 bits of coefficient 5461 0x1A 0x0002 Lower 2 bits of coefficient 5562 0x1B 0x0000 Lower 2 bits of coefficient 5663 0x1C 0x0003 Lower 2 bits of coefficient 5764 0x1D 0x0000 Lower 2 bits of unused coefficient RAM location65 0x1E 0x0000 Lower 2 bits of unused coefficient RAM location66 0x1F 0x0000 Lower 2 bits of unused coefficient RAM location67 0x21 0x04C0 Page register for DDC2 CFIR Coefficient RAM 0–31, MSBs.68 0x00 0xFFFC Upper 16 bits of coefficient 069 0x01 0xFFFB Upper 16 bits of coefficient 170 0x02 0x0003 Upper 16 bits of coefficient 271 0x03 0x0019 Upper 16 bits of coefficient 372 0x04 0x002E Upper 16 bits of coefficient 473 0x05 0x0021 Upper 16 bits of coefficient 574 0x06 0xFFDB Upper 16 bits of coefficient 675 0x07 0xFF73 Upper 16 bits of coefficient 776 0x08 0xFF40 Upper 16 bits of coefficient 877 0x09 0xFFA5 Upper 16 bits of coefficient 978 0x0A 0x00B3 Upper 16 bits of coefficient 1079 0x0B 0x01DC Upper 16 bits of coefficient 1180 0x0C 0x0213 Upper 16 bits of coefficient 1281 0x0D 0x008D Upper 16 bits of coefficient 1382 0x0E 0xFDA4 Upper 16 bits of coefficient 1483 0x0F 0xFB24 Upper 16 bits of coefficient 1584 0x10 0xFB75 Upper 16 bits of coefficient 1685 0x11 0xFFC6 Upper 16 bits of coefficient 1786 0x12 0x066D Upper 16 bits of coefficient 1887 0x13 0x0B00 Upper 16 bits of coefficient 1988 0x14 0x08B5 Upper 16 bits of coefficient 2089 0x15 0xFE16 Upper 16 bits of coefficient 2190 0x16 0xEFA8 Upper 16 bits of coefficient 2291 0x17 0xE720 Upper 16 bits of coefficient 2392 0x18 0xEED0 Upper 16 bits of coefficient 2493 0x19 0x0B4A Upper 16 bits of coefficient 2594 0x1A 0x3721 Upper 16 bits of coefficient 2695 0x1B 0x63D1 Upper 16 bits of coefficient 2796 0x1C 0x7FFF Upper 16 bits of coefficient 2897 0x1D 0x0000 Upper 16 bits of unused coefficient RAM location98 0x1E 0x0000 Upper 16 bits of unused coefficient RAM location99 0x1F 0x0000 Upper 16 bits of unused coefficient RAM location100 0x21 0x04E0 Page register for DDC2 CFIR Coefficient RAM 32–63, MSBs.101 0x00 0x7FFF Upper 16 bits of coefficient 29102 0x01 0x63D1 Upper 16 bits of coefficient 30103 0x02 0x3721 Upper 16 bits of coefficient 31104 0x03 0x0B4A Upper 16 bits of coefficient 32105 0x04 0xEED0 Upper 16 bits of coefficient 33106 0x05 0xE720 Upper 16 bits of coefficient 34107 0x06 0xEFA8 Upper 16 bits of coefficient 35
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7.2.8 DDC Programmable FIR Filter (PFIR)
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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Step Address Data Descriptiona[5:0] d[15:0]
108 0x07 0xFE16 Upper 16 bits of coefficient 36109 0x08 0x08B5 Upper 16 bits of coefficient 37110 0x09 0x0B00 Upper 16 bits of coefficient 38111 0x0A 0x066D Upper 16 bits of coefficient 39112 0x0B 0xFFC6 Upper 16 bits of coefficient 40113 0x0C 0xFB75 Upper 16 bits of coefficient 41114 0x0D 0xFB24 Upper 16 bits of coefficient 42115 0x0E 0xFDA4 Upper 16 bits of coefficient 43116 0x0F 0x008D Upper 16 bits of coefficient 44117 0x10 0x0213 Upper 16 bits of coefficient 45118 0x11 0x01DC Upper 16 bits of coefficient 46119 0x12 0x00B3 Upper 16 bits of coefficient 47120 0x13 0xFFA5 Upper 16 bits of coefficient 48121 0x14 0xFF40 Upper 16 bits of coefficient 49122 0x15 0xFF73 Upper 16 bits of coefficient 50123 0x16 0xFFDB Upper 16 bits of coefficient 51124 0x17 0x0021 Upper 16 bits of coefficient 52125 0x18 0x002E Upper 16 bits of coefficient 53126 0x19 0x0019 Upper 16 bits of coefficient 54127 0x1A 0x0003 Upper 16 bits of coefficient 55128 0x1B 0xFFFB Upper 16 bits of coefficient 56129 0x1C 0xFFFC Upper 16 bits of coefficient 57130 0x1D 0x0000 Upper 16 bits of unused coefficient RAM location131 0x1E 0x0000 Upper 16 bits of unused coefficient RAM location132 0x1F 0x0000 Upper 16 bits of unused coefficient RAM location133 0x21 0x0500 Page register for DDC2 control registers 0–31134 0x00 0x8EE0 DDC2 FIR_MODE register; cdma_mode enabled, 60-tap PFIR, 58-tap CFIR135 0x01 0x2000 DDC2 PFIR gain = sum(taps) ×2
–18
and CFIR gain = sum(taps) ×2
–19
A
PROGRAMMING
VARIABLE DESCRIPTION
crastarttap_cfir(4:0) Number of DDC CFIR filter taps is 2 ×gbl_ddc_writegbl_ddc_writegbl_ddc_writempu_ram_read What set, the PFIR and CFIR coefficient rams are readable via the MPU control interface. The AFE8405 signalpath is not operational when this bit is set, it is intended for debug purposes only.cfir_gain 0 = 2e
–19
, 1 = 2e
–18
The CFIR filter’s 18-bit coefficients are loaded in two 32-word memories.
Note: CFIR filter coefficients are shared between A and B channels of a DDC block in CDMA mode.
The receive programmable FIR filter (PFIR) provides final pulse shaping of the baseband signal data. Itdoes not perform any decimation. Filter coefficient size, input, and output data size is 18 bits. A specialstrapped mode can be employed for UMTS where two adjacent DDCs (2k and 2k + 1, k = 0 to 3) can becombined to yield a filter with twice the number of coefficients. This means the AFE8405 can support 4UMTS DDC channels with double-length filter coefficients (up to 128 taps).
The filter is organized in four partial filter blocks, each containing a data RAM, a coefficient RAM and adual multiplier, a common state machine and output accumulator.
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B0125-01
reg
Read
Pointer
Write
Pointer
ReadPointer
MPUControl
Interface
ComplexInput
SamplesFromcfir
(or AdjacentDDCif
double_tap="01")
COEF
RAM
16x18
DATA
RAM
32x36
Complex
Output
Samples
Output
Sample
Valid
crastarttap StateMachine
WritePointer
MUX
mpu
ram_read
ReadData
WriteData
From AdjacentDDC
(ifdouble_tap="10")
To AdjacentDDC
(ifdouble_tap="10")
FilterCell1 Cell2 Cell3 Cell4
AFE8405
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Figure 7-25. DDC PFIR Block Diagram
The PFIR length is programmable. This permits turning off taps and saving power if short filters areappropriate. The filter’s output data can be shifted over a range of 0 to 7 bits where it is then rounded andhard-limited to 18 bits. The shift range results in a gain that ranges from 2e
–19
to 2e
–12
.
The gain of the PFIR block is: sum(coefficients) ×2
–shift
, where shift ranges from 12 to 19.
The maximum PFIR filter length is a function of AFE8405 clock rate and output sample rate and is limitedby the number of coefficient memory registers. The maximum number of taps is 64 and the minimumnumber is 32 (for both CDMA and UMTS). Lengths between these limits can be specified in increments of4. For strapped UMTS with double length filters, the range of taps available is 64 to 128 in incrementsof 8.
Subject to the above minimum and maximum values, the number of maximum taps available is:UMTS mode: 4 ×(rxclk ÷output + sample rate)Strapped UMTS mode: 8 ×(rxclk ÷output + sample rate)CDMA mode: 2 ×(rxclk ÷output + sample rate)
PFIR coefficients and gain shift values are shared between both A and B CDMA channels in a DDC block.
Example PFIR filter lengths available based on mode and rxclk frequency:
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Mode rxclk CIC PFIR PFIR COMMENTS(MHz) DECIMATIO MAX LENGTH MIN LENGTHN
UMTS 153.6 10 64 32 UMTS, 1 to 6 DDC channelsUMTS 122.88 8 64 32 UMTS, 1 to 6 DDC channelsUMTS 153.6 10 128 64 Strapped UMTS double length PFIR configuration; 1, 2, or 3 DDCchannels.UMTS 122.88 8 128 64 Strapped UMTS double length PFIR configuration; 1, 2, or 3 DDCchannelsCDMA 157.2864 32 64 32 CDMA2000CDMA 122.88 25 64 32 CDMA2000CDMA 78.6432 16 64 32 CDMA2000 low power configurationCDMA 153.6 30 64 32 TD-SCDMACDMA 81.92 16 64 32 TD-SCDMACDMA 76.8 15 60 32 TD-SCDMA low power configuration
Coefficients are organized in four groups of 16 words, each 18 bits wide. For fully utilized filters, the 64coefficients are loaded 0 through 31 into the first and second RAMs, and 32 through 63 into the third andfourth RAMs. The 16-bit MSBs and 2-bit LSBs are written into the RAMs using different page registervalues. Shorter filters require the coefficients be loaded into the four RAMs equally, starting from address0 and address 16.
For example, a CFIR coefficient set for a symmetric 60-tap TD-SCDMA PFIR is:
Taps Coefficient Taps Coefficient
0 = 59 –2 15 = 44 4201 = 58 1 16 = 43 –3312 = 57 4 17 = 42 –3193 = 56 –8 18 = 41 7444 = 55 –2 19 = 40 –4405 = 54 21 20 = 39 –1,0056 = 53 –13 21 = 38 2,3897 = 52 –28 22 = 37 5148 = 51 46 23 = 36 –6,1829 = 50 1 24 = 35 1,84510 = 49 –85 25 = 34 12,95911 = 48 96 26 = 33 –8,69112 = 47 82 27 = 32 –27,24613 = 46 –266 28 = 31 34,16614 = 45 38 29 = 30 131,071
The first 15 coefficients are loaded into addresses 0 through 14 in the first coefficient RAM, the secondgroup of 15 are loaded into addresses 16 through 30 corresponding to the second coefficient RAM, thethird group of 15 are loaded into the third coefficient ram at addresses 0 through 14, and the fourth groupof 15 are loaded into addresses 16 through 30 in the fourth coefficient RAM. Loading the 18-bitcoefficients requires two writes per coefficient, one for the upper 16 bits and another for the lower 2 bits.
To program this coefficient set for the DDC2 PFIR, the following control microprocessor interfacesequence would be used.
A
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Step Address Data Descriptiona[5:0] d[15:0]
1 0x21 0x0400 Page register for DDC2 CFIR Coefficient RAMs 0–15 and 16–31, LSBs.2 0x00 0x0002 Lower 2 bits of coefficient 03 0x01 0x0001 Lower 2 bits of coefficient 14 0x02 0x0000 Lower 2 bits of coefficient 25 0x03 0x0000 Lower 2 bits of coefficient 36 0x04 0x0002 Lower 2 bits of coefficient 47 0x05 0x0001 Lower 2 bits of coefficient 58 0x06 0x0003 Lower 2 bits of coefficient 69 0x07 0x0000 Lower 2 bits of coefficient 710 0x08 0x0002 Lower 2 bits of coefficient 811 0x09 0x0001 Lower 2 bits of coefficient 912 0x0A 0x0003 Lower 2 bits of coefficient 1013 0x0B 0x0000 Lower 2 bits of coefficient 1114 0x0C 0x0002 Lower 2 bits of coefficient 1215 0x0D 0x0002 Lower 2 bits of coefficient 1316 0x0E 0x0002 Lower 2 bits of coefficient 1417 0x0F 0x0000 Lower 2 bits of unused coefficient RAM location18 0x10 0x0000 Lower 2 bits of coefficient 1519 0x11 0x0001 Lower 2 bits of coefficient 1620 0x12 0x0001 Lower 2 bits of coefficient 1721 0x13 0x0000 Lower 2 bits of coefficient 1822 0x14 0x0000 Lower 2 bits of coefficient 1923 0x15 0x0003 Lower 2 bits of coefficient 2024 0x16 0x0001 Lower 2 bits of coefficient 2125 0x17 0x0002 Lower 2 bits of coefficient 2226 0x18 0x0002 Lower 2 bits of coefficient 2327 0x19 0x0001 Lower 2 bits of coefficient 2428 0x1A 0x0003 Lower 2 bits of coefficient 2529 0x1B 0x0001 Lower 2 bits of coefficient 2630 0x1C 0x0002 Lower 2 bits of coefficient 2731 0x1D 0x0002 Lower 2 bits of coefficient 2832 0x1E 0x0003 Lower 2 bits of coefficient 2933 0x1F 0x0000 Lower 2 bits of unused coefficient RAM location34 0x21 0x0420 Page register for DDC2 CFIR Coefficient RAMs 32–47 and 48–63, LSBs.35 0x00 0x0003 Lower 2 bits of coefficient 3036 0x01 0x0002 Lower 2 bits of coefficient 3137 0x02 0x0002 Lower 2 bits of coefficient 3238 0x03 0x0001 Lower 2 bits of coefficient 3339 0x04 0x0003 Lower 2 bits of coefficient 3440 0x05 0x0001 Lower 2 bits of coefficient 3541 0x06 0x0002 Lower 2 bits of coefficient 3642 0x07 0x0002 Lower 2 bits of coefficient 3743 0x08 0x0001 Lower 2 bits of coefficient 3844 0x09 0x0003 Lower 2 bits of coefficient 3945 0x0A 0x0000 Lower 2 bits of coefficient 4046 0x0B 0x0000 Lower 2 bits of coefficient 4147 0x0C 0x0001 Lower 2 bits of coefficient 4248 0x0D 0x0001 Lower 2 bits of coefficient 43
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Step Address Data Descriptiona[5:0] d[15:0]
49 0x0E 0x0000 Lower 2 bits of coefficient 4450 0x0F 0x0000 Lower 2 bits of unused coefficient RAM location51 0x10 0x0002 Lower 2 bits of coefficient 4552 0x11 0x0002 Lower 2 bits of coefficient 4653 0x12 0x0002 Lower 2 bits of coefficient 4754 0x13 0x0000 Lower 2 bits of coefficient 4855 0x14 0x0003 Lower 2 bits of coefficient 4956 0x15 0x0001 Lower 2 bits of coefficient 5057 0x16 0x0002 Lower 2 bits of coefficient 5158 0x17 0x0000 Lower 2 bits of coefficient 5259 0x18 0x0003 Lower 2 bits of coefficient 5360 0x19 0x0001 Lower 2 bits of coefficient 5461 0x1A 0x0002 Lower 2 bits of coefficient 5562 0x1B 0x0000 Lower 2 bits of coefficient 5663 0x1C 0x0000 Lower 2 bits of coefficient 5764 0x1D 0x0001 Lower 2 bits of coefficient 5865 0x1E 0x0002 Lower 2 bits of coefficient 5966 0x1F 0x0000 Lower 2 bits of unused coefficient RAM location67 0x21 0x0440 Page register for DDC2 PFIR Coefficient RAMs 0–15 and 16–31, MSBs.68 0x00 0xFFFF Upper 16 bits of coefficient 069 0x01 0x0000 Upper 16 bits of coefficient 170 0x02 0x0001 Upper 16 bits of coefficient 271 0x03 0xFFFE Upper 16 bits of coefficient 372 0x04 0xFFFF Upper 16 bits of coefficient 473 0x05 0x0005 Upper 16 bits of coefficient 574 0x06 0xFFFC Upper 16 bits of coefficient 675 0x07 0xFFF9 Upper 16 bits of coefficient 776 0x08 0x000B Upper 16 bits of coefficient 877 0x09 0x0000 Upper 16 bits of coefficient 978 0x0A 0xFFEA Upper 16 bits of coefficient 1079 0x0B 0x0018 Upper 16 bits of coefficient 1180 0x0C 0x0014 Upper 16 bits of coefficient 1281 0x0D 0xFFBD Upper 16 bits of coefficient 1382 0x0E 0x0009 Upper 16 bits of coefficient 1483 0x0F 0x0000 Upper 16 bits of unused coefficient RAM location84 0x10 0x0069 Upper 16 bits of coefficient 1585 0x11 0xFFAD Upper 16 bits of coefficient 1686 0x12 0x0FFB0 Upper 16 bits of coefficient 1787 0x13 0x0B0A Upper 16 bits of coefficient 1888 0x14 0xFF92 Upper 16 bits of coefficient 1989 0x15 0xFF04 Upper 16 bits of coefficient 2090 0x16 0x0255 Upper 16 bits of coefficient 2191 0x17 0x0080 Upper 16 bits of coefficient 2292 0x18 0xF9F6 Upper 16 bits of coefficient 2393 0x19 0x01CD Upper 16 bits of coefficient 2494 0x1A 0x0CA7 Upper 16 bits of coefficient 2595 0x1B 0xF783 Upper 16 bits of coefficient 2696 0x1C 0xE564 Upper 16 bits of coefficient 27
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Step Address Data Descriptiona[5:0] d[15:0]
97 0x1D 0x215D Upper 16 bits of coefficient 2898 0x1E 0x7FFF Upper 16 bits of coefficient 2999 0x1F 0x0000 Upper 16 bits of unused coefficient RAM location100 0x21 0x0460 Page register for DDC2 PFIR Coefficient RAMS 32–47 and 48–63, MSBs.101 0x00 0x7FFF Upper 16 bits of coefficient 30102 0x01 0x215D Upper 16 bits of coefficient 31103 0x02 0xE564 Upper 16 bits of coefficient 32104 0x03 0xF783 Upper 16 bits of coefficient 33105 0x04 0x0CA7 Upper 16 bits of coefficient 34106 0x05 0x01CD Upper 16 bits of coefficient 35107 0x06 0xF9F6 Upper 16 bits of coefficient 36108 0x07 0x0080 Upper 16 bits of coefficient 37109 0x08 0x0255 Upper 16 bits of coefficient 38110 0x09 0xFF04 Upper 16 bits of coefficient 39111 0x0A 0xFF92 Upper 16 bits of coefficient 40112 0x0B 0x00BA Upper 16 bits of coefficient 41113 0x0C 0xFFB0 Upper 16 bits of coefficient 42114 0x0D 0xFFAD Upper 16 bits of coefficient 43115 0x0E 0x0069 Upper 16 bits of coefficient 44116 0x0F 0x008D Upper 16 bits of unused coefficient RAM location117 0x10 0x0009 Upper 16 bits of coefficient 45118 0x11 0xFFBD Upper 16 bits of coefficient 46119 0x12 0x0014 Upper 16 bits of coefficient 47120 0x13 0x0018 Upper 16 bits of coefficient 48121 0x14 0xFFEA Upper 16 bits of coefficient 49122 0x15 0x0000 Upper 16 bits of coefficient 50123 0x16 0x000B Upper 16 bits of coefficient 51124 0x17 0xFFF9 Upper 16 bits of coefficient 52125 0x18 0xFFFC Upper 16 bits of coefficient 53126 0x19 0x0005 Upper 16 bits of coefficient 54127 0x1A 0xFFFF Upper 16 bits of coefficient 55128 0x1B 0xFFFE Upper 16 bits of coefficient 56129 0x1C 0x0001 Upper 16 bits of coefficient 57130 0x1D 0x0000 Upper 16 bits of coefficient 58131 0x1E 0xFFFF Upper 16 bits of coefficient 59132 0x1F 0x0000 Upper 16 bits of unused coefficient RAM location133 0x21 0x0500 Page register for DDC2 control registers 0–31134 0x00 0x8EE0 DDC2 FIR_MODE register; cdma_mode enabled, 60-tap PFIR, 58-tap CFIR135 0x01 0x2000 DDC2 PFIR gain = sum(taps) ×2
–18
and CFIR gain = sum(taps) ×2
–19
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7.2.9 DDC RMS Power Meter
B0108-02
18-Bit
Integration
Counter
Clear
55-Bit
Integrator
55-Bit
Register
8-Bit
SyncDelay
Counter
18-Bit
Interval
Counter
Transfer
Sync
Delay
(in8Sample
Increments)
Integration
(in8Sample
Increments)
1688
RMSPower
Interrupt
I
Q
37
36
18
Interval
(in8Sample
Increments)
18
36
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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PROGRAMMING
VARIABLE DESCRIPTION
crastarttap_pfir(4:0) Number of DDC PFIR filter taps is 4 ×(crastartap + 1)For double length PFIR the number of taps is 8 ×(crastartap + 1)cdma_mode When set, puts the CFIR & PFIR blocks in CDMA mode.mpu_ram_read What set, the PFIR and CFIR coefficient rams are readable via the MPU control interface.The AFE8405 signal path is not operational when this bit is set, it is intended for debug purposes only.pfir_gain(2:0) Sets the gain of the PFIR filter.The range is from 2e
–19
to 2e
–12
; 000 = 2e
–19
and 111 = 2e
–12
double_tap(1:0) When set, puts two adjacent DDC (2k and 2k + 1, k = 0 to 2) in double length (from 64- to 128-tap)UMTS mode.Set to 00 for normal mode.In double-tap mode, data out of the last PFIR RAM in the main DDC (DDC0, DDC2, DDC4, or DDC6) issent to the adjacent secondary DDC (DDC1, DDC3, DDC5, or DDC7) PFIR as input, thus forming a128-tap delay line. Data received from the adjacent PFIR summers is added into the main DDC’s PFIRsum to form the final output.When using double-tap mode, set double_tap to 10 for the main DDC, and to 01 for the secondaryDDC.
When in double-tap mode, the first half of the coefficients should be loaded into the main DDC (DDC0,DDC2, DDC4, or DDC6), the remaining coefficients are loaded into the secondary DDC (DDC1, DDC3,DDC5, or DDC7).In double-tap mode, the main DDC must be turned on (ddc_ena = 1), and the secondary DDC must beturned off (ddc_ena = 0).The PFIR filter’s 18-bit coefficients are loaded in four 16-word memories.
Note: PFIR filter coefficients are shared between A and B channels of a DDC block when in CDMA mode.
Figure 7-26. DDC RMS Power Meter Block Diagram
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T0116-01
Sync
Delay
Sync
Event
Integration Time Integration Time Integration Time
Interval Time
Interrupt Interrupt Interrupt
Interval Time
Integration
Start
Integration
Start
Integration
Start
AFE8405
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Figure 7-27. DDC RMS Power Meter Timing
Each DDC channel includes an RMS power meter which is used to measure the total power within thechannel pass band.
The power meter samples the I and Q data stream after the PFIR filter. Both 18-bit I and Q data aresquared, summed, and then integrated over a period determined by a programmable counter. Theintegration time is a 16-bit word which is programmed into the 18-bit counter.
There is a programmable 18-bit interval timer which sets the interval over which power measurements aremade. The timer counts in increments of 1024 samples. This allows the user to select intervals from 1 ×1024 samples up to 256 ×1024 samples. For UMTS systems with sample rate rate at 7.68 MHz, thepower meter interval range is from 133 µs to 34.1 ms. For a CDMA system with the sample rate at 2.4576MHz, the power meter interval range is 417 µs to 107 ms.
The power measurement process starts with a sync event. The integration starts at sync event + 3 chips +sync_delay. The 8-bit delay register permits delays from 1 to 256 samples after sync. The integrationcontinues until the integration count is met. At that point, the result in the 55-bit accumulator is transferredto the read holding register and an interrupt is generated indicating the power value is ready to read. Theinterval counter continues until the programmed interval count is reached. When reached, the integrationcounter and the interval counter start over again. Each time the integration count is reached, the 55 resultbits are again transferred to the read register, overwriting the previous value, and an interrupt is generatedsignifying the data is ready to be read. Failure to read the data in time results in overwriting the previousinterval measurement.
Sync starts the process. Whenever a sync is received, all the counters are reset to zero no matter whatthe status.
For UMTS, I and Q are calculated and the integrated power is read. When in CDMA mode, the power iscalculated for both the A (signal) path and the B (diversity) signal. As a result, there are two 55-bit wordsrepresenting the signal and diversity when in CDMA mode.
The power read is:power = [(I
2
+ Q
2
)×(N ×4 + 1)], where N is the integration count.
A
PROGRAMMING
VARIABLE DESCRIPTION
pmeter_result_a(54:0) 55-bit UMTS or CDMA mode-A channel-power measurement resultpmeter_result_b(54:0) 55-bit CDMA mode-B channel-power measurement resultpmeter_sqr_sum_ddc(15:0) Integration (square and sum) count in increments of four samples.pmeter_sync_delay_ddc(7:0) Sync delay count in samples.pmeter_interval_ddc(7:0) The measurement interval in increments of 2048 samples. This value must be greater than SQR_SUM.ssel_pmeter(2:0) Sync source selection.
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7.2.10 DDC AGC
B0126-01
Limit
and
Round
18
24
12Integer
and
12Fractional
I,Q I,QOutputs(Upto25Bitsin AGCBypassMode)
18
Magnitude Compare
threshold
8
zeromask
4
Under/Over
Detect
ucnt
8
ocnt
4
8 2
ShiftSelect
dsat
4
2
dzro
4
dabv
4
dblw
4
24
Gain
Shift
29
Accumulate
29
Limit
24
Freeze
(FromRegisterBit)
Freeze
(FromSyncSource)
amin
16
amax
16
Gain Adjust
MinLimit
MaxLimit
clear 5
S=+/-1,D=4-BitShift
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
PROGRAMMING
VARIABLE DESCRIPTION
pmeter_sync_disable Turns off the sync to the channel power meter. This can be used to individually turn off syncs to achannel power meter while still having syncs to other power meters on the chip.
Figure 7-28. DDC AGC Block Diagram
The AFE8405 automatic gain control circuit is shown in Figure 7-28 . The basic operation of the circuit is tomultiply the 18-bit input data from the PFIR by a 24-bit gain word that represents a gain or attenuation inthe range of 0 to 4096. The gain format is mixed integer and fraction. The 12-bit integer allows the gain tobe boosted by up to factor of 4096 (72 dB). The 12-bit fractional part allows the gain to be adjusted up ordown in steps of one part in 4096, or approximately 0.002 dB. If the integer portion is zero, then the circuitattenuates the signal. The gain-adjusted output data is saturated to full scale and then rounded tobetween 4 and 18 bits in steps of one bit.
The AGC portion of the circuit is used to adjust the gain automatically so that the median magnitude of theoutput data matches a target value, which is performed by comparing the magnitude of the output datawith a target threshold. If the magnitude is greater than the threshold, then the gain is decreased,otherwise it is increased. The gain is adjusted as: G(t) = G + A(t), where G is the default user-suppliedgain value and A(t) is the time-varying adjustment. A(t) is updated as A(t) = A(t) + G(t) ×S×2
–D
, where S= 1 if the magnitude is less than the threshold and is –1 if the magnitude exceeds the threshold, andwhere D sets the adjustment step size. Note that the adjustment is a fraction of the current gain. This isdesigned to set the AGC noise level to a known and acceptable level while keeping the AGC convergenceand tracking rate constant, independent of the gain level. The AGC noise is equal to 2
–D
, and the AGCattack and decay rate is exponential, with a time constant equal to 2
–D
. Hence, the AGC increases ordecreases by 0.63 times G(t) in 2
D
updates.
If one assumes the data is random with a Gaussian distribution, which is valid for UMTS if more than 12users with different codes have been overlaid, then the relationship between the RMS level and themedian is MEDIAN = 0.6745 ×RMS, hence the threshold should be set to 0.6745 times the desired RMSlevel.
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Samples
0
1
2
3
4
5
6
7
Gain Error − dB
1 1M100 1k
D = 3
G027
10 10k 100k
D = 18
D=3
D=4
D=5
D=6
D=7
D=8
D=9
D=10
D=11
D=12
D=13
D=14
D=15
D=16
D=17
D=18
AFE8405
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The gain step size can be set using four different values of D, each of which is a 4-bit integer. D can rangefrom 3 to 18. The user can specify values of D for different situations, i.e., when the signal magnitude isbelow the user-specified threshold (Dblw), is above the threshold (Dabv), is consistently equal to zero(Dzro) or is consistently equal to maximum (Dsat). It is important to note that D represents a gain stepsize. Smaller values of D represent larger gain steps. The definition of equal to zero is any number whenmasked by zero_mask is considered to be zero. This permits consistently very small amplitude signals tohave their gain increased rapidly.
Separate programmable D values allow the user to set different attack and decay time constants, and toset shorter time constants for when the signal falls too low (equal to zero), or is too high (saturates). Themagnitude is considered to be consistently equal to zero by using a 4-bit counter that counts up everytime the 8-bit magnitude value is zero, and counts down otherwise. If the counter value exceeds auser-specified threshold, then Dabv is used. Similarly the magnitude is considered too high by using acounter that counts up when the magnitude is maximum, and counts down otherwise. If this counterexceeds another user specified threshold, then Dsat is used.
As an example, if the AGC’s current gain at a particular moment in time is 5.123, and the magnitude of thesignal is greater than zero, but less than the user-programmed threshold. Step size Dblw is used to modifythe gain for the next sample. This represents the AGC attack profile. If Dblw is set to a value of 5, then thegain for the next sample is 5.123 + 5.123 ×2
–5
= 5.123 + 0.160 = 5.283. If the signal magnitude is still lessthan the user-programmed threshold, then the gain for the next sample is 5.283 + 5.283 ×2
–5
= 5.283 +0.165 = 5.448. This continues until the signal magnitude exceeds the user-programmed threshold. Whenthe magnitude exceeds threshold (but is not saturated), then step size Dabv is automatically employed asa size rather than Dblw.
The AGC converges linearly in dB with a step size of 40 log(1 + 2
–D
) when the error is greater than 12 dB(i.e., the gain is off by 12 dB or more). Within 6 dB, the behavior is approximately an exponential decaywith a time constant of 2
(D – 0.5)
samples.
The suggested value of D is 5 or 6 when the error is greater than 12 dB (i.e., in the fast range detected byconsistently zero or saturated data). This gives a step size of 0.5 or 0.25 dB per sample.
The suggested value when the gain is off by less than 12 dB is D = 10, giving an exponential timeconstant for delay of around 724 samples (63% decay every 724 samples).
Figure 7-29. AGC Gain Error Over Time vs. D
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The AGC noise once the AGC has converged is a random error of amplitude 2
–D
relative to the RMSsignal level. This means that the error level is –6 ×D dB below the signal RMS level. At D = 10 (–60 dB)the error is negligible. The plot of Figure 7-29 shows the AGC response for vales of D ranging from 3 to18. Error dB represents the distance the signal level is from the desired target threshold.
The AGC is also subject to user-specified upper and lower adjustment limits. The AGC stops incrementingthe gain if the adjustment exceeds Amax. It stops decrementing the gain if the adjustment is less thanAmin.
The input data is received with a valid flag that is high when a valid sample is received. For complex data,the I and Q samples are on the same data input line and are not treated independently. An adjustment ismade for the magnitude of the I sample, and then another adjustment is made for the Q sample.
The AGC operates on UMTS and CDMA data. When in UMTS mode, the I and Q data are each used toproduce the AGC level. There is no separate I path gain and Q path gain. When in CDMA mode there areseparate gain levels for the signal and diversity I and Q data. The I and Q for A (or the signal) pair iscalculated and then the I' and Q' for the B (or diversity) pair is calculated.
There is a freeze mode for holding the accumulator at its current level. This puts the AGC in a hold modeusing the user-programmed gain along with the current gain_adjust value. To use only theuser-programmed gain value as the gain, set the freeze bit and then clear the accumulator. When usingthe freeze bit, the full 25-bit output is sent out of the AGC block to support transferring up to 25 bits whenthe AGC is disabled.
For TDD applications, freeze mode can be controlled using a sync source. This allows rxsync_a/b/c/d tobe assigned as an AGC hold signal to keep the AGC from responding during the transmit interval and runduring the receive interval. The freeze register bit is logically ORed with the freeze sync source.
The current AGC gain and state can also be optionally output with the DDCs I and Q output data bysetting the gain_mon variable. When in this mode, the top 14 bits of the current AGC gain word areappended to the 8-bit AGC-modified I and Q output data.
A
Output Bits(17:10) Bits(9:4) Bits(3:2) Bits(1:0)
I I output data Gain(23:16) 00Q Q output data Gain(15:10) AGC State(1:0) 00
PROGRAMMING
VARIABLE DESCRIPTION
agc_dblw(3:0) Below threshold gain. Sets the value of gain step size Dblw (data x current gain below threshold). Ranges from3 to 18, and maps to a 4-bit field. For example: 3 = 0000, 4 = 0001, …18 = 1111agc_dabv(3:0) Above threshold gain. Sets the value of gain step size Dabv (data x current gain above threshold). Rangesfrom 3 to 18, and maps to a 4-bit field. For example: 3 = 0000, 4 = 0001, …18 = 1111agc_dzro(3:0) Zero signal gain. Sets the value of gain step size Dzro (data x current gain consistently zero). Ranges from 3 to18, and maps to a 4-bit field. For example: 3 = 0000, 4 = 0001, …18 = 1111agc_dsat(3:0) Saturated signal gain. Sets the value of gain step size Dsat (data x current gain consistently saturated).Ranges from 3 to 18, and maps to a 4-bit field. For example: 3 = 0000, 4 = 0001, …18 = 1111agc_zero_msk(3:0) Masks the lower 4 bits of signal data so as to be considered zeros.agc_md(3:0) AGC rounding. 0000 = 18 bits out, 1111 = 3 bits out.agc_thresh(7:0) AGC threshold. Compared with magnitude of 8 bits of input ×gain.agc_rnd_disable AGC rounding is disabled when this bit is set.agc_freeze The AGC gain adjustment updates are disabled when set.agc_clear The AGC gain adjustment accumulator is cleared when set.agc_gaina(23:0) 24-bit gain word for DDC Aagc_gainb(23:0) 24-bit gain word for DDC B (in CDMA mode)agc_zero_cnt(3:0) When the AGC output (input ×gain) is zero-value this number of times, the shift value is changed toagc_dzero.
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7.2.11 DDC Output Interface
7.2.11.1 Serial Output Interface
B0127-01
rx_sync_out_X
rxout_X_a
rxout_X_b
rxout_X_c
rxout_X_d
SerialOutputs
Ich A
IchB
Qch A
QchB
Imsb
Imsb-1
Qmsb
Qmsb-1
CDMA UMTS DoubleLength
PFIRUMTS
sync
clkdiv
Frame
Strobe
Delay
DDCBlock
1UMTSModeChannelor
2CDMA ModeChannels
4
2
FourOutputsFrom
AdjacentDDCBlock
Imsb
Qmsb
Imsb-1
Qmsb-1
Imsb-2
Qmsb-2
Imsb-3
Qmsb-3
AFE8405
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PROGRAMMING
VARIABLE DESCRIPTION
agc_max_cnt(3:0) When the AGC output (input ×gain) is zero-value this number of times, the shift value is changed to agc_dsat.agc_amax(15:0) The maximum value that gain can be adjusted up to. Top 12 bits are integer, bottom 4 bits are fractional.agc_amin(15:0) The minimum value that gain can be adjusted down to. Top 12 bits are integer, bottom 4 bits are fractional.gain_mon When set, combines current AGC gain with I and Q data. The 18-bit output format thus becomes:I portion: 8 bits of AGC’d I data - Gain(23:16) - 00Q portion: 8 bits of AGC’d Q data - Gain(15:10) - Status(1:0) - 00.
Note: Bit 0 of Status, when set, indicates the data is saturated. Bit 1 of Status, when set, indicates the data iszero.ssel_agc_freeze(2:0) Sync selection for freeze mode, 1 of 8 sources. This source is ORed with the freeze register bit.ssel_gain(2:0) Sync selection for the double buffered agc_gaina and agc_gainb register.ssel_ddc_agc(2:0) Sync selection used to initialize the AGC, primarily for test purposes.
The baseband I/Q sample interface can be configured as serial or parallel formatted data. The serialinterface closely matches the GC5316-style interface. The parallel interface is provided to interface directlyto the TMS320TCI110 when delayed antenna streams used to implement channel estimation bufferingand/or transport format combination indicator (TFCI) buffering are not required.
The DDC output data is 2s-complement format.
Figure 7-30. Serial Output Block Diagram and Output Pins for Each DDC Filter Mode
Each DDC block can be assigned four serial output data pins. These pins are used to transferdownconverted I/Q baseband data out of the AFE8405 for subsequent processing. The usage of thesepins changes depending on how the DDC block is configured.
When the block is configured for two CDMA channels, a pair of serial data pins provides separate I and Qdata output for the two DDC channels. Word size is selectable from 4 to 25 bits with the most-significantbit first.
When the DDC block is configured for a single UMTS channel, even and odd I and Q data drive the fourserial pins separately, most-significant bit first.
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T0117-01
rxclk
rxsync_out_X
MSB
rxsync_X
ProgrammedBit Time
(2rxclkCyclesfor ThisExample)
tsetup thold tpd
rxout_X_Y
rxsync_XCanbeaPulseorLevel-InterfaceWillGeneratePeriodicFrameStrobesUsingProgrammedFrameSyncInterval
3rxclk+1ProgrammedBit Time
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Four serial pins each for I and Q data can be optionally employed (instead of two for I and two for Q) athalf the output rate. This would most likely be used when two DDC channels (2k and 2k + 1, k = 0 to 5)are combined to support double-length PFIR filtering (a channel is sacrificed). Formatting for I data is then:Imsb, Imsb-1, Imsb-2, Imsb-3. Q data formatting is: Qmsb, Qmsb-1, Qmsb-2, Qmsb-3.
The frame strobe signal provided on the rx_sync_out_X pins can be programmed to arrive from 0 to 3 bitclocks early via a 2-bit control parameter. The frame interval can be programmed from 1 to 63 bits. Aprogrammable 4-bit clock divider circuit is used to specify the serial bit rate. The clock divider circuit issynchronized using a sync block discussed later in this document.
Programming the serial port clock divider requires some thought and depends upon the channel's overalldecimation ratio, frame sync interval, number of output bits, and CDMA-UMTS mode.
In general:
the serial clock divide ratio נthe frame sync interval = the total receive decimation
The relationship between the number of serial bits output, clock divide ratio, and overall decimation ratiois:
CDMA: [overall decimation נ(pser_recv_8pin + 1) ] / (pser_recv_clkdiv + 1) ≥pser_recv_bits + 1UMTS: 2 נ[overall decimation נ(pser_recv_8pin + 1) ] / (pser_recv_clkdiv + 1) ≥pser_recv_bits + 1where overall decimation = CIC DECIMATION ×CFIR DECIMATION.
Decimation by 2 in the output interface can be achieved by setting the frame strobe interval and clockdivider to 1/2 the PFIR output rate. The serial interface samples the PFIR output each time the transferinterval defined by these two settings has completed. The decimation moment can be controlled using therxsync_X input signal selected as the sync source for the serial interface.
The timing diagram in Figure 7-31 shows the DDC serial output timing.
Figure 7-31. Serial Output Interface Timing Diagram
PROGRAMMING
VARIABLE DESCRIPTION
pser_recv_fsinvl(6:0) Frame sync interval in bitspser_recv_bits(4:0) Number of data output bits – 1. e.g., 10001 = 18 bitspser_recv_clkdiv(3:0) Receive serial interface clock divider rate – 1.0 = rcclk, 15 = rxclk/16pser_recv_8pin When set, configures the serial out pins for 4I and 4Q in UMTS mode. When cleared, the mode is 2Iand 2Q. Used in conjunction with pser_recv_alt.pser_recv_alt When set, outputs Q data from adjacent DDC channel.pser_recv_fsdel(1:0) Number of bit clocks the frame sync is output early with respect to serial data.
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7.2.11.2 Parallel Output Interface
B0128-01
DDC0
DDC1
DDC2
DDC3
DDC4
DDC5
rx_sync_out_6
Output
Format
rxclk_out
rxout_7_d
rxout_7_c
rxout_7_b
rxout_4_b
rxout_4_a
rxout_3_d
rxout_3_c
rxout_3_b
rxout_0_b
rxout_0_a
I(15)
I(14)
I(13)
I(1)
I(0)
Q(15)
Q(14)
Q(13)
Q(1)
Q(0)
rxclk_out
par_sync_out
ParallelI/Q
DDC6
DDC7
T0118-01
rxclk_out
par_sync_out
ParallelI/Q
IQDDC0 IQDDC1 IQDDC2 IQDDC3 IQDDC4 IQDDC5 IQDDC6 IQDDC7
AFE8405
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PROGRAMMING
VARIABLE DESCRIPTION
ssel_serial(2:0) Sync source selection, 1 of 8.3-state(6:3) 3-state controls for the rx_sync_out_X and rxout_X_X pins. Pins are in the high-impedance state whenthe 3-state register bits are set.
Figure 7-32. Parallel Output Interface Block Diagram and Output Pins
When a parallel I/Q interface is required, a 32-bit time-division-multiplexed output mode can be selectedusing the rxout_X_X pins. This interface is provided for direct connection to the TMS320TCI110 receivechip-rate ASSP when delayed antenna streams are not required. The output sample rate, rxclk_out clockpolarity, par_sync_out position and number of channels to be output are all programmable.
Figure 7-33. Parallel Output Interface Timing Diagram
The DDC channel serial interface synchronization source selections should all be programmed to thesame value when using this parallel output interface (each DDC channel ssel_serial(2:0) in the SYNC_0register should be programmed to the same rxsync_A/B/C/D value).
Decimation by 2 in the output interface can be achieved by setting the frame strobe interval and clockdivider to 1/2 the PFIR output rate. The parallel interface samples the PFIR outputs each time the transferinterval defined by these two settings has completed.
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7.2.12 DDC Checksum Generator
B0129-01
Checksum
Generator
ChecksumRead-Only
ResultsUpdatedon
EachSyncEvent
0
101415 1
32
9
InitializedOnSyncEventto “0000000000000010”
rxout_X_d
rxout_X_c
rxout_X_b
rxout_X_a
rxout_X_a
rxout_X_b
rxout_X_c
rxout_X_d
rxclk
sync
Results
register
11
1213
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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PROGRAMMING
VARIABLE DESCRIPTION
par_recv_fsinvl(6:0) rx_sync_out (frame strobe) sync interval. 0 is 1 rxclk cycle and 127 is 128 rxclk cycles.par_recv_clkdiv(6:0) rxclk_out cycles per IQ channel sample; 1 is full rate, 2 is rxclk/2, etc.par_recv_chan(3:0) Number channels to be output. 0 is 1 channel, and 15 is 16 channels.par_recv_sync_del(6:0) Delays the DDC0 pser sync source to establish the timing of IQ DDC0. Increasing the value delays thepar_sync_out location.par_recv_syncout_del(3:0) Delays the rx_sync_out position with respect to IQ DDC0. Setting to 0 moves the rx_sync_out pulse onerxclk_out cycle before the IQ DDC0 word, setting to 1 places it as shown above, lined up with IQ DDC0,etc.par_recv_rxclk_pol rxclk_out polarity. Outputs data on falling edges when cleared, rising edges when set.par_recv_sync_pol Parallel interface par_sync_out polarity. 0 is active-low, 1 for active-highpar_recv_ena Parallel TCI110 style interface enabled when set, serial interface enabled when cleared.ssel_serial(2:0) DDC channel serial interface sync source selection. All DDCs should be programmed to the same syncsource when using this parallel output interface.gain_mon When set, the parallel output data includes 8b I at I(15:8), 8b Q at Q(15:8), 14b AGC gain at I(7:0) andQ(7:2) and 2b AGC state at Q(1:0).3-state(6:3) 3-state controls for the rx_sync_out_X and rxout_X_X pins. Pins are in the high-impedance state whenthe 3-state register bits are set.
The checksum generator is used in conjunction with the input test signal generator to implement a self-testcapability.
Figure 7-34. DDC Checksum Generator Block Diagram
The sync for the checksum generator is internally connected to the ddc_counter output.
A
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PROGRAMMING
VARIABLE DESCRIPTION
ddc_chk_sum(15:0) Read-only DDC channel checksum results
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8 AFE8405 GENERAL CONTROL
8.1 Microprocessor Interface Control Data, Address, and Strobes
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The AFE8405 is configured over a bidirectional 16-bit parallel-data microprocessor control port. Thecontrol port permits access to the control registers which configure the chip. The control registers areorganized using a paged-access scheme using 6 address lines. Half of the 64 addresses (address 32through address 63) represent global registers. The other 32 (address 0 through address 31) are pagedregisters. This arrangement permits accessing a large number of control registers using relatively fewaddress lines.
Global registers (address 32 through address 63) are used to read/write AFE8405 parameters that areglobal in nature and can benefit from single read/write operations. Examples include chip status, reset,sync options, checksum ramp parameters, interrupt sources, interrupt masks, 3-state controls and thepage register.
Global address 33 is the page register. Writing a 16-bit value to this register sets the page to which futurewrite or read operations performed. These paged registers contain the actual parameters that configurethe chip and are accessed by writing/reading address 0 through address 31.
The global 3-state register can be used to place the output drivers on the AFE8405 in the high-impedancestate, and also includes the capability of disabling the internal rxclk of the chip.
A
PROGRAMMING
VARIABLE DESCRIPTION
rxclk_ena Enables the internal rxclk when set. When cleared, the AFE8405 ignores the rxclk input signal and holdthe internal clock low.3-state(10:0) Various output pins are forced into the high-impedance state when these bits are asserted. See theGBL_3STATE register description for pin groups to bit assignments.arst_func When asserted, the internal data path is held reset. The control register programming is not affected.
The microprocessor control bus consists of 16 bidirectional control data lines d[15:0], 6 address linesa[5:0], a read enable line rd_n, a write enable line wr_n, and a chip enable line ce_n. These lines usuallyinterface to a microprocessor or DSP chip and are intended to look like a block of memory.
The interface can be operated in a three-pin control mode (using rd_n, wr_n and ce_n) or two-pin controlmode (using wr_n and ce_n with rd_n always low).
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8.1.1 MPU Timing Diagrams
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Figure 8-1. Read Operation—Three-Pin Control Mode
Figure 8-2. Read Operation—Two-Pin Control Mode (rd_n Tied Low)
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Figure 8-3. Write Operation—Three-Pin Control Mode
Figure 8-4. Write Operation—2-Pin Control Mode (rd_n Tied Low)
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8.2 Synchronization Signals
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Various function blocks within the AFE8405 must be synchronized in order to realize predictable results.The AFE8405 provides a flexible system where each function block that requires synchronization can beindependently synchronized from either device pins or from a software one-shot. The one-shot option issetup and triggered through control registers. The four sync input pins, rxsync_a, rxsync_b, rxsync_c andrxsync_d are qualified on the rxclk rising clock edge. Table 8-1 shows the different sync modes available.
Table 8-1. Different Sync Modes Available
SYNC SELECT CODE RECEIVE SYNC SOURCE
000 rxsync_a001 rxsync_b010 rxsync_c011 rxsync_d100 ddc sync counter terminal count101 ddc sync triggered by software one-shot (register bit)110 0 (always off)111 1 (always on)
Table 8-2 and Table 8-3 summarizes the blocks which have functions that can be synchronized using theeight sync source options listed in Table 8-1 .
Table 8-2. Receive Common Syncs
Sync Name Purpose
sync_ddc_counter Initializes the receive sync countersync_ddc Initializes the receive ADC interface and clock generation circuitssync_rxsync_out Selects sync signal to be output on the rx_sync_out pin.sync_adc_fifo Initializes the input and output pointers in the ADC fifo circuits.sync_tst_decim Initializes the testbus decimation counter.sync_recv_pmeterX Initializes the rxin power meters. {X = 0, 1, 2, or 3}sync_ragc_interval_X Initializes the rxin receive AGC timers. {X = 0, 1, 2, or 3}sync_ragc_freeze_X rxin receive AGC freeze mode control. {X = 0, 1, 2, or 3}sync_ragc_clear_X Initializes the receive AGC error accumulator. {X = 0, 1, 2, or 3}
Table 8-3. DDC Channel Syncs
Sync Name Purpose
sync_ddc_tadj Selects zero stuff moment in the tadj fine-adjustment sectionsync_ddc_tadj_reg Updates the tadj output pointer register delay in the tadj coarse-adjustment sectionsync_ddc_nco Resets the NCO accumulatorsync_ddc_freq Updates the NCO freq registerssync_ddc_phase Updates the NCO phase registersync_ddc_dither Initializes the NCO dither circuitssync_ddc_cic Selects the CIC decimation momentsync_ddc_pmeter Initializes the receive channel power meterssync_ddc_gain Updates the DDC channel AGC gain registerssync_ddc_agc Initializes the AGC accumulatorsync_ddc_agc_freeze AGC freeze mode controlsync_ddc_serial Initializes the receive serial interface
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8.3 Interrupt Handling
8.4 AFE8405 Programming
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A 32-bit general-purpose timer is included in the synchronization function. The timer loads theuser-programmed terminal count on a sync event and counts down to zero using rxclk. The duration of theterminal-count pulse can also be programmed up to rxclk cycles. The timer output can be used as a syncsource for any other circuits requiring a sync if desired, and can also be routed to the rx_sync_out pin.
A
PROGRAMMING
VARIABLE DESCRIPTION
ddc_counter(31:0) 32-bit programmable terminal countddc_counter_width(7:0) 8-bit programmable terminal-count pulse durationssel_ddc_counter(2:0) Sync source selection for the ddc counterssel_rxsync_out(2:0) Sync source selection for the rx_sync_out pin3-state(0) When set, the interrupt and rx_sync_out pins are placed in the high-impedance state.rx_oneshot Register bit used to generate the S/W oneshot signal for sync. This bit must be programmed fromcleared to set in order to generate a rising edge sync signal.
When an AFE8405 block sets an interrupt, the interrupt pin goes active if the interrupt source is notmasked. The microprocessor should then read the interrupt register to determine the source of theinterrupt. The microprocessor then must write the interrupt register to clear the interrupt pin and theinterrupt source. The interrupt register and interrupt mask are located in the global registers section of thecontrol registers.
The AFE8405 has 16 interrupt sources; power meters in each of the eight DDC blocks, power meters inthe four receive input interface, and four rxin_X_ovr (adc overflow) input pins where X = {a, b, c, d}.
A
PROGRAMMING
VARIABLE DESCRIPTION
pmeterX_im(7:0) Channel pmeter interrupt mask bits. Interrupt source is masked when set.recv_pmeterX_im(3:0) Receive input power meter interrupt masks.rxin_X_ovr_im ADC overflow input pin interrupt masks.pmeterX(7:0) Channel pmeter interrupt status.recv_pmeterX(3:0) Receive input power meter interrupt status.rxin_X_ovr ADC overflow input pin interrupt status.intr_clr When asserted, holds all interrupt status bits cleared. The interrupt pin is inactive (always low) when this bit isset. Intended for lab/debug use only3-state(0) When set, the interrupt and rx_sync_out pins are placed in the high-impedance state.
The AFE8405 includes over 2000 internal configuration registers and therefore implements a pagedaddressing scheme. The register map includes a global control variables register address space that isaccessed directly when the a5 signal is high. This global control variables address space includes thepage register. All other registers are addressed using a combination of an address consisting of theinternal page register contents and the 6-bit external address: a5, a4, a3, a2, a1, and a0.
The page register is accessed when the 6-bit address a5:a0 is 0x21 (or 10 0001b).
A
Page Register Address Registers Addressed With 5-Bit Address Space, Pins (a4:a0)Contents in Hex Pin a5
Don’t care 1 Global control variables 0x00 through 0x1F
0x0000 0 DDC0 PFIR taps 0 through 31 coefficient lsbs(1:0)
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SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
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Page Register Address Registers Addressed With 5-Bit Address Space, Pins (a4:a0)Contents in Hex Pin a5
0x0020 0 DDC0 PFIR taps 32 through 63 coefficient lsbs(1:0)0x0040 0 DDC0 PFIR taps 0 through 31 coefficient msbs(17:2)0x0060 0 DDC0 PFIR taps 32 through 63 coefficient msbs(17:2)0x0080 0 DDC0 CFIR taps 0 through 31 coefficient lsbs(1:0)0x00A0 0 DDC0 CFIR taps 32 through 63 coefficient lsbs(1:0)0x00C0 0 DDC0 CFIR taps 0 through 31 coefficient msbs(17:2)0x00E0 0 DDC0 CFIR taps 32 through 63 coefficient msbs(17:2)0x0100 0 DDC0 control registers 0x00 through 0x1F0x0120 0 DDC0 control registers 0x20 through 0x3F
0x0200 0 DDC1 PFIR taps 0 through 31 coefficient lsbs(1:0)0x0220 0 DDC1 PFIR taps 32 through 63 coefficient lsbs(1:0)0x0240 0 DDC1 PFIR taps 0 through 31 coefficient msbs(17:2)0x0260 0 DDC1 PFIR taps 32 through 63 coefficient msbs(17:2)0x0280 0 DDC1 CFIR taps 0 through 31 coefficient lsbs(1:0)0x02A0 0 DDC1 CFIR taps 32 through 63 coefficient lsbs(1:0)0x02C0 0 DDC1 CFIR taps 0 through 31 coefficient msbs(17:2)0x02E0 0 DDC1 CFIR taps 32 through 63 coefficient msbs(17:2)0x0300 0 DDC1 control registers 0x00 through 0x1F0x0320 0 DDC1 control registers 0x20 through 0x3F
0x0400 0 DDC2 PFIR taps 0 through 31 coefficient lsbs(1:0)0x0420 0 DDC2 PFIR taps 32 through 63 coefficient lsbs(1:0)0x0440 0 DDC2 PFIR taps 0 through 31 coefficient msbs(17:2)0x0460 0 DDC2 PFIR taps 32 through 63 coefficient msbs(17:2)0x0480 0 DDC2 CFIR taps 0 through 31 coefficient lsbs(1:0)0x04A0 0 DDC2 CFIR taps 32 through 63 coefficient lsbs(1:0)0x04C0 0 DDC2 CFIR taps 0 through 31 coefficient msbs(17:2)0x04E0 0 DDC2 CFIR taps 32 through 63 coefficient msbs(17:2)0x0500 0 DDC2 control registers 0x00 through 0x1F0x0520 0 DDC2 control registers 0x20 through 0x3F
0x0600 0 DDC3 PFIR taps 0 through 31 coefficient lsbs(1:0)0x0620 0 DDC3 PFIR taps 32 through 63 coefficient lsbs(1:0)0x0640 0 DDC3 PFIR taps 0 through 31 coefficient msbs(17:2)0x0660 0 DDC3 PFIR taps 32 through 63 coefficient msbs(17:2)0x0680 0 DDC3 CFIR taps 0 through 31 coefficient lsbs(1:0)0x06A0 0 DDC3 CFIR taps 32 through 63 coefficient lsbs(1:0)0x06C0 0 DDC3 CFIR taps 0 through 31 coefficient msbs(17:2)0x06E0 0 DDC3 CFIR taps 32 through 63 coefficient msbs(17:2)0x0700 0 DDC3 control registers 0x00 through 0x1F0x0720 0 DDC3 control registers 0x20 through 0x3F
0x0800 0 DDC4 PFIR taps 0 through 31 coefficient lsbs(1:0)0x0820 0 DDC4 PFIR taps 32 through 63 coefficient lsbs(1:0)0x0840 0 DDC4 PFIR taps 0 through 31 coefficient msbs(17:2)0x0860 0 DDC4 PFIR taps 32 through 63 coefficient msbs(17:2)0x0880 0 DDC4 CFIR taps 0 through 31 coefficient lsbs(1:0)0x08A0 0 DDC4 CFIR taps 32 through 63 coefficient lsbs(1:0)0x08C0 0 DDC4 CFIR taps 0 through 31 coefficient msbs(17:2)
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SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
Page Register Address Registers Addressed With 5-Bit Address Space, Pins (a4:a0)Contents in Hex Pin a5
0x08E0 0 DDC4 CFIR taps 32 through 63 coefficient msbs(17:2)0x0900 0 DDC4 control registers 0x00 through 0x1F0x0920 0 DDC4 control registers 0x20 through 0x3F
0x0A00 0 DDC5 PFIR taps 0 through 31 coefficient lsbs(1:0)0x0A20 0 DDC5 PFIR taps 32 through 63 coefficient lsbs(1:0)0x0A40 0 DDC5 PFIR taps 0 through 31 coefficient msbs(17:2)0x0A60 0 DDC5 PFIR taps 32 through 63 coefficient msbs(17:2)0x0A80 0 DDC5 CFIR taps 0 through 31 coefficient lsbs(1:0)0x0AA0 0 DDC5 CFIR taps 32 through 63 coefficient lsbs(1:0)0x0AC0 0 DDC5 CFIR taps 0 through 31 coefficient msbs(17:2)0x0AE0 0 DDC5 CFIR taps 32 through 63 coefficient msbs(17:2)0x0B00 0 DDC5 control registers 0x00 through 0x1F0x0B20 0 DDC5 control registers 0x20 through 0x3F
0x0C00 0 DDC6 PFIR taps 0 through 31 coefficient lsbs(1:0)0x0C20 0 DDC6 PFIR taps 32 through 63 coefficient lsbs(1:0)0x0C40 0 DDC6 PFIR taps 0 through 31 coefficient msbs(17:2)0x0C60 0 DDC6 PFIR taps 32 through 63 coefficient msbs(17:2)0x0C80 0 DDC6 CFIR taps 0 through 31 coefficient lsbs(1:0)0x0CA0 0 DDC6 CFIR taps 32 through 63 coefficient lsbs(1:0)0x0CC0 0 DDC6 CFIR taps 0 through 31 coefficient msbs(17:2)0x0CE0 0 DDC6 CFIR taps 32 through 63 coefficient msbs(17:2)0x0D00 0 DDC6 control registers 0x00 through 0x1F0x0D20 0 DDC6 control registers 0x20 through 0x3F
0x0E00 0 DDC7 PFIR taps 0 through 31 coefficient lsbs(1:0)0x0E20 0 DDC7 PFIR taps 32 through 63 coefficient lsbs(1:0)0x0E40 0 DDC7 PFIR taps 0 through 31 coefficient msbs(17:2)0x0E60 0 DDC7 PFIR taps 32 through 63 coefficient msbs(17:2)0x0E80 0 DDC7 CFIR taps 0 through 31 coefficient lsbs(1:0)0x0EA0 0 DDC7 CFIR taps 32 through 63 coefficient lsbs(1:0)0x0EC0 0 DDC7 CFIR taps 0 through 31 coefficient msbs(17:2)0x0EE0 0 DDC7 CFIR taps 32 through 63 coefficient msbs(17:2)0x0F00 0 DDC7 control registers 0x00 through 0x1F0x0F20 0 DDC7 control registers 0x20 through 0x3F
0x1000 0 Receive input AGC0 error RAM addresses 0 through 310x1020 0 Receive input AGC0 error RAM addresses 32 through 630x1040 0 Receive input AGC0 DVGA RAM addresses 0 through 310x1080 0 Receive input AGC0 gain RAM addresses 0 through 310x10A0 0 Receive input AGC0 gain RAM addresses 32 through 63
0x1100 0 Receive input AGC1 error RAM addresses 0 through 310x1120 0 Receive input AGC1 error RAM addresses 32 through 630x1140 0 Receive input AGC1 DVGA RAM addresses 0 through 310x1180 0 Receive input AGC1 gain RAM addresses 0 through 310x11A0 0 Receive input AGC1 gain RAM addresses 32 through 63
0x1400 0 Receive input AGC2 error RAM addresses 0 through 310x1420 0 Receive input AGC2 error RAM addresses 32 through 630x1440 0 Receive input AGC2 DVGA RAM addresses 0 through 31
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8.4.1 Control Register Index
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
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Page Register Address Registers Addressed With 5-Bit Address Space, Pins (a4:a0)Contents in Hex Pin a5
0x1480 0 Receive input AGC2 gain RAM addresses 0 through 310x14A0 0 Receive input AGC2 gain RAM addresses 32 through 63
0x1500 0 Receive input AGC3 error RAM addresses 0 through 310x1520 0 Receive input AGC3 error RAM addresses 32 through 630x1540 0 Receive input AGC3 DVGA RAM addresses 0 through 310x1580 0 Receive input AGC3 gain RAM addresses 0 through 310x15A0 0 Receive input AGC3 gain RAM addresses 32 through 63
0x1800 0 Receive input control registers 0x00 through 0x1F0x1820 0 Receive input control registers 0x20 through 0x3F
0x1840 0 Receive input AGC control registers 0x00 through 0x1F0x1860 0 Receive input AGC control registers 0x20 through 0x3F
REGISTER NAME SECTION
PMETER_RESULT_A_LSB Section 8.4.5.32Table 8-4. Control Register Index
PMETER_RESULT_A_MID Section 8.4.5.33REGISTER NAME SECTION
PMETER_RESULT_A_MSB Section 8.4.5.34AGC_AMAX Section 8.4.5.23
PMETER_RESULT_B_LSB Section 8.4.5.35AGC_AMIN Section 8.4.5.24
PMETER_RESULT_B_MID Section 8.4.5.36AGC_CONFIG1 Section 8.4.5.17
PMETER_RESULT_B_MSB Section 8.4.5.37AGC_CONFIG2 Section 8.4.5.18
PMETER_RESULT_AB_UMSB Section 8.4.5.38AGC_CONFIG3 Section 8.4.5.19
PSER_CONFIG1 Section 8.4.5.25AGC_GAINA Section 8.4.5.21
PSER_CONFIG2 Section 8.4.5.26AGC_GAINB Section 8.4.5.22
RAGC_CONFIG0 Section 8.4.4.1AGC_GAINMSB Section 8.4.5.20
RAGC_CONFIG1 Section 8.4.4.2CIC_MODE1 Section 8.4.5.5
RAGC_CONFIG2 Section 8.4.4.3CIC_MODE2 Section 8.4.5.6
RAGC_CONFIG3 Section 8.4.4.4CONFIG Section 8.4.2.3
RAGC0_ACCUM_LSB Section 8.4.4.57CONFIG1 Section 8.4.5.15
RAGC0_ACCUM_MSB Section 8.4.4.58CONFIG2 Section 8.4.5.16
RAGC0_CLIP_ERROR Section 8.4.4.17DDC_CHK_SUM Section 8.4.5.31
RAGC0_CLIP_HITHRESH Section 8.4.4.12DDCCONFIG1 Section 8.4.5.27
RAGC0_CLIP_HITIMER Section 8.4.4.14FIR_GAIN Section 8.4.5.2
RAGC0_CLIP_LOTHRESH Section 8.4.4.13FIR_MODE Section 8.4.5.1
RAGC0_CLIP_LOTIMER Section 8.4.4.15GBL_IMASK0 Section 8.4.2.8
RAGC0_CLIP_SAMPLES Section 8.4.4.16GBL_INTERRUPT0 Section 8.4.2.9
RAGC0_CONFIG0 Section 8.4.4.7GBL_ONESHOT Section 8.4.2.7
RAGC0_CONFIG1 Section 8.4.4.8GBL_PAR_CONFIG0 Section 8.4.2.4
RAGC0_INTEGINVL_LSB Section 8.4.4.5GBL_PAR_CONFIG1 Section 8.4.2.5
RAGC0_INTEGINVL_MSB Section 8.4.4.6GBL_3STATE Section 8.4.2.6
RAGC0_SD_SAMPLES Section 8.4.4.11NZ_PWR_MASK Section 8.4.3.7
RAGC0_SD_THRESH Section 8.4.4.9PAGE Section 8.4.2.2
RAGC0_SD_TIMER Section 8.4.4.10PHASE_OFFSETA Section 8.4.5.13
RAGC1_ACCUM_LSB Section 8.4.4.59PHASE_OFFSETB Section 8.4.5.14
RAGC1_ACCUM_MSB Section 8.4.4.60PHASEADD0A Section 8.4.5.9
RAGC1_CLIP_ERROR Section 8.4.4.30PHASEADD0B Section 8.4.5.11
RAGC1_CLIP_HITHRESH Section 8.4.4.25PHASEADD1A Section 8.4.5.10
RAGC1_CLIP_HITIMER Section 8.4.4.27PHASEADD1B Section 8.4.5.12
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REGISTER NAME SECTIONTable 8-4. Control Register Index (continued)
RECV_PMETER0_CONFIG Section 8.4.3.12REGISTER NAME SECTION
RECV_PMETER0_LMSB Section 8.4.3.28RAGC1_CLIP_LOTHRESH Section 8.4.4.26
RECV_PMETER0_LSB Section 8.4.3.26RAGC1_CLIP_LOTIMER Section 8.4.4.28
RECV_PMETER0_MID Section 8.4.3.27RAGC1_CLIP_SAMPLES Section 8.4.4.29
RECV_PMETER0_SQR_SUM_LSB Section 8.4.3.9RAGC1_CONFIG0 Section 8.4.4.20
RECV_PMETER0_STRT_INTVL_LSB Section 8.4.3.10RAGC1_CONFIG1 Section 8.4.4.21
RECV_PMETER0_SYNC_DLY Section 8.4.3.11RAGC1_INTEGINVL_LSB Section 8.4.4.18
RECV_PMETER0_UMSB Section 8.4.3.29RAGC1_INTEGINVL_MSB Section 8.4.4.19
RECV_PMETER1_CONFIG Section 8.4.3.16RAGC1_SD_SAMPLES Section 8.4.4.24
RECV_PMETER1_LMSB Section 8.4.3.32RAGC1_SD_THRESH Section 8.4.4.22
RECV_PMETER1_LSB Section 8.4.3.30RAGC1_SD_TIMER Section 8.4.4.23
RECV_PMETER1_MID Section 8.4.3.31RAGC2_ACCUM_LSB Section 8.4.4.61
RECV_PMETER1_SQR_SUM_LSB Section 8.4.3.13RAGC2_ACCUM_MSB Section 8.4.4.62
RECV_PMETER1_STRT_INTVL_LSB Section 8.4.3.14RAGC2_CLIP_ERROR Section 8.4.4.43
RECV_PMETER1_SYNC_DLY Section 8.4.3.15RAGC2_CLIP_HITHRESH Section 8.4.4.38
RECV_PMETER1_UMSB Section 8.4.3.33RAGC2_CLIP_HITIMER Section 8.4.4.40
RECV_PMETER2_CONFIG Section 8.4.3.20RAGC2_CLIP_LOTHRESH Section 8.4.4.39
RECV_PMETER2_LMSB Section 8.4.3.36RAGC2_CLIP_LOTIMER Section 8.4.4.41
RECV_PMETER2_LSB Section 8.4.3.34RAGC2_CLIP_SAMPLES Section 8.4.4.42
RECV_PMETER2_MID Section 8.4.3.35RAGC2_CONFIG0 Section 8.4.4.33
RECV_PMETER2_SQR_SUM_LSB Section 8.4.3.17RAGC2_CONFIG1 Section 8.4.4.34
RECV_PMETER2_STRT_INTVL_LSB Section 8.4.3.18RAGC2_INTEGINVL_LSB Section 8.4.4.31
RECV_PMETER2_SYNC_DLY Section 8.4.3.19RAGC2_INTEGINVL_MSB Section 8.4.4.32
RECV_PMETER2_UMSB Section 8.4.3.37RAGC2_SD_SAMPLES Section 8.4.4.37
RECV_PMETER3_CONFIG Section 8.4.3.24RAGC2_SD_THRESH Section 8.4.4.35
RECV_PMETER3_LMSB Section 8.4.3.40RAGC2_SD_TIMER Section 8.4.4.36
RECV_PMETER3_LSB Section 8.4.3.38RAGC3_ACCUM_LSB Section 8.4.4.63
RECV_PMETER3_MID Section 8.4.3.39RAGC3_ACCUM_MSB Section 8.4.4.64
RECV_PMETER3_SQR_SUM_LSB Section 8.4.3.21RAGC3_CLIP_ERROR Section 8.4.4.56
RECV_PMETER3_STRT_INTVL_LSB Section 8.4.3.22RAGC3_CLIP_HITHRESH Section 8.4.4.51
RECV_PMETER3_SYNC_DLY Section 8.4.3.23RAGC3_CLIP_HITIMER Section 8.4.4.53
RECV_PMETER3_UMSB Section 8.4.3.41RAGC3_CLIP_LOTHRESH Section 8.4.4.52
RECV_SLF_TST_VALUE Section 8.4.3.25RAGC3_CLIP_LOTIMER Section 8.4.4.54
SQR_SUM Section 8.4.5.3RAGC3_CLIP_SAMPLES Section 8.4.4.55
SSEL_DDC_CNTR Section 8.4.3.3RAGC3_CONFIG0 Section 8.4.4.46
SSEL_RX_0 Section 8.4.3.4RAGC3_CONFIG1 Section 8.4.4.47
STRT_INTRVL Section 8.4.5.4RAGC3_INTEGINVL_LSB Section 8.4.4.44
SYNC_0 Section 8.4.5.28RAGC3_INTEGINVL_MSB Section 8.4.4.45
SYNC_1 Section 8.4.5.29RAGC3_SD_SAMPLES Section 8.4.4.50
SYNC_2 Section 8.4.5.30RAGC3_SD_THRESH Section 8.4.4.48
SYNC_DDC_CNTR_LSB Section 8.4.3.1RAGC3_SD_TIMER Section 8.4.4.49
SYNC_DDC_CNTR_MSB Section 8.4.3.2RECV_CONFIG0 Section 8.4.3.5
TADJC Section 8.4.5.7RECV_CONFIG1 Section 8.4.3.6
TADJF Section 8.4.5.8RECV_PMETER_SYNC Section 8.4.3.8
VER Section 8.4.2.1
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8.4.2 Global Control Variables
8.4.2.1 VER Register
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
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These registers are accessed directly without page address extension; when pin a5 is high during a reador write access, this block of 32 registers is accessed.
Register name: VER Address: 0x00 Read-onlyBIT 15 BIT 8Unused Unused Unused Unused Unused Unused Unused Unused00000000
BIT 7 BIT 0
Unused Unused Unused Unused VER3 VER2 VER1 VER0000000**
VER(3:0): A hardwired read-only register that returns the version of the chip* A valid version code is 0010.
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8.4.2.2 PAGE Register
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SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
Register name: PAGE Address: 0x01BIT 15 BIT 8Unused Unused Unused W(2:0) X Y(2)00000000
BIT 7 BIT 0
Y(1) Y(0) Zp Unused Unused Unused Unused Unused00000000
W(2:0): Selects which dual-DDC block to address.
X: The DDC modules are configured as dual DDCs; an even-numbered DDC andodd-numbered DDC are contained in each dual-DDC module, the X bit selects which DDCgets address. (DDC0/2/4/6=0, DDC1/3/5/7=1)
W(2:0) X bit Selected Block
000 0 DDC0000 1 DDC1001 0 DDC2001 1 DDC3010 0 DDC4010 1 DDC5011 0 DDC6011 1 DDC7100 0 Receive AGC0/1 RAMs101 0 Receive AGC2/3 RAMs110 0 Receive input interface
Y(2:0): Within each major block, there are up to 8 different zones that can be addressed using the Ybits.
Y(2:0) DDC Zone Receive Input Interface Zone Receive AGC RAMs Zone
000 PFIR coeffient lower 2 bits CHIPS control registers RAGC0/2 ERRMAP001 PFIR coeffient upper 16 bits RAGC control registers RAGC0/2 DVGAMAP010 CFIR coeffient lower 2 bits Not assigned RAGC0/2 GAINMAP011 CFIR coeffient upper 16 bits Not assigned Not assigned100 Control registers Not assigned RAGC1/3 ERRMAP101 Not assigned Not assigned RAGC1/3 DVGAMAP110 Not assigned Not assigned RAGC1/3 GAINMAP111 Not assigned Not assigned Not assigned
Zp: The Zp bit is the MSB of the address word sent to the registers and RAMs. This bit can bethought of as an upper/lower selector of the 64-word addressing.
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8.4.2.3 CONFIG Register
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
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Register name: CONFIG Address: 0x02BIT 15 BIT 8slf_ tst_ena rduz_sens_ena arst_ func tst_rate_sel(4:0)0 0 0 0 0 0 0 0
BIT 7 BIT 0
par_recv_ena gbl_ ddc_write intr_ clr tst_select(3:0) tst_ on0 0 0 1 1 1 0 0
slf_tst_ena: Turns on the checksum LFSR for the receivers. They are located in the RECEIVE INPUTINTERFACE and DDC blocks.
rduz_sens_ena: When enabled, adds noise to the LSBs of the ADC inputs.
arst_func: When asserted, resets the functional portion of the circuits. The MPU registers are not resetand retain their programmed value.
tst_rate_sel(4:0): Sets the rate of the output test data and clock. The length of the clock cycle is thevalue in tst_rate_sel+1 multiplied by the RXCLK period. When the test bus source is set to1000 (rxin_a and rxin_b FIFO outputs), tst_rate_sel(4:0) must be set to 0 for output.Otherwise, it does not output a clock at the decimated test-bus rate.
par_recv_ena: When asserted, the rxout_*_* serial pins join to form a 32-bit parallel output using 32 pinsas a data bus, one pin as an output clock, and one pin as a sync. This is used to connect tothe TCI110 Chip rate processor from TI.
gbl_ddc_write: Factory use only. When asserted, the mpu writes are global. This means that DDC0/2/4/6or DDC1/3/5/7 can be programmed simultaneously with the same values. This is an effort toreduce the amount of time spent programming the device. A common setup can be used toprogram DDC0/2/4/6, then DDC1/3/5/7. Afterwards, just individual writes to the registerswhich differ between DDCs can be done. To use this feature, this bit must be asserted andthe DDC0/1 must be addressed. Any other DDC address does not work.
intr_clr: When asserted, this bit forces all interrupts to be cleared. To allow the interrupts to be setagain, this bit must be programmed to zero. This does not stop blocks from generatinginterrupts, but rather just keeps the interrupts from being reported.
tst_select(3:0): This selects which block the test output comes from:
tst_select(3:0) Test Data Sent to Output
0000 DDC 00001 DDC 10010 DDC 20011 DDC 30100 DDC 40101 DDC 50110 DDC 60111 DDC 71000 rxin_a and rxin_b FIFO outputsOthers None selected
tst_on: When asserted, the testbus is active. The ADC input ports rxin_c(15:0), rxin_d(15:0),dvga_c(5:0) and dvga_d(5:0) become the testbus output ports. When this bit is set, therxin_c(15:0) and rxin_d(15:0) ports become chip outputs. The dvga_c(5:0) and dvga_d(5:0)ports are enabled separately using the GBL_3STATE register.
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8.4.2.4 GBL_PAR_CONFIG0 Register
8.4.2.5 GBL_PAR_CONFIG1 Register
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SLWS212A – OCTOBER 2008 – REVISED JANUARY 2009
Register name: GBL_PAR_CONFIG0 Address: 0x03BIT 15 BIT 8par_recv_sync_del(6:0) tst_clk_pol00000000
BIT 7 BIT 0
par_recv_clkdiv(6:0) par_recv_
rxclk_pol00000000
par_recv_sync_del(6:0): Delays the sync source from the DDC0 AGC output by (par_recv_sync_del+1)rxclk cycles.
tst_clk_pol: Selects the polarity of the test clock output at dvga_c(1) when the test bus is enabled; 0 forrising edge in the center of valid data, 1 for falling edge in the center of valid data. No effectwhen tst_rate_sel is 0 0000.
par_recv_clkdiv(6:0): Selects the parallel interface output clock rate.
par_recv_rxclk_pol: Selects the polarity of the rxclk_out clock output; 0 for rising edge in the center ofvalid data, 1 for falling edge in the center of valid data.
Register name: GBL_PAR_CONFIG1 Address: 0x04BIT 15 BIT 8par_recv_syncout_del(3:0) par_recv_chan(3:0)00000000
BIT 7 BIT 0
par_recv_fsinvl(6:0) par_recv_
sync_pol00000000
par_recv_syncout_del(3:0): Changes the rx_sync_out position with respect to IQ DDC0. Setting to 0causes rx_sync_out to lead IQ DDC0 by 1 output sample, setting to 1 causes rx_sync_out toline up with IQ DDC0, setting to 2 causes rx_sync_out to trail IQ DDC0 by 1 output sample,etc.
par_recv_chan(3:0): Selects the number of channels to be output over the parallel interface, from 1 to 16channels.
par_recv_fsinvl(6:0): Selects the number of rxclk cycles per parallel interface frame, from 1 to 128cycles.
par_recv_sync_pol: Selects the polarity of the parallel interface sync pulse; 0 for active-low, 1 foractive-high.
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8.4.2.6 GBL_3STATE Register
8.4.2.7 GBL_ONESHOT Register
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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Register name: GBL_3STATE Address: 0x05BIT 15 BIT 8rxclk_ena Unused Unused Unused Unused 3-state(10) 3-state(9) 3-state(8)10000111
BIT 7 BIT 0
3-state(7) 3-state(6) 3-state(5) 3-state(4) 3-state(3) 3-state(2) 3-state(1) 3-state(0)11111111
rxclk_ena: Master rxclk enable. When set, the chip’s rxclk is enabled, when cleared, rxclk is disabled.
All 3-states are ACTIVE-LOW so a 0 turns on the output and a 1 places it in the high-impedancestate.
3-state(10): This bit turns on the dvga_d outputs.
3-state(9): This bit turns on the dvga_c outputs.
3-state(8): This bit turns on the dvga_b outputs.
3-state(7): This bit turns on the dvga_a outputs.
3-state(6): This bit turns on the rx_sync_out_6/7 and the rxout_6/7_a/b/c/d outputs. (For parallelinterface use only)
3-state(5): This bit turns on the rx_sync_out_4/5 and the rxout_4/5_a/b/c/d outputs.
3-state(4): This bit turns on the rx_sync_out_2/3 and the rxout_2/3_a/b/c/d outputs.
3-state(3): This bit turns on the rx_sync_out_0/1 and the rxout_0/1_a/b/c/d outputs.
3-state(2): Unused
3-state(1): rxclk_out
3-state(0): interrupt and rx_sync_out.
Register name: GBL_ONESHOT Address: 0x06BIT 15 BIT 8Unused Unused Unused Unused Unused Unused Unused Unused00000000
BIT 7 BIT 0
rx_oneshot Unused Unused Unused Unused Unused Unused Unused00000000
rx_oneshot: When set, a one-shot pulse is sent to the receive blocks for syncing. This only works if theblocks are programmed to use the one-shot as the sync source. To use the one-shot again,it must be programmed to a 0 and then back to a 1.
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8.4.2.8 GBL_IMASK0 Register
8.4.2.9 GBL_INTERRUPT0 Register
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Register name: GBL_IMASK0 Address: 0x07BIT 15 BIT 8pmeter7_im pmeter6_im pmeter5_im pmeter4_im pmeter3_im pmeter2_im pmeter1_im pmeter0_im00000000
BIT 7 BIT 0
recv_ recv_ recv_ recv_
rxin_a_ ovr_im rxin_b_ ovr_im rxin_c_ ovr_im rxin_d_ ovr_impmeter0_im pmeter1_im pmeter2_im pmeter3_im00000000
pmeterX_im: When asserted, masks the interrupt for the particular DDC pmeter, X = {0, 1, 2, 3,4, 5, 6, 7}.
recv_pmeterX_im: When asserted, masks the interrupt for the particular receive input pmeter,X = {0, 1, 2, 3}.
rxin_X_ovr_im: When asserted, masks the interrupt for the particular rxin overflow, X = {a, b, c, d}.
Register name: GBL_INTERRUPT0 Address: 0x08BIT 15 BIT 8pmeter7 pmeter6 pmeter5 pmeter4 pmeter3 pmeter2 pmeter1 pmeter000000000
BIT 7 BIT 0
recv_ pmeter0 recv_ pmeter1 recv_ pmeter2 recv_ pmeter3 rxin_a_ovr rxin_b_ovr rcin_c_ovr rxin_d_ovr00000000
pmeterX: Asserted when an interrupt has been generated by this DDC pmeterX block,X = {0, 1, 2, 3, 4, 5, 6, 7}
recv_pmeterX: Asserted when an interrupt has been generated by this receive input pmeter,X = {0, 1, 2, 3}.
rxin_X_ovr: Asserted when a logic high input from the rxin_X_ovr pin occurs, X={a,b,c,d}.
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8.4.3 Receive Input Interface Controls
8.4.3.1 SYNC_DDC_CNTR_LSB Register
8.4.3.2 SYNC_DDC_CNTR_MSB
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Register name: SYNC_DDC_CNTR_LSB Page: 0x1800 Address: 0x00BIT 15 BIT 8ddc_counter(15:8)00000000
BIT 7 BIT 0
ddc_counter(7:0)00000000
Register name: SYNC_DDC_CNTR_MSB Page: 0x1800 Address: 0x01BIT 15 BIT 8ddc_counter(31:24)00000000
BIT 7 BIT 0
ddc_counter(23:16)00000000
ddc_counter(32:0): 32-bit interval timer common to all DDC sync inputs. This timer may be programmedto any interval count, and each DDC synchronization input can select this counter as asource. The value programmed into the counter is: (desired number – 1). The counterincrements on each RX clock rising edge.
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8.4.3.3 SSEL_DDC_CNTR Register
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Register name: SSEL_DDC_CNTR Page: 0x1800 Address: 0x02BIT 15 BIT 8rxinab_mux rxincd_mux Unused Unused Unused ssel_ddc_counter(2:0)00000000
BIT 7 BIT 0
ddc_counter_width(7:0)00000000
rxinab_mux: When asserted, the rxin_a and rxin_b inputs are internally driven by the rxin_c and rxin_dports, respectively (factory-test use only).
rxincd_mux: When asserted, the rxin_c and rxin_d inputs are internally driven by the rxin_a and rxin_bports, respectively (factory-test use only).
ssel_ddc_counter(2:0): Selects the sync source for the DDC sync counter
ddc_counter_width(7:0): Sets the duration of the counter-generated sync pulse in RX clock cycles, from1 to 256.
Sync sources are contained in this and many of the following registers. For all sync source selections:
ssel_ddc_XXXXX(2:0) Selected Sync Source
000 rxsyncA001 rxsyncB010 rxsyncC011 rxsyncD100 DDC sync counter101 One-shot (register write triggered)110 Always 0111 Always 1
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8.4.3.4 SSEL_RX_0 Register
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Register name: SSEL_RX_0 Page: 0x1800 Address: 0x03BIT 15 BIT 8Unused ssel_adc_fifo(2:0) Unused ssel_tst_decim(2:0)00000000
BIT 7 BIT 0
Unused ssel_rxsync_out(2:0) Unused ssel_ddc(2:0)00000000
ssel_adc_fifo(2:0): Selects the sync source for the adc FIFO blocks. Sync reinitializes the read and writepointers of the FIFO.
ssel_tst_decim(2:0): Selects the sync source for the test bus decimator block.
ssel_rxsync_out(2:0): Selects the sync source for the RXSYNC_OUT pin.
ssel_ddc(2:0): Selects the sync source for the DDC data input multiplexer and mixer. Controls clockgeneration in each DDC block (before the CIC input), which must match because the FIFOoutput clock is common for all DDC blocks.
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8.4.3.5 RECV_CONFIG0 Register
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Register name: RECV_CONFIG0 Page: 0x1800 Address: 0x04BIT 15 BIT 8adc_ adc_ self_test_ adc_ ragc_mpu_ramrate_sel(1:0) tst_ decim17fifo_strap_ab fifo_strap_cd const_ena fifo_bypass _read00000000
BIT 7 BIT 0
tst_decim_delay(3:0) pmeter3_iq pmeter2_iq pmeter1_iq pmeter0_iq00000000
rate_sel(1:0): Tells RECV_CDRV the input rate. This is the rxin_a/b/c/d input rate and the rate that thereceive input interface block sends data to the DDCs.
rate_sel Input clock rate
00 rxclk01 rxclk/210 rxclk/411 rxclk/8
adc_fifo_strap_ab: When asserted, the input pointers of the rxin_a FIFO and rxin_b FIFO are hookedtogether in lock-step configuration. This is used for maintaining FIFO delay consistency whencomplex inputs are driven on rxin_a(I) and rxin_b(Q). rxin_a is the master.
adc_fifo_strap_cd: When asserted, the input pointers of the rxin_c FIFO and rxin_d FIFO are hookedtogether in lock-step configuration. This is used for maintaining FIFO delay consistency whencomplex inputs are driven on rxin_c(I) and rxin_d(Q). rxin_c is the master.
self_test_const_ena: When asserted, (with slf_tst_ena also asserted), a constant value is output by thetest and noise generator instead of the pseudorandom sequence. The constant value isprogrammable.
adc_fifo_bypass: When asserted, the ADC FIFO circuits are bypassed. Input data is then clocked indirectly using the rxclk input. The ssel_ddc selection value controls the location of theinternally generated sample clock when this bit is asserted, where rate_sel is rxclk/2, rxclk/4,or rxclk/8.
ragc_mpu_ram_read: When asserted, the RAMs in the RAGC blocks can be read. This bit should onlybe set when reading the RAGC map RAMs via the MPU interface, and must be cleared forproper RAGC operation.
tst_decim17: Must be cleared
tst_decim_delay(3:0): These bits set the delay from the occurrence of sync until the decimator samples.In other words, the moment of the decimator is set by this delay value.
pmeter3_iq: When asserted, the pmeter3 block takes input from both rxin_c and rxin_d as a complexsample pair. When de-asserted, only input from rxin_d is used for the power measurement.
pmeter2_iq: When asserted, the pmeter2 block takes input from both rxin_c and rxin_d as a complexsample pair. When de-asserted, only input from rxin_c is used for the power measurement.
pmeter1_iq: When asserted, the pmeter1 block takes input from both rxin_a and rxin_b as a complexsample pair. When de-asserted, only input from rxin_b is used for the power measurement.
pmeter0_iq: When asserted, the pmeter0 block takes input from both rxin_a and rxin_b as a complexsample pair. When de-asserted, only input from rxin_a is used for the power measurement.
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8.4.3.6 RECV_CONFIG1 Register
8.4.3.7 NZ_PWR_MASK Register
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Register name: RECV_CONFIG1 Page: 0x1800 Address: 0x05BIT 15 BIT 8msb_pos_d(2:0) offset_bin_d msb_pos_c(2:0) offset_bin_c00000000
BIT 7 BIT 0
msb_pos_b(2:0) offset_bin_b msb_pos_a(2:0) offset_bin_a00000000
msb_pos_X(2:0): Places the MSB of the input word from the ADC. The value programmed into these 3bits is the MSB location in bit positions to the left of bit 16 of the input word. For example, if a14-bit input word is driving rxin_a input and is aligned with rxin_a_0, then msb_pos_a isprogrammed to 010 meaning the MSB is shifted down 2 bits from bit 16. X = {a, b, c, d}.
offset_bin_X: rxin_X input data is in 2s complement and not offset binary. If cleared, the input value isconverted to 2s complement using the MSB from the corresponding msb_pos_X value. X ={a, b, c, d}. Note that the internal ADCs use 2s complement format, so offset_bin_Aand offset_bin_B must be cleared.
Register name: NZ_PWR_MASK Page: 0x1800 Address: 0x06BIT 15 BIT 8nz_pwr_mask(15:8)00000000
BIT 7 BIT 0
nz_pwr_mask(7:0)00000000
nz_pwr_mask(15:0): Used with rduz_sens_ena, it selects the noise bits to be added to the ADC inputsample when asserted.
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8.4.3.8 RECV_PMETER_SYNC Register
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Register name: RECV_PMETER_SYNC Page: 0x1800 Address: 0x07BIT 15 BIT 8recv_pmeter0_ ssel_recv_pmeter0(2:0) recv_pmeter1_ ssel_ recv_pmeter1(2:0)ena ena00000000
BIT 7 BIT 0
recv_pmeter2_ ssel_ recv_pmeter2(2:0) recv_pmeter3_ ssel_ recv_pmeter3(2:0)ena ena00000000
recv_pmeter0_ena: Enables the receive input interface pmeter0 block when set
recv_pmeter1_ena: Enables the receive input interface pmeter1 block when set
recv_pmeter2_ena: Enables the receive input interface pmeter2 block when set
recv_pmeter3_ena: Enables the receive input interface pmeter3 block when set
ssel_ recv_pmeter0(2:0): Selects the sync source for the receive input interface pmeter0 block
ssel_ recv_pmeter1(2:0): Selects the sync source for the receive input interface pmeter1 block
ssel_ recv_pmeter2(2:0): Selects the sync source for the receive input interface pmeter2 block
ssel_ recv_pmeter3(2:0): Selects the sync source for the receive input interface pmeter3 block
Submit Documentation Feedback AFE8405 GENERAL CONTROL 93
8.4.3.9 RECV_PMETER0_SQR_SUM_LSB Register
8.4.3.10 RECV_PMETER0_STRT_INTVL_LSB Register
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Register name: RECV_PMETER0_SQR_SUM_LSB Page: 0x1800 Address: 0x08BIT 15 BIT 8recv_pmeter0_sqr_sum(15:8)00000000
BIT 7 BIT 0
recv_pmeter0_sqr_sum(7:0)00000000
recv_pmeter0_sqr_sum(15:0): The sqr_sum register controls the number of samples to accumulate for apower measurement. Ia is (or Ia and Qa are) if complex mode is selected squared andaccumulated. Eight Ia samples (or eight pairs of Ia and Qa samples) equal one sqr_sumcount. The accumulation interval is initiated when sync is asserted and the programmed (8 ×sync_delay + 2) samples have expired or when the interval start time is reached. When the(8 ×sqr_sum + 1) sample time is reached, the accumulated powers are made available forMPU access and an interrupt is generated.
Register name: RECV_PMETER0_STRT_INTVL_LSB Page: 0x1800 Address: 0x09BIT 15 BIT 8recv_pmeter0_strt_intrvl(15:8)00000000
BIT 7 BIT 0
recv_pmeter0_strt_intrvl(7:0)00000000
recv_pmeter0_strt_intrvl(15:0): The start interval timer is the interval over which sqr_sum is restarted.The timer value is (8 ×strt_intrvl + 1) samples and must be larger than (8 ×sqr_sum + 1)samples. The interval start counter and RMS power accumulation is started at the sync pulseafter the programmed delay and every time the STRT_INTRVL counter reaches its limit.
94 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.3.11 RECV_PMETER0_SYNC_DLY Register
8.4.3.12 RECV_PMETER0_CONFIG Register
8.4.3.13 RECV_PMETER1_SQR_SUM_LSB Register
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Register name: RECV_PMETER0_SYNC_DLY Page: 0x1800 Address: 0x0ABIT 15 BIT 8delay_line_0(5:0) Unused recv_pmeter0_
sync_delay(8)00000000
BIT 7 BIT 0
recv_pmeter0_sync_delay(7:0)00000000
delay_line_0(5:0): Pointer offset for the rxin_a path variable delay line. Larger values result in largerpointer offsets and therefore more path delay.
recv_pmeter0_sync_delay(8:0): Programmable start delay from sync, in eight-sample units. The actualvalue is (8 ×sync_delay + 2) samples.
Register name: RECV_PMETER0_CONFIG Page: 0x1800 Address: 0x0BBIT 15 BIT 8recv_pmeter0_sqr_sum(20:16) recv_pmeter0_strt_intrvl(20:18)00000000
BIT 7 BIT 0
recv_pmeter0_strt_ intrvl(17:16) Unused Unused Unused ssel_delay_line_0(2:0)00000000
recv_pmeter0_sqr_sum(20:16): MSBs of sqr_sum value, in eight-sample units
recv_pmeter0_strt_intrvl(20:16): MSBs of start interval value, in eight-sample units.
ssel_delay_line_0(2:0): Sync source selection for the 64-sample delay line pointer value update
Register name: RECV_PMETER1_SQR_SUM_LSB Page: 0x1800 Address: 0x0CBIT 15 BIT 8recv_pmeter1_sqr_sum(15:8)00000000
BIT 7 BIT 0
recv_pmeter1_sqr_sum(7:0)00000000
recv_pmeter1_sqr_sum(15:0): Lower 16 bits of the sqr_sum interval timer, in eight-sample units.
Submit Documentation Feedback AFE8405 GENERAL CONTROL 95
8.4.3.14 RECV_PMETER1_STRT_INTVL_LSB Register
8.4.3.15 RECV_PMETER1_SYNC_DLY Register
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Register name: RECV_PMETER1_STRT_INTVL_LSB Page: 0x1800 Address: 0x0DBIT 15 BIT 8recv_pmeter1_strt_intrvl(15:8)00000000
BIT 7 BIT 0
recv_pmeter1_strt_intrvl(7:0)00000000
recv_pmeter1_strt_intrvl(15:0): Lower 16 bits of the interval timer, in eight-sample units.
Register name: RECV_PMETER1_SYNC_DLY Page: 0x1800 Address: 0x0EBIT 15 BIT 8delay_line_1(5:0) Unused recv_pmeter1_
sync_ delay(8)00000000
BIT 7 BIT 0
recv_pmeter1_sync_delay(7:0)00000000
delay_line_1(5:0): Pointer offset for the rxin_b path variable delay line. Larger values result in largerpointer offsets and therefore more path delay.
recv_pmeter1_sync_delay(8:0): Programmable start delay from sync, in eight-sample units
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8.4.3.16 RECV_PMETER1_CONFIG Register
8.4.3.17 RECV_PMETER2_SQR_SUM_LSB Register
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Register name: RECV_PMETER1_CONFIG Page: 0x1800 Address: 0x0FBIT 15 BIT 8recv_pmeter1_sqr_sum(20:16) recv_pmeter1_strt_intrvl(20:18)00000000
BIT 7 BIT 0
recv_pmeter1_strt_ intrvl(17:16) Unused Unused Unused ssel_delay_line_1(2:0)00000000
recv_pmeter1_sqr_sum(20:16): MSBs of sqr_sum value, in eight-sample units
recv_pmeter1_strt_intrvl(20:16): MSBs of start interval value, in eight-sample units
ssel_delay_line_1(2:0): Sync source selection for the 64-sample delay-line pointer-value update
Register name: RECV_PMETER2_SQR_SUM_LSB Page: 0x1800 Address: 0x10BIT 15 BIT 8recv_pmeter2_sqr_sum(15:8)00000000
BIT 7 BIT 0
recv_pmeter2_sqr_sum(7:0)00000000
recv_pmeter2_sqr_sum(15:0): Lower 16 bits of the sqr_sum interval timer, in eight-sample units
Submit Documentation Feedback AFE8405 GENERAL CONTROL 97
8.4.3.18 RECV_PMETER2_STRT_INTVL_LSB Register
8.4.3.19 RECV_PMETER2_SYNC_DLY Register
8.4.3.20 RECV_PMETER2_CONFIG Register
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Register name: RECV_PMETER2_STRT_INTVL_LSB Page: 0x1800 Address: 0x11BIT 15 BIT 8recv_pmeter2_strt_intrvl(15:8)00000000
BIT 7 BIT 0
recv_pmeter2_strt_intrvl(7:0)00000000
recv_pmeter2_strt_intrvl(15:0): Lower 16 bits of the interval timer, in eight-sample units
Register name: RECV_PMETER2_SYNC_DLY Page: 0x1800 Address: 0x12BIT 15 BIT 8delay_line_2(5:0) Unused recv_pmeter2_
sync_ delay(8)00000000
BIT 7 BIT 0
recv_pmeter2_sync_delay(7:0)00000000
delay_line_2(5:0): Pointer offset for the rxin_c path variable delay line. Larger values result in largerpointer offsets and therefore more path delay.
recv_pmeter2_sync_delay(8:0): Programmable start delay from sync, in eight-sample units
Register name: RECV_PMETER2_CONFIG Page: 0x1800 Address: 0x13BIT 15 BIT 8recv_pmeter2_sqr_sum(20:16) recv_pmeter2_strt_intrvl(20:18)00000000
BIT 7 BIT 0
recv_pmeter2_strt_ intrvl(17:16) Unused Unused Unused ssel_delay_line_2(2:0)00000000
recv_pmeter2_sqr_sum(20:16): MSBs of sqr_sum value, in eight-sample units
recv_pmeter2_strt_intrvl(20:16): MSBs of start interval value, in eight-sample units
ssel_delay_line_2(2:0): Sync source selection for the 64-sample delay-line pointer-value update
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8.4.3.21 RECV_PMETER3_SQR_SUM_LSB Register
8.4.3.22 RECV_PMETER3_STRT_INTVL_LSB Register
8.4.3.23 RECV_PMETER3_SYNC_DLY Register
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Register name: RECV_PMETER3_SQR_SUM_LSB Page: 0x1800 Address: 0x14BIT 15 BIT 8recv_pmeter3_sqr_sum(15:8)00000000
BIT 7 BIT 0
recv_pmeter3_sqr_sum(7:0)00000000
recv_pmeter3_sqr_sum(15:0): Lower 16 bits of the sqr_sum interval timer, in eight-sample units
Register name: RECV_PMETER3_STRT_INTVL_LSB Page: 0x1800 Address: 0x15BIT 15 BIT 8recv_pmeter3_strt_intrvl(15:8)00000000
BIT 7 BIT 0
recv_pmeter3_strt_intrvl(7:0)00000000
recv_pmeter3_strt_intrvl(15:0): Lower 16 bits of the interval timer, in eight-sample units
Register name: RECV_PMETER3_SYNC_DLY Page: 0x1800 Address: 0x16BIT 15 BIT 8delay_line_3(5:0) Unused recv_pme
ter3_sync_
delay(8)00000000
BIT 7 BIT 0
recv_pmeter3_sync_delay(7:0)00000000
delay_line_3(5:0): Pointer offset for the rxin_d path variable delay line. Larger values result in largerpointer offsets and therefore more path delay.
recv_pmeter3_sync_delay(8:0): Programmable start delay from sync, in eight-sample units
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8.4.3.24 RECV_PMETER3_CONFIG Register
8.4.3.25 RECV_SLF_TST_VALUE Register
8.4.3.26 RECV_PMETER0_LSB Register
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Register name: RECV_PMETER3_CONFIG Page: 0x1800 Address: 0x17BIT 15 BIT 8recv_pmeter3_sqr_sum(20:16) recv_pmeter3_strt_intrvl(20:18)00000000
BIT 7 BIT 0
recv_pmeter3_strt_ intrvl(17:16) Unused Unused Unused ssel_delay_line_3(2:0)00000000
recv_pmeter3_sqr_sum(20:16): MSBs of sqr_sum value, in eight-sample units
recv_pmeter3_strt_intrvl(20:16): MSBs of start interval value, in eight-sample units
ssel_delay_line_3(2:0): Sync source selection for the 64-sample delay-line pointer-value update
Register name: RECV_SLF_TST_VALUE Page: 0x1800 Address: 0x18BIT 15 BIT 8self_test_constant(15:8)00000000
BIT 7 BIT 0
self_test_constant(7:0)00000000
self_test_constant(15:0): 16-bit constant presented at the test and noise generator output whenenabled. Used for test and debug purposes.
Register name: RECV_PMETER0_LSB Page: 0x1820 Address: 0x00 Read-onlyBIT 15 BIT 8recv_pmeter0(15:8)00000000
BIT 7 BIT 0
recv_pmeter0(7:0)00000000
recv_pmeter0(15:0): Lower bits of the power meter 0 measurement
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8.4.3.27 RECV_PMETER0_MID Register
8.4.3.28 RECV_PMETER0_LMSB Register
8.4.3.29 RECV_PMETER0_UMSB Register
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Register name: RECV_PMETER0_MID Page: 0x1820 Address: 0x01 Read-onlyBIT 15 BIT 8recv_pmeter0(31:24)00000000
BIT 7 BIT 0
recv_pmeter0(23:16)00000000
recv_pmeter0(31:16): Mid bits of the power meter 0 measurement
Register name: RECV_PMETER0_LMSB Page: 0x1820 Address: 0x02 Read-onlyBIT 15 BIT 8recv_pmeter0(47:40)00000000
BIT 7 BIT 0
recv_pmeter0(39:32)00000000
recv_pmeter0(47:32): Lower MSB bits of the power meter 0 measurement
Register name: RECV_PMETER0_UMSB Page: 0x1820 Address: 0x03 Read-onlyBIT 15 BIT 8Unused Unused Unused Unused Unused Unused recv_pmeter0(57:56)00000000
BIT 7 BIT 0
recv_pmeter0(55:48)00000000
recv_pmeter0(57:48): Upper MSB bits of the power meter 0 measurement
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8.4.3.30 RECV_PMETER1_LSB Register
8.4.3.31 RECV_PMETER1_MID Register
8.4.3.32 RECV_PMETER1_LMSB Register
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Register name: RECV_PMETER1_LSB Page: 0x1820 Address: 0x04 Read-onlyBIT 15 BIT 8recv_pmeter1(15:8)00000000
BIT 7 BIT 0
recv_pmeter1(7:0)00000000
recv_pmeter1(15:0): Lower bits of the power meter 1 measurement
Register name: RECV_PMETER1_MID Page: 0x1820 Address: 0x05 Read-onlyBIT 15 BIT 8recv_pmeter1(31:24)00000000
BIT 7 BIT 0
recv_pmeter1(23:16)00000000
recv_pmeter1(31:16): Mid bits of the power meter 1 measurement
Register name: RECV_PMETER1_LMSB Page: 0x1820 Address: 0x06 Read-onlyBIT 15 BIT 8recv_pmeter1(47:40)00000000
BIT 7 BIT 0
recv_pmeter1(39:32)00000000
recv_pmeter1(47:32): Lower MSB bits of the power meter 1 measurement
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8.4.3.33 RECV_PMETER1_UMSB Register
8.4.3.34 RECV_PMETER2_LSB Register
8.4.3.35 RECV_PMETER2_MID Register
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Register name: RECV_PMETER1_UMSB Page: 0x1820 Address: 0x07 Read-onlyBIT 15 BIT 8Unused Unused Unused Unused Unused Unused recv_pmeter1(57:56)00000000
BIT 7 BIT 0
recv_pmeter1(55:48)00000000
recv_pmeter1(57:48): Upper MSB bits of the power meter 1 measurement
Register name: RECV_PMETER2_LSB Page: 0x1820 Address: 0x08 Read-onlyBIT 15 BIT 8recv_pmeter2(15:8)00000000
BIT 7 BIT 0
recv_pmeter2(7:0)00000000
recv_pmeter2(15:0): Lower bits of the power meter 2 measurement
Register name: RECV_PMETER2_MID Page: 0x1820 Address: 0x09 Read-onlyBIT 15 BIT 8recv_pmeter2(31:24)00000000
BIT 7 BIT 0
recv_pmeter2(23:16)00000000
recv_pmeter2(31:16): Mid bits of the power meter 2 measurement
Submit Documentation Feedback AFE8405 GENERAL CONTROL 103
8.4.3.36 RECV_PMETER2_LMSB Register
8.4.3.37 RECV_PMETER2_UMSB Register
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Register name: RECV_PMETER2_LMSB Page: 0x1820 Address: 0x0A Read-onlyBIT 15 BIT 8recv_pmeter2(47:40)00000000
BIT 7 BIT 0
recv_pmeter2(39:32)00000000
recv_pmeter2(47:32): Lower MSB bits of the power meter 2 measurement
Register name: RECV_PMETER2_UMSB Page: 0x1820 Address: 0x0B Read-onlyBIT 15 BIT 8Unused Unused Unused Unused Unused Unused recv_pmeter2(57:56)00000000
BIT 7 BIT 0
recv_pmeter2(55:48)00000000
recv_pmeter2(57:48): Upper MSB bits of the power meter 2 measurement
104 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.3.38 RECV_PMETER3_LSB Register
8.4.3.39 RECV_PMETER3_MID Register
8.4.3.40 RECV_PMETER3_LMSB Register
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Register name: RECV_PMETER3_LSB Page: 0x1820 Address: 0x0C Read-onlyBIT 15 BIT 8recv_pmeter3(15:8)00000000
BIT 7 BIT 0
recv_pmeter3(7:0)00000000
recv_pmeter3(15:0): Lower bits of the power meter 3 measurement
Register name: RECV_PMETER3_MID Page: 0x1820 Address: 0x0D Read-onlyBIT 15 BIT 8recv_pmeter3(31:24)00000000
BIT 7 BIT 0
recv_pmeter3(23:16)00000000
recv_pmeter3(31:16): Mid bits of the power meter 3 measurement
Register name: RECV_PMETER3_LMSB Page: 0x1820 Address: 0x0E READ_ONLYBIT 15 BIT 8recv_pmeter3(47:40)00000000
BIT 7 BIT 0
recv_pmeter3(39:32)00000000
recv_pmeter3(47:32): Lower MSB bits of the power meter 3 measurement
Submit Documentation Feedback AFE8405 GENERAL CONTROL 105
8.4.3.41 RECV_PMETER3_UMSB Register
8.4.4 Receive AGC Controls
8.4.4.1 RAGC_CONFIG0 Register
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Register name: RECV_PMETER3_UMSB Page: 0x1820 Address: 0x0F READ_ONLYBIT 15 BIT 8Unused Unused recv_pmeter3(57:56)00000000
BIT 7 BIT 0
recv_pmeter3(55:48)00000000
recv_pmeter3(57:48): Upper MSB bits of the power meter 3 measurement
Register name: RAGC_CONFIG0 Page: 0x1840 Address: 0x00BIT 15 BIT 8hp_ena_0 hp_ena_1 hp_ena_2 hp_ena_3 sd_ena_0 sd_ena_1 sd_ena_2 sd_ena_300000000
BIT 7 BIT 0
ragc_ bypass_0 ragc_ bypass_1 ragc_ bypass_2 ragc_ bypass_3 Unused Unused Unused Unused00000000
hp_ena_X: Enables the high pass filter in receive AGC X when set.
sd_ena_X: Enables the Signal Detect block in receive AGC X when set.
ragc_bypass_X: Bypasses the receive AGC X block when set.
106 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.4.2 RAGC_CONFIG1 Register
8.4.4.3 RAGC_CONFIG2 Register
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Register name: RAGC_CONFIG1 Page: 0x1840 Address: 0x01BIT 15 BIT 8ragc_ freeze_0 ragc_ freeze_1 ragc_ freeze_2 ragc_ freeze_3 ragc_ clear_0 ragc_ clear_1 ragc_ clear_2 ragc_ clear_300000000
BIT 7 BIT 0
complex01 complex23 ssel_ragc_interval_0(2:0) ssel_ragc_interval_1(2:0)00000000
ragc_freeze_X: Freezes the receive AGC block when set.
ragc_clear_X: Clears the loop error accumulator when set.
complex01: When set, receive AGC 0 uses complex input with the second sample stream coming fromreceive AGC 1. The clip detect, high pass, and squarer from receive AGC 1 are used togenerate inputs for receive AGC 0.
complex23: When set, receive AGC 2 uses complex input with the second sample stream coming fromreceive AGC 3. The clip detect, high pass, and squarer from receive AGC 3 are used togenerate inputs for receive AGC 2.
ssel_ragc_interval_0(2:0): Selects the sync source for receive AGC 0. After a programmed delay fromsync, the interval update timer is started.
ssel_ragc_interval_1(2:0): Selects the sync source for receive AGC 1. After a programmed delay fromsync, the interval update timer is started.
Register name: RAGC_CONFIG2 Page: 0x1840 Address: 0x02BIT 15 BIT 8ssel_ragc_freeze_0(2:0) ssel_ragc_freeze_1(2:0) ssel_ragc_ freeze_2(2:1)00000000
BIT 7 BIT 0
ssel_ragc_freez ssel_ragc_interval_2(2:0)ssel_ragc_freeze_3(2:0) Unusede_2(0)
00000000
ssel_ragc_freeze_X(2:0): Selects the sync source that freezes the receive AGC loop when asserted.
ssel_ragc_interval_2(2:0): Selects the sync source for receive AGC 2. After a programmed delay fromsync, the interval update timer is started.
Submit Documentation Feedback AFE8405 GENERAL CONTROL 107
8.4.4.4 RAGC_CONFIG3 Register
8.4.4.5 RAGC0_INTEGINVL_LSB Register
8.4.4.6 RAGC0_INTEGINVL_MSB Register
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Register name: RAGC_CONFIG3 Page: 0x1840 Address: 0x03BIT 15 BIT 8ssel_ragc_clear_0(2:0) ssel_ragc_clear_1(2:0) ssel_ragc_ clear_2(2:1)00000000
BIT 7 BIT 0
ssel_ragc_
ssel_ragc_clear_3(2:0) Unused ssel_ragc_interval_3(2:0)clear_2(0)
00000000
ssel_agc_clear_X(2:0: Controls the selection of the sync that clears the receive AGC error accumulator.
ssel_agc_interval_3(2:0): Selects the sync source for receive AGC 3. After a programmed delay fromsync, the interval update timer is started.
Register name: RAGC0_INTEGINVL_LSB Page: 0x1840 Address: 0x04BIT 15 BIT 8integ_interval_0(15:8)00000000
BIT 7 BIT 0
integ_interval_0(7:0)00000000
integ_interval_0(15:0): The 16 LSBs of the integration time for receive AGC 0.
Register name: RAGC0_INTEGINVL_MSB Page: 0x1840 Address: 0x05BIT 15 BIT 8ragc_update_0(7:0)00000000
BIT 7 BIT 0
integ_interval_0(23:16)00000000
ragc_update_0(7:0): Sets the number of receive AGC updates per sync event (0x00 is infinite).
integ_interval_0(23:16): The eight MSBs of the integration time for receive AGC 0.
108 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.4.7 RAGC0_CONFIG0 Register
8.4.4.8 RAGC0_CONFIG1 Register
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Register name: RAGC0_CONFIG0 Page: 0x1840 Address: 0x06BIT 15 BIT 8ragc_sync_delay_0(7:0)00000000
BIT 7 BIT 0
hp_corner_0(2:0) acc_shift_0(4:0)00000000
ragc_sync_delay_0(7:0): The input sync to the receive AGC block is delayed by this number of samples.
hp_corner_0(2:0): Sets the corner frequency of the high-pass filter. Larger values result in higher cornerfrequencies
acc_shift_0(4:0): Selects the integrated power measurements result bits to be used as the error lookuptable address. A larger number means fewer samples must be integrated to achieve thesame result.
Register name: RAGC0_CONFIG1 Page: 0x1840 Address: 0x07BIT 15 BIT 8acc_offset_0(5:0) err_shift_0(4:3)00000000
BIT 7 BIT 0
err_shift_0(2:0) delay_adj_0(4:0)00000000
acc_offset_0(5:0): Constant subtracted from the integrated power measurement result before the errorlookup table.
err_shift_0(4:0): Adjusts the loop gain by controlling the amount of shifting applied to the error lookuptable output. Larger values result in higher gain.
delay_adj_0(4:0): Sets the delay difference, in samples, between the DVGA outputs and the valueapplied to the sample multiplier.
Submit Documentation Feedback AFE8405 GENERAL CONTROL 109
8.4.4.9 RAGC0_SD_THRESH Register
8.4.4.10 RAGC0_SD_TIMER Register
8.4.4.11 RAGC0_SD_SAMPLES Register
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Register name: RAGC0_SD_THRESH Page: 0x1840 Address: 0x08BIT 15 BIT 8sd_thresh_0(15:8)00000000
BIT 7 BIT 0
sd_thresh_0(7:0)00000000
sd_thresh_0(15:0): This is the threshold used by the signal-detect block to determine if there is a signalon the inputs. The comparison is done to the output of the squarer block, which is a 32-bitword. Because of this, these bits are aligned with bits 24 down to 8 of the 32-bit squaredvalue.
Register name: RAGC0_SD_TIMER Page: 0x1840 Address: 0x09BIT 15 BIT 8sd _timer_0(15:8)00000000
BIT 7 BIT 0
sd _timer_0(7:0)00000000
sd_timer_0(15:0): Qualification window timer for loss of input signal.
Register name: RAGC0_SD_SAMPLES Page: 0x1840 Address: 0x0ABIT 15 BIT 8sd_samples_0(15:8)00000000
BIT 7 BIT 0
sd_samples_0(7:0)00000000
sd_samples_0(15:0): Number of samples that must be below the sd_thresh_X within the sd_timer_Xtimer value for the loss-of-signal condition to occur.
110 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.4.12 RAGC0_CLIP_HITHRESH Register
8.4.4.13 RAGC0_CLIP_LOTHRESH Register
8.4.4.14 RAGC0_CLIP_HITIMER Register
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Register name: RAGC0_CLIP_HITHRESH Page: 0x1840 Address: 0x0BBIT 15 BIT 8clip_hi_thresh_0(15:8)00000000
BIT 7 BIT 0
clip_hi_thresh_0(7:0)00000000
clip_hi_thresh_0(15:0): The high threshold value for clip detection
Register name: RAGC0_CLIP_LOTHRESH Page: 0x1840 Address: 0x0CBIT 15 BIT 8clip_lo_thresh_0(15:8)00000000
BIT 7 BIT 0
clip_lo_thresh_0(7:0)00000000
clip_lo_thresh_0(15:0): The low threshold value for clip detection
Register name: RAGC0_CLIP_HITIMER Page: 0x1840 Address: 0x0DBIT 15 BIT 8clip_hi_timer_0(15:8)00000000
BIT 7 BIT 0
clip_hi_timer_0(7:0)00000000
clip_hi_timer_0(15:0): The high timer value in samples
Submit Documentation Feedback AFE8405 GENERAL CONTROL 111
8.4.4.15 RAGC0_CLIP_LOTIMER Register
8.4.4.16 RAGC0_CLIP_SAMPLES Register
8.4.4.17 RAGC0_CLIP_ERROR Register
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Register name: RAGC0_CLIP_LOTIMER Page: 0x1840 Address: 0x0EBIT 15 BIT 8clip_lo_timer_0(15:8)00000000
BIT 7 BIT 0
clip_lo_timer_0(7:0)00000000
clip_lo_timer_0(15:0): The low timer value in samples
Register name: RAGC0_CLIP_SAMPLES Page: 0x1840 Address: 0x0FBIT 15 BIT 8clip_hi_samples_0(7:0)00000000
BIT 7 BIT 0
clip_lo_samples_0(7:0)00000000
clip_hi_samples_0(7:0): Number of samples above the high threshold within the clip high time to enablethe clip event
clip_lo_samples_0(7:0): Number of samples below the low threshold within the clip low time to disablethe clip event
Register name: RAGC0_CLIP_ERROR Page: 0x1840 Address: 0x10BIT 15 BIT 8clip_error_0(15:8)00000000
BIT 7 BIT 0
clip_error_0(7:0)00000000
clip_error_0(15:0): This is the error value that is added into the loop accumulator when a clip is detected.
112 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.4.18 RAGC1_INTEGINVL_LSB Register
8.4.4.19 RAGC1_INTEGINVL_MSB Register
8.4.4.20 RAGC1_CONFIG0 Register
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Register name: RAGC1_INTEGINVL_LSB Page: 0x1840 Address: 0x11BIT 15 BIT 8integ_interval_1(15:8)00000000
BIT 7 BIT 0
integ_interval_1(7:0)00000000
integ_interval_1(15:0): The LSBs of the integration time for receive AGC 1
Register name: RAGC1_INTEGINVL_MSB Page: 0x1840 Address: 0x12BIT 15 BIT 8ragc_update_1(7:0)00000000
BIT 7 BIT 0
integ_interval_1(23:16)00000000
ragc_update_1(7:0): Sets the number of receive AGC updates per sync event (0x00 is infinite).
integ_interval_1(23:16): The MSBs of the integration time for receive AGC 1
Register name: RAGC1_CONFIG0 Page: 0x1840 Address: 0x13BIT 15 BIT 8ragc_sync_delay_1(7:0)00000000
BIT 7 BIT 0
hp_corner_1(2:0) acc_shift_1(4:0)00000000
ragc_sync_delay_1(7:0): The input sync to the receive AGC block is delayed by this value of samples.
hp_corner_1(2:0): This sets the corner frequency of the high-pass filter. Larger values result in highercorner frequencies.
acc_shift_1(4:0): Selects the integrated power measurements result bits to be used as the error lookuptable address. A larger number means fewer samples must be integrated to achieve thesame result.
Submit Documentation Feedback AFE8405 GENERAL CONTROL 113
8.4.4.21 RAGC1_CONFIG1 Register
8.4.4.22 RAGC1_SD_THRESH Register
8.4.4.23 RAGC1_SD_TIMER Register
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Register name: RAGC1_CONFIG1 Page: 0x1840 Address: 0x14BIT 15 BIT 8acc_offset_1(5:0) err_shift_1(4:3)00000000
BIT 7 BIT 0
err_shift_1(2:0) delay_adj_1(4:0)00000000
acc_offset_1(5:0): Constant subtracted from the integrated power measurement result before the errorlookup table
err_shift_1(4:0): Controls the loop gain by left-shifting the error output. Larger values result in highergain.
delay_adj_1(4:0): Sets the delay difference, in samples, between the DVGA outputs and the valueapplied to the sample multiplier.
Register name: RAGC1_SD_THRESH Page: 0x1840 Address: 0x15BIT 15 BIT 8sd_thresh_1(15:8)00000000
BIT 7 BIT 0
sd_thresh_1(7:0)00000000
sd_thresh_1(15:0): This is the threshold used by the signal-detect block to determine if there is signal onthe inputs. The comparison is done to the output of the squarer block, which is a 32-bit word.Because of this, these bits are aligned with bits 24 down to 8 of the 32-bit squared value.
Register name: RAGC1_SD_TIMER Page: 0x1840 Address: 0x16BIT 15 BIT 8sd_timer_1(15:8)00000000
BIT 7 BIT 0
sd_timer_1(7:0)00000000
sd_timer_1(15:0): After the first no-signal sample occurs, this is the amount of samples that controls thelength of time to determine the loss-of-signal condition.
114 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.4.24 RAGC1_SD_SAMPLES Register
8.4.4.25 RAGC1_CLIP_HITHRESH Register
8.4.4.26 RAGC1_CLIP_LOTHRESH Register
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Register name: RAGC1_SD_SAMPLES Page: 0x1840 Address: 0x17BIT 15 BIT 8sd_samples_1(15:8)00000000
BIT 7 BIT 0
sd_samples_1(7:0)00000000
sd_samples_1(15:0): Number of samples that must be below the sd_thresh_X threshold within thesd_timer_X timer value for the loss-of-signal condition to occur.
Register name: RAGC1_CLIP_HITHRESH Page: 0x1840 Address: 0x18BIT 15 BIT 8clip_hi_thresh_1(15:8)00000000
BIT 7 BIT 0
clip_hi_thresh_1(7:0)00000000
clip_hi_thresh_1(15:0): The high threshold value for clip detection
Register name: RAGC1_CLIP_LOTHRESH Page: 0x1840 Address: 0x19BIT 15 BIT 8clip_lo_thresh_1(15:8)00000000
BIT 7 BIT 0
clip_lo_thresh_1(7:0)00000000
clip_lo_thresh_1(15:0): The low threshold value for clip detection
Submit Documentation Feedback AFE8405 GENERAL CONTROL 115
8.4.4.27 RAGC1_CLIP_HITIMER Register
8.4.4.28 RAGC1_CLIP_LOTIMER Register
8.4.4.29 RAGC1_CLIP_SAMPLES Register
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Register name: RAGC1_CLIP_HITIMER Page: 0x1840 Address: 0x1ABIT 15 BIT 8clip_hi_timer_1(15:8)00000000
BIT 7 BIT 0
clip_hi_timer_1(7:0)00000000
clip_hi_timer_1(15:0): The high timer value in samples
Register name: RAGC1_CLIP_LOTIMER Page: 0x1840 Address: 0x1BBIT 15 BIT 8clip_lo_timer_1(15:8)00000000
BIT 7 BIT 0
clip_lo_timer_1(7:0)00000000
clip_lo_timer_1(15:0): The low timer value in samples
Register name: RAGC1_CLIP_SAMPLES Page: 0x1840 Address: 0x1CBIT 15 BIT 8clip_hi_samples_1(7:0)00000000
BIT 7 BIT 0
clip_lo_samples_1(7:0)00000000
clip_hi_samples_1(7:0): Number of samples above the high threshold within the clip high time to enablethe clip event.
clip_lo_samples_1(7:0): Number of samples below the low threshold within the clip low time to disablethe clip event.
116 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.4.30 RAGC1_CLIP_ERROR Register
8.4.4.31 RAGC2_INTEGINVL_LSB Register
8.4.4.32 RAGC2_INTEGINVL_MSB Register
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Register name: RAGC1_CLIP_ERROR Page: 0x1840 Address: 0x1DBIT 15 BIT 8clip_error_1(15:8)00000000
BIT 7 BIT 0
clip_error_1(7:0)00000000
clip_error_1(15:0): This is the error value that is added into the loop accumulator when a clip is detected.
Register name: RAGC2_INTEGINVL_LSB Page: 0x1840 Address: 0x1EBIT 15 BIT 8integ_interval_2(15:8)00000000
BIT 7 BIT 0
integ_interval_2(7:0)00000000
integ_interval_2(15:0): The LSBs of the integration time for receive AGC 2
Register name: RAGC2_INTEGINVL_MSB Page: 0x1840 Address: 0x1FBIT 15 BIT 8ragc_update_2(7:0)00000000
BIT 7 BIT 0
integ_interval_2(23:16)00000000
ragc_update_2(7:0): Sets the number of receive AGC updates per sync event (0x00 is infinite).
integ_interval_2(23:16): The MSBs of the integration time for receive AGC 2
Submit Documentation Feedback AFE8405 GENERAL CONTROL 117
8.4.4.33 RAGC2_CONFIG0 Register
8.4.4.34 RAGC2_CONFIG1 Register
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Register name: RAGC2_CONFIG0 Page: 0x1860 Address: 0x00BIT 15 BIT 8ragc_sync_delay_2(7:0)00000000
BIT 7 BIT 0
hp_corner_2(2:0) acc_shift_2(4:0)00000000
ragc_sync_delay_2(7:0): The input sync to the receive AGC block is delayed by this value of samples.
hp_corner_2(2:0): This sets the corner frequency of the high-pass filter. Larger values result in highercorner frequencies.
acc_shift_2(4:0): Selects the integrated power measurements result bits to be used as the error lookuptable address. A larger number means fewer samples must be integrated to achieve thesame result.
Register name: RAGC2_CONFIG1 Page: 0x1860 Address: 0x01BIT 15 BIT 8acc_offset_2(5:0) err_shift_2(4:3)00000000
BIT 7 BIT 0
err_shift_2(2:0) delay_adj_2(4:0)00000000
acc_offset_2(5:0): Constant subtracted from the integrated power measurement result before the errorlookup table.
err_shift_2(4:0): Controls the loop gain by left-shifting the error output. Larger values result in highergain..
delay_adj_2(4:0): Sets the delay difference, in samples, between the DVGA outputs and the valueapplied to the sample multiplier.
118 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.4.35 RAGC2_SD_THRESH Register
8.4.4.36 RAGC2_SD_TIMER Register
8.4.4.37 RAGC2_SD_SAMPLES Register
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Register name: RAGC2_SD_THRESH Page: 0x1860 Address: 0x02BIT 15 BIT 8sd_thresh_2(15:8)00000000
BIT 7 BIT 0
sd_thresh_2(7:0)00000000
sd_thresh_2(15:0): This is the threshold used by the signal-detect block to determine if there is signal onthe inputs. The comparison is done to the output of the squarer block, which is a 32-bit word.Because of this, these bits are aligned with bits 24 down to 8 of the 32-bit squared value.
Register name: RAGC2_SD_TIMER Page: 0x1860 Address: 0x03BIT 15 BIT 8sd_timer_2(15:8)00000000
BIT 7 BIT 0
sd_timer_2(7:0)00000000
sd_timer_2(15:0): After the first no-signal sample occurs, this is the amount of samples that control thelength of time to determine the loss-of-signal condition.
Register name: RAGC2_SD_SAMPLES Page: 0x1860 Address: 0x04BIT 15 BIT 8sd_samples_2(15:8)00000000
BIT 7 BIT 0
sd_samples_2(7:0)00000000
sd_samples_2(15:0): Number of samples that must be below the sd_thresh_X threshold within thesd_timer_X timer value for the loss-of-signal condition to occur.
Submit Documentation Feedback AFE8405 GENERAL CONTROL 119
8.4.4.38 RAGC2_CLIP_HITHRESH Register
8.4.4.39 RAGC2_CLIP_LOTHRESH Register
8.4.4.40 RAGC2_CLIP_HITIMER Register
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Register name: RAGC2_CLIP_HITHRESH Page: 0x1860 Address: 0x05BIT 15 BIT 8clip_hi_thresh_2(15:8)00000000
BIT 7 BIT 0
clip_hi_thresh_2(7:0)00000000
clip_hi_thresh_2(15:0): The high threshold value for clip detection
Register name: RAGC2_CLIP_LOTHRESH Page: 0x1860 Address: 0x06BIT 15 BIT 8clip_lo_thresh_2(15:8)00000000
BIT 7 BIT 0
clip_lo_thresh_2(7:0)00000000
clip_lo_thresh_2(15:0): The low threshold value for clip detection
Register name: RAGC2_CLIP_HITIMER Page: 0x1860 Address: 0x07BIT 15 BIT 8clip_hi_timer_2(15:8)00000000
BIT 7 BIT 0
clip_hi_timer_2(7:0)00000000
clip_hi_timer_2(15:0): The high timer value in samples
120 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.4.41 RAGC2_CLIP_LOTIMER Register
8.4.4.42 RAGC2_CLIP_SAMPLES Register
8.4.4.43 RAGC2_CLIP_ERROR Register
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Register name: RAGC2_CLIP_LOTIMER Page: 0x1860 Address: 0x08BIT 15 BIT 8clip_lo_timer_2(15:8)00000000
BIT 7 BIT 0
clip_lo_timer_2(7:0)00000000
clip_lo_timer_2(15:0): The low timer value in samples
Register name: RAGC2_CLIP_SAMPLES Page: 0x1860 Address: 0x09BIT 15 BIT 8clip_hi_samples_2(7:0)00000000
BIT 7 BIT 0
clip_lo_samples_2(7:0)00000000
clip_hi_samples_2(7:0): Number of samples above the high threshold within the clip high time to enablethe clip event
clip_lo_samples_2(7:0): Number of samples below the low threshold within the clip low time to disablethe clip event
Register name: RAGC2_CLIP_ERROR Page: 0x1860 Address: 0x0ABIT 15 BIT 8clip_error_2(15:8)00000000
BIT 7 BIT 0
clip_error_2(7:0)00000000
clip_error_2(15:0): This is the error value that is added into the loop accumulator when a clip is detected.
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8.4.4.44 RAGC3_INTEGINVL_LSB Register
8.4.4.45 RAGC3_INTEGINVL_MSB Register
8.4.4.46 RAGC3_CONFIG0 Register
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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Register name: RAGC3_INTEGINVL_LSB Page: 0x1860 Address: 0x0BBIT 15 BIT 8integ_interval_3(15:8)00000000
BIT 7 BIT 0
integ_interval_3(7:0)00000000
integ_interval_3(15:0): The LSBs of the integration time for receive AGC 3
Register name: RAGC3_INTEGINVL_MSB Page: 0x1860 Address: 0x0CBIT 15 BIT 8ragc_update_3(7:0)00000000
BIT 7 BIT 0
integ_interval_3(23:16)00000000
ragc_update_3(7:0): Sets the number of receive AGC updates per sync event (0x00 is infinite).
integ_interval_3(23:16): The MSBs of the integration time for receive AGC 3
Register name: RAGC3_CONFIG0 Page: 0x1860 Address: 0x0DBIT 15 BIT 8ragc_sync_delay_3(7:0)00000000
BIT 7 BIT 0
hp_corner_3(2:0) acc_shift_3(4:0)00000000
ragc_sync_delay_3(7:0): The input sync to the receive AGC block is delayed by this value of samples.
hp_corner_3(2:0): This sets the corner frequency of the high-pass filter. Larger values result in highercorner frequencies.
acc_shift_3(4:0): Selects the integrated power measurements result bits to be used as the error lookuptable address. A larger number means fewer samples must be integrated to achieve thesame result.
122 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.4.47 RAGC3_CONFIG1 Register
8.4.4.48 RAGC3_SD_THRESH Register
8.4.4.49 RAGC3_SD_TIMER Register
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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Register name: RAGC3_CONFIG1 Page: 0x1860 Address: 0x0EBIT 15 BIT 8acc_offset_3(5:0) err_shift_3(4:3)00000000
BIT 7 BIT 0
err_shift_3(2:0) delay_adj_3(4:0)00000000
acc_offset_3(5:0): Constant subtracted from the integrated power measurement result before the errorlookup table
err_shift_3(4:0): Controls the loop gain by left-shifting the error output. Larger values result in highergain.
delay_adj_3(4:0): Sets the delay difference, in samples, between the DVGA outputs and the valueapplied to the sample multiplier.
Register name: RAGC3_SD_THRESH Page: 0x1860 Address: 0x0FBIT 15 BIT 8sd_thresh_3(15:8)00000000
BIT 7 BIT 0
sd_thresh_3(7:0)00000000
sd_thresh_3(15:0): This is the threshold used by the signal-detect block to determine if there is signal onthe inputs. The comparison is done to the output of the squarer block, which is a 32-bit word.Because of this, these bits are aligned with bits 24 down to 8 of the 32-bit squared value.
Register name: RAGC3_SD_TIMER Page: 0x1860 Address: 0x10BIT 15 BIT 8sd_timer_3(15:8)00000000
BIT 7 BIT 0
sd_timer_3(7:0)00000000
sd_timer_3(15:0): After the first no signal sample occurs, this is the amount of samples that control thelength of time to determine the loss-of-signal condition.
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8.4.4.50 RAGC3_SD_SAMPLES Register
8.4.4.51 RAGC3_CLIP_HITHRESH Register
8.4.4.52 RAGC3_CLIP_LOTHRESH Register
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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Register name: RAGC3_SD_SAMPLES Page: 0x1860 Address: 0x11BIT 15 BIT 8sd_samples_3(15:8)00000000
BIT 7 BIT 0
sd_samples_3(7:0)00000000
sd_samples_3(15:0): Number of samples that must be below the sd_thresh_X threshold within thesd_timer_X timer value for the loss-of-signal condition to occur
Register name: RAGC3_CLIP_HITHRESH Page: 0x1860 Address: 0x12BIT 15 BIT 8clip_hi_thresh_3(15:8)00000000
BIT 7 BIT 0
clip_hi_thresh_3(7:0)00000000
clip_hi_thresh_3(15:0): The high threshold value for clip detection
Register name: RAGC3_CLIP_LOTHRESH Page: 0x1860 Address: 0x13BIT 15 BIT 8clip_lo_thresh_3(15:8)00000000
BIT 7 BIT 0
clip_lo_thresh_3(7:0)00000000
clip_lo_thresh_3(15:0): The low threshold value for clip detection
124 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.4.53 RAGC3_CLIP_HITIMER Register
8.4.4.54 RAGC3_CLIP_LOTIMER Register
8.4.4.55 RAGC3_CLIP_SAMPLES Register
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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Register name: RAGC3_CLIP_HITIMER Page: 0x1860 Address: 0x14BIT 15 BIT 8clip_hi_timer_3(15:8)00000000
BIT 7 BIT 0
clip_hi_timer_3(7:0)00000000
clip_hi_timer_3(15:0): The clip high timer value in samples
Register name: RAGC3_CLIP_LOTIMER Page: 0x1860 Address: 0x15BIT 15 BIT 8clip_lo_timer_3(15:8)00000000
BIT 7 BIT 0
clip_lo_timer_3(7:0)00000000
clip_lo_timer_3(15:0): The clip low timer value in samples
Register name: RAGC3_CLIP_SAMPLES Page: 0x1860 Address: 0x16BIT 15 BIT 8clip_hi_samples_3(7:0)00000000
BIT 7 BIT 0
clip_lo_samples_3(7:0)00000000
clip_hi_samples_3(7:0): Number of samples above the high threshold within the clip high time to enablea clip event
clip_lo_samples_3(7:0): Number of samples below the low threshold within the clip low time to disable aclip event
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8.4.4.56 RAGC3_CLIP_ERROR Register
8.4.4.57 RAGC0_ACCUM_LSB Register
8.4.4.58 RAGC0_ACCUM_MSB Register
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Register name: RAGC3_CLIP_ERROR Page: 0x1860 Address: 0x17BIT 15 BIT 8clip_error_3(15:8)00000000
BIT 7 BIT 0
clip_error_3(7:0)00000000
clip_error_3(15:0): Error value that is added into the loop accumulator when a clip is detected.
Register name: RAGC0_ACCUM_LSB Page: 0x1860 Address: 0x18 Read-onlyBIT 15 BIT 8ragc0_accum(15:8)00000000
BIT 7 BIT 0
ragc0_accum(7:0)00000000
ragc0_accum(15:0): Lower 16 bits of the ragc0 error accumulator
Register name: RAGC0_ACCUM_MSB Page: 0x1860 Address: 0x19 Read-onlyBIT 15 BIT 8ragc0_accum(31:24)00000000
BIT 7 BIT 0
ragc0_accum(23:16)00000000
ragc0_accum(31:16): Upper 16 bits of the ragc0 error accumulator
126 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.4.59 RAGC1_ACCUM_LSB Register
8.4.4.60 RAGC1_ACCUM_MSB Register
8.4.4.61 RAGC2_ACCUM_LSB Register
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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Register name: RAGC1_ACCUM_LSB Page: 0x1860 Address: 0x1A Read-onlyBIT 15 BIT 8ragc1_accum(15:8)00000000
BIT 7 BIT 0
ragc1_accum(7:0)00000000
ragc1_accum(15:0): Lower 16 bits of the ragc1 error accumulator
Register name: RAGC1_ACCUM_MSB Page: 0x1860 Address: 0x1B Read-onlyBIT 15 BIT 8ragc1_accum(31:24)00000000
BIT 7 BIT 0
ragc1_accum(23:16)00000000
ragc1_accum(31:16): Upper 16 bits of the ragc1 error accumulator
Register name: RAGC2_ACCUM_LSB Page: 0x1860 Address: 0x1C Read-onlyBIT 15 BIT 8ragc2_accum(15:8)00000000
BIT 7 BIT 0
ragc2_accum(7:0)00000000
ragc2_accum(15:0): Lower 16 bits of the ragc2 error accumulator
Submit Documentation Feedback AFE8405 GENERAL CONTROL 127
8.4.4.62 RAGC2_ACCUM_MSB Register
8.4.4.63 RAGC3_ACCUM_LSB Register
8.4.4.64 RAGC3_ACCUM_MSB Register
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Register name: RAGC2_ACCUM_MSB Page: 0x1860 Address: 0x1D Read-onlyBIT 15 BIT 8ragc2_accum(31:24)00000000
BIT 7 BIT 0
ragc2_accum(23:16)00000000
ragc2_accum(31:16): Upper 16 bits of the ragc2 error accumulator
Register name: RAGC3_ACCUM_LSB Page: 0x1860 Address: 0x1E Read-onlyBIT 15 BIT 8ragc3_accum(15:8)00000000
BIT 7 BIT 0
ragc3_accum(7:0)00000000
ragc3_accum(15:0): Lower 16 bits of the ragc3 error accumulator
Register name: RAGC3_ACCUM_MSB Page: 0x1860 Address: 0x1F Read-onlyBIT 15 BIT 8ragc3_accum(31:24)00000000
BIT 7 BIT 0
ragc3_accum(23:16)00000000
ragc3_accum(31:16): Upper 16 bits of the ragc3 error accumulator
AFE8405 GENERAL CONTROL128 Submit Documentation Feedback
8.4.5 DDC Channel Controls
8.4.5.1 FIR_MODE Register
8.4.5.2 FIR_GAIN Register
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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Register name: FIR_MODE Page: 0x0%00 Address: 0x00where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8cdma_mode Unused Unused crastarttap_pfir(4:0)00000000
BIT 7 BIT 0
crastarttap_cfir(4:0) Unused Unused Unused00000000
cdma_mode: When asserted, the DDC block is in CDMA mode (2 streams per DDC block).
crastarttap_pfir: These bits define the number of taps that PFIR uses for the filtering.
crastarttap_cfir: These bits define the number of taps that CFIR uses for the filtering.
Formulas for the number of taps, in the different FIRs, using the crastarttap word.DDC PFIR: 4 ×(crastarttap_pfir + 1)DDC PFIR long mode: 8 ×(crastarttap_pfir + 1)DDC CFIR: 2 ×(crastarttap_cfir + 1)
Register name: FIR_GAIN Page: 0x0%00 Address: 0x01where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8pfir_gain(2:0) Unused Unused Unused Unused Unused00000000
BIT 7 BIT 0
Unused Unused Unused Unused Unused Unused Unused Unused00000000
pfir_gain(2:0): PFIR gain, from 2e–19 to 2e–12 for the receive PFIR. (000 = 2e–19 and 111 = 2e–12)
cfir_gain: When 0, then the gain of the CFIR is 2e-19; when set to 1, the gain is 2e-18.
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8.4.5.3 SQR_SUM Register
8.4.5.4 STRT_INTRVL Register
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Register name: SQR_SUM Page: 0x0%00 Address: 0x02where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8pmeter_sqr_sum_ddc(15:8)00000000
BIT 7 BIT 0
pmeter_sqr_sum_ddc(7:0)00000000
pmeter_sqr_sum_ddc(15:0): The sqr_sum register is the number of four-sample sets to accumulate fora power measurement. In CDMA mode, one sample set is the I & Q of the signal anddiversity. Ia & Qa (signal) are each squared and accumulated and Ib & Qb (diversity) aresquared and accumulated. In UMTS mode, each I and Q pair is squared and accumulated.Four samples are equal to one SQR_SUM count. The count is initiated when sync isasserted or when the interval start time is reached. When the SQR_NUM number is reached,the accumulated powers are made available for MPU access and an interrupt is generated.
Register name: STRT_INTRVL Page: 0x0%00 Address: 0x03where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8pmeter_sync_delay_ddc(7:0)00000000
BIT 7 BIT 0
pmeter_interval_ddc(7:0)00000000
pmeter_sync_delay_ddc(7:0): The delay from selected sync source to when the power calculationstarts. The actual value is sync_delay + 1.
pmeter_interval_ddc(7:0): The start interval timer is the interval over which the SQR_SUM is restartedand must be greater than the SQR_SUM. The actual interval is interval +1, and must begreater than the sqr_sum interval. The interval start counter and RMS power accumulationis started at the sync pulse after the programmed delay and every time the interval counterreaches its limit. This value is in 1024-sample units.
130 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.5.5 CIC_MODE1 Register
8.4.5.6 CIC_MODE2 Register
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Register name: CIC_MODE1 Page: 0x0%00 Address: 0x04where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8cic_scale_a(4:0) cic_scale_b(4:2)00000000
BIT 7 BIT 0
cic_scale_b(1:0) cic_gain_ ddc cic_decim(4:0)00000000
cic_scale_a(4:0): This sets the gain shift at the output of the A channel CIC. 0x00 is no shift; eachincrement by 1 increases the signal amplitude by 2X.
cic_scale_b(4:0): This sets the gain shift at the output of the B channel CIC. 0x00 is no shift; eachincrement by 1 increases the signal amplitude by 2X.
cic_gain_ddc: Adds a fixed gain of 12 dB at the CIC output when asserted.
cic_decim(4:0): Sets the CIC decimation rate, where decimation is cic_decim + 1.
Register name: CIC_MODE2 Page: 0x0%00 Address: 0x05where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8cic_m2_ena_a(5:0) cic_m2_ena_b(5:4)00000000
BIT 7 BIT 0
cic_m2_ena_b(3:0) Unused Unused Unused Unused00000000
cic_m2_ena_a(5:0): Programs the A channel CIC fir sections M value to 2 when set, 1 when cleared.cic_m2_ena_a(0) controls the M value for the first comb section and cic_m2_ena_a(5)controls the M value for the last comb section.
cic_m2_ena_b(5:0): Programs the B channel CIC fir sections M value to 2 when set, 1 when cleared.cic_m2_ena_b(0) controls the M value for the first comb section and cic_m2_ena_b(5)controls the M value for the last comb section.
Submit Documentation Feedback AFE8405 GENERAL CONTROL 131
8.4.5.7 TADJC Register
8.4.5.8 TADJF Register
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Register name: TADJC Page: 0x0%00 Address: 0x06 Double buffered, requires sync for loadingwhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8Unused Unused Unused tadj_offset_coarse_a(2:0) Unused Unused00000000
BIT 7 BIT 0
Unused tadj_offset_coarse_b(2:0) Unused Unused Unused Unused00000000
tadj_offset_coarse_a(2:0): This is the coarse time adjustment offset and acts as an offset from the writeaddress in the delay RAM. This value affects the A-data in the path if CDMA mode is beingused. Each LSB is one more offset between input to the caurse delay block and the output ofthe coarse block.
tadj_offset_coarse_b(2:0): Affects the B-channel in CDMA, just as tadj_offset_coarse_a(2:0) affects theA-channel.
Register name: TADJF Page: 0x0%00 Address: 0x07 Double buffered, requires sync for loadingwhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8tadj_offset_fine_a(2:0) tadj_offset_fine_b(2:0) tadj_interp(2:1)00000000
BIT 7 BIT 0
tadj_interp(0) Unused Unused Unused Unused Unused Unused Unused00000000
tadj_offset_fine_a(2:0): This is the fine-adjust (zero stuff offset) value. It adjusts the time delay at therxclk rate. This value affects the A-channel data in the path if CDMA mode is being used.
tadj_offset_fine_b(2:0): Same as tadj_offset_fine_a(2:0) except this value affects the B-channel data inCDMA mode.
tadj_interp(2:0): This is the interpolation (zero stuff) value for the fine time adjust block. Interpolation canbe from 1 to 8 (tadj_interp + 1). This value affects the A and B data in the path if CDMAmode is being used.
132 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.5.9 PHASEADD0A Register
8.4.5.10 PHASEADD1A Register
8.4.5.11 PHASEADD0B Register
AFE840514-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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Register name: PHASEADD0A Page: 0x0%00 Address: 0x08 Double buffered, requires sync for loadingwhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8phase_add_a(15:8)00000000
BIT 7 BIT 0
phase_add_a(7:0)00000000
phase_add_a(15:0) This 32-bit word is used to control the frequency of the NCO. This value is added tothe frequency accumulator every clock cycle (UMTS mode and Main channel in CDMAmode).
Register name: PHASEADD1A Page: 0x0%00 Address: 0x09 Double buffered, requires sync for loadingwhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8phase_add_a(31:24)00000000
BIT 7 BIT 0
phase_add_a(23:16)00000000
phase_add_a(31:16): This 32-bit word is used to control the frequency of the NCO. This value is addedto the frequency accumulator every clock cycle (UMTS mode and A channel in CDMAmode).
Register name: PHASEADD0 Page: 0x0%00 Address: 0x0A Double buffered, requires sync for loadingwhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8phase_add_b(15:8)00000000
BIT 7 BIT 0
phase_add_b(7:0)00000000
phase_add_b(15:0): This 32-bit word is used to control the frequency of the NCO. This value is added tothe frequency accumulator every clock cycle (B channel in CDMA mode).
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8.4.5.12 PHASEADD1B Register
8.4.5.13 PHASE_OFFSETA Register
8.4.5.14 PHASE_OFFSETB Register
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Register name: PHASEADD1B Page: 0x0%00 Address: 0x0B Double buffered, requires sync for loadingwhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8phase_add_b(31:24)00000000
BIT 7 BIT 0
phase_add_b(23:16)00000000
phase_add_b(31:16): This 32-bit word is used to control the frequency of the NCO. This value is addedto the frequency accumulator every clock cycle (B channel in CDMA mode).
Register name: Page: 0x0%00 Address: 0x0C Double buffered, requires sync for loadingPHASE_OFFSETA where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8phase_offset_a(15:8)00000000
BIT 7 BIT 0
phase_offset_a(7:0)00000000
phase_offset_a(15:0): This is the fixed phase offset added to the output of the frequency accumulator forsinusoid generation in the NCO. (UMTS mode and A channel in CDMA mode).
Register name: Page: 0x0%00 Address: 0x0D Double buffered, requires sync for loadingPHASE_OFFSETB where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8phase_offset_b(15:8)00000000
BIT 7 BIT 0
phase_offset_b(7:0)00000000
phase_offset_b(15:0): This is the fixed phase offset added to the output of the frequency accumulator forsinusoid generation in the NCO. (B channel in CDMA mode)
134 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.5.15 CONFIG1 Register
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Register name: CONFIG1 Page: 0x0%00 Address: 0x0Ewhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8dither_ena dither_mask(1:0) pmeter_ sync_ ddc_ena muxed _data mixer_gain mpu_ram_readdisable00000000
BIT 7 BIT 0
Unused Unused Unused Unused Unused zero_ qsample mux_pos mux_factor00000000
dither_ena: This bit controls whether dither is turned on (1) or off (0).
dither_mask(1): This bit controls the MASKing of the dither word MSB. (1 = MASKed, 0 = used in ditherword).
dither_mask(0): This bit controls the MASKing of the dither word MSB-1. (1 = MASKed, 0 = used indither word).
pmeter_sync_disable: Turns off the sync to the channel power meter. This can be used to turn off syncsindividually to a channel power meter while still having syncs available to other powermeters.
ddc_ena: When set, this turns on the DDC. When cleared, the clocks to this block are turned off. Forthe DDC blocks used as the second half in the long PFIR configuration, this bit should becleared.
muxed_data: When asserted the DDC multiplexer block assumes that multiple channels are multiplexedtogether on one input data stream. For factory use only.For a 2 ×multiplexed stream it would look like: Sa0, Sb0, Sa1, Sb1, Sa2, Sb2 …. etc...
mixer_gain: Adds a fixed 6 dB of gain to the mixer output(before round and limiting) when asserted.
mpu_ram_read: (TESTING PURPOSES) Allows the coefficient RAMs in the PFIR/CFIR to be read outthe MPU data bus. Unfortunately, this cannot be done during normal operation and must bedone when the state of the output data is not important. THIS BIT MUST BE SET ONLYDURING THE MPU READ OPERATION AND MUST BE CLEARED FOR NORMAL DDCOPERATION.
zero_qsample: When asserted, the Q sample into the mixer is held to zero. For UMTS mode at any inputrate, and CDMA mode with input rates of rxclk/2 or lower, this bit must be set for real-onlyinput data mode (also for multiplexed input data stream modes). For real-only inputs at thefull rxclk rate in CDMA mode, the remix_only bit must be set in the DDCCONFIG1 register.
mux_pos: These bits set the position for selection in the multiplexed data stream. This value must beless than or equal to the mux_factor bits.
mux_factor: These two bits set the number of channels in the data stream. 0 = one stream, 1 = twostreams. The ch_rate_sel bits for the DDC should be programmed to rxclk/2 for thetwo-stream mode.
Submit Documentation Feedback AFE8405 GENERAL CONTROL 135
8.4.5.16 CONFIG2 Register
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Register name: CONFIG2 Page: 0x0%00 Address: 0x0Fwhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8Unused Unused Unused Unused Unused Unused Unused Unused00000000
BIT 7 BIT 0
Unused Unused ddc_tst_sel(5:0)00000000
ddc_tst_sel(5:0): This is the selection of which signal comes out the test bus. When a constant 0 isselected, this also reduces power by preventing the data at the input of the tst_blk fromchanging. It does not stop the clock, however. The 36 bits for the test bus are routed to therxin_c, rxin_d, dvga_c and dvga_d pins on the chip.
SYNC on dvga_c(0) Data selected for output (36 bits total)ddc_tst_sel(5:0)AFLAG on dvga_d(5) rxin_d(15:0), dvga_c(3:2), rxin_c(15:0), dvga_c(5:4)
N 00 0000 constant 0Y 00 0001 pfir output – (35:18) I and (17:0) QY 00 0010 cfir output – (35:18) I and (17:0) QN 00 0011 tadj A output – (35:18) I and (17:0) QN 00 0100 tadj B output – (35:18) I and (17:0) QN 00 0101 nco SINE output – (35:20) zeroed (19:0) SINEN 00 0110 nco COSINE output – (35:20) zeroed (19:0) COSINEN 00 0111 cic output – (35:18) I and (17:0) QY 00 1000 agc output – (35:11) I and (10:0) Q {full 25b I result and upper 11b Q result}N 00 1001 mix A output – (35:18) i ×cos – q ×sin and (17:0) i ×sin + q ×cosN 00 1010 mix B output – (35:18) i ×cos – q ×sin and (17:0) i ×sin + q ×cosN 00 1011 DDC MUX A output (35:18) I and (17:0) QN 00 1100 DDC MUX B output (35:18) I and (17:0) Q
AFE8405 GENERAL CONTROL136 Submit Documentation Feedback
8.4.5.17 AGC_CONFIG1 Register
8.4.5.18 AGC_CONFIG2 Register
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Register name: AGC_CONFIG1 Page: 0x0%00 Address: 0x10where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8agc_dblw(3:0) agc_dabv(3:0)00000000
BIT 7 BIT 0
agc_dzro(3:0) agc_dsat(3:0)00000000
agc_dblw(3:0): The value to shift the gain that is then added to the accumulator when the value of theincoming data * current gain value is below the threshold.
agc_dabv(3:0): The value to shift the gain that is then subtracted from the accumulator when the value ofthe incoming data * the current gain value is above the threshold.
agc_dzro(3:0): The value to shift the gain that is then added to the accumulator when the value of theincoming data * current gain value is consistently equal to zero (usually a smaller numberthan agc_dblw).
agc_dsat(3:0): The value to shift the gain that is then subtracted form the accumulator when the value ofthe incoming data * the current gain value is consistently equal to maximum (saturation).
NOTE:The larger the number in the foregoing words, the smaller the step size. The preceding valuescontrol the AGC gain shifting (range is from 3 to 18).
Register name: AGC_CONFIG2 Page: 0x0%00 Address: 0x11where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8zero_msk(3:0) agc_rnd(3:0)00000000
BIT 7 BIT 0
agc_thresh(7:0)00000000
zero_msk(3:0): Masks the lower 4 bits of the magnitude of the input signal so that they are counted aszeros.
agc_rnd(3:0): Determines where to round the output of the AGC; the number of bits output is (18 –agc_rnd). For example, 0000 is 18 bits.
agc_thresh(7:0): Threshold for (input ×gain) comparison. This value is compared to the magnitude of theupper 8 bits of the agc output.
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8.4.5.19 AGC_CONFIG3 Register
8.4.5.20 AGC_GAINMSB Register
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Register name: AGC_CONFIG3 Page: 0x0%00 Address: 0x12where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8Unused Unused Unused agc_ freeze agc_max_cnt(3:0)00000000
BIT 7 BIT 0
Unused Unused Unused agc_ clear agc_zero_cnt(3:0)00000000
agc_freeze: Freezes the agc when set. This should be asserted when the AGC algorithm is bypassed orheld constant.
agc_max_cnt(3:0): When the agc_output (input ×gain) is at full scale for this number of samples, thenthe gain shift value is changed to agc_dsat.
agc_clear: Clears the AGC accumulator when set. Assert this when the AGC is in bypass mode.
agc_zero_cnt(3:0): when the agc_output (input ×gain) is zero value for this number of samples, then thegain shift value is changed to agc_dzro.
Register name: Page: 0x0%00 Address: 0x13 Double buffered, requires sync for loadingAGC_GAINMSB where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8agc_gaina(23:16)00000000
BIT 7 BIT 0
agc_gainb(23:16)00000000
agc_gaina(23:16): MSBs of the agc_gaina word.
agc_gainb(23:16): MSBs of the agc_gainb word.
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8.4.5.21 AGC_GAINA Register
8.4.5.22 AGC_GAINB Register
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Register name: AGC_GAINA Page: 0x0%00 Address: 0x14 Double buffered, requires sync for loadingwhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8agc_gaina(15:8)00000000
BIT 7 BIT 0
agc_gaina(7:0)00000000
agc_gaina(15:0): This is the lower 16 bits of the total 24 bits of programmable gain. The gain value isalways positive with the upper 12 bits being the integer value and the lower 12 bits being thefractional. This gain value is used for all UMTS operations and for A-channel data when inCDMA mode. A 24-bit value of 0000 000 0001.0000 0000 0000 is unity gain.
Register name: AGC_GAINB Page: 0x0%00 Address: 0x15 Double buffered, requires sync for loadingwhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8agc_gainb(15:8)00000000
BIT 7 BIT 0
agc_gainb(7:0)00000000
agc_gainb(15:0): This is the lower 16 of the total of 24 bits of programmable gain. The gain value isalways positive with the upper 12 bits being the integer value and the lower 12 bits being thefractional. This gain value is used for B-channel data when in CDMA. A 24-bit value of0000 0000 0001.0000 0000 0000 is unity gain.
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8.4.5.23 AGC_AMAX Register
8.4.5.24 AGC_AMIN Register
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Register name: AGC_AMAX Page: 0x0%00 Address: 0x16where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8agc_amax(15:8)00000000
BIT 7 BIT 0
agc_amax(7:0)00000000
agc_amax(15:0): This is the maximum gaina or gainb can be adjusted up. The value programmed is apositive value that is used to generate the most-positive AGC gain adjust. For example, if512 is programmed, the maximum gain is the programmed gain (AGC_GAINA/B) + 512.
Register name: AGC_AMIN Page: 0x0%00 Address: 0x17where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8agc_amin(15:8)00000000
BIT 7 BIT 0
agc_amin(7:0)00000000
agc_amin(15:0): This is the minimum gaina or gainb can be adjusted down. The value programmed is apositive value that is inverted internally to generate the most-negative AGC gain adjust. Forexample, if 512 is programmed, the minimum gain is the programmed gain (AGC_GAINA/B)– 512.
140 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.5.25 PSER_CONFIG1 Register
8.4.5.26 PSER_CONFIG2 Register
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Register name: PSER_CONFIG1 Page: 0x0%00 Address: 0x18where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8Unused pser_recv_fsinvl(6:0)00000000
BIT 7 BIT 0
Unused Unused Unused pser_recv_bits(4:0)00000000
pser_recv_fsinvl(6:0): Receive serial interface frame sync interval in bit clocks.
pser_recv_bits(4:0): Number of output bits per sample – 1; for 18 bits, this is set to 1 0001.
Register name: PSER_CONFIG2 Page: 0x0%00 Address: 0x19where:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8pser_recv_clkdiv(3:0) Unused Unused Unused Unused00000000
BIT 7 BIT 0
pser_recv_8pin pser_recv_alt Unused Unused Unused Unused pser_recv_fsdel(1:0)00000000
pser_recv_clkdiv(3:0): Receive serial interface clock divider rate – 1; 0 is full-rate and 15 divides theclock by 16. For example, to run the receive serial interface at 1/4 the AFE8405 clock, setpser_recv_clkdiv(3:0) = 0011.
pser_recv_8pin: When set, four pins are used for I and four pins for Q in UMTS mode. When cleared,two pins are used for I and two pins for Q. This is used in combination with the pser_recv_altbit. When this bit is set, it would be set in two adjacent DDC channels; one would also setthe pser_recv_alt bit in the adjacent DDC. This causes the I channel to be serialized on fourpins and the Q channel to be serialized on the four adjacent-channel pins.
pser_recv_alt: When set, this channel's receive serial interface outputs the Q data from the adjacentDDC channel.
pser_recv_fsdel(1:0): Delay between the receive frame sync output and the MSB of serial data {3, 2, 1,0}. This number is in serial output bit times, not rxclk periods.
Submit Documentation Feedback AFE8405 GENERAL CONTROL 141
8.4.5.27 DDCCONFIG1 Register
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Register name: DDCCONFIG1 Page: 0x0%00 Address: 0x1Awhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8agc_rnd_ddcmux_sel_a(3:0) gain_mon ch_rate_sel(1:0)disable00000000
BIT 7 BIT 0
ddcmux_sel_b(3:0) remix_only cic_ bypass double_tap(1:0)00000000
ddcmux_sel_X(3:0): Controls which samples go to the mixer for I/Q. Because in CDMA there are twostreams, an A and B stream, two multiplex select values are used.
Select Value I data from X input
(1)
Q data from X input
(1)
0000 RXINA RXINA0001 RXINB RXINB0010 RXINC RXINC0011 RXIND RXIND0100 RXINA RXINB0101 RXINA RXINC0110 RXINA RXIND0111 RXINB RXINA1000 RXINB RXINC1001 RXINB RXIND1010 RXINC RXINA1011 RXINC RXINB1100 RXINC RXIND1101 RXIND RXINA1110 RXIND RXINB1111 RXIND RXINC
(1) RXINA = internal A-side ADC, RXINB not used, RXINC = external input C, RXIND = external input Dagc_rnd_disable: When set, the agc_rnd bits have no effect. The whole 29 bits are used in the roundingand the round bit is bit 4.
gain_mon: Combines the gain with the I/Q output signals when asserted.
OUTPUT Bits(17:10) Bits(9:4) Bits(3:2) Bits(1:0)
I Gained I value Gain(18:11) 00Q Gained Q value Gain(10:5) Shift status(1:0) 00
ch_rate_sel(1:0): Sets the DDC channel input data rate. The value set here should match the value inthe receive input interface rate-select bits (rate_sel).
ch_rate_sel Input data rate
00 rxclk01 rxclk/210 rxclk/411 rxclk/8
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When muxed_data is set (Factory Use Only), rate_sel should be set to rxclk 00 and ch_rate_sel should beset to rxclk/2 01.
remix_only: Assert this when real only, full rxclk rate input data is used in CDMA mode. The signal on theQ bus selected by the ddcmux_sel_X(3:0) bits above is ignored (functions as if the Q data is0).
cic_bypass: Factory Use Only. If asserted, then the data from the rxin_a(15:0) and rxin_b(15:0) are feddirectly into the cfir input as I and Q respectively. rxin_a(0) also functions as the sync_cfirsignal and should rise at the beginning of input data.
ONLY DDC0, DDC2, DDC4 and DDC6 can be the UMTS double-tap (64- to 128-tap) PFIR mode.DDC1, DDC3, DDC5 and DDC7 PFIRs are used to lengthen the DDC0, DDC2, DDC4 and DDC6PFIRs.
double_tap(1): When set, the DDC is in double-length PFIR mode, which sends the data out of the lastPFIR sample RAM in this DDC (DDC0, DDC2, DDC4, DDC6) to the adjacent secondaryDDC (DDC1, DDC3, DDC5, DDC7) PFIR forming a 128-tap delay line. Output data receivedfrom the adjacent secondary DDC PFIR summer is added into the main DDC PFIR sum toform the final output.
double_tap(0): When set, the PFIR input comes from the adjacent (main) PFIR. When cleared, PFIRinput is from the CFIR connected directly to this PFIR. Only valid in DDC1, DDC3, DDC5and DDC7. The ddc_ena bit in the CONFIG1 register should be cleared for DDC1,DDC3, DDC5 and DDC7 when double_tap(0) is set.
NOTE: To put 2 DDCs into 128 tap mode:Program DDC0/DDC2/DDC4/DDC6 double_tap(1:0) to 10 and ddc_ena to 1.Program DDC1/DDC3/DDC5/DDC7 double_tap(1:0) to 01 and ddc_ena to 0.
Submit Documentation Feedback AFE8405 GENERAL CONTROL 143
8.4.5.28 SYNC_0 Register
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Register name: SYNC_0 Page: 0x0%00 Address: 0x1Bwhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8Unused ssel_cic(2:0) Unused ssel_pmeter(2:0)00000000
BIT 7 BIT 0
Unused ssel_agc_freeze(2:0) Unused ssel_serial(2:0)01100000
ssel_cic(2:0): Selects the sync source for the DDC CIC filter, thus setting the decimation moment
ssel_pmeter(2:0): Selects the sync source for the channel power meter
ssel_agc_freeze(2:0): Selects the sync that is used to hold the AGC in freeze mode. With thisfunctionality the user can program the AGC freeze control to look at the state of an inputsync, or the one-shots. It defaults to being off or not looking at any syncs and not driving thefreeze control. This way, on startup, the chip looks at the MPU register bit for AGC freezingand not the syncs.
ssel_serial(2:0): Selects the sync source for the DDC serial interface state machines.
Sync sources are contained in this and many of the following registers. For all sync source selections:
ssel_XXXX(2:0) Selected sync source for DDC
000 rxsyncA001 rxsyncB010 rxsyncC011 rxsyncD100 DDC sync counter101 one shot (register write triggered)110 always 0111 always 1
AFE8405 GENERAL CONTROL144 Submit Documentation Feedback
8.4.5.29 SYNC_1 Register
8.4.5.30 SYNC_2 Register
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Register name: SYNC_1 Page: 0x0%00 Address: 0x1Cwhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8Unused ssel_tadj_fine(2:0) Unused ssel_tadj_reg(2:0)00000000
BIT 7 BIT 0
Unused ssel_gain(2:0) Unused ssel_ddc_agc(2:0)00000000
ssel_tadj_fine(2:0): Selects the sync source for the fine time adjust zero stuff moment.
ssel_tadj_reg(2:0): Selects the sync source for the fine and coarse time adjust register updates.
ssel_gain(2:0): Selects the sync source for the DDC AGC gain register.
ssel_ddc_agc(2:0): Selects the sync source to initialize the AGC, primarily for test purposes.
Register name: SYNC_2 Page: 0x0%00 Address: 0x1Dwhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8Unused ssel_nco(2:0) Unused ssel_dither(2:0)00000000
BIT 7 BIT 0
Unused ssel_freq(2:0) Unused ssel_phase(2:0)00000000
ssel_nco: Selects the sync source for the NCO accumulator reset.
ssel_dither: Selects the sync source for the NCO phase dither generator reset.
ssel_freq: Selects the sync source for the NCO frequency register.
ssel_phase: Selects the sync source for the NCO phase offset register.
Submit Documentation Feedback AFE8405 GENERAL CONTROL 145
8.4.5.31 DDC_CHK_SUM Register
8.4.5.32 PMETER_RESULT_A_LSB Register
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Register name: DDC_CHK_SUM Page: 0x0%20 Address: 0x00 Read-onlywhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8ddc_chk_sum(15:0)00000000
BIT 7 BIT 0
ddc_chk_sum(7:0)00000000
ddc_chk_sum: The DDC self test checksum value
Register name: PMETER_RESULT_A_LSB Page: 0x0%20 Address: 0x01 Read-onlywhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8pmeter_result_a(15:8)00000000
BIT 7 BIT 0
pmeter_result_a(7:0)00000000
pmeter_result_a(15:0): Lower 16 bits of the UMTS-mode or CDMA-mode A-channel powermeasurement.
146 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.5.33 PMETER_RESULT_A_MID Register
8.4.5.34 PMETER_RESULT_A_MSB Register
8.4.5.35 PMETER_RESULT_B_LSB Register
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Register name: PMETER_RESULT_A_MID Page: 0x0%20 Address: 0x02 Read-onlywhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8pmeter_result_a(31:24)00000000
BIT 7 BIT 0
pmeter_result_a(23:16)00000000
pmeter_result_a(31:16): Mid 16 bits of the UMTS-mode or CDMA-mode A-channel power measurement.
Register name: PMETER_RESULT_A_MSB Page: 0x0%20 Address: 0x03 Read-onlywhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8pmeter_result_a(47:40)00000000
BIT 7 BIT 0
pmeter_result_a(39:32)00000000
pmeter_result_a(47:32): Upper mid 16 bits of the UMTS-mode or CDMA-mode A-channel powermeasurement.
Register name: PMETER_RESULT_B_LSB Page: 0x0%20 Address: 0x04 Read-onlywhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8pmeter_result_b(15:8)00000000
BIT 7 BIT 0
pmeter_result_b(7:0)00000000
pmeter_result_b(15:0): Lower 16 bits of the CDMA-mode B-channel power measurement
Submit Documentation Feedback AFE8405 GENERAL CONTROL 147
8.4.5.36 PMETER_RESULT_B_MID Register
8.4.5.37 PMETER_RESULT_B_MSB Register
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Register name: PMETER_RESULT_B_MID Page: 0x0%20 Address: 0x05 Read-onlywhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8pmeter_result_b(31:24)00000000
BIT 7 BIT 0
pmeter_result_b(23:16)00000000
pmeter_result_b(31:16): Mid 16 bits of the CDMA-mode B-channel power measurement.
Register name: PMETER_RESULT_B_MSB Page: 0x0%20 Address: 0x06 Read-onlywhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8pmeter_result_b(47:40)00000000
BIT 7 BIT 0
pmeter_result_b(39:32)00000000
pmeter_result_b(47:32): Upper mid 16 bits of the CDMA-mode B-channel power measurement.
148 AFE8405 GENERAL CONTROL Submit Documentation Feedback
8.4.5.38 PMETER_RESULT_AB_UMSB Register
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Register name: PMETER_RESULT_AB_UMSB Page: 0x0%20 Address: 0x07 Read-onlywhere:
% = 2 ×(DDC channel #) + 1BIT 15 BIT 8pmeter_result_a(54:48)00000000
BIT 7 BIT 0
pmeter_result_b(54:48)00000000
pmeter_result_a(54:48): Most-significant 7 bits of the 55-bit UMTS- or CDMA-mode A-channel powermeasurement. Bits 15–9 are used, bit 8 is not used.
pmeter_result_b(54:48): Most-significant 7 bits of the 55-bit CDMA-mode B-channel powermeasurement. Bits 7–1 are used, bit 0 is not used.
Submit Documentation Feedback AFE8405 GENERAL CONTROL 149
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
AFE8405IZDQ ACTIVE BGA ZDQ 484 60 Pb-Free
(RoHS) SNAGCU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DLP® Products www.dlp.com Communications and www.ti.com/communications
Telecom
DSP dsp.ti.com Computers and www.ti.com/computers
Peripherals
Clocks and Timers www.ti.com/clocks Consumer Electronics www.ti.com/consumer-apps
Interface interface.ti.com Energy www.ti.com/energy
Logic logic.ti.com Industrial www.ti.com/industrial
Power Mgmt power.ti.com Medical www.ti.com/medical
Microcontrollers microcontroller.ti.com Security www.ti.com/security
RFID www.ti-rfid.com Space, Avionics & www.ti.com/space-avionics-defense
Defense
RF/IF and ZigBee® Solutions www.ti.com/lprf Video and Imaging www.ti.com/video
Wireless www.ti.com/wireless-apps
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