SST39VF088-90-4I-EK - Silicon Storage Technology

OBSOLETE

EOL Data Sheet

S71227-05-EOL 2/07

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

8 Mbit (x8) Multi-Purpose Flash

SST39VF088

FEATURES:

• Organized as 1M x8

• Single Voltage Read and Write Operations

– 2.7-3.6V

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption (typical values at 5 MHz)

– Active Current: 12 mA (typical)

– Standby Current: 4 µA (typical)

• Sector-Erase Capability

– Uniform 4 KByte sectors

• Block-Erase Capability

– Uniform 64 KByte blocks

• Fast Read Access Time:

– 70 and 90 ns

• Latched Address and Data

• Fast Erase and Byte-Program

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time: 15 seconds (typical)

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 48-lead TSOP (12mm x 20mm)

PRODUCT DESCRIPTION

The SST39VF088 device is a 1M x8 CMOS Multi-Purpose

Flash (MPF) manufactured with SST’s proprietary, high

performance CMOS SuperFlash technology. The split-gate

cell design and thick-oxide tunneling injector attain better

reliability and manufacturability compared with alternate

approaches. The SST39VF088 writes (Program or Erase)

with a 2.7-3.6V power supply. It conforms to JEDEC stan-

dard pinouts for x8 memories.

Featuring high performance Byte-Program, the

SST39VF088 device provides a typical Byte-Program time

of 14 µsec. The devices use Toggle Bit or Data# Polling to

indicate the completion of Program operation. To protect

against inadvertent write, they have on-chip hardware and

Software Data Protection schemes. Designed, manufac-

tured, and tested for a wide spectrum of applications, these

devices are offered with a guaranteed endurance of 10,000

cycles. Data retention is rated at greater than 100 years.

The SST39VF088 device is suited for applications that

require convenient and economical updating of program,

configuration, or data memory. For all system applications,

they significantly improve performance and reliability, while

lowering power consumption. They inherently use less

energy during Erase and Program than alternative flash

technologies. The total energy consumed is a function of

the applied voltage, current, and time of application. Since

for any given voltage range, the SuperFlash technology

uses less current to program and has a shorter erase time,

the total energy consumed during any Erase or Program

operation is less than alternative flash technologies. They

also improve flexibility while lowering the cost for program,

data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles.

To meet high density, surface mount requirements, the

SST39VF088 is offered in 48-lead TSOP packaging. See

Figure 1 for pin assignments.

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39VF088

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asserting WE# low while keeping CE#

low. The address bus is latched on the falling edge of WE#

or CE#, whichever occurs last. The data bus is latched on

the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST39VF088 is controlled by

CE# and OE#, both have to be low for the system to obtain

data from the outputs. CE# is used for device selection.

When CE# is high, the chip is deselected and only standby

power is consumed. OE# is the output control and is used

to gate data from the output pins. The data bus is in high

impedance state when either CE# or OE# is high. Refer to

the Read cycle timing diagram for further details (Figure 2).

Byte-Program Operation

The SST39VF088 is programmed on a byte-by-byte basis.

Before programming, the sector where the byte exists must

be fully erased. The Program operation is accomplished in

three steps. The first step is the three-byte load sequence

for Software Data Protection. The second step is to load

byte address and byte data. During the Byte-Program

operation, the addresses are latched on the falling edge of

either CE# or WE#, whichever occurs last. The data is

latched on the rising edge of either CE# or WE#, whichever

occurs first. The third step is the internal Program operation

which is initiated after the rising edge of the fourth WE# or

CE#, whichever occurs first. The Program operation, once

initiated, will be completed within 20 µs. See Figures 3 and

4 for WE# and CE# controlled Program operation timing

diagrams and Figure 13 for flowcharts. During the Program

operation, the only valid reads are Data# Polling and Tog-

gle Bit. During the internal Program operation, the host is

free to perform additional tasks. Any commands issued

during the internal Program operation are ignored.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST39VF088 offers both Sector-Erase

and Block-Erase mode. The sector architecture is based

on uniform sector size of 4 KByte. The Block-Erase mode

is based on uniform block size of 64 KByte. The Sector-

Erase operation is initiated by executing a six-byte com-

mand sequence with Sector-Erase command (50H) and

sector address (SA) in the last bus cycle. The Block-Erase

operation is initiated by executing a six-byte command

sequence with Block-Erase command (30H) and block

address (BA) in the last bus cycle. The sector or block

address is latched on the falling edge of the sixth WE#

pulse, while the command (30H or 50H) is latched on the

rising edge of the sixth WE# pulse. The internal Erase

operation begins after the sixth WE# pulse. The End-of-

Erase operation can be determined using either Data#

Polling or Toggle Bit methods. See Figures 8 and 9 for tim-

ing waveforms. Any commands issued during the Sector-

or Block-Erase operation are ignored.

Chip-Erase Operation

The SST39VF088 provides a Chip-Erase operation, which

allows the user to erase the entire memory array to the “1”

state. This is useful when the entire device must be quickly

erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command (10H)

at address AAAH in the last byte sequence. The Erase

operation begins with the rising edge of the sixth WE# or

CE#, whichever occurs first. During the Erase operation,

the only valid read is Toggle Bit or Data# Polling. See Table

4 for the command sequence, Figure 7 for timing diagram,

and Figure 16 for the flowchart. Any commands issued dur-

ing the Chip-Erase operation are ignored.

Write Operation Status Detection

The SST39VF088 provides two software means to detect

the completion of a write (Program or Erase) cycle, in order

to optimize the system Write cycle time. The software

detection includes two status bits: Data# Polling (DQ7) and

Toggle Bit (DQ6). The End-of-Write detection mode is

enabled after the rising edge of WE#, which initiates the

internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ7 or DQ6. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39VF088

Data# Polling (DQ7)

When the SST39VF088 is in the internal Program opera-

tion, any attempt to read DQ7 will produce the complement

of the true data. Once the Program operation is completed,

DQ7 will produce true data. Note that even though DQ7

may have valid data immediately following the completion

of an internal Write operation, the remaining data outputs

may still be invalid: valid data on the entire data bus will

appear in subsequent successive Read cycles after an

interval of 1 µs. During internal Erase operation, any

attempt to read DQ7 will produce a ‘0’. Once the internal

Erase operation is completed, DQ7 will produce a ‘1’. The

Data# Polling is valid after the rising edge of fourth WE# (or

CE#) pulse for Program operation. For Sector-, Block- or

Chip-Erase, the Data# Polling is valid after the rising edge

of sixth WE# (or CE#) pulse. See Figure 5 for Data# Polling

timing diagram and Figure 14 for a flowchart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating 1s

and 0s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the DQ6 bit will

stop toggling. The device is then ready for the next opera-

tion. The Toggle Bit is valid after the rising edge of fourth

WE# (or CE#) pulse for Program operation. For Sector-,

Block-, or Chip-Erase, the Toggle Bit is valid after the rising

edge of sixth WE# (or CE#) pulse. See Figure 6 for Toggle

Bit timing diagram and Figure 14 for a flowchart.

Data Protection

The SST39VF088 provides both hardware and software

features to protect nonvolatile data from inadvertent

writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5

ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the Write operation. This prevents inadvert-

ent writes during power-up or power-down.

Software Data Protection (SDP)

The SST39VF088 provides the JEDEC approved Software

Data Protection scheme for all data alteration operations,

i.e., Program and Erase. Any Program operation requires

the inclusion of the three-byte sequence. The three-byte

load sequence is used to initiate the Program operation,

providing optimal protection from inadvertent Write opera-

tions, e.g., during the system power-up or power-down.

Any Erase operation requires the inclusion of six-byte

sequence. The SST39VF088 device is shipped with the

Software Data Protection permanently enabled. See Table

4 for the specific software command codes. During SDP

command sequence, invalid commands will abort the

device to Read mode within TRC.

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39VF088

Product Identification

The Product Identification mode identifies the device as the

SST39VF088 and manufacturer as SST. This mode may

be accessed by software operations. Users may use the

Software Product Identification operation to identify the part

(i.e., using the device ID) when using multiple manufactur-

ers in the same socket. For details, see Table 4 for software

operation, Figure 10 for the Software ID Entry and Read

timing diagram and Figure 15 for the Software ID Entry

command sequence flowchart.

Product Identification Mode Exit

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exit is accom-

plished by issuing the Software ID Exit command

sequence, which returns the device to the Read operation.

This command may also be used to reset the device to the

Read mode after any inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. Please note that the Software ID Exit

command is ignored during an internal Program or Erase

operation. See Table 4 for software command codes and

Figure 15 for a flowchart.

TABLE 1: PRODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST39VF088 0001H D8H

T1.0 1227

Y-Decoder

I/O Buffers and Data Latches

1227 B1.0

Address Buffer & Latches

X-Decoder

DQ7 - DQ0

Memory

Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

FUNCTIONAL BLOCK DIAGRAM

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39VF088

FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

AMS1-A0

1. AMS = Most significant address

AMS = A19 for SST39VF088

Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the

sector. During Block-Erase AMS-A16 address lines will select the block.

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide power supply voltage: 2.7-3.6V for SST39VF088

VSS Ground

NC No Connection Unconnected pins.

T2.0 1227

A16

A15

A14

A13

A12

A11

A10

WE#

A19

A18

A17

VSS

DQ7

DQ6

DQ5

DQ4

VDD

DQ3

DQ2

DQ1

DQ0

OE#

VSS

CE#

1227 48-tsop P01.0

Standard Pinout

Top View

Die Up

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39VF088

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1Sector or Block address,

XXH for Chip-Erase

Standby VIH X X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Product Identification

Software Mode VIL VIL VIH See Table 4

T3.0 1227

1. X can be VIL or VIH, but no other value.

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1

1. Address format A14-A0 (Hex),

Addresses A19-A15 can be VIL or VIH, but no other value, for the Command sequence.

Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Byte-Program AAAH AAH 555H 55H AAAH A0H WA2

2. WA = Program Byte address

Data

Block-Erase AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H BAX330H

Sector-Erase AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SAX3

3. SAX for Sector-Erase; uses AMS-A12 address lines

BAX for Block-Erase; uses AMS-A16 address lines

AMS = Most significant address

AMS = A19 for SST39VF088

50H

Chip-Erase AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H

Software ID Entry4,5

4. The device does not remain in Software Product ID mode if powered down.

5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0

SST39VF088 Device ID = D8H, is read with A0 = 1

AAAH AAH 555H 55H AAAH 90H

Software ID Exit6

6. Both Software ID Exit operations are equivalent

XXH F0H

T4.1 1227

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39VF088

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE FOR SST39VF088

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . CL = 100 pF

See Figures 11 and 12

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39VF088

TABLE 5: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT, at f=5 MHz,

VDD=VDD Max

Read215 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

Program and Erase 30 mA CE#=WE#=VIL, OE#=VIH

ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

VIH Input High Voltage 0.7VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

T5.1 1227

1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C

(room temperature), and VDD = 3V. Not 100% tested.

2. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Ty p i c a l VDD is 3V.

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T6.0 1227

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T7.0 1227

TABLE 8: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1,2

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a

higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T8.0 1227

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39VF088

AC CHARACTERISTICS

TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V

Symbol Parameter

SST39VF088-70 SST39VF088-90

UnitsMin Max Min Max

TRC Read Cycle Time 70 90 ns

TCE Chip Enable Access Time 70 90 ns

TAA Address Access Time 70 90 ns

TOE Output Enable Access Time 35 45 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 0 ns

TOLZ1OE# Low to Active Output 0 0 ns

TCHZ1CE# High to High-Z Output 20 30 ns

TOHZ1OE# High to High-Z Output 20 30 ns

TOH1Output Hold from Address Change 0 0 ns

T9.0 1227

TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TBP Byte-Program Time 20 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 100 ms

T10.0 1227

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39VF088

FIGURE 2: READ CYCLE TIMING DIAGRAM

FIGURE 3: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

1227 F02.1

ADDRESS AMS-0

DQ7-0

WE#

OE#

CE# TCE

TRC TAA

TOE

TOLZVIH

HIGH-Z TCLZ TOH

TCHZ

HIGH-Z

DATA VALIDDATA VALID

TOHZ

Note: AMS = Most significant address

AMS = A19 for SST39VF088

1227 F03.2

Note: AMS = Most significant address

MS = A19 for SST39VF088

ADDRESS AMS-0

DQ7-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0 SW1 SW2

AAA 555 AAA ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

WE#

TBP

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39VF088

FIGURE 4: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

FIGURE 5: DATA# POLLING TIMING DIAGRAM

1227 F04.2

ADDRESS AMS-0

DQ7-0

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

AAA 555 AAA ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

CE#

TBP

Note: AMS = Most significant address

MS = A19 for SST39VF088

1227 F05.1

Note: AMS = Most significant address

AMS = A19 for SST39VF088

ADDRESS AMS-0

DQ7DATA DATA# DATA # DATA

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39VF088

FIGURE 6: TOGGLE BIT TIMING DIAGRAM

FIGURE 7: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

1227 F06.1

ADDRESS AMS-0

DQ6

WE#

OE#

CE#

TOETOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note: AMS = Most significant address

AMS = A19 for SST39VF088

1227 F07.2

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

AAA 555 555AAA AAA

55 1055AA 80 AA

AAA

OE#

CE#

Six-byte Code for Chip-Erase

TSCE

TWP

Note: The device also supports CE# controlled Chip-Erase operation.

The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 10)

AMS = Most significant address

AMS = A19 for SST39VF088

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39VF088

FIGURE 8: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM

FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

1227 F08.2

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

AAA 555 555AAA AAA

55 3055AA 80 AA

BAX

OE#

CE#

Six-Byte Code for Block-Erase

TBE

TWP

Note: The device also supports CE# controlled Block-Erase operation.

The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 10)

AMS = Most significant address

AMS = A19 for SST39VF088

1227 F09.2

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

AAA 555 555AAA AAA

55 5055AA 80 AA

SAX

OE#

CE#

Six-byte Code for Sector-Erase

TSE

TWP

Note: The device also supports CE# controlled Sector-Erase operation.

The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 10)

AMS = Most significant address

AMS = A19 for SST39VF088

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EOL Data Sheet

8 Mbit Multi-Purpose Flash

SST39VF088

FIGURE 10: SOFTWARE ID ENTRY AND READ

1227 F10.1

ADDRESS A14-0

TIDA

DQ7-0

WE#

SW0 SW1 SW2

AAA 555 AAA 0000 0001

OE#

CE#

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

TWP

TWPH TAA

Device ID

55AA 90

Note: Device ID = D8H for SST39VF088

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SST39VF088

FIGURE 11: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 12: A TEST LOAD EXAMPLE

1227 F12.0

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points

for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Te st

VOT - VOUTPUT Tes t

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1227 F13.0

TO TESTER

TO DUT

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SST39VF088

FIGURE 13: BYTE-PROGRAM ALGORITHM

1227 F14.0

Start

Load data: AAH

Address: AAAH

Load data: 55H

Address: 555H

Load data: A0H

Address: AAAH

Load Byte

Address/Byte

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

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FIGURE 14: WAIT OPTIONS

1227 F15.0

Wait TBP,

TSCE, TSE

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match?

Read same

byte

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read byte

Is DQ7 =

true data?

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

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SST39VF088

FIGURE 15: SOFTWARE ID COMMAND FLOWCHARTS

1227 F16.1

Load data: AAH

Address: AAAH

Software Product ID Entry

Command Sequence

Load data: 55H

Address: 555H

Load data: 90H

Address: AAAH

Wait TIDA

Read Software ID

Software ID Exit

Command Sequence

Load data: F0H

Address: XXH

Return to normal

operation

Wait TIDA

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SST39VF088

FIGURE 16: ERASE COMMAND SEQUENCE

1227 F17.0

Load data: AAH

Address: AAAH

Chip-Erase

Command Sequence

Load data: 55H

Address: 555H

Load data: 80H

Address: AAAH

Load data: 55H

Address: 555H

Load data: 10H

Address: AAAH

Load data: AAH

Address: AAAH

Wait TSCE

Chip erased

to FFH

Load data: AAH

Address: AAAH

Sector-Erase

Command Sequence

Load data: 55H

Address: 555H

Load data: 80H

Address: AAAH

Load data: 55H

Address: 555H

Load data: 50H

Address: SAX

Load data: AAH

Address: AAAH

Wait TSE

Sector erased

to FFH

Load data: AAH

Address: AAAH

Block-Erase

Command Sequence

Load data: 55H

Address: 555H

Load data: 80H

Address: AAAH

Load data: 55H

Address: 555H

Load data: 30H

Address: BAX

Load data: AAH

Address: AAAH

Wait TBE

Block erased

to FFH

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SST39VF088

PRODUCT ORDERING INFORMATION

Valid combinations for SST39VF088

SST39VF088-70-4C-EK

SST39VF088-70-4C-EKE

SST39VF088-90-4C-EK

SST39VF088-90-4C-EKE

SST39VF088-70-4I-EK

SST39VF088-70-4I-EKE

SST39VF088-90-4I-EK

SST39VF088-90-4I-EKE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Environmental Attribute

E = non-Pb

Package Modifier

K = 48 leads

Package Type

E = TSOP (type 1, die up, 12mm x 20mm)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

90 = 90 ns

Device Density

088 = 8 Mbit

Voltage

V = 2.7-3.6V

Product Series

39 = Multi-Purpose Flash

SST 39 VF 088 - 70 - 4C - EK E

XX XX XXXX - XXX -XX- XXX X

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SST39VF088

PACKAGING DIAGRAMS

48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM

SST PACKAGE CODE: EK

TABLE 11: REVISION HISTORY

Number Description Date

00 •Initial Release Mar 2003

01 •Corrected Byte-Program 3rd Cycle Data from 20H to A0H in Table 4 on page 6 Apr 2003

02 •Corrected Byte-Program 3rd Cycle Data from 20H to A0H in Figures 3 and 4 Jun 2003

03 •Auto Low Power feature references removed.

(CE# toggled high achieves same effect.)

Aug 2003

04 •2004 Data Book Nov 2003

05 •End of Life data sheet for all devices in S71227 Feb 2007

1.05

0.95

0.70

0.50

18.50

18.30

20.20

19.80

0.70

0.50

12.20

11.80

0.27

0.17

0.15

0.05

48-tsop-EK-8

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

0˚- 5˚

DETAIL

Pin # 1 Identifier

0.50

BSC

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SST39VF088

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

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