SLUS362A − FEBRUAR Y 1997 − REVISED NOVEMBER 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DComplies With SPI-2 and SPI-3 Standards
D2.75-V to 7-V Operation
D1.8-pF Channel Capacitance during
Disconnect
D0.5-µA Supply Current in Disconnect Mode
D110-Ω/2.5-kΩ Programmable Termination
DCompletely Meets SCSI Hot Plugging
D−650-mA Sourcing Current for Termination
D+400-mA Sinking Current for Active
Negation Drivers
DTrimmed Termination Current to 4%
DTrimmed Impedance to 7%
DCurrent Limit and Thermal Shutdown
Protection
description
The UCC5610 provides 18 lines of active termination for a SCSI (small computer systems interface) parallel
bus. The SCSI standard recommends active termination at both ends of the cable.
The UCC5610 is ideal for high performance 3.3-V SCSI systems. The key features contributing to such low
operating voltage are the 0.1-V drop-out regulator and the 2.75-V reference. During disconnect the supply
current is typically only 0.5 µA, which makes the IC attractive for battery powered systems.
The UCC5610 is designed with an ultralow-channel capacitance of 1.8 pF, which eliminates effects on signal
integrity from disconnected terminators at interim points on the bus.
The UCC5610 can be programmed for either a 110-Ω or 2.5-kΩ termination. The 110-Ω termination is used for
standard SCSI bus lengths and the 2.5-kΩ termination is typically used in short bus applications. When driving
the TTL compatible DISCNCT pin directly, the 110-Ω termination is connected when the DISCNCT pin is driven
low, and disconnected when driven high. When the DISCNCT pin is driven through an impedance between
80 kΩ and 150 kΩ, the 2.5-kΩ termination is connected when the DISCNCT pin is driven low , and disconnected
when driven high.
block diagram
UDG-94128-1
3
Copyright 2000, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SLUS362A − FEBRUAR Y 1997 − REVISED NOVEMBER 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The power amplifier output stage allows the UCC5610 to source full termination current and sink active negation
current when all termination lines are actively negated.
The UCC5610 is pin for pin compatible with Unitrode’s other 18-line SCSI terminators, allowing lower
capacitance and lower voltage upgrades to existing systems. The UCC5610, as with all Unitrode terminators,
is completely hot-pluggable and appears as high impedance at the terminating channels with VTRMPWR = 0 V
or open.
Internal circuit trimming is utilized, first to trim the 110-Ω termination impedance to a 7% tolerance, and then most
importantly, to trim the output current to a 4% tolerance, which maximizes noise margin.
Other features include thermal shutdown and current limit.
This device is offered in low thermal resistance versions of the industry standard 28-pin wide body SOIC and
28-pin PLCC.
321
13 14
5
6
7
8
9
10
11
LINE6
LINE5
LINE4
LINE3
LINE2
LINE1
DISCNCT
LINE12
LINE13
LINE14
LINE15
LINE16
LINE17
LINE18
4
15 16 17 18
GND*
GND*
GND*
GND*
GND*
GND*
LINE11
LINE10
REG
TRMPWR
QP PACKAGE
TOP VIEW
28 27 2625
24
23
22
21
20
19
12
GND*
LINE9
LINE8
LINE7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DISCNCT
LINE1
LINE2
LINE3
LINE4
LINE5
GND*
GND*
GND*
LINE6
LINE7
LINE8
LINE9
TRMPWR
GND
LINE18
LINE17
LINE16
LINE15
LINE14
GND*
GND*
GND*
LINE13
LINE12
LINE11
LINE10
REG
DWP PACKAGE
TOP VIEW
* DWP package pin 28 serves as signal ground;
pins 7, 8, 9, 20, 21, 22 serve as heatsink/ground. * QP package pins 12-18 serve as both heatsink
and signal ground.
AVAILABLE OPTIONS
TJ
PACKAGED DEVICES{
TJ
SOIC (DWP) PLCC (QP)
0°C to 70°C UCC5610DWP UCC5610QP
†Available tape and reeled. Add TR suffix to device type to order quantities of 1000 devices per reel.
SLUS362A − FEBRUAR Y 1997 − REVISED NOVEMBER 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†}
Termpwr voltage 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal line voltage 0 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Regulator output current Self-regulating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature −65°Cto 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating temperature −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature (soldering, 10 Sec.) 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡Unless otherwise specified all voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal. Consult
Packaging Section of Interface Products Data Book (TI Literature Number SLUD002) for thermal limitations and considerations of packages.
recommended operating conditions
Termpwr voltage 2.75 V to 5.25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal line voltage 0 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disconnect input voltage 0 V to Termpwr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
electrical characteristics, these specifications apply for TA = 0°C to 70°C, TRMPWR = 3.3 V,
DISCNCT = 0 V, RDISCNCT = 0 Ω, TA = TJ, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Supply Current Section
Termpwr supply current
All termination lines = open 1 2 mA
Termpwr supply current All termination lines = 0.2 V 415 455 mA
Power down mode DISCNCT = termpwr 0.5 5 µA
Output Section (110 Ω − Terminator Lines)
Terminator impedance See Note 4 102.3 110 117.7 Ω
Output high voltage See Note 1 2.5 2.7 3.0 V
VLINE = 0.2 V, TJ = 25°C −25.4 −23 −22.1 mA
VLINE = 0.2 V −25.4 −23 −21 mA
Max output current VLINE = 0.2 V, TRMPWR = 3 V, TJ = 25°C
See Note 1 −25.4 −23 −20.2 mA
VLINE = 0.2 V, TRMPWR = 3 V, See Note 1 −25.4 −23 −19 mA
VLINE = 0.5 V −22.4 mA
Output leakage DISCNCT = 2.4 V, TRMPWR = 0 V to 5.25 V 10 400 nA
Output capacitance DISCNCT = 2.4 V, See Note 2, See Note 3,
DWP package 1.8 2.5 pF
Output Section (2.5 kΩ − Terminator Lines) (RDISCNCT = 80 kΩ)
Terminator impedance 2 2.5 3 kΩ
Output high voltage TRMPWR = 3 V, See Note 1 2.5 2.7 3.0 V
Max output current
VLINE = 0.2 V −1.4 −1 −0.7 mA
Max output current VLINE = 0.2 V, TRMPWR = 3 V, See Note 1 −1.5 −1 −0.6 mA
Output leakage DISCNCT = 2.4 V, TRMPWR = 0 to 5.25 V 10 400 nA
Output capacitance DISCNCT = 2.4 V See Note 2, See Note 3,
DWP package 1.8 2.5 pF
NOTES: 1. Measuring each termination line while other 17 are low (0.2 V).
2. Ensured by design. Not production tested.
3. Output capacitance is measured at 0.5 V.
4. Tested by measuring IOUT with VOUT = 0.2 V and VOUT = VREG − 0.1 V then calculating the impedance.
SLUS362A − FEBRUAR Y 1997 − REVISED NOVEMBER 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, these specifications apply for TA = 0°C to 70°C, TRMPWR = 3.3 V,
DISCNCT = 0 V, RDISCNCT = 0 Ω, TA = TJ, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Regulator Section
Regulator output voltage 5.25 V > TRMPWR > 3 V 2.5 2.7 3.0 V
Drop out voltage All termination lines = 0.2 V 0.1 0.2 V
Short circuit current VREG = 0 V −800 −650 −450 mA
Sinking current capability VREG = 3 V 200 400 800 mA
Thermal shutdown See Note 2 170 °C
Thermal shutdown hysteresis See Note 2 10 °C
Disconnect Section
Disconnect threshold RDISCNCT = 0 & 80 kΩ0.8 1.5 2.0 V
Input current DISCNCT = 0 V 30 50 µA
NOTES: 2. Ensured by design. Not production tested.
APPLICATION INFORMATION
UDG-94130
Figure 1. Typical SCSI Bus Configurations Utilizing a UCC5610 Device
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
UCC5610DWP NRND SOIC DW 28 TBD Call TI Call TI
UCC5610DWPG4 NRND SOIC DW 28 TBD Call TI Call TI
UCC5610DWPTR NRND SOIC DW 28 TBD Call TI Call TI
UCC5610DWPTRG4 NRND SOIC DW 28 TBD Call TI Call TI
UCC5610QP NRND PLCC FN 28 TBD Call TI Call TI
UCC5610QPTR NRND PLCC FN 28 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Mar-2007
Addendum-Page 1
MECHANICAL DATA
MPLC004A – OCTOBER 1994
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
4040005/B 03/95
20 PIN SHOWN
0.026 (0,66)
0.032 (0,81)
D2/E2
0.020 (0,51) MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D2/E2
0.013 (0,33)
0.021 (0,53)
Seating Plane
MAX
D2/E2
0.219 (5,56)
0.169 (4,29)
0.319 (8,10)
0.469 (11,91)
0.569 (14,45)
0.369 (9,37)
MAX
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.008 (0,20) NOM
1.158 (29,41)
0.958 (24,33)
0.756 (19,20)
0.191 (4,85)
0.141 (3,58)
MIN
0.441 (11,20)
0.541 (13,74)
0.291 (7,39)
0.341 (8,66)
18
19
14
13
D
D1
13
9
E1E
4
8
MINMAXMIN
PINS
**
20
28
44
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
52
68
84 1.185 (30,10)
0.985 (25,02)
0.785 (19,94)
D/E
0.395 (10,03)
0.495 (12,57)
1.195 (30,35)
0.995 (25,27)
0.695 (17,65)
0.795 (20,19)
NO. OF D1/E1
0.350 (8,89)
0.450 (11,43)
1.150 (29,21)
0.950 (24,13)
0.650 (16,51)
0.750 (19,05)
0.004 (0,10)
M
0.007 (0,18)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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