M28W160BT M28W160BB 16 Mbit (1Mb x16, Boot Block) 3V Supply Flash Memory FEATURES SUMMARY SUPPLY VOLTAGE Figure 1. Packages - VDD = 2.7V to 3.6V Core Power Supply - VDDQ= 1.65V to 3.6V for Input/Output - VPP = 12V for fast Program (optional) ACCESS TIME: 70, 85, 90,100ns PROGRAMMING TIME - 10s typical BGA BGA46 (GB) 6.39 x 6.37mm - Double Word Programming Option COMMON FLASH INTERFACE - 64 bit Security Code MEMORY BLOCKS - Parameter Blocks (Top or Bottom location) - Main Blocks FBGA TFBGA46 (ZB) 6.39 x 6.37mm BLOCK PROTECTION on TWO PARAMETER BLOCKS - WP for Block Protection AUTOMATIC STAND-BY MODE PROGRAM and ERASE SUSPEND 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE TSOP48 (N) 12 x 20mm - Manufacturer Code: 20h - Top Device Code, M28W160BT: 90h - Bottom Device Code, M28W160BB: 91h May 2002 1/45 M28W160BT, M28W160BB TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. BGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address Inputs (A0-A19). . . . . . . . Data Input/Output (DQ0-DQ15). . . Chip Enable (E). . . . . . . . . . . . . . . Output Enable (G). . . . . . . . . . . . . Write Enable (W). . . . . . . . . . . . . . Write Protect (WP). . . . . . . . . . . . . Reset (RP). . . . . . . . . . . . . . . . . . . VDD Supply Voltage . . . . . . . . . . . . VDDQ Supply Voltage. . . . . . . . . . . VPP Program Supply Voltage . . . . VSS Ground. . . . . . . . . . . . . . . . . . ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 10 . . . . 10 . . . . 10 . . . . 10 . . . . 10 . . . . 10 . . . . 10 . . . . 10 . . . . 10 . . . . 10 . . . . 10 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read. . . . . . . . . . . . . . . . . . Write. . . . . . . . . . . . . . . . . . Output Disable. . . . . . . . . . Standby. . . . . . . . . . . . . . . Automatic Standby. . . . . . . Reset. . . . . . . . . . . . . . . . . Table 2. Bus Operations . . ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... . . . . . . . . . . 11 . . . . . . . . . . 11 . . . . . . . . . . 11 . . . . . . . . . . 11 . . . . . . . . . . 11 . . . . . . . . . . 11 . . . . . . . . . . 11 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/45 M28W160BT, M28W160BB Table 5. Memory Blocks Protection Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 6. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 15 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Program/Erase Controller Status (Bit 7) . . . Erase Suspend Status (Bit 6) . . . . . . . . . . . Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . Program Status (Bit 4) . . . . . . . . . . . . . . . . . VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . Program Suspend Status (Bit 2) . . . . . . . . . Block Protection Status (Bit 1). . . . . . . . . . . Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . Table 7. Status Register Bits . . . . . . . . . . . . ...... ...... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 16 . . . . 16 . . . . 16 . . . . 16 . . . . 16 . . . . 16 . . . . 17 . . . . 17 . . . . 17 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 11. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 14. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 12. Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 15. Power-Up and Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 27 Table 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 27 Figure 14. BGA46 6.39x6.37mm - 8 x 6 ball array, 0.75 mm pitch, Bottom View Package Outline28 Table 17. BGA46 6.39x6.37mm - 8 x 6 ball array, 0.75 mm pitch, Package Mechanical Data . . . 28 Figure 15. BGA46 Daisy Chain - Package Connections (Top view through package) . . . . . . . . . 29 Figure 16. BGA46 Daisy Chain - PCB Connections proposal (Top view through package) . . . . . 29 Figure 17. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline30 Table 18. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data . . . 30 Figure 18. TFBGA46 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 31 Figure 19. TFBGA46 Daisy Chain - PCB Connections proposal (Top view through package) . . . . 31 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3/45 M28W160BT, M28W160BB Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 20. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 22. Top Boot Block Addresses, M28W160BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 23. Bottom Boot Block Addresses, M28W160BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 24. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 25. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 26. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 27. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 28. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 29. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 20. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 21. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 22. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 41 Figure 23. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 24. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 43 APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE . . . . . . . 44 Table 30. Write State Machine Current/Next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4/45 M28W160BT, M28W160BB SUMMARY DESCRIPTION The M28W160B is a 16 Mbit (1 Mbit x 16) non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. VDDQ allows to drive the I/O pin down to 1.65V. An optional 12V VPP power supply is provided to speed up customer programming. The device features an asymmetrical blocked architecture. The M28W160B has an array of 39 blocks: 8 Parameter Blocks of 4 KWord and 31 Main Blocks of 32 KWord. M28W160BT has the Parameter Blocks at the top of the memory address space while the M28W160BB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Figure 6, Block Addresses. Parameter blocks 0 and 1 can be protected from accidental programming or erasure. Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The memory is offered in TSOP48 (10 X 20mm), BGA46 (6.39 x 6.37mm, 0.75mm pitch) and TFBGA46 (6.39 x 6.37mm, 0.75mm pitch) packages and is supplied with all the bits erased (set to '1'). Figure 2. Logic Diagram VDD VDDQ VPP 20 16 A0-A19 DQ0-DQ15 W E G M28W160BT M28W160BB RP WP VSS AI02628 Table 1. Signal Names A0-A19 Address Inputs DQ0-DQ15 Data Input/Output E Chip Enable G Output Enable W Write Enable RP Reset WP Write Protect VDD Core Power Supply VDDQ Power Supply for Input/Output VPP Optional Supply Voltage for Fast Program & Erase VSS Ground 5/45 M28W160BT, M28W160BB Figure 3. TSOP Connections A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP VPP WP A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 12 M28W160BT 37 13 M28W160BB 36 24 25 A16 VDDQ VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 AI02630 6/45 M28W160BT, M28W160BB Figure 4. BGA Connections (Top view through package) 1 2 3 4 5 6 7 8 A A13 A11 A8 VPP WP A19 A7 A4 B A14 A10 W RP A18 A17 A5 A2 C A15 A12 A9 A6 A3 A1 D A16 DQ14 DQ5 DQ11 DQ2 DQ8 E A0 E VDDQ DQ15 DQ6 DQ12 DQ3 DQ9 DQ0 VSS F VSS DQ7 DQ13 DQ4 VDD DQ10 DQ1 G AI02629 7/45 M28W160BT, M28W160BB Figure 5. TFBGA Connections (Top view through package) 1 2 3 4 5 6 7 8 A A13 A11 A8 VPP WP A19 A7 A4 B A14 A10 W RP A18 A17 A5 A2 C A15 A12 A9 A6 A3 A1 D A16 DQ14 DQ5 DQ11 DQ2 DQ8 E A0 E VDDQ DQ15 DQ6 DQ12 DQ3 DQ9 DQ0 VSS F VSS DQ7 DQ13 DQ4 VDD DQ10 DQ1 G AI03804 8/45 M28W160BT, M28W160BB Figure 6. Block Addresses M28W160BB Bottom Boot Block Addresses M28W160BT Top Boot Block Addresses FFFFF FFFFF 32 KWords 4 KWords F8000 F7FFF FF000 Total of 8 4 KWord Blocks 32 KWords F0000 Total of 31 32 KWord Blocks F8FFF 4 KWords F8000 F7FFF 32 KWords 0FFFF F0000 32 KWords 08000 07FFF 4 KWords Total of 31 32 KWord Blocks 07000 Total of 8 4 KWord Blocks 0FFFF 32 KWords 08000 07FFF 00FFF 32 KWords 00000 4 KWords 00000 AI04310 Note: Also see Appendix A, Tables 22 and 23 for a full listing of the Block Addresses. 9/45 M28W160BT, M28W160BB SIGNAL DESCRIPTIONS See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A19). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or data to be programmed during a Write Bus operation. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. Output Enable (G). The Output Enable controls data outputs during the Bus Read operation of the memory. Write Enable (W). The Write Enable controls the Bus Write operation of the memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first. Write Protect (WP). Write Protect is an input to protect or unprotect the two lockable parameter blocks. When Write Protect is at VIL, the lockable blocks are protected and Program or Erase operations are not possible. When Write Protect is at VIH, the lockable blocks are unprotected and can be programmed or erased (refer to Table 4, Memory Blocks Protection Truth). Reset (RP). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is mini- 10/45 mized. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters read array mode, but a negative transition of Chip Enable or a change of the address is required to ensure valid data outputs. V DD Supply Voltage. VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). V DDQ Supply Voltage. VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply. V PP Program Supply Voltage. VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. The Supply Voltage VDD and the Program Supply Voltage VPP can be applied in any order. If VPP is kept in a low voltage range (0V to 3.6V) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions (see Table 11, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range 11.4V to 12.6V it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed (see Table 13 and 14). VSS Ground. VSS is the reference for all voltage measurements. Note: Each device in a system should have VDD,VDDQ and VPP decoupled with a 0.1F capacitor close to the pin. See Figure 8, AC Measurement Load Circuit. The PCB trace widths should be sufficient to carry the required VPP Program and Erase currents. M28W160BT, M28W160BB BUS OPERATIONS There are six standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby, Automatic Standby and Reset. See Table 2, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Read. Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figure 9, Read Mode AC Waveforms, and Table 12, Read AC Characteristics, for details of when the output becomes valid. Read mode is the default state of the device when exiting Reset or after power-up. Write. Bus Write operations write Commands to the memory or latch Input Data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. See Figures 10 and 11, Write AC Waveforms, and Tables 13 and 14, Write AC Characteristics, for details of the timing requirements. Output Disable. The data outputs are high impedance when the Output Enable is at VIH. Standby. Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable is at VIH and the device is in read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished. Automatic Standby. Automatic Standby provides a low power consumption state during Read mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity, even if Chip Enable is low, VIL, and the supply current is reduced to IDD1. The data Inputs/Outputs will still output data. Reset. During Reset mode, when Output Enable is low, VIL, the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid. Table 2. Bus Operations E G W RP WP VPP DQ0-DQ15 Read VIL VIL VIH VIH X Don't Care Data Output Write VIL VIH VIL VIH X VDD or VPPH Data Input Output Disable VIL VIH VIH VIH X Don't Care Hi-Z Standby VIH X X VIH X Don't Care Hi-Z X X X VIL X Don't Care Hi-Z Operation Reset Note: X = VIL or VIH, VPPH = 12V 5%. 11/45 M28W160BT, M28W160BB COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time, to monitor the progress of an operation, or the Program/ Erase states. See Appendix D, Table 30, Write State Machine Current/Next, for a summary of the Command Interface. The Command Interface is reset to Read mode when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands will reset the device to Read mode. Refer to Table 3, Commands, in conjunction with the text descriptions below. Read Memory Array command The Read command returns the memory to its Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will read the addressed location and output the data. When a device Reset occurs, the memory defaults to Read mode. Read Status Register Command The Status Register indicates when a program or erase operation is complete and the success or failure of the operation itself. Issue a Read Status Register command to read the Status Register's contents. Subsequent Bus Read operations read the Status Register, at any address, until another command is issued. See Table 7, Status Register Bits, for details on the definitions of the bits. The Read Status Register command may be issued at any time, even during a Program/Erase operation. Any Read attempt during a Program/ Erase operation will automatically output the content of the Status Register. Read Electronic Signature Command The Read Electronic Signature command reads the Manufacturer and Device Codes. The Read Electronic Signature command consists of one write cycle, a subsequent read will output the Manufacturer or the Device Code depending on the levels of A0. The Manufacturer Code is output when the address line A0 is at VIL, the Device Code is output when A0 is at VIH. Addresses A1A7 must be kept to VIL, other addresses are ignored. The codes are output on DQ0-DQ7 with DQ8-DQ15 at 00h. (see Table 4) 12/45 Read CFI Query Command The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area, allowing programming equipment or applications to automatically match their interface to the characteristics of the device. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See Appendix B, Common Flash Interface, Tables 24, 25, 26, 27, 28 and 29 for details on the information contained in the Common Flash Interface memory area. Block Erase Command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to '1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command. The first bus cycle sets up the Erase command. The second latches the block address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. During Erase operations the memory will only accept the Read Status Register command and the Program/Erase Suspend command, all other commands will be ignored. Typical Erase times are given in Table 6, Program, Erase Times and Program/Erase Endurance Cycles. See Appendix C, Figure 23, Erase Flowchart and Pseudo Code, for the flowchart for using the Erase command. Program Command The memory array can be programmed word-byword. Two bus write cycles are required to issue the Program command. The first bus cycle sets up the Program command. The second latches the Address and the Data to be written and starts the Program/Erase Controller. During Program operations the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other M28W160BT, M28W160BB commands will be ignored. Typical Program times are given in Table 6, Program, Erase Times and Program/Erase Endurance Cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 20, Program Flowchart and Pseudo Code, for the flowchart for using the Program command. Double Word Program Command This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. Programming should not be attempted when VPP is not at VPPH. The command can be executed if VPP is below VPPH but the result is not guaranteed. Three bus write cycles are necessary to issue the Double Word Program command. The first bus cycle sets up the Double Word Program command. The second bus cycle latches the Address and the Data of the first word to be written. The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 21, Double Word Program Flowchart and Pseudo Code, for the flowchart for using the Double Word Program command. Clear Status Register Command The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to `0'. One bus write cycle is required to issue the Clear Status Register command. The bits in the Status Register do not automatically return to `0' when a new Program or Erase command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase controller. During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array, Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Program command will also be accepted. Only the blocks not being erased may be read or programmed correctly. During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by taking Chip Enable to VIH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 22, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 24, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/ Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the command. Once the command is issued subsequent Bus Read operations read the Status Register. See Appendix C, Figure 22, Program or Double Word Program Suspend & Resume Flowchart and Pseudo Code, and Figure 24, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/Erase Resume command. Block Protection Two parameter/lockable blocks (blocks #0 and #1) can be protected against Program or Erase operations. Unprotected blocks can be programmed or erased. To protect the two lockable blocks set Write Protect to VIL. When VPP is below VPPLK all blocks are protected. Any attempt to Program or Erase protected blocks will abort, the data in the block will not be changed and the Status Register outputs the error. Table 5, Memory Blocks Protection Truth Table, defines the protection methods. 13/45 M28W160BT, M28W160BB Table 3. Commands Bus Write Operations No. of Cycles Commands 1st Cycle 2nd Cycle 3nd Cycle Bus Op. Addr Data Bus Op. Addr Data Read Memory Array 1+ Write X FFh Read Read Addr Data Read Status Register 1+ Write X 70h Read X Status Register Read Electronic Signature 1+ Write X 90h Read Signature Addr (2) Signature Read CFI Query 1+ Write X 98h Read CFI Addr Query Erase 2 Write X 20h Write Block Addr D0h Program 2 Write X 40h or 10h Write Addr Data Input Double Word Program (3) 3 Write X 30h Write Addr 1 Data Input Clear Status Register 1 Write X 50h Program/Erase Suspend 1 Write X B0h Program/Erase Resume 1 Write X D0h Bus Op. Addr Data Write Addr 2 Data Input Note: 1. X = Don't Care. 2. A0=VIL outputs Manufacturer code, A0=VIH outputs Device code. Address A7-A1 must be VIL. 3. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0. Table 4. Read Electronic Signature Code Device E G W A0 A1-A7 A8-A19 DQ0-DQ15 VIL VIL VIH VIL VIL Don't Care 20h M28W160BT VIL VIL VIH VIH VIL Don't Care 90h M28W160BB VIL VIL VIH VIH VIL Don't Care 91h Manufact. Code Device Code Note: RP = VIH. Table 5. Memory Blocks Protection Truth Table VPP (1) RP WP (1) Lockable Blocks (blocks #0 and #1) Other Blocks X VIL X Protected Protected VIL VIH X Protected Protected VDD or VPPH (2) VIH VIL Protected Unprotected VDD or VPPH (2) VIH VIH Unprotected Unprotected Note: 1. X = Don't Care 2. VPP must also be greater than the Program Voltage Lock Out VPPLK. 14/45 M28W160BT, M28W160BB Table 6. Program, Erase Times and Program/Erase Endurance Cycles M28W160B Parameter Word Program Double Word Program Test Conditions Unit Min Typ Max VPP = VDD 10 200 s VPP = 12V 5% 10 200 s VPP = 12V 5% 0.16 5 s VPP = VDD 0.32 5 s VPP = 12V 5% 0.02 4 s VPP = VDD 0.04 4 s VPP = 12V 5% 1 10 s VPP = VDD 1 10 s VPP = 12V 5% 0.8 10 s VPP = VDD 0.8 10 s Main Block Program Parameter Block Program Main Block Erase Parameter Block Erase Program/Erase Cycles (per Block) 100,000 cycles 15/45 M28W160BT, M28W160BB STATUS REGISTER The Status Register provides information on the current or previous Program or Erase operation. The various bits convey information and errors on the operation. To read the Status register the Read Status Register command can be issued, refer to the Read Status Register Command section. To output the contents, the Status Register is latched on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to VIH. Either Chip Enable or Output Enable must be toggled to update the latched data. Bus Read operations from any address always read the Status Register during Program and Erase operations. The bits in the Status Register are summarized in Table 7, Status Register Bits. Refer to Table 7 in conjunction with the following text descriptions. Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is Low (set to `0'), the Program/Erase Controller is active; when the bit is High (set to `1'), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High . During Program, Erase, operations the Program/ Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, VPP Status and Block Protection Status bits should be tested for errors. Erase Suspend Status (Bit 6). The Erase Suspend Status bit (set to `1') indicates that an Erase operation has been suspended or is going to be suspended. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 7 is set within 30s of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. 16/45 Erase Status (Bit 5). The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase Status bit is High (set to `1'), the Program/ Erase Controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status (Bit 4). The Program Status bit is used to identify a Program failure. When the Program Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. VPP Status (Bit 3). The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if VPP becomes invalid during an operation. When the VPP Status bit is Low (set to `0'), the voltage on the VPP pin was sampled at a valid voltage; when the VPP Status bit is High (set to `1'), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK, the memory is protected and Program and Erase operations cannot be performed. Once set High, the VPP Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Suspend Status (Bit 2). The Program Suspend Status bit (set to `1') indicates that a Program operation has been suspended or is going to be suspended. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 2 is set within 5s of the Program/Erase Suspend command being issued therefore the M28W160BT, M28W160BB memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is High (set to `1'), a Program or Erase operation has been attempted on a protected block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value must be masked. Note: Refer to Appendix C, Flowcharts and Pseudo Codes, for using the Status Register. Table 7. Status Register Bits Bit 7 6 5 4 3 2 1 0 Name Logic Level Definition '1' Ready '0' Busy '1' Suspended '0' In progress or Completed '1' Erase Error '0' Erase Success '1' Program Error '0' Program Success '1' VPP Invalid, Abort '0' VPP OK '1' Suspended '0' In Progress or Completed '1' Program/Erase on protected Block, Abort '0' No operation to protected blocks P/E.C. Status Erase Suspend Status Erase Status Program Status VPP Status Program Suspend Status Block Protection Status Reserved Note: Logic level '1' is High, '0' is Low. 17/45 M28W160BT, M28W160BB MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 8. Absolute Maximum Ratings Value Symbol Parameter Max Ambient Operating Temperature (1) -40 85 C TBIAS Temperature Under Bias -40 125 C TSTG Storage Temperature -55 155 C Input or Output Voltage -0.6 VDDQ+0.6 V Supply Voltage -0.6 4.1 V Program Voltage -0.6 13 V TA VIO VDD, VDDQ VPP Note: 1. Depends on range. 18/45 Unit Min M28W160BT, M28W160BB DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measure- ment Conditions summarized in Table 9, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 9. Operating and AC Measurement Conditions M28W160BT, M28W160BB 70 85 90 100 Parameter Units Min Max Min Max Min Max Min Max VDD Supply Voltage 2.7 3.6 2.7 3.6 2.7 3.6 2.7 3.6 V VDDQ Supply Voltage (VDDQ VDD) 2.7 3.6 2.7 3.6 2.7 3.6 1.65 3.6 V Ambient Operating Temperature - 40 85 - 40 85 - 40 85 - 40 85 C Load Capacitance (CL) 50 Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 50 50 50 pF 5 5 5 5 ns 0 to VDDQ 0 to VDDQ 0 to VDDQ 0 to VDDQ V VDDQ/2 VDDQ/2 VDDQ/2 VDDQ/2 V Figure 7. AC Measurement I/O Waveform Figure 8. AC Measurement Load Circuit VDDQ VDDQ VDDQ/2 VDDQ VDD 0V 25k AI00610 DEVICE UNDER TEST CL 0.1F 25k 0.1F CL includes JIG capacitance AI00609C Table 10. Device Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Note: Sampled only, not 100% tested. 19/45 M28W160BT, M28W160BB Table 11. DC Characteristics Symbol Parameter Test Condition Min Typ Max Unit ILI Input Leakage Current 0V VIN VDDQ 1 A ILO Output Leakage Current 0V VOUT VDDQ 10 A IDD Supply Current (Read) IDD1 Supply Current (Stand-by or Automatic Stand-by) IDD2 Supply Current (Reset) IDD3 IDD4 Supply Current (Program) Supply Current (Erase) E = VSS, G = VIH, f = 5MHz 10 20 mA E = VDDQ 0.2V, RP = VDDQ 0.2V 15 50 A RP = VSS 0.2V 15 50 A Program in progress VPP = 12V 5% 10 20 mA Program in progress VPP = VDD 10 20 mA Erase in progress VPP = 12V 5% 5 20 mA Erase in progress VPP = VDD 5 20 mA E = VDDQ 0.2V, Erase suspended 50 A IDD5 Supply Current (Program/Erase Suspend) IPP Program Current (Read or Stand-by) VPP > VDD 400 A IPP1 Program Current (Read or Stand-by) VPP VDD 5 A IPP2 Program Current (Reset) RP = VSS 0.2V 5 A Program in progress VPP = 12V 5% 10 mA Program in progress VPP = VDD 5 A Erase in progress VPP = 12V 5% 10 mA Erase in progress VPP = VDD 5 A 0.4 V IPP3 IPP4 VIL Program Current (Program) Program Current (Erase) Input Low Voltage -0.5 VDDQ 2.7V -0.5 0.8 V VDDQ -0.4 VDDQ +0.4 V 0.7 VDDQ VDDQ +0.4 V 0.1 V VIH Input High Voltage VOL Output Low Voltage IOL = 100A, VDD = VDD min, VDDQ = VDDQ min VOH Output High Voltage IOH = -100A, VDD = VDD min, VDDQ = VDDQ min VPP1 Program Voltage (Program or Erase operations) 1.65 3.6 V VPPH Program Voltage (Program or Erase operations) 11.4 12.6 V VPPLK Program Voltage (Program and Erase lock-out) 1 V VLKO VDD Supply Voltage (Program and Erase lock-out) 2 V 20/45 VDDQ 2.7V VDDQ -0.1 V M28W160BT, M28W160BB Figure 9. Read Mode AC Waveforms tAVAV VALID A0-A19 tAVQV tAXQX E tELQV tELQX tEHQX tEHQZ G tGLQV tGHQX tGLQX tGHQZ VALID DQ0-DQ15 ADDR. VALID CHIP ENABLE OUTPUTS ENABLED DATA VALID STANDBY AI00619 Table 12. Read AC Characteristics M28W160B Symbol Alt Parameter Unit 70 85 90 100 tAVAV tRC Address Valid to Next Address Valid Min 70 85 90 100 ns tAVQV tACC Address Valid to Output Valid Max 70 85 90 100 ns tAXQX (1) tOH Address Transition to Output Transition Min 0 0 0 0 ns tEHQX (1) tOH Chip Enable High to Output Transition Min 0 0 0 0 ns tEHQZ (1) tHZ Chip Enable High to Output Hi-Z Max 20 20 25 30 ns tELQV (2) tCE Chip Enable Low to Output Valid Max 70 85 90 100 ns tELQX (1) tLZ Chip Enable Low to Output Transition Min 0 0 0 0 ns tGHQX (1) tOH Output Enable High to Output Transition Min 0 0 0 0 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z Max 20 20 25 30 ns tGLQV (2) tOE Output Enable Low to Output Valid Max 20 20 30 35 ns tGLQX (1) tOLZ Output Enable Low to Output Transition Min 0 0 0 0 ns Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 21/45 22/45 VPP WP DQ0-DQ15 W G E A0-A19 tWLWH COMMAND SET-UP COMMAND tDVWH tELWL tWHDX tWHWL tWHEH CMD or DATA CONFIRM COMMAND OR DATA INPUT tVPHWH tWPHWH tAVWH VALID tAVAV tWHEL tWHGL tWHAX PROGRAM OR ERASE AI03572 tQVVPL tQVWPL STATUS REGISTER STATUS REGISTER READ 1st POLLING tELQV M28W160BT, M28W160BB Figure 10. Write AC Waveforms, Write Enable Controlled M28W160BT, M28W160BB Table 13. Write AC Characteristics, Write Enable Controlled M28W160B Symbol Alt Parameter Unit 70 85 90 100 tAVAV tWC Write Cycle Time Min 70 85 90 100 ns tAVWH tAS Address Valid to Write Enable High Min 45 45 50 50 ns tDVWH tDS Data Valid to Write Enable High Min 45 45 50 50 ns tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 0 0 ns Chip Enable Low to Output Valid Min 70 85 90 100 ns Output Valid to VPP Low Min 0 0 0 0 ns Output Valid to Write Protect Low Min 0 0 0 0 ns tELQV tQVVPL (1,2) tQVWPL tVPHWH (1) tVPS VPP High to Write Enable High Min 200 200 200 200 ns tWHAX tAH Write Enable High to Address Transition Min 0 0 0 0 ns tWHDX tDH Write Enable High to Data Transition Min 0 0 0 0 ns tWHEH tCH Write Enable High to Chip Enable High Min 0 0 0 0 ns tWHEL Write Enable High to Chip Enable Low Min 25 25 30 30 ns tWHGL Write Enable High to Output Enable Low Min 20 20 30 30 ns tWHWL tWPH Write Enable High to Write Enable Low Min 25 25 30 30 ns tWLWH tWP Write Enable Low to Write Enable High Min 45 45 50 50 ns Write Protect High to Write Enable High Min 45 45 50 50 ns tWPHWH Note: 1. Sampled only, not 100% tested. 2. Applicable if VPP is seen as a logic input (VPP < 3.6V). 23/45 24/45 VPP WP DQ0-DQ15 E G W A0-A19 tELEH COMMAND POWER-UP AND SET-UP COMMAND tDVEH tWLEL tEHDX tEHEL tEHWH CMD or DATA CONFIRM COMMAND OR DATA INPUT tVPHEH tWPHEH tAVEH VALID tAVAV tEHGL tEHAX PROGRAM OR ERASE AI03573 tQVVPL tQVWPL STATUS REGISTER STATUS REGISTER READ 1st POLLING tELQV M28W160BT, M28W160BB Figure 11. Write AC Waveforms, Chip Enable Controlled M28W160BT, M28W160BB Table 14. Write AC Characteristics, Chip Enable Controlled M28W160B Symbol Alt Parameter Unit 70 85 90 100 tAVAV tWC Write Cycle Time Min 70 85 90 100 ns tAVEH tAS Address Valid to Chip Enable High Min 45 45 50 50 ns tDVEH tDS Data Valid to Chip Enable High Min 45 45 50 50 ns tEHAX tAH Chip Enable High to Address Transition Min 0 0 0 0 ns tEHDX tDH Chip Enable High to Data Transition Min 0 0 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low Min 25 25 30 30 ns Chip Enable High to Output Enable Low Min 25 25 30 30 ns tEHGL tEHWH tWH Chip Enable High to Write Enable High Min 0 0 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High Min 45 45 50 50 ns Chip Enable Low to Output Valid Min 70 85 90 100 ns Output Valid to VPP Low Min 0 0 0 0 ns Data Valid to Write Protect Low Min 0 0 0 0 ns tELQV tQVVPL (1,2) tQVWPL tVPHEH (1) tVPS VPP High to Chip Enable High Min 200 200 200 200 ns tWLEL tCS Write Enable Low to Chip Enable Low Min 0 0 0 0 ns Write Protect High to Chip Enable High Min 45 45 50 50 ns tWPHEH Note: 1. Sampled only, not 100% tested. 2. Applicable if VPP is seen as a logic input (VPP < 3.6V). 25/45 M28W160BT, M28W160BB Figure 12. Power-Up and Reset AC Waveforms W, E, G tPHWL tPHEL tPHGL tPHWL tPHEL tPHGL RP tVDHPH tPLPH VDD, VDDQ Power-Up Reset AI03453b Table 15. Power-Up and Reset AC Characteristics M28W160B Symbol tPHWL tPHEL tPHGL Parameter Reset High to Write Enable Low, Chip Enable Low, Output Enable Low Test Condition Unit 70 85 90 100 During Program and Erase Min 50 50 50 50 s others Min 30 30 30 30 ns tPLPH(1,2) Reset Low to Reset High Min 100 100 100 100 ns tVDHPH(3) Supply Voltages High to Reset High Min 50 50 50 50 s Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during power up or reset. 26/45 M28W160BT, M28W160BB PACKAGE MECHANICAL Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline A2 1 N e E B N/2 D1 A CP D DIE C A1 TSOP-a L Note: Drawing is not to scale. Table 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data Symbol mm Typ Min A inches Max Typ Min 1.20 Max 0.0472 A1 0.05 0.15 0.0020 0.0059 A2 0.95 1.05 0.0374 0.0413 B 0.17 0.27 0.0067 0.0106 C 0.10 0.21 0.0039 0.0083 D 19.80 20.20 0.7795 0.7953 D1 18.30 18.50 0.7205 0.7283 E 11.90 12.10 0.4685 0.4764 - - - - e 0.50 0.0197 L 0.50 0.70 0.0197 0.0279 0 5 0 5 N 48 CP 48 0.10 0.0039 27/45 M28W160BT, M28W160BB Figure 14. BGA46 6.39x6.37mm - 8 x 6 ball array, 0.75 mm pitch, Bottom View Package Outline D D1 FD SD FE SE E E1 e ddd BALL "A1" e b A A2 A1 BGA-G05 Note: Drawing is not to scale Table 17. BGA46 6.39x6.37mm - 8 x 6 ball array, 0.75 mm pitch, Package Mechanical Data mm inch Symbol Typ Min A Typ Min 1.000 A1 Max 0.0394 0.180 0.0071 A2 0.700 - - 0.0276 - - b 0.350 0.300 0.400 0.0138 0.0118 0.0157 D 6.390 6.340 6.440 0.2516 0.2496 0.2535 D1 5.250 - - 0.2067 - - ddd 28/45 Max 0.008 0.0003 e 0.750 - - 0.0295 - - E 6.370 6.320 6.420 0.2508 0.2488 0.2528 E1 3.750 - - 0.1476 - - FD 0.570 - - 0.0224 - - FE 1.310 - - 0.0516 - - SD 0.375 - - 0.0148 - - SE 0.375 - - 0.0148 - - M28W160BT, M28W160BB Figure 15. BGA46 Daisy Chain - Package Connections (Top view through package) 1 2 3 4 5 6 7 8 A B C D E F AI03298 Figure 16. BGA46 Daisy Chain - PCB Connections proposal (Top view through package) 1 2 3 4 5 6 7 8 START POINT A B C D E END POINT F AI3299 29/45 M28W160BT, M28W160BB Figure 17. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline D D1 FD SD FE SE E E1 e ddd BALL "A1" e b A A2 A1 BGA-Z13 Drawing is not to scale. Table 18. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data millimeters inches Symbol Typ Min A Typ Min 1.200 A1 Max 0.0472 0.200 A2 0.0079 1.000 0.0394 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 D 6.390 6.290 6.490 0.2516 0.2476 0.2555 D1 5.250 - - 0.2067 - - ddd 30/45 Max 0.100 0.0039 E 6.370 6.270 6.470 0.2508 0.2469 0.2547 e 0.750 - - 0.0295 - - E1 3.750 - - 0.1476 - - FD 0.570 - - 0.0224 - - FE 1.310 - - 0.0516 - - SD 0.375 - - 0.0148 - - SE 0.375 - - 0.0148 - - M28W160BT, M28W160BB Figure 18. TFBGA46 Daisy Chain - Package Connections (Top view through package) 1 2 3 4 5 6 7 8 A B C D E F AI03298 Figure 19. TFBGA46 Daisy Chain - PCB Connections proposal (Top view through package) 1 2 3 4 5 6 7 8 START POINT A B C D E END POINT F AI3299 31/45 M28W160BT, M28W160BB PART NUMBERING Table 19. Ordering Information Scheme Example: M28W160BT 90 N 6 T Device Type M28 Operating Voltage W = VDD = 2.7V to 3.6V; VDDQ = 1.65V to 3.6V Device Function 160B = 16 Mbit (x16), Boot Block Array Matrix T = Top Boot B = Bottom Boot Speed 70 = 70 ns 85 = 85 ns 90 = 90 ns 100 = 100 ns Package N = TSOP48: 12 x 20 mm GB = BGA46: 6.39 x 6.37mm, 0.75 mm pitch ZB = TFBGA46: 6.39 x 6.37mm, 0.75 mm pitch Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Option T = Tape & Reel Packing Table 20. Daisy Chain Ordering Scheme Example: M28W160B -GB T Device Type M28W160B Daisy Chain -GB = BGA46: 6.39 x 6.37mm, 0.75 mm pitch -ZB = TFBGA46: 6.39 x 6.37mm, 0.75 mm pitch Option T = Tape & Reel Packing Note:Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 32/45 M28W160BT, M28W160BB REVISION HISTORY Table 21. Document Revision History Date Version Revision Details July 1999 -01 First Issue 9/21/99 -02 Parameter Block Erase Typ. specification change Added tWHGL and tEHGL 10/20/99 -03 BGA Package Mechanical Data change Daisy Chain diagrams, Package and PCB Connections, added 2/09/00 -04 Access Time conditions change Reset mode function change to remove Power Down mode Instructions description clarification Change of Parameter Block Erase value Block Protections description clarification Security Code Area definition change IDD2 and IDD3 value change tPLRH value change Program, Erase, Command Interface flowcharts clarification Package Mechanical Data change BGA Package Outline diagram change 4/19/00 -05 Daisy Chain part numbering defined BGA Daisy Chain diagrams, Package and PCB Connections re-designed 5/17/00 -06 BGA Package Outline diagram change 1/15/01 -07 TFBGA Package added CFI specification clarification 3/06/01 -08 Document type : from Preliminary Data to Data Sheet 70ns Speed Class added 3/12/01 -09 4/13/01 -10 Completely rewritten and restructured, 85ns speed class added. 5/29/01 -11 Corrections made to CFI data. 31-May-2001 -12 Corrections to TFBGA46 package dimensions. 30-Oct-2001 -13 VDDQ Maximum changed to 3.3V Commands Table, Read CFI Query Address on 1st cycle changed to `X' (Table 3) tWHEL description clarified (Table 13) 16-May-2002 -14 VDDQ Maximum changed to 3.6V, TFBGA and BGA package dimensions added to descriptions. 33/45 M28W160BT, M28W160BB APPENDIX A. BLOCK ADDRESS TABLES Table 22. Top Boot Block Addresses, M28W160BT Table 23. Bottom Boot Block Addresses, M28W160BB # Size (KWord) Address Range # Size (KWord) Address Range 0 4 FF000-FFFFF 38 32 F8000-FFFFF 1 4 FE000-FEFFF 37 32 F0000-F7FFF 2 4 FD000-FDFFF 36 32 E8000-EFFFF 3 4 FC000-FCFFF 35 32 E0000-E7FFF 4 4 FB000-FBFFF 34 32 D8000-DFFFF 5 4 FA000-FAFFF 33 32 D0000-D7FFF 6 4 F9000-F9FFF 32 32 C8000-CFFFF 7 4 F8000-F8FFF 31 32 C0000-C7FFF 8 32 F0000-F7FFF 30 32 B8000-BFFFF 9 32 E8000-EFFFF 29 32 B0000-B7FFF 10 32 E0000-E7FFF 28 32 A8000-AFFFF 11 32 D8000-DFFFF 27 32 A0000-A7FFF 12 32 D0000-D7FFF 26 32 98000-9FFFF 13 32 C8000-CFFFF 25 32 90000-97FFF 14 32 C0000-C7FFF 24 32 88000-8FFFF 15 32 B8000-BFFFF 23 32 80000-87FFF 16 32 B0000-B7FFF 22 32 78000-7FFFF 17 32 A8000-AFFFF 21 32 70000-77FFF 18 32 A0000-A7FFF 20 32 68000-6FFFF 19 32 98000-9FFFF 19 32 60000-67FFF 20 32 90000-97FFF 18 32 58000-5FFFF 21 32 88000-8FFFF 17 32 50000-57FFF 22 32 80000-87FFF 16 32 48000-4FFFF 23 32 78000-7FFFF 15 32 40000-47FFF 24 32 70000-77FFF 14 32 38000-3FFFF 25 32 68000-6FFFF 13 32 30000-37FFF 26 32 60000-67FFF 12 32 28000-2FFFF 27 32 58000-5FFFF 11 32 20000-27FFF 28 32 50000-57FFF 10 32 18000-1FFFF 29 32 48000-4FFFF 9 32 10000-17FFF 30 32 40000-47FFF 8 32 08000-0FFFF 31 32 38000-3FFFF 7 4 07000-07FFF 32 32 30000-37FFF 6 4 06000-06FFF 33 32 28000-2FFFF 5 4 05000-05FFF 34 32 20000-27FFF 4 4 04000-04FFF 35 32 18000-1FFFF 3 4 03000-03FFF 36 32 10000-17FFF 2 4 02000-02FFF 37 32 08000-0FFFF 1 4 01000-01FFF 38 32 00000-07FFF 0 4 00000-00FFF 34/45 M28W160BT, M28W160BB APPENDIX B. COMMON FLASH INTERFACE (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query Command (RCFI) is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 24, 25, 26, 27, 28 and 29 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 29, Security Code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read command to return to Read mode. Table 24. Query Structure Overview Offset Sub-section Name Description 00h Reserved Reserved for algorithm-specific information 10h CFI Query Identification String Command set ID and algorithm data offset 1Bh System Interface Information Device timing & voltage information 27h Device Geometry Definition Flash device layout P Primary Algorithm-specific Extended Query table Additional information specific to the Primary Algorithm (optional) A Alternate Algorithm-specific Extended Query table Additional information specific to the Alternate Algorithm (optional) Note: Query data are always presented on the lowest order data outputs. Table 25. CFI Query Identification String Offset Data Description Value 00h 0020h Manufacturer Code 01h 0090h 0091h Device Code 02h-0Fh reserved 10h 0051h Query Unique ASCII String "QRY" "Q" 11h 0052h Query Unique ASCII String "QRY" "R" 12h 0059h Query Unique ASCII String "QRY" "Y" 13h 0003h 14h 0000h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm 15h offset = P = 0035h 16h 0000h 17h 0000h 18h 0000h 19h value = A = 0000h 1Ah 0000h ST Top Bottom Reserved Address for Primary Algorithm extended Query table Intel Compatible P=35h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (note: 0000h means none exists) NA Address for Alternate Algorithm extended Query table note: 0000h means none exists NA Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'. 35/45 M28W160BT, M28W160BB Table 26. CFI Query System Interface Information Offset Data 1Bh 0027h VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV 2.7V 1Ch 0036h VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV 3.6V 1Dh 00B4h VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 11.4V 1Eh 00C6h VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 12.6V 1Fh 0004h Typical timeout per single word program = 2n s 16s 20h 0004h Typical timeout for Double Word Program = 2n s 16s 21h 000Ah Typical timeout per individual block erase = 2n ms 1s 22h 0000h Typical timeout for full chip erase = 2n ms NA 23h 0005h Maximum timeout for word program = 2n times typical 512s 24h 0005h Maximum timeout for Double Word Program = 2n times typical 512s 25h 0003h Maximum timeout per individual block erase = 2n times typical 8s 26h 0000h Maximum timeout for chip erase = 2n times typical NA 36/45 Description Value M28W160BT, M28W160BB Table 27. Device Geometry Definition Data 27h 0015h Device Size = 2n in number of bytes 28h 29h 0001h 0000h Flash Device Interface Code description 2Ah 2Bh 0002h 0000h Maximum number of bytes in multi-byte program or page = 2n 4 2Ch 0002h Number of Erase Block Regions within the device. It specifies the number of regions within the device containing contiguous Erase Blocks of the same size. 2 2Dh 2Eh 001Eh 0000h Region 1 Information Number of identical-size erase block = 001Eh+1 2Fh 30h 0000h 0001h Region 1 Information Block size in Region 1 = 0100h * 256 byte 31h 32h 0007h 0000h Region 2 Information Number of identical-size erase block = 0007h+1 33h 34h 0020h 0000h Region 2 Information Block size in Region 2 = 0020h * 256 byte 2Dh 2Eh 0007h 0000h Region 1 Information Number of identical-size erase block = 0007h+1 2Fh 30h 0020h 0000h Region 1 Information Block size in Region 1 = 0020h * 256 byte 31h 32h 001Eh 0000h Region 2 Information Number of identical-size erase block = 001Eh+1 33h 34h 0000h 0001h Region 2 Information Block size in Region 2 = 0100h * 256 byte M28W160BB M28W160BT Offset Word Mode Description Value 2MByte x16 Async 31 64KByte 8 8KByte 8 8KByte 31 64KByte 37/45 M28W160BT, M28W160BB Table 28. Primary Algorithm-Specific Extended Query Table Offset P = 35h (1) Data (P+0)h = 35h 0050h (P+1)h = 36h 0052h (P+2)h = 37h 0049h (P+3)h = 38h 0031h Major version number, ASCII "1" (P+4)h = 39h 0030h Minor version number, ASCII "0" (P+5)h = 3Ah 0006h (P+6)h = 3Bh 0000h Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte. (P+7)h = 3Ch 0000h (P+8)h = 3Dh 0000h (P+9)h = 3Eh 0001h Description "P" Primary Algorithm extended Query table unique ASCII string "PRI" 0000h (P+B)h = 40h 0000h "R" "I" bit 0 bit 1 bit 2 bit 3 bit 4 bit 31 to 5 Chip Erase supported Erase Suspend supported Program Suspend Lock/Unlock supported Queued Erase supported Reserved; undefined bits are `0' (1 (1 (1 (1 (1 = Yes, 0 = No) = Yes, 0 = No) = Yes, 0 = No) = Yes, 0 = No) = Yes, 0 = No) No Yes Yes No No Supported Functions after Suspend Read Array, Read Status Register and CFI Query are always supported during Erase or Program operation bit 0 bit 7 to 1 (P+A)h = 3Fh Value Program supported after Erase Suspend (1 = Yes, 0 = No) Reserved; undefined bits are `0' Block Lock Status Defines which bits in the Block Status Register section of the Query are implemented. Yes NA bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0' (P+C)h = 41h 0030h VDD Logic Supply Optimum Program/Erase voltage (highest performance) bit 7 to 4 bit 3 to 0 (P+D)h = 42h 00C0h (P+E)h 0000h HEX value in volts BCD value in 100 mV VPP Supply Optimum Program/Erase voltage bit 7 to 4 bit 3 to 0 HEX value in volts BCD value in 100 mV Reserved Note: 1. See Table 25, offset 15h for P pointer definition. Table 29. Security Code Area Offset Data 81h XXXX 82h XXXX 83h XXXX 84h XXXX 38/45 3V Description 64 bits unique device number. 12V M28W160BT, M28W160BB APPENDIX C. FLOWCHARTS AND PSEUDO CODES Figure 20. Program Flowchart and Pseudo Code Start program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10) ; */ Write 40h or 10h writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ Write Address & Data do { status_register=readFlash (any_address) ; /* E or G must be toggled*/ Read Status Register b7 = 1 NO } while (status_register.b7== 0) ; YES b3 = 0 NO VPP Invalid Error (1, 2) if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.b4==1) /*program error */ error_handler ( ) ; NO Program to Protected Block Error (1, 2) YES b4 = 0 YES b1 = 0 if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; YES End } AI03538b Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 39/45 M28W160BT, M28W160BB Figure 21. Double Word Program Flowchart and Pseudo Code Start Write 30h double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (any_address, 0x30) ; writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/ Write Address 1 & Data 1 (3) Write Address 2 & Data 2 (3) do { status_register=readFlash (any_address) ; /* E or G must be toggled*/ Read Status Register b7 = 1 NO } while (status_register.b7== 0) ; YES b3 = 0 NO VPP Invalid Error (1, 2) if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.b4==1) /*program error */ error_handler ( ) ; NO Program to Protected Block Error (1, 2) YES b4 = 0 YES b1 = 0 if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; YES End } AI03539b Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0. 40/45 M28W160BT, M28W160BB Figure 22. Program Suspend & Resume Flowchart and Pseudo Code Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; Write B0h writeToFlash (any_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (any_address) ; /* E or G must be toggled*/ Read Status Register b7 = 1 NO } while (status_register.b7== 0) ; YES b2 = 1 NO Program Complete YES Write FFh } Read data from another address Write D0h if (status_register.b2==0) /*program completed */ { writeToFlash (any_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/ else { writeToFlash (any_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ } Write FFh } Program Continues Read Data AI03540b 41/45 M28W160BT, M28W160BB Figure 23. Erase Flowchart and Pseudo Code Start erase_command ( blockToErase ) { writeToFlash (any_address, 0x20) ; Write 20h writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */ Write Block Address & D0h do { status_register=readFlash (any_address) ; /* E or G must be toggled*/ Read Status Register b7 = 1 NO } while (status_register.b7== 0) ; YES b3 = 0 NO VPP Invalid Error (1) YES Command Sequence Error (1) if (status_register.b3==1) /*VPP invalid error */ error_handler ( ) ; YES b4, b5 = 1 if ( (status_register.b4==1) && (status_register.b5==1) ) /* command sequence error */ error_handler ( ) ; NO b5 = 0 NO Erase Error (1) if ( (status_register.b5==1) ) /* erase error */ error_handler ( ) ; YES b1 = 0 NO Erase to Protected Block Error (1) if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; YES End } AI03541b Note: If an error is found, the Status Register must be cleared before further Program/Erase operations. 42/45 M28W160BT, M28W160BB Figure 24. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h erase_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (any_address, 0x70) ; /* read status register to check if erase has already completed */ Write 70h Read Status Register b7 = 1 do { status_register=readFlash (any_address) ; /* E or G must be toggled*/ NO } while (status_register.b7== 0) ; YES b6 = 1 NO Erase Complete if (status_register.b6==0) /*erase completed */ { writeToFlash (any_address, 0xFF) ; YES read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/ Write FFh Read data from another block or Program } else Write D0h Write FFh Erase Continues Read Data { writeToFlash (any_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume erase*/ } } AI03549b 43/45 M28W160BT, M28W160BB APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE Table 30. Write State Machine Current/Next Command Input (and Next State) Current State SR bit 7 Data When Read Read Array "1" Read Status Erase Confirm (D0h) Program/ Program/ Erase Erase Suspend Resume (B0h) (D0h) Read Array (FFh) Program Setup (10/40h) Erase Setup (20h) Array Read Array Program Setup Erase Setup "1" Status Read Array Program Setup Read Elect.Sg. "1" Electronic Signature Read Array Program Setup Program Setup "1" Status Program (Command input = Data to be Programmed) Program Suspend to Read Status Read Status (70h) Clear Status (50h) Read Elect.Sg. (90h) Read Array Read Status Read Array Read Elect.Sg. Erase Setup Read Array Read Status Read Array Read Elect.Sg. Erase Setup Read Array Read Status Read Array Read Elect.Sg. Program (continue) "0" Status Program Suspend to Read Status "1" Status Program Suspend to Read Array Program Suspend to Read Array Program (continue) Program Suspend to Read Array Program (continue) Program Suspend to Read Status Program Suspend to Read Array Program Suspend to Read Elect.Sg. Program Suspend to Read Array "1" Array Program Suspend to Read Array Program Suspend to Read Array Program (continue) Program Suspend to Read Array Program (continue) Program Suspend to Read Status Program Suspend to Read Array Program Suspend to Read Elect.Sg. Program Suspend to Read Elect.Sg. "1" Electronic Signature Program Suspend to Read Array Program Suspend to Read Array Program (continue) Program Suspend to Read Array Program (continue) Program Suspend to Read Status Program Suspend to Read Array Program Suspend to Read Elect.Sg. Program (complete) "1" Status Read Array Read Status Read Array Read Elect.Sg. Erase Setup "1" Status Erase Cmd. Error "0" Status Program (continue) Program Setup Erase Setup Erase Command Error Read Array Program Setup Program (continue) Read Array Erase Erase Erase Command (continue) (continue) Error Erase Setup Erase Command Error Read Status Read Array Erase Suspend to Read Status Read Array Read Elect.Sg. Erase (continue) "1" Status Erase Suspend to Read Status "1" Status Erase Suspend to Read Array Program Setup Erase Suspend to Read Array Erase (continue) Erase Suspend to Read Array Erase (continue) Erase Suspend to Read Status Erase Suspend to Read Array Erase Suspend to Read Elect.Sg. Erase Suspend to Read Array "1" Array Erase Suspend to Read Array Program Setup Erase Suspend to Read Array Erase (continue) Erase Suspend to Read Array Erase (continue) Erase Suspend to Read Status Erase Suspend to Read Array Erase Suspend to Read Elect.Sg. Erase Suspend to Read Elect.Sg. "1" Electronic Signature Erase Suspend to Read Array Program Setup Erase Suspend to Read Array Erase (continue) Erase Suspend to Read Array Erase (continue) Erase Suspend to Read Status Erase Suspend to Read Array Erase Suspend to Read Elect.Sg. Erase (complete) "1" Status Read Array Program Setup Erase Setup Read Status Read Array Read Elect.Sg. Erase (continue) Note: Elect.Sg. = Electronic Signature. 44/45 Read Array Erase (continue) M28W160BT, M28W160BB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 45/45