ESDU3121MXT5G - APTINA IMAGING

September, 2018 − Rev. 1 1Publication Order Number:

ESDU3121/D

ESDU3121

12 V Unidirectional ESD and

Surge Protection Device

The ESDU3121 is designed to protect voltage sensitive components

from ESD. Excellent clamping capability, low leakage, high peak

pulse current handling capability and fast response time provide best

in class protection on designs that are exposed to ESD. Because of its

small size, it is suited for use in cellular phones, tablets, MP3 players,

digital cameras and many other portable applications where board

space comes at a premium.

Features

•Low Clamping Voltage

•Low Leakage

•Small Body Outline: 1.0 mm x 0.6 mm

•Protection for the Following IEC Standards:

IEC61000−4−2 Level 4: ±30 kV Contact Discharge

IEC61000−4−5 (Lightning): 8.5 A (8/20 ms)

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

•Power Line Protection

•GPIO Protection

Table 1. MAXIMUM RATINGS

Rating Symbol Value Unit

IEC 61000−4−2 (ESD)

Contact ±30 kV

Air ±30

Operating Junction Temperature

Range TJ−65 to + 150 °C

Storage Temperature Range TSTG −65 to + 150 °C

Minimum Peak Pulse Current IPP 8.5 A

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be af fected.

CATHODE 2

ANODE

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Device Package Shipping†

ORDERING INFORMATION

ESDU3121MXT5G X2DFN2

(Pb−Free) 8000 / Tape &

Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer t o our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

X2DFN2

CASE 714AB

MARKING

DIAGRAM

YK = Specific Device Code

M = Date Code

YK M

ESDU3121

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Table 2. ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol Parameter

IPP Maximum Reverse Peak Pulse Current

VCClamping Voltage @ IPP

VRWM Working Peak Reverse Voltage

IRMaximum Reverse Leakage Current @ VRWM

VBR Breakdown Voltage @ IT

ITTest Current

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

Uni−Directional Surge Protection

IPP

VRWM

VCVBR VF

Table 3. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)

Parameter Symbol Conditions Min Typ Max Unit

Reverse Working Voltage VRWM I/O Pin to GND 12 V

Breakdown Voltage VBR IT = 1 mA, I/O Pin to GND 14.1 15 15.8 V

Reverse Leakage Current IR@ VRWM, I/O Pin to GND 0.1 mA

Reverse Peak Pulse Current IPP IEC−61000−4−5 (8x20 ms) 8.5 A

Clamping Voltage 8x20 ms

Waveform per Figure 3 VCIPP = 8.5 A 20.3 22 V

Dynamic Resistance RDYN I/O Pin to GND, IEC−61000−4−5 (8x20 ms) 0.70 W

Junction Capacitance CJVR = 0 V, f = 1 MHz 55 pF

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

ESDU3121

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TYPICAL CHARACTERISTICS

Figure 1. ESD Clamping Voltage Positive 8 kV

Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Negative 8 kV

Contact per IEC61000−4−2

TIME (ns) TIME (ns)

Figure 3. 8 x 20 ms Pulse Waveform Figure 4. Positive Clamping Voltage vs. Peak

Pulse Current (tp = 8/20 ms)

IPK (A)

Figure 5. Line Capacitance, ƒ = 1MHz Figure 6. Positive TLP I−V Curve

VBIAS (V) VCLTP (V)

VOLTAGE (V)

VOLTAGE (V)VC @ IPK (V)

C (pF)

ITLP (A)

100

0020406080

t, TIME (ms)

% OF PEAK PULSE CURRENT

PULSE WIDTH (tP) IS DEFINED

AS THAT POINT WHERE THE

PEAK CURRENT DECAY = 8 ms

PEAK VALUE IRSM @ 8 ms

HALF VALUE IRSM/2 @ 20 ms

−10

−20 0 20 40 60 80 100 120 140 −40

−30

−20

−10

−20 0 20 40 60 80 100 120 140

024681012

0 1 2 3 4 5 6 7 8 9 10 11 12 0

0 5 10 15 20 25

VIEC (kV)

ESDU3121

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Transmission Line Pulse (TLP) Measurement

Transmission Line Pulse (TLP) provides current versus

voltage (I−V) curves in which each data point is obtained

from a 100 ns long rectangular pulse from a charged

transmission line. A simplified schematic of a typical TLP

system is shown in Figure 7. TLP I−V curves of ESD

protection devices accurately demonstrate the product’s

ESD capability because the 10s of amps current levels and

under 100 ns time scale match those of an ESD event. This

is illustrated in Figure 8 where an 8 kV IEC 61000−4−2

current waveform is compared with TLP current pulses at

8 A and 16 A. A TLP I−V curve shows the voltage at which

the device turns on as well as how well the device clamps

voltage over a range of current levels. For more information

on TLP measurements and how to interpret them please

refer to AND9007/D.

Figure 7. Simplified Schematic of a Typical TLP

System

DUT

LS÷

Oscilloscope

Attenuator

10 MW

50 W Coax

Cable

50 W Coax

Cable

Figure 8. Comparison Between 8 kV IEC 61000−4−2

and 8 A and 16 A TLP Waveforms

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the

voltage that an IC will be exposed to during an ESD event

to as low a voltage as possible. The ESD clamping voltage

is the voltage drop across the ESD protection diode during

an ESD event per the IEC61000−4−2 waveform. Since the

IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not

clearly defined in the spec how to specify a clamping voltage

at the device level. ON Semiconductor has developed a way

to examine the entire voltage waveform across the ESD

protection diode over the time domain of an ESD pulse in the

form of an oscilloscope screenshot, which can be found on

the datasheets for all ESD protection diodes. For more

information on how ON Semiconductor creates these

screenshots and how to interpret them please refer to

AND8307/D.

IEC 61000−4−2 Spec.

Level Test Volt-

age (kV)

First Peak

Current

(A) Current at

30 ns (A) Current at

60 ns (A)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

Ipeak

90%

10%

IEC61000−4−2 W aveform

100%

I @ 30 ns

I @ 60 ns

tP = 0.7 ns to 1 ns

Figure 9. IEC61000−4−2 Spec

50 W

Cable

DUT Oscilloscope

ESD Gun

Figure 10. Diagram of ESD Test Setup

X2DFN2 1.0x0.6, 0.65P

CASE 714AB

ISSUE B DATE 21 NOV 2017

SCALE 8:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. EXPOSED COPPER ALLOWED AS SHOWN.

A B

BOTTOM VIEW

0.10 C

T OP VIEW

0.05 C

0.10 C

CSEATING

PLANE

SIDE VIEW

DIM MIN NOM

MILLIMETERS

A0.34 0.37

A1 −−− 0.03

b0.45 0.50

SOLDER FOOTPRINT*

DIMENSIONS: MILLIMETERS

1.20

0.60

L0.20 0.25

0.47

RECOMMENDED

PIN 1

INDICATOR

e0.65 BSC

0.05 BC

e/2

2X 2X

GENERIC

MARKING DIAGRAM*

XX = Specific Device Code

M = Date Code

XX M

NOTE 3

*This information is generic. Please refer to de-

vice data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present. Some products

may not follow the Generic Marking.

0.95 1.00

0.55 0.60

MAX

0.40

0.05

0.55

0.30

1.05

0.65

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

http://onsemi.com

October, 2002 − Rev. 0 Case Outline Number:

XXX

DOCUMENT NUMBER:

STATUS:

NEW STANDARD:

DESCRIPTION:

98AON98172F

ON SEMICONDUCTOR STANDARD

X2DFN2 1.0X0.6, 0.65P

Electronic versions are uncontrolled except when

acc essed d irectly fr om the Doc ument Reposit ory. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

PAGE 1 OF 2

DOCUMENT NUMBER:

98AON98172F

PAGE 2 OF 2

November, 2017 − Rev. B Case Outline Number

714AB

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