Features
•High-performance, Low-power 8/16 -bit AVR XMEGA Microcontroller
•Non-volatile Program and Data Memories
– 64 KB - 256 KB of In-System Self-Programmable Flash
– 4 KB - 8 KB Boot Code Section with Independent Lock Bits
– 2 KB - 4 KB EEPROM
– 4 KB - 16 KB Internal SRAM
•Peripheral Features
– Four-channel DMA Controller with support for external requests
– Eight-channel Event System
– Seven 16-bit Timer/Counters
Four Timer/Counters with 4 Output Compare or Input Captu r e channels
Three Timer/Counters with 2 Output Compare or Input Capture channels
High Resolution Exten s ions on all Timer/Co unters
Advanced Waveform Extensio n on one Timer/Cou nter
– Seven USARTs
IrDA Extension on 1 USART
– AES and DES Crypto Engine
– Two Two-wire Interfaces with dual address match(I2C and SMBus compatible)
– Three SPI (Serial Peripheral Interfaces)
– 16-bit Real Time Counter with Separate Oscillator
– Two Eight-channel, 12-bit, 2 Msps Analog to Digital Conver ters
– One Two-channel, 12-bit, 1 Msps Digital to Analog Converter
– Four Analog Comparators with Window compare function
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
•Special Microcontroller Features
– Power -on Reset and Pr ogrammabl e Brown-out Detection
– Internal and External Cloc k Option s with PLL
– Programmable Multi-level Interrupt Controller
– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
– Advanced Programming, Test and Debugging Interfaces
JTAG (IEEE 1149.1 Compliant) Interface for test, debug and programming
PDI (Program and Debug Interface) f o r programming, test and debu gging
•I/O and Pac kages
– 50 Programmable I/O Lines
– 64-lead TQFP
– 64-pad QFN
•Operatin g Voltage
– 1.6 – 3.6V
•Speed performance
– 0 – 12 MHz @ 1.6 – 3.6V
– 0 – 32 MHz @ 2.7 – 3.6V
Typical Applications
•Industrial control •Climate co ntrol •Hand-held battery applications
•Factory automation •ZigBee •Power tools
•Building control •Motor control •HVAC
•Boar d cont rol •Networking •Metering
•White Goods •Optical •Medical Applications
8/16-bit
XMEGA A3
Microcontroller
ATxmega256A3
ATxmega192A3
ATxmega128A3
ATxmega64A3
Preliminary
8068K–AVR–02/09
2
8068K–AVR–02/09
XMEGA A3
1. Ordering Information
Notes: 1. This device can also be supplied i n wafer form. Please contact your lo cal Atmel sales office for detailed ordering information.
2. Pb-free packaging, complies to the Europea n Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
3. For packaging information, see ”Packaging information” on page 63.
2. Pinout/Block Diagram
Figure 2-1. Block diagram and pin o ut.
Note: 1. For full details on pinout and alternate pin functions refer to ”Pinout and Pin Functions” on page 48.
Ordering Code Flash E2SRAM Speed (MHz) Power Supply Package(1)(2)(3) Temp
ATxmega256A3-AU 256 KB + 8 KB 4 KB 16 KB 32 1.6 - 3.6V
64A
-40°C - 85°C
ATxmega192A3-AU 192 KB + 8 KB 4 KB 16 KB 32 1.6 - 3.6V
ATxmega128A3-AU 128 KB + 8 KB 2 KB 8 KB 32 1.6 - 3.6V
ATxmega64A3-AU 64 KB + 4 KB 2 KB 4 KB 32 1.6 - 3.6V
ATxmega256A3-MU 256 KB + 8 KB 4 KB 16 KB 32 1.6 - 3.6V
64M2
ATxmega192A3-MU 192 KB + 8 KB 4 KB 16 KB 32 1.6 - 3.6V
ATxmega128A3-MU 128 KB + 8 KB 2 KB 8 KB 32 1.6 - 3.6V
ATxmega64A3-MU 64 KB + 4 KB 2 KB 4 KB 32 1.6 - 3.6V
Package Type
64A 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
64M2 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 7.65 mm Exposed Pad, Quad Flat No-L ead Package (QFN)
INDEX CORNER
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PF2
PF1
PF0
VCC
GND
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
VCC
GND
PD7
PA 3
PA 4
PA 5
PA 6
PA 7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
GND
VCC
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
GND
VCC
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PA 2
PA 1
PA 0
AVCC
GND
PR1
PR0
RESET/PDI_CLK
PDI_DATA
PF7
PF6
VCC
GND
PF5
PF4
PF3
FLASH
RAM
E
2
PROM
DMA
Interrupt Controller
OCD
ADC A
ADC B
DAC B
AC A0
AC A1
AC B0
AC B1
Por t A
Por t B
Event System ctrl
Por t R
Power
Control
Reset
Control
Watchdog
OSC/CLK
Control BOD POR
RTC
EVENT ROUTING NETWORK
DATA BU S
DATA BU S
VREF
TEMP
Port C Port D Port E Port F
CPU
T/C0:1
USART0:1
SPI
TWI
T/C0:1
USART0:1
SPI
T/C0:1
USART0:1
SPI
TWI
T/C0
USART0
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8068K–AVR–02/09
XMEGA A3
3. Overview
The XMEGA A3 is a family of low power, high perfor mance and peripheral rich CMOS 8/16-bit
microcontrollers based on the AVR® enhanced RISC architecture. By executing powerful
instructions in a single clock cycle, the XMEGA A3 achieves throughputs approaching 1 Million
Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power con-
sumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction, executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs many times faster than conven-
tional single-accumulator or CISC based microcontrollers.
The XMEGA A3 devices provide the following features: In-System Programmable Flash with
Read-While-Write capabilities, Internal EEPROM and SRAM, four-channe l DMA Controller,
eight-channel Event System, Programmable Multi-level Interrupt Controller, 50 general purpose
I/O lines, 16-bit Real Time Counter (RTC), seven flexible 16-bit Timer/Counters with compare
modes and PWM, seven USARTs, two Two Wire Serial Interfaces (TWIs), three Serial Periph-
eral Interfaces (SPIs), AES and DES crypto engine, two 8-channel 12-bit ADCs with optional
differential input with programmable gain, one 2-channel 12-bit DACs, four analog comparators
with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate
internal oscillators with PLL and prescaler and programmable Brown-Out Detection.
The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,
is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this
can also be used for On-chip Debug and programming.
The XMEGA A3 devices have five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and
all peripherals to continue functioning. Th e Power-down mode saves the SRAM and register
contents but stops the oscillators, disabling all other functions until the next TWI or pin-change
interrupt, or Reset. In Power-sa ve mod e, the asynchrono us Real Time Count er contin ues to run,
allowing the application to maintain a timer base while the rest of the device is sleeping. In
Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is
sleeping. This allows very fast start-up from external crystal combined wit h low power consump-
tion. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue
to run. To fu rther re duce pow er consum ption, the peripher al clock for each indiv idual perip heral
can optionally be stopped in Active mode and Idle sleep mode.
The device is manu factured using Atmel's high-d ensity nonvolat ile memory techno logy. The pr o-
gram Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader
running in the de vice can use any interface to download th e application program to the Fla sh
memory. The Bootloader software in the Boot Flash section will continue to run while the Appli-
cation Flash section is updated, providing true Read-While-Write operation. By combining an
8/16-bit RISC CPU with In-System Se lf-P rogr ammab le F las h, th e Atmel XMEGA A3 is a power-
ful microcontroller family that provides a highly flexible and cost effe ctive solution for many
embedded applications.
The XMEGA A3 devices are supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simula tors, programmers,
and evaluation kits.
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8068K–AVR–02/09
XMEGA A3
3.1 Block Diagram
Figure 3-1. XMEGA A3 Block Diagram
PE[0..7]
PORT E (8)
TCE0:1
USARTE0:1
TWIE
SPIE
TCF0
USARTF0
PORT F (8)
Power
Supervision
POR/BOD &
RESET
PORT A (8)
PORT B (8)
DMA
Controller
BUS
Controller
SRAM
ADCA
ACA
DACB
ADCB
ACB
OCD
PDI
CPU
PA[0..7]
PB[0..7]/
JTAG
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
DATA BUS
Prog/Debug
Controller
VCC
GND
Oscillator
Circuits/
Clock
Generation
Oscillator
Control
Real Time
Counter
Event Syst em
Controller
JTAG
PDI_DATA
RESET/
PDI_CLK
PORT B
Sleep
Controller
Flash EEPROM
NVM Controller
DES
AES
IRCOM
PORT C (8)
PC[0..7]
TCC0:1
USARTC0:1
TWIC
SPIC
PD[0..7]
PORT R (2)
XTAL1
XTAL2
PR[0..1]
PORT D (8)
TCD0:1
USARTD0:1
SPID
TOSC1
TOSC2
EVENT ROUTING NETWORK
PF[0..7]
To Clock
Generator
Int. Ref.
AREFA
AREFB
Tempref
VCC/10
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8068K–AVR–02/09
XMEGA A3
4. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
4.1 Recommended reading
• XMEGA A Manual
• XMEGA A Application Notes
This device data shee t only contains part specific inf ormation and a short de scription of each
peripheral and module. The XMEGA A Manual describes the modules and peripherals in depth.
The XMEGA A application notes contain example code and show applied use of the modules
and peripherals.
The XMEGA A Manual and Application Notes are available from http://www.atmel.com/avr.
5. Disclaimer
For devices that are not available yet, typical values contained in this datasheet are based on
simulations and characterization of other AVR XMEGA microcontrollers manufactured on the
same process technology. Min. and Max values will be available after the device is
characterized.
6
8068K–AVR–02/09
XMEGA A3
6. AVR CPU
6.1 Features •8/16-bit high performance AVR RISC Architecture
– 138 instructions
– Hardware multiplier
•32x8-bit registers directly connected to the ALU
•Stack in RAM
•Stack Pointer accessible in I/O memory space
•Direct addressing of up to 16M b ytes of program and data memory
•True 16/24-bit access to 16/24-bit I/O registers
•Support for 8-, 16- and 32-bit Arithmetic
•Configuration Change Protection of system critical features
6.2 Overview
The XMEGA A3 uses an 8/16-bit AVR CPU. The main fu nction of th e AVR CPU is to ensu re cor-
rect program execution. The CPU must therefore be able to access memories, perform
calculations and control peripherals. Interrupt handling is described in a separate section. Figure
6-1 on page 6 shows the CPU block diagram.
Figure 6-1. CPU block diagram
The AVR uses a Harvard architecture - with separate memories and buses for program and
data. Instructions in the program memory are executed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program me mory.
Flash
Program
Memory
Instruction
Decode
Program
Counter
OCD
32 x 8 General
Purpose
Registers
ALU Multiplier/
DES
Instruction
Register
STATUS/
CONTROL
Peripheral
Module 1 Peripheral
Module 2 EEPROM PMICSRAM
DATA BUS
DATA BUS
7
8068K–AVR–02/09
XMEGA A3
This concept enables instructions to be executed in every clock cycle. The program memory is
In-System Re-programmable Flash memory.
6.3 Register File
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Re gister File - in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing - enablin g efficient address calculations. One of thes e address pointers can
also be used as an address pointer for look up tables in Flash program memory.
6.4 ALU - Arithmetic Logic Unit
The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations
between registers or between a constant and a register. Single register operations can also be
executed. Within a single clock cycle, arithmetic operations between general purpose registers
or between a register and an immediate are executed. After an arithmetic or logic operation, the
Status Register is updated t o reflect information about the result of the operation.
The ALU operations are divided into three main categories – arithmetic, logical, and bit-func-
tions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy
implementation of 32-bit arithmetic. The ALU also provides a powerful multiplier supporting both
signed and unsigned multiplication and fractional format.
6.5 Program Flow
When the device is powered on, the CPU starts to execute instructions from the lowest address
in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to
be fetched. After a re se t, the PC is set to locatio n ‘0’.
Program flow is provided by conditional and unconditional jump and call instructions, capable of
addressing the whole address space directly. Most AVR instructions use a 16-bit word format,
while a limited number uses a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack
is effectively allocated in the general d ata SRAM, and conseque ntly the Stack size is only limited
by the total SRAM size and the usage of the SRAM. After reset th e Stack Poin ter (SP) points to
the highest address in th e internal SRAM. The SP is read/write accessib le in the I/O memory
space, enabling easy imp lementation of multiple stacks or stack areas. The data SRAM can
easily be acces se d th ro ug h th e five diffe re n t ad dressing modes supp orted in the AVR CPU.
8
8068K–AVR–02/09
XMEGA A3
7. Memories
7.1 Features •Flash Program Memory
– One linear address space
– In-System Programmable
– Self-Programming and Bootloader support
– Applica tio n Se ction for appl ic ation code
– Application Tab le Section for application code or data storage
– Boot Section for application code or bootloader code
– Separate lock bits and protection for all sections
– Built in fast CRC check of a selectable flash program memory section
•Data Memory
– One linear address space
– Single cycle access from CPU
– SRAM
– EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
– I/O Memory
Configuration and Status registers for all periphe rals and modules
16 bit-accessible General Purpose Register for global variables or flags
– Bus arbitration
Safe and deterministic handling of CPU and DMA Controller priority
– Separate buses for SRAM, EEPROM, I/O Memory and External Memory access
Simultaneous bus access for CPU and DMA Controller
•Production Signature Row Memory for factory programmed data
Device ID for each microcontroller device type
Serial number for each device
Oscillator calibration bytes
ADC, DAC and temperature sensor ca libration data
•User Signature Row
One flash page in size
Can be read and writte n from software
Content is kept after chip erase
7.2 Overview
The AVR architecture has two main memory spaces, the Program Memory and the Data Mem-
ory. In addition, the XMEGA A3 features an EEPROM Memory for non-volatile data storage. All
three memory spaces are linear and require no paging. The available memory size configura-
tions are shown in ”Ordering Information” on page 2. In addition each device has a Flash
memory signature row for calibration data, device identification, serial number etc.
Non-volatile memory spaces can be locked for further write or read/write operations. This pre-
vents unrestricted access to the application software.
9
8068K–AVR–02/09
XMEGA A3
7.3 In-System Programmable Flash Program Memory
The XMEGA A3 devices contains On-chip In-System Programmable Flash memory for program
storage, see Figur e 7-1 on page 9. Since all AVR instr uctions are 16- or 32- bits wide, each Flash
address locatio n is 16 bits.
The Program Flash memory space is divided into Application and Boot sections. Both se ctions
have dedicate d Lock Bits for setting re strict ions on write or read/writ e operations. The Store Pro-
gram Memory (SPM) instruction must reside in the Boot Section when used to write to the Flash
memory.
A third section inside the App lication section is referred t o as the Applicat ion Table section which
has separate Lock bits for storage of write or read/write protection. The Application Table sec-
tion can be used for sto rin g no n- vo lat ile da ta or ap plic at ion soft wa re .
The Application Table Section and Boot Section can also be used for general application
software.
Figure 7-1. Flash Program Memory (Hexadecimal address)
Word Address
0Application Section
(256 KB/192 KB/128 KB/64 KB)
...
1EFFF / 16FFF / EFFF / 77FF
1F000 / 17000 / F000 / 7800 Application Table Section
(8 KB/8 KB/8 KB/4 KB)
1FFFF / 17FFF / FFFF / 7FFF
20000 / 18000 / 10000 / 8000 Boot Section
(8 KB/8 KB/8 KB/4 KB)
20FFF / 18FFF / 10FFF / 87FF
10
8068K–AVR–02/09
XMEGA A3
7.4 Data Memory
The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one lin-
ear address space, see Figur e 7-2 on pag e 10. To simplify development, the memory map for all
devices in the family is identical and with empty, reserved memory space for smaller devices.
Figure 7-2. Data Memory Map (Hexadecima l address)
Byte Address ATxmega192A3 Byte Address ATxmega128A3 Byte Address ATxmega64A3
0I/O Registers
(4 KB) 0I/O Registers
(4 KB) 0I/O Registers
(4 KB)
FFF FFF FFF
1000 EEPROM
(4 KB)
1000 EEPROM
(2 KB) 1000 EEPROM
(2 KB)
17FF 17FF
1FFF RESERVED RESERVED
2000 Internal SRAM
(16 KB) 2000 Internal SRAM
(8 KB) 2000 Internal SRAM
(4 KB)
5FFF 3FFF 2FFF
Byte Address ATxmega256 A3
0I/O Registers
(4 KB)
FFF
1000 EEPROM
(4 KB)
1FFF
2000 Internal SRAM
(16 KB)
5FFF
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8068K–AVR–02/09
XMEGA A3
7.4.1 I/O Memory
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, tran sferring data between the 32 general purpo se registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The va lue of single bits can be checked by usin g the SBIS and SBIC instruc-
tions on these registers.
The I/O memory address for all peripherals and modules in XMEGA A3 is shown in the ”Periph-
eral Module Address Map” on page 53.
7.4.2 SRAM Data Memor y
The XMEGA A3 devices have internal SRAM me mory for data storage.
7.4.3 EEPROM Data Memory
The XMEGA A3 devices have internal EEPROM memory for non-volatile data storage. It is
addressable either in a sep arate data space or it can be memory mapped into the normal data
memory space. The EEPROM memory supports both byte and page access.
12
8068K–AVR–02/09
XMEGA A3
7.5 Production Signature Row
The Production Signature Row is a separate memory section for factory programmed data. It
contains calibration data for functions such as oscillators and analog modules.
The production signature row also contains a device ID that identify each microcontroller device
type, and a serial number that is unique for each manufactured device. The device ID for the
available XMEGA A3 devices is shown in Table 7-1 on page 12. The serial num ber consist of
the production LOT number, wafer number, and wafer coordinates for the device.
The production signature row can not be written or erased, but it can be read from both applica-
tion software and external programming.
Table 7-1. Device ID bytes for XMEGA A3 devices.
7.6 User Signature Row
The User Signature Row is a separate me mory section that is fully accessible (read and write)
from application software and external programming. The user signature row is one flash page
in size, and is meant for static user parameter storage, such as calibration data, custom serial
numbers or ident ification numbers, random number seeds etc. This section is not erased by
Chip Erase commands that erase the Flash, and requires a dedicated erase command. This
ensures para meter storage during multiple program/erase session and on-chip debug sessions.
Device Device ID bytes
Byte 2 Byte 1 Byte 0
ATxmega64A3 42 96 1E
ATxmega128A3 42 97 1E
ATxmega192A3 44 97 1E
ATxmega256A3 42 98 1E
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8068K–AVR–02/09
XMEGA A3
7.7 Flash and EEPROM Page Siz e
The Flash Program Memory and EEPROM data memory are organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 13 shows the Flash Program Memory organization. Flash write and erase
operations are performed on one page at the time, while reading the Flash is done one byte at
the time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant
bits in the address (FPAGE) gives the page number and the least significant address bits
(FWORD) gives the word in the page.
Table 7-2. Number of words and Pages in the Flash.
Table 7-3 on page 13 shows EEPROM memory organization for the XMEGA A3 devices.
EEEPROM write and erase operations can be performed one page or one byte at the time, while
reading the EEPROM is done one byte at the time. For EEPROM access the NVM Address
Register (ADDR[m:n] ) is used for addr essing. The most significant bit s in the addr ess (E2PAGE)
gives the page number and the least significant address bits (E2BYTE) gives the byte in the
page.
Table 7-3. Number of bytes and Pages in the EEPROM.
Devices Flash Page Size FWORD FPAGE Application Boot
Size (words) Size No of Pages Size No of Pages
ATxmega64A3 64 KB + 4 KB 128 Z[7:1] Z[16:8] 64K 256 4 KB 16
ATxmega128A3 128 KB + 8 KB 256 Z[8:1] Z[17:9] 128K 256 8 KB 16
ATxmega192A3 192 KB + 8 KB 256 Z[8:1] Z[18:9] 192K 384 8 KB 16
ATxmega256A3 256 KB + 8 KB 256 Z[8:1] Z[18:9] 256K 512 8 KB 16
Devices EEPROM Page Size E2BYTE E2PAGE No of Pages
Size (Bytes)
ATxmega64A3 2 KB 32 ADDR[4:0] ADDR[10:5] 64
ATxmega128A3 2 KB 32 ADDR[4:0] ADDR[10:5] 64
ATxmega192A3 2 KB 32 ADDR[4:0] ADDR[10:5] 64
ATxmega256A3 4 KB 32 ADDR[4:0] ADDR[11:5] 128
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8068K–AVR–02/09
XMEGA A3
8. DMAC - Direct Memory Access Controller
8.1 Features
•Allows High-speed data transfer
– From memory to peripheral
– From memory to memory
– From peripheral to memory
– From peripheral to peripheral
•4 Channels
•From 1 byte and up to 16 M bytes transfers in a single transa ction
•Multiple addressing modes for source and destination address
–Increment
– Decrement
– Static
•1, 2, 4, or 8 bytes Burst Transfers
•Programmable priority between channels
8.2 Overview
The XMEGA A3 has a Direct Memory Access (DMA) Con troller to move data bet ween memories
and peripherals in the data space. The DMA controller uses the same data bus as the CPU to
transfer data.
It has 4 channels that can be configured independently. Each DMA channel can perform data
transfers in blocks of configurable size from 1 to 64K bytes. A repeat counter can be used to
repeat each block transfer for single transactions up to 16M bytes. Each DMA channel can be
configured to a ccess the source and d estination m emory address with i ncrementing, d ecrement-
ing or static addressing. The addressing is independent for source and destination address.
When the transaction is complete the original source and destination address can automatically
be reloaded to be ready for the next transact ion.
The DMAC can access all t he per iph erals t hroug h t hei r I/ O m emory r egist ers, a nd th e DMA m ay
be used for automatic transfer of data to/from communication modules, as well as automatic
data retrieval from ADC conversions, data transfer to DAC conversions, or data transfer to or
from port pins. A wide range of transfer triggers is available from the peripherals, Event System
and software. Each DMA channel has different transfer tr iggers.
To allow for continuous transfers, two channels can be interlinked so that the second takes over
the transfer when the first is finished and vice versa.
The DMA controller can read from memory mapped EEPROM, but it cannot write to the
EEPROM or access the Flash.
15
8068K–AVR–02/09
XMEGA A3
9. Event System
9.1 Features
•Inter-peripheral communication and signalling with minimum latency
•CPU and DMA independent operation
•8 Event Channels allows for up to 8 signals to be routed at the same time
•Events can be generated by
– Timer/Counters (TCxn)
– Real Time Counter (RTC)
– Analog to Digital Con v erters (ADCx)
– Analog Comparator s (ACx)
– Ports (PORTx)
– System Clock (ClkSYS)
– Software (CPU)
•Events can be used by
– Timer/Counters (TCxn)
– Analog to Digital Con v erters (ADCx)
– Digital to Analog Converters (D ACx)
– Ports (PORTx)
– DMA Controller (DMAC)
– IR Communication Module (IRCOM)
•The same event can be used by multiple peripherals for synchronized timing
•Adv a nced Features
– Manual Event Generation from software (CPU)
– Quadrature Decoding
– Digital Filtering
•Functions in Active and Idle mode
9.2 Overview
The Event System is a set of feature s for inter-pe ripheral communicat ion. It enab les the possibil-
ity for a change of state in one peripheral to automatically trigger actions in one or more
peripherals. What changes in a peripheral that will trigger actions in other peripherals are config-
urable by software. It is a simple, but powerful system as it allows for autonomous control of
peripherals without any use of interrupts, CPU or DMA resources.
The indication of a change in a peripheral is referred to as an event, and is usually the same as
the interrupt conditions for that per ipheral. Events are passed between peripherals using a dedi-
cated routing network called the Event Routing Network. Figure 9-1 on page 16 shows a basic
block diagram of t he Event System wit h the Event Routin g Networ k an d the pe ripher als t o wh ich
it is connected. This highly flexible system can be used for simple routing of signals, pin func-
tions or for sequencing of events.
The maximum latency is two CPU clock cy cles from when an event is generated in one periph-
eral, until the actions are triggered in one or more oth er peripherals.
The Event System is functional in both Active and Idle modes.
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XMEGA A3
Figure 9-1. Event system block diagram.
The Event Routing Ne twork can directly connect togethe r ADCs, DACs, Analog Comparators
(ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Com-
munication Module (IRCOM). Events can also be generated from software (CPU).
All events from all p eri ph e ral s ar e always routed into th e Eve nt Rou tin g Netw or k. T his con sist of
eight multiplexers where each can be configured in software to select which event to be routed
into that event channel. All eight event channels are connected to the perip herals that can use
events, and each of these peripherals can be configured to use events from one or more event
channels to automatically trigger a software selectable action.
ADCx
DACx
E v e n t R outin g
Network
PORTx CPU
ACx
RTC
T/Cxn DMACIRCOM
ClkSYS
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XMEGA A3
10. System Clock and Clock options
10.1 Features
•Fast start-up time
•Safe run-time clock switching
•Internal Oscillators:
– 32 MHz run-time calibrated RC oscillator
– 2 MHz run-time calibrated RC oscillator
– 32 kHz cali br a ted RC oscillator
– 32 kHz Ultra Low Power (ULP) oscillator
•External clock options
– 0.4 - 16 MHz Crysta l Oscillator
– 32 kHz Crystal Oscillator
– External clock
•PLL with internal and external clock options with 2 to 31x m ultiplication
•Clock Prescalers with 2 to 2048x division
•Fast peripheral clock running at 2 and 4 times the CPU clock speed
•Automatic Run-Time Calibration of internal oscillators
•Crystal Oscillator fa ilure detection
10.2 Overview
XMEGA A3 has an adva nced clock syst em, suppo rting a large nu mber of clock sources. It incor-
porates both integrated oscillators, external crystal osc illators and resonators. A high frequency
Phase Locked Loop (PLL) and clock prescalers can be controlled from software to generate a
wide range of clock frequencies from the clock source input.
It is possible to switch between clock sources from software during run-time. After reset the
device will always start up running from the 2 Mhz internal oscillator.
A calibration feature is available, and can be used for automatic run-time calibration of the inter-
nal 2 MHz and 32 MHz oscillators. This reduce frequency drift over voltage and temperature.
A Crystal Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and
switch to internal oscillator if the external oscillator fails. Figure 10-1 on page 18 shows the prin-
cipal clock system in XMEGA A3.
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XMEGA A3
Figure 10-1. Clock system overview
Each clock source is briefly described in the following sub-sections.
10.3 Clock Options
10.3.1 32 kHz Ultra Low Power Internal Oscill at or
The 32 kHz Ultra Low Power (ULP) Inte rnal Oscillator is a very low power consumptio n clock
source. It is used for the Watchdog Timer, Brown-Out Detection and as an asynchronous clock
source for the Real Time Counter. This oscillator cannot be used as the system clock source,
and it cannot be directly controlled from software.
10.3.2 32.768 kHz Calibrated Internal Oscillator
The 32.768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used
as the system clock source or as an asynchronous clock source for the Real Time Counter. It is
calibrated during production to provide a default frequency which is close to its nominal
frequency.
32 MHz
Run-time Calibrated
Internal Oscillator
32 kHz ULP
Internal Oscillator
32.768 kHz
Calibrated Internal
Oscillator
32.768 KHz
Crystal Oscillator
0.4 - 16 MHz
Crystal Oscillator
2 MHz
Run-Time Calibrated
Internal Oscillator
External
Clock Input
CLOCK CONTROL
UNIT
with PLL and
Prescaler
WDT/BOD
clkULP
RTC
clkRTC
EVSYS
PERIPHERALS
ADC
DAC
PORTS
...
clkPER
DMA
INTERRUPT
RAM
NVM MEMORY
FLASH
EEPROM
CPU
clkCPU
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10.3.3 32.768 kHz Crystal Oscillator
The 32.768 kHz Crystal Oscilla tor is a low power driver for an exte rnal watch crystal. It can be
used as system clock source or as asynchronous clock source for t he Real Time Counter.
10.3.4 0.4 - 16 MHz Crystal Os cillator
The 0.4 - 16 MHz Crystal Oscillator is a driver intended for driving both external res onators and
crystals ranging from 400 kHz to 16 MHz.
10.3.5 2 MHz Run-time Calibrated Internal Oscillator
The 2 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during production to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32 kHz Calibrated Internal Oscillato r or the 32 kHz Crystal Oscillator as a
source for calibrating the frequency run-time to compensate for temperature and voltage drift
hereby optimizing the accuracy of the oscillator.
10.3.6 32 MHz Run-time Calibrated Internal Oscillator
The 32 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during production to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32 kHz Calibrated Internal Oscillato r or the 32 kHz Crystal Oscillator as a
source for calibrating the frequency run-time to compensate for temperature and voltage drift
hereby optimizing the accuracy of the oscillator.
10.3.7 External Clock input
The external clock input gives the possibility to connect a clock from an external source.
10.3.8 PLL with Multiplication factor 1 - 31x
The PLL provides the possibility of multiplying a frequenc y by any number from 1 to 31. In com-
bination with th e prescalers, this gives a wide range of output frequ encies from all clock sources.
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XMEGA A3
11. Power Management and Sleep Modes
11.1 Features
•5 sleep modes
–Idle
– Power-down
–Power-save
–Standby
– Extended standby
•Power Reduction registers to disable clocks to unused peripherals
11.2 Overview
The XMEGA A3 provides various sleep modes tailored to reduce power consumption to a mini-
mum. All sleep modes ar e available and can be entere d from Active mode. In Active mode the
CPU is executing application code . The applicat ion code decides when and which slee p mode to
enter. Interrupts from enabled peripherals and all enabled reset sources can restore the micro-
controller from sleep to Active mode.
In addition, Power Reduction registers provide a method to stop the clock to individual peripher-
als from software. When this is done, the current state of the peripheral is frozen and there is no
power consumption from that peripheral. This reduces the power consumption in Active mode
and Idle sleep mode.
11.3 Sleep Modes
11.3.1 Idle Mode
In Idle mode the CPU and Non-Volatile Memory are stopped , but all peripherals including the
Interrupt Controller, Event System and DMA Controller are kept running. Interrupt requests from
all enabled interrupts will wake the device.
11.3.2 Power-down Mode
In Power-down mode all syste m clock sources, and the asynchr onous Real Time Co unter (RTC)
clock source, are stopped. This allows operation of asynchronous modules only. The only inter-
rupts that can wake up the MCU are the Two Wire Interface address match interrupts, and
asynchronous port interrupts, e.g pin change.
11.3.3 Power-save Mode
Power-save mode is identical to Power-do wn, with one exception: If the RTC is enabled, it will
keep running during sleep and the device can also wake up from RTC interru pts.
11.3.4 Standby Mode
Standby mode is identical to Power-down with the exception that all enabled system clock
sources are kept running, while the CPU, Peripheral and R TC clocks are stopped. This reduces
the wake-up time when external crystals or resonators are used.
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11.3.5 Extended Standby Mode
Extended Standby mode is identical to Power-save mode with the exception that all enabled
system clock sources are kept running while the CPU and Peripheral clocks are stopped. This
reduces the wake-up time when external crystals or resonators are used.
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XMEGA A3
12. System Control and Reset
12.1 Features
•Multiple reset sources for safe operation and device reset
– Power-On Reset
– External Reset
– Watchdog Reset
The Watchdog Timer runs from separate, dedicated oscill at or
– Brown-Out Reset
Accurate, programmable Brown-Out levels
– JTAG Reset
– PDI reset
– Software reset
•Asynchronous reset
– No running clock in the device is required for reset
•Reset status register
12.2 Resetting the AVR
During reset, all I/O r egister s ar e set t o thei r initial value s. The SRAM content is not re se t. Ap pli-
cation execution starts from the Reset Vector. The instruction placed at the Reset Vector should
be an Absolute Jump ( JMP) instruct ion to t he reset handling routin e. By def ault the Re set Vector
address is the lowest F lash program memory addr ess, ‘0’, but it is possible to mov e the Reset
Vector to the first add ress in the Boot Section.
The I/O ports of the AVR are immediately tri-stated when a reset source goes active.
The reset functionality is asynchronous, so no running clock is required to reset the device.
After the device is reset, the reset source can be determined by the application by reading the
Reset Status Register.
12.3 Reset Sources
12.3.1 Power-On Reset
The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage.
12.3.2 External Reset
The MCU is reset when a low level is present on the RESET pin.
12.3.3 Watchdog Reset
The MCU is reset when the Wa tchdog Timer pe riod expire s and the Watchdo g Reset is enabled.
The Watchdog Timer ru ns from a dedicated oscillator independent of the Syste m Clock. For
more details see ”WDT - Watchdog Timer” on page 23 .
12.3.4 Brown-Out Reset
The MCU is reset when the supply voltage VCC is below the Brown-Out Reset thresh old voltage
and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmabl e.
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12.3.5 JTAG reset
The MCU is reset as long as there is a logic one in the Reset Register in one of the scan chains
of the JTAG system. Refer to IEEE 1149.1 (JTAG) Boundary-scan for details.
12.3.6 PDI reset
The MCU can be reset through the Program and Debug Interface (PDI).
12.3.7 Software reset
The MCU can be reset by the CPU writing to a special I/O register through a timed sequence.
12.4 WDT - Watchdog Timer
12.4.1 Features
•11 selectable timeout periods, from 8 ms to 8s.
•Two operation modes
– Standard mode
– Window mode
•Runs from the 1 kHz output of the 32 kHz Ultra Low Power oscillator
•Configuration lock to prevent unwanted changes
12.4.2 Overview
The XMEGA A3 has a Watchdog Timer (WDT). The WDT will run continuously when turned on
and if the Watchdog Timer is not reset within a software configurable tim e-out period, the micro-
controller will be reset. The Watchdog Reset (WDR) instruction must be run by software to reset
the WDT, and prevent microcontroller reset.
The WDT has a Window mode. In this mode the WDR instruction must be run within a specified
period called a window. Ap plication software can set the minimum and ma ximum limits for this
window. If the WDR instruction is not executed inside the window limits, the microcontroller will
be reset.
A protection mechanism using a timed write sequence is implemented in order to prevent
unwanted enabling, disabling or change of WDT settings.
For maximum safety , the WDT also has an Always-on mode. This mode is enabled by program-
ming a fuse. In Always-on mode, application software can not disable the WDT.
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XMEGA A3
13. PMIC - Programmable Multi-level Interrupt Controller
13.1 Features
•Separate interrupt vector for each interrupt
•Short, predictable interrupt response time
•Programmable Multi-level Interrupt Controller
– 3 programmable interrupt levels
– Selectable priority scheme within low level interrupts (round-robin or fixed)
– Non-Maskable Interrupts (NMI)
•Interrupt vectors can be moved to the start of the Boot Section
13.2 Overview
XMEGA A3 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can
define three different priority levels for interrup ts; high, medium or low. Medium level interrupts
may interrupt low level interrupt service routines. High level interrupts may interrupt both low-
and medium level interrupt service routines. Low level interrupts have an optional round robin
scheme to make sure all interrupts are serviced within a certain amount of time.
The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).
13.3 Interrupt vectors
When an interrupt is serviced, the program counter will jump to the interrupt vector address. The
interrupt vector is the sum of the pe ripheral’s base interrupt ad dress and the offset address for
specific interrupts in each periph eral. The base addresses for th e XMEGA A3 devices are shown
in Table 13-1. Offset addresses for each interrupt available in the peripheral are described for
each peripheral in the XMEGA A manua l. For peripherals or modules that have on ly one inter-
rupt, the interrupt vector is shown in Table 13-1. The program address is the word address.
Table 13-1. Reset and Interrupt Vectors
Program Address
(Base Address) Source Interrupt Description
0x000 RESET
0x002 OSCF_INT_vect Crystal Osci llato r Failure Interrupt vector (NMI)
0x004 PORTC_INT_base Port C Interrupt base
0x008 PORTR_INT_base Port R Interrupt base
0x00C DMA_INT_base DMA Controller Interrupt base
0x014 RTC_INT_base Real Time Counter Interrupt base
0x018 TWIC_INT_base Two-Wire Interface on Po rt C Interrupt base
0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base
0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base
0x030 SPIC_INT_vect SPI on port C Interrupt vector
0x032 USARTC0_INT_base USART 0 on port C Interru pt base
0x03D USARTC1_INT_base USART 1 on port C Interrupt base
0x03E AES_INT_vect AES Interrupt vector
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XMEGA A3
0x040 NVM_INT_base Non-Volatile Memory Interrupt base
0x044 PORTB_INT_base Port B Interrupt base
0x048 ACB_INT_base Analog Comparator on Port B Interrupt base
0x04E ADCB_INT_base Analog to Digital Converter on Port B Interrupt base
0x056 PORTE_INT_base Port E INT base
0x05A TWIE_INT_base Two-Wire Interface on Port E Interrupt base
0x05E TCE0_INT_base Timer/Counter 0 on port E Interrupt base
0x06A TCE1_INT_base Timer/Counter 1 on port E Interrupt base
0x072 SPIE_INT_vect SPI on por t E Interrupt vector
0x074 USARTE0_INT_base USART 0 on port E Interrup t base
0x07A USARTE1_INT_base USART 1 on port E Interrupt base
0x080 PORTD_INT_base Port D Interrupt base
0x084 PORTA_INT_base Port A Interrupt base
0x088 ACA_INT_base Analog Comparator on Port A Interrupt base
0x08E ADCA_INT_base Analog to Digital Converter on Port A Interrupt base
0x09A TC D0_INT_base Timer /Counter 0 on port D Interrupt base
0x0A6 TC D1_INT_base Timer /Counter 1 on port D Interrupt base
0x0AE SPID_INT_vector SPI D Interrupt vector
0x0B0 USARTD0_INT_base USART 0 on port D Interrupt base
0x0B6 USARTD1_INT_base USART 1 on port D Interrupt base
0x0D0 PORTF_INT_base Port F Interrupt base
0x0D8 TCF0_INT_base Timer/Counter 0 on port F Interrupt base
0x0EE USARTF0_INT_base USART 0 on port F Interrupt base
Table 13-1. Reset and Interrupt Vectors (Continued)
Program Address
(Base Address) Source Interrupt Description
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XMEGA A3
14. I/O Ports
14.1 Features
•Selectable input and output configur ation for each pin individually
•Flexible pin configuration through dedicated Pin Configuration Register
•Synchronous and/or asynchronous input sensing with port inte rrupts and events
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
•Asynchronous wake-up from all input sensing configurations
•Two port interrupts with flexible pin masking
•Highly configurable output dr iver and pull settings:
– Totem-pole
– Pull-up/-down
– Wired-AND
– Wired-OR
– Bus-keeper
– Inverted I/O
•Optional Sle w rate co ntrol
•Configuration of multiple pins in a single operation
•Read-Modify-Write (RMW) support
•Toggle/clear/set registers for Output and Direction registers
•Clock output on port pin
•Event Channel 7 output on port pin
•Mapping of port registers (virtual ports) into bit accessible I/O memory space
14.2 Overview
The XMEGA A3 devices have flexible General Purpose I /O Ports. A port consists of up to 8 pins,
ranging from pin 0 to pin 7. The ports implement several functions, including synchronous/asyn-
chronous input sensing, pin change interrupts and configurable output settings. All functions are
individual per pin, but several pins may be configured in a single operation.
14.3 I/O configuration
All port pins (Pn) have programmable output configuration. In addition, all port pins have an
inverted I/O function. For an input, this means inverting the signal between the port pin and the
pin register. For an output, this means inverting the output signal between the port register and
the port pin. The inverted I/O function can be used also when the pin is used for alternate func-
tions. The port pins also have configurable slew rate limitation to reduce electromagnetic
emission.
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XMEGA A3
14.3.1 Push-pull
Figure 14-1. I/O configuration - Totem-pole
14.3.2 Pull-down
Figure 14-2. I/O configuration - Totem-pole with pull-down (on input)
14.3.3 Pull-up
Figure 14-3. I/O configuration - Totem-pole with pull-up (on input)
14.3.4 Bus-keeper
The bus-keeper’s weak outpu t prod uces the same logi cal level as the last output level. It acts as
a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’.
INn
OUTn
DIRn
Pn
INn
OUTn
DIRn
Pn
INn
OUTn
DIRn
Pn
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XMEGA A3
Figure 14-4. I/O configuration - Totem-pole with bus-keeper
14.3.5 Others
Figure 14-5. Output configuration - Wired-OR with optional pull-down
Figure 14-6. I/O configuration - Wired-AND with optional pull-up
INn
OUTn
DIRn
Pn
INn
OUTn
Pn
INn
OUTn
Pn
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XMEGA A3
14.4 Input sensing
•Sense both edges
•Sense rising edges
•Sense falling edges
•Sense low level
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports,
and the configuration is shown in Figure 14-7 on page 29.
Figure 14-7. Input sensing system overview
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
14.5 Port Interrupt
Each port has two interrupts with separate priority and interrupt vector. All pins on the port can
be individually selected as so urce for each of the interrupts. The interrupts are then triggered
according to the input sense configuration for each pin configured as source for the interrupt.
14.6 Alternate Port Functions
In addition to the input/output functions on all port pins, most pins have alternate functions. This
means that other modules or peripherals connected to the port can use the port pins for their
functions, such as communication or pulse-width modulation. ”Pinout and Pin Functions” on
page 48 shows which modules on peripherals that enable alternate functions on a pin, and
which alternat e fun ct i on s tha t ar e av aila ble on a pin.
INVERTED I/O
Interrupt
Control IREQ
Event
Pn
DQ
R
DQ
R
Synchronizer
INn
EDGE
DETECT
Asynchronous sensing
Synchronous sensing
EDGE
DETECT
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15. T/C - 16-bits Timer/Counter with PWM
15.1 Features
•Seven 16-bit Timer/Counters
– Four Timer/Counters of type 0
– Three Timer/Counters of type 1
•Four Compare or Capture (CC) Channels in Timer/Counter 0
•Two Compare or Capture (CC) Channels in Timer/Counter 1
•Double Buffered Timer Period Setting
•Double Buffered Compare or Capture Channels
•Waveform Generation:
– Single Slope Pulse Width Modulation
– Dual Slope Pulse Width Modulation
– Frequency Generation
•Input Capture:
– Input Capture wi th Noise Cancelling
– Frequency capture
– Pulse width capture
– 32-bit input capture
•Event Counter with Direction Control
•Timer Overflow and Timer Error Interrupts and Events
•One Compare Match or Captu re Interrupt and Event per CC Chan nel
•Supports DMA Operation
•Hi-Resolution Extension (Hi-Res)
•Adv a nced Waveform Extension (AWEX)
15.2 Overview
XMEGA A3 has seven Timer/Counters, four Timer/Counter 0 and three Timer/Counter 1. The
difference between them is that Timer/Counter 0 has four Compare/Captu re channels, while
Timer/Counter 1 has two Compare/Capture channels.
The Timer/Counters (T/C) are 16-bit and can count any clock, event or external input in the
microcontroller. A progra mmable prescaler is availa ble to get a useful T/C re solution. Upd ates of
Timer and Compare registers are double buffered to ensure glitch free operation. Single slope
PWM, dual slope PWM and frequency generation waveforms can be generated using the Com-
pare Channels.
Through the Event System, any input pin or eve nt in the microcontroller can be used to trigger
input capture, hence no ded icated pins is req uired for this. The input capture has a no ise cancel-
ler to avoid incorrect capture of the T/C, and can be used to do frequency and pulse width
measurements.
A wide range of interrupt or event sources are available, including T/C Overflow, Compare
match and Capture for each Compare/Capture channel in the T/C.
PORTC, PORTD and PORTE each has one Timer/Counter 0 and one Timer/Counter1. PORTF
has one Timer/Counter 0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1,
TCE0, TCE1 and TCF0, respectively.
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Figure 15-1. Overview of a Timer/Counter and closely related peripherals
The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by
2 bits (4x). This is available for all Timer/Counters. See ”Hi-Res - High Resolution Extension” on
page 33 for more details.
The Advanced Waveform Extension can be enabled to provide extra and more advanced fea-
tures for the Timer /Counter. This are only available fo r Timer/Counter 0. See ”AWEX - Advanced
Waveform Extension” on page 32 for more details.
AWeX
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
Waveform
Generation
Buffer
Comparator
Hi-Res
Fault
Protection
Capture
Control
Base Counter
Counter Control Logic
Timer Period
Prescaler
DTI
Dead-Time
Insertion
Pattern
Generation
clkPER4
PORT
Event
System
clkPER
Timer/Counter
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16. AWEX - Advanced Waveform Extension
16.1 Features
•Output with complementar y output from each Capture channel
•Four Dead Time Insertion (DTI) Units, one f or each Capture channel
•8-bit DTI Resolution
•Separate High and Low Side Dead-Time Setting
•Double Buffered Dead-Time
•Event Controlled Fault Protection
•Single Channel Multiple Output Operation (for BLDC motor control)
•Double Buffered Pattern Generation
16.2 Overview
The Advanced Waveform Extension (AWEX) provides extra features to the Timer/Counter in
Waveform Generation (WG) mo des. The AWEX enables easy and safe implementation of for
example, advanced motor control (AC, BLDC, SR, and Stepper) and power control applications.
Any WG output from a Timer/Counter 0 is split into a complimentary pair of outputs when any
AWEX feature is enabled. These ou tput pairs go through a Dead -Time Insertion (DTI) u nit that
enables generation of the non-inverted Low Side (LS) and inverted High Side (HS) of the WG
output with dead time insertion between LS and HS switching. Th e DTI output will override the
normal port value according to the port override setting. Optionally the final output can be
inverted by using the invert I/O setting for the port pin.
The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is
connected to. In addition, the waveform generator output from Compare Channel A can be dis-
tributed to, and overri de all port pin s. When the Patter n Gener ator unit is enable d, the DT I unit is
bypassed.
The Fault Protection unit is connected to the Event System. This enables any event to trigger a
fault condition that will disable the AWEX output. Several event c hannels can be used to trigger
fault on several different conditions.
The AWEX is available for TCC0. The notation of this is AWEXC.
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17. Hi-Res - High Resolution Extension
17.1 Features •Increases Waveform Generator resolution by 2-bits (4x)
•Supports Frequency, single- and dual-slope PWM operation
•Supports the AWEX when this is enabled and used for the same Timer/Counter
17.2 Overview The Hi-Resolution (Hi-Res) Exten sion is able to incr ease the resolu ti on of t he wavefor m gener a-
tion output by a fa ctor of 4. When enabled f or a Timer/Counter, the Fast Periphera l clock running
at four times the CPU clock speed will be as input to the Timer/Counter.
The High Resolution Extension can also be used when an AWEX is enabled and used with a
Timer/Counter.
XMEGA A3 devices have four Hi-Res Extensions that each can be enabled for each
Timer/Counters pair on PORTC, PORTD, PORTE and PORTF. The notation of these are
HIRESC, HIRESD, HIRESE and HIRESF, respectively.
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18. RTC - Real-Time Counter
18.1 Features
•16-bit Timer
•Flexible Tick resolution ranging from 1 Hz to 32.768 kHz
•One Compare register
•One Period register
•Clear timer on Overflow or Compare Match
•Overflow or Compare Match event and interrupt generation
18.2 Overview
The XMEGA A3 includes a 16-bit Real-time Counter (RTC). The RTC can be clocked from an
accurate 32.768 kHz Crystal Oscillator, the 32.768 kHz Calibrated Internal Oscillator, or from the
32 kHz Ultra Low Power Internal Oscillator. The RTC includes both a Period and a Compare
register. For details, see Figure 18-1.
A wide range of Resolutio n and Time- out per iods can be conf igure d usin g the RTC. With a max-
imum resolution of 30.5 µs, time-out periods range up to 2000 seconds. With a resolution of 1
second, the maximum time-out period is over 18 hours (65536 seconds).
Figure 18-1. Real-time Counter overview
10-bit
prescaler Counter
Period
Compare
=
=
Overflow
Compare Match
1 kHz
32 kHz
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19. TWI - Two Wire Interface
19.1 Features
•Two Identical TWI peripherals
•Simple yet Powerful and Flexible Communication Interface
•Both Master and Slave Operation Supported
•Device can Operate as Transmitter or Receiver
•7-bit Address Space Allows up to 128 Different Slave Addresses
•Multi-master Arbitration Support
•Up to 400 kHz Data Transfer Speed
•Slew-rate Limited Output Drivers
•Noise Suppression Circuitry Rejects Spikes on Bus Lines
•Fully Programmable Slave Address with General Call Support
•Address Recognition Causes Wake-up when in Sleep Mode
•I2C and System Management Bus (SMBus) compatible
19.2 Overview
The Two-Wire In terface (TWI) is a bi-direct ional wired-AND bus with only two lines, the clock
(SCL) line and the data (SDA) line. The protocol makes it possible to interconn ect up to 128 indi-
vidually addressable devices. Since it is a multi-master bus, one or more devices capable of
taking control of the bus can be connected.
The only external hardware needed to implement the bus is a single pull-up resistor for each of
the TWI bus lines. Mechanisms for resolving bus contention ar e inherent in the TWI protocol.
PORTC and PORTE each has one TWI. Notati on of these peripherals are TWIC and TWI E.
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20. SPI - Serial Pe ripheral Interface
20.1 Features
•Three Identical SPI peripherals
•Full-duplex, Three-wire Synchronous Data Transfer
•Master or Slave Operation
•LSB Fir st or MSB First Data Transfer
•Seven Programmable Bit Rates
•End of Transmission Interrupt Flag
•Write Collision Flag Protection
•Wake-up from Idle Mode
•Double Speed (CK/2) Master SPI Mode
20.2 Overview
The Serial Peripheral Interface (SPI) allows high-speed full-duplex, synchronous data transfer
between different devices. Devices can communicate using a master-slave scheme, and data is
transferred both to and from the devices simultaneously.
PORTC, PORTD, and PORTE each has one SPI. Not ation of these per ipherals are SPIC, SPID,
and SPIE respectively.
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21. USART
21.1 Features
•Seven Identical USART peripherals
•Full Duplex Operation (Independent Serial Rece ive and Transmit Registers)
•Asynchronous or Synchronous Op eration
•Master or Slave Clocked Synchronous Operation
•High-resolution Arithmetic Baud Rate Generator
•Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
•Odd or Even Parity Generation and Parity Check Supported by Hardware
•Data OverRun Detection
•Framing Error Detection
•Noise Filterin g Includes False Start Bit Detection and Digital Low Pass Filter
•Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
•Multi-processor Communicat ion Mode
•Double Speed Asynchronous Communication Mode
•Master SPI mode for SPI communication
•IrDA support through the IRCOM module
21.2 Overview
The Universal Syn chronous and Asynchronous serial Re ceiver and Transmitter (USART) is a
highly flexible serial communication module. The USART supports full duplex communication,
and both asynchronous and clocked synchronous operation. The USART can also be set in
Master SPI mode to be used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide
range of standards. The USART is buffered in both direction, enabling continued data transmis-
sion without any delay between frames. There are separate interrupt vectors for receive and
transmit complete, enabling fully interrupt driven communication. Frame error and buffer over-
flow are detected in hardware and indicated with separate status flags. Even or odd parity
generation and parity check can also be enabled.
One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modula-
tion and demodulation for baud rates up to 115.2 kbps.
PORTC, PORTD, and PORTE each has two USARTs, while PORTF has one USART only.
Notation of these peripherals are USARTC0, USARTC1, USARTD0, USARTD1, USARTE0,
USARTE1 and USARTF 0 , respe ct ively .
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22. IRCOM - IR Communication Module
22.1 Features
•Pulse modulation/demodul ati on for infrared commu ni cation
•Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps
•Selectable pulse modulation scheme
– 3/16 of baud rate period
– Fixed pulse period , 8-b it programmable
– Pulse modulation disab led
•Built in filtering
•Can be connected to and used by one USART at the time
22.2 Overview
XMEGA contains an Infrared Communication Module (IRCOM) for IrDA communication with
baud rates up to 115. 2 kb ps. This suppor t s thr ee mo dulat ion sch eme s: 3/ 16 of baud rate pe rio d,
fixed programmable pulse time based on the Peripheral Clo ck speed, or pulse modulation dis-
abled. There is on e IRCOM ava ilable which can be connected to any USART to enable infrared
pulse coding/decoding for that USART.
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23. Crypto Engine
23.1 Features
•Data Encryption Standard (DES) CPU instruction
•Adv a nced Encryption Standard (AES) Crypto module
•DES Instruction
– Encryption and Decryption
– Single- cycle DES instru ction
– Encryption/Decryption in 16 clock cycles per 8-byte block
•AES Crypto Module
– Encryption and Decryption
– Support 128-bit keys
– Support XOR data load mode to the State memory for Cipher Block Chaining
– Encryption/Decryption in 375 clock cycles per 16-byte block
23.2 Overview
The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two com-
monly used encryption standards. These are supported through an AES peripheral module and
a DES CPU instruction. All communication interfaces and the CPU can optionally use AES and
DES encrypted communication and data storage.
DES is supported by a DES instruction in the AVR XMEGA CPU. The 8-byte key and 8-byte
data blocks must be loaded into the Register file, and then DES must be executed 16 times to
encrypt/decrypt the data block.
The AES Crypto Module encr ypts and de crypt s 128-bit data bl ocks with the use of a 12 8-bi t key.
The key and data must be loaded into the key and state memory in the module before encryp-
tion/decryption is sta rted. It takes 375 periphe ral clock cycles before the encryptio n/decr yption is
done and decr ypted/en crypted da ta can be read o ut, and a n optional interru pt can be g enerate d.
The AES Crypto Module also has DMA support with transfer triggers when encryption/decryp-
tion is done and optional auto-start of encryptio n/decryptio n when the state memory is fully
loaded.
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24. ADC - 12-bit Analog to Digital Converter
24.1 Features
•Two ADCs with 12-bit resolution
•2 Msps sample rate for each ADC
•Signed and Unsigned con versions
•4 result registers with individual input channel control for ea ch ADC
•8 single ended inputs f or each ADC
•8x4 differential inputs for each ADC
•4 internal inputs:
– Integrated Temperature Sensor
– DAC Output
– VCC voltage divided by 10
– Bandgap voltage
•Software selectable gain of 2, 4, 8, 16, 32 or 64
•Software selectable resolution of 8- or 12-bit.
•Internal or External Reference selection
•Event triggered conversion for accurate timing
•DMA transfer of conversion results
•Interrupt/Event on compare result
24.2 Overview
XMEGA A3 devices have two Analog to Digital Converters (ADC), see Figure 24-1 on page 41.
The two ADC modules can be operated simultaneously, individually or synchronized.
The ADC converts analog voltages to digital values. The ADC has 12-bit resolution and is capa-
ble of converting up to 2 million samples per second. The input selection is flexible, and both
single-ended and differential measurements can be done. For differential measurements an
optional gain stage is available to increase the dynamic range. In addition several in ternal signal
inputs are available. The ADC can provide both signed and unsigned results.
This is a pipeline ADC. A pipeline ADC consists of several consecutive stages, where each
stage convert one part of the result. The pipeline design enables high sample rate at low clock
speeds, and remove limitations on samples speed versus propagation delay. This also means
that a new analog voltage can be sampled and a new ADC measurement started while other
ADC measurements are ongoing.
ADC measurements can either be started by application software or an incoming event from
another peripheral in the device. Four different result registers with individual input selection
(MUX selection) are pro vided to make it easie r for t he app lication t o ke ep track of the dat a. Each
result register and MUX selection pair is referred to as an ADC Channel. It is pos sible to use
DMA to move ADC results directly to memory or peripherals when conversions are done.
Both internal and external analog reference voltages can be used. An accurate internal 1.0V
reference is available.
An integrated te mperature sensor is available and the outpu t from th is can be meas ured with the
ADC. The output from the DAC, VCC/10 and the Bandgap voltage can also be measured by the
ADC.
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Figure 24-1. ADC overview
Each ADC has four MUX se lection registers with a correspon ding result register. This me ans
that four channels can be sampled wit hin 1.5 µs with out any inter vention by the application o ther
than starting the conversion. The results will be available in the result registers.
The ADC may be conf igure d for 8- or 12-bit resu lt, redu cing t he minimum conversio n time ( prop-
agation delay) from 3. 5 µs for 12-bit to 2.5 µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This
eases calculation when the result is represented as a signed integer (signed 16-bit number).
PORTA and PORTB each has one ADC. Notatio n of these peripherals are ADCA and ADCB,
respectively.
ADC
Channel A
Register
Channel B
Register
Channel C
Register
Channel D
Register
Pin inputsPin inputs
1-64 X
Internal inputs
Channel A MUX selection
Channel B MUX selection
Channel C MUX selection
Channel D MUX selection
Event
Trigger
Configuration
Reference selection
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25. DAC - 12-bit Digital to Analog Converter
25.1 Features
•One DAC with 12-bit resolution
•Up to 1 Msps conversion rate for each DAC
•Flexible conversion range
•Multiple trigger sources
•1 continuous output or 2 Sample and Hold (S/H) outputs for each DAC
•Built-in offset and gain calibrati on
•High drive capabilities
•Low Power Mode
25.2 Overview
The XMEGA A3 features two 12-bit, 1 Msps DACs with built-in offset and gain calibration, see
Figure 25-1 on page 42.
A DAC converts a digital value into an analog signal. The DAC may use an internal 1.1 voltage
as the upper limit for conversion, but it is also possible to use the supply voltage or any applied
voltage in-between. The external reference input is shared with the ADC reference input.
Figure 25-1. DAC overview
Each DAC has one continuous output with high drive capabilities for both resistive and capaci-
tive loads. It is also possible to split the co ntinuous t ime ch annel int o two Sample a nd Hold ( S/H)
channels, each with separate data conversion registers.
A DAC conversion may be started from the application software by writing the data conversion
registers. The DAC can also be configured to do conversions triggered by the Event System to
have regular timing, independent of the application software. DMA may be used for transferring
data from memory locations to DAC data registers.
The DAC has a built-in calibration system to reduce offset and gain error when loading with a
calibration value from software.
PORTB each has one DAC. Notation of this peripheral is DACB.
DAC
Channel A
Register
Channel B
Register
Event
Trigger
Configuration
Reference selection
Channel A
Channel B
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26. AC - Analog Comparator
26.1 Features
•Four Analog Comparators
•Selectable Power vs. Speed
•Selectable hysteresis
– 0, 20 mV, 50 mV
•Analog Comparator output available on pin
•Flexible Input Selection
– All pins on the port
– Output from the DAC
– Bandgap reference vo ltage.
– Voltage scaler that can perform a 64-level scaling of the internal VCC voltage.
•Interrupt and event generation on
– Rising edge
– Fal lin g ed ge
–Toggle
•Window function interrupt and event generation on
– Signal above windo w
– Signal inside win dow
– Signal belo w wind ow
26.2 Overview
XMEGA A3 features four Analog Comparators (AC). An Analog Comparator compares two volt-
ages, and the o utput indicat es which in put is larg est. The Ana log Compara tor may be configured
to give interrupt requests and/or events upon several different combinations of input change.
Both hysteresis and propagation delays may be adjusted in order to find the optimal operation
for each application.
A wide range of input selection is available, both external pins and several internal signals can
be used.
The Analog Comparators are always grouped in pairs (AC0 and AC1) on each analog port. They
have identical behavior but separate control registe rs.
Optionally, the state of the comparator is directly available on a pin.
PORTA and PORTB each has one AC pair. Notati ons are ACA and ACB, respectively.
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Figure 26-1. Analog comparator overview
AC0
+
-
Pin inputs
Internal inputs
Pin inputs
Internal inputs
VCC scaled Interrupt
sensitivity
control
Interrupts
AC1
+
-
Pin inputs
Internal inputs
Pin inputs
Internal inputs
VCC scaled
Events
Pin 0 output
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26.3 Input Selection
The Analog comparators have a very flexible input selection and the two comparators grouped
in a pair may be used to realize a window function. One pair of analog comparators is shown in
Figure 26-1 on page 44.
•Input selection from pin
– Pin 0, 1, 2, 3, 4, 5, 6 selectable to positive input of analog comparator
– Pin 0, 1, 3, 5, 7 selectable to negative input of analog comparator
•Internal signals available on positive analog comparator inputs
– Output from 12-bit DAC
•Internal signals available on negative analog comparator inputs
– 64-level scaler of the VCC, available on negative analog comparator input
– Bandgap volta ge reference
•Output from 12-bit DAC
26.4 Window Function
The window function is realize d by connecting t he ext ernal inpu ts of the two analog co mparato rs
in a pair as shown in Figure 26-2.
Figure 26-2. Analog comparator window function
AC0
+
-
AC1
+
-
Input signal
Upper limit of window
Lower limit of window
Interrupt
sensitivity
control
Interrupts
Events
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27. OCD - On-chip Debug
27.1 Features
•Complete Program Flow Control
– Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor
•Debugging on C and high-level language source code level
•Debugging on Assembler and disassembler level
•1 dedicated program address or source level breakp oint for AVR Studio / de bugger
•4 Hardware Breakpoints
•Unlimited Number of User Program Breakpoints
•Unlimited Number of User Data Breakpoints, with break on:
– Data location read , write or both read and write
– Data location content equal or not equal to a value
– Data loca tio n content is greater or less tha n a value
– Data loca tio n co ntent is within or outside a ra nge
– Bits of a data location are equal or not equal to a value
•Non-Intrusive Operation
– No hard ware or software resources in the device are used
•High Speed Operation
– No limitation on debug/programming clock freq ue ncy versus sy stem clock frequency
27.2 Overview
The XMEGA A3 has a powerful O n-Chip Debug (OCD) system that - in comb ination with Atm el’s
development tools - provides all the necessary functions to debug an application. It has support
for program and d ata brea kpoin ts, and ca n debug an applica tion fro m C and high level lan guage
source code level, as well as assembler and disassembler level. It has full Non-Intrusive Opera-
tion and no hardware or software resources in the device are used. The ODC system is
accessed through an external debugging tool which connects to the JTAG or PDI physical inter-
faces. Refer to ”Program and Debug Interfaces” on page 47.
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28. Program and Debug Interfaces
28.1 Features
•PDI - Program and Debug Interface (Atmel proprietary 2-pin interface)
•JTAG Interface (IEEE std. 1149.1 compliant)
•Boundary-scan capabilities ac cording to the IEEE Std. 1149.1 (JTAG)
•Access to the OCD system
•Programming of Flash, EEPROM, Fuses and Lock Bits
28.2 Overview
The program ming and debug facilit ies are accessed thro ugh the JTAG and PDI ph ysical inter-
faces. The PDI physical uses one dedicated pin together with the Re set pin, and no general
purpose pins are used. JTAG uses four general purpose pins on PORTB.
28.3 JTAG interface
The JTAG physical layer handles the basic low-level serial communication over four I/O lines
named TMS, TCK, T DI, and TDO. It comp lies to the IEEE Std. 1149.1 for test access port an d
boundary scan.
28.4 PDI - Program and Debug Interface
The PDI is an Atmel proprietary protocol for communication between the microcontroller and
Atmel’s development to ols.
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29. Pinout and Pin Functions
The pinout of XMEGA A3 is shown in ”For packaging information, see ”Packaging information”
on page 63.” on page 2. In addition to general I/O functionality, each pin may have several func-
tion. This will depend on which peripheral is enabled and connected to the actual pin. Only one
of the alterna te pin functions can be used at ti me.
29.1 Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
29.1.1 Operation/Power Supply
29.1.2 Port Interrupt functions
29.1.3 Analog functions
VCC Digital supply voltage
AVCC Analog supply voltage
GND Ground
SYNC Port pin with full synchronous and limited asynchronous interrupt functio n
ASYNC Port pin with full synchronous and full asynchronous interrupt function
ACn Analog Comparator input pin n
AC0OU T Analog Comparator 0 Output
ADCn Analog to Digital Converter input pin n
DACn Digital to Analog Converter output pin n
AREF Analog Reference input pin
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29.1.4 Timer/Counter and AWEX functions
29.1.5 Communication functions
29.1.6 Oscillators, Clock and Event
29.1.7 Debug/System functions
OCnx Ou tput Compare Channel x for Timer/Counter n
OCxn Invert ed Output Compare Channel x for Timer/Counter n
SCL Serial Clock for TWI
SDA Serial Data for TWI
SCLIN Serial Clock In for TWI when extern al driver interface is enabled
SCLOUT Serial Clock Out for TWI when exter nal driver interface is enabled
SDAIN Serial Data In for TWI when external driver interface is enabled
SDAOUT Serial Data Out for TWI when external driver interface is enabled
XCKn Transfer Clock for USART n
RXDn Receiver Data for USART n
TXDn Transmitter Data for USART n
SS Slave Select for SPI
MOSI Master Out Slave In for SPI
MISO Master In Slave Out for SPI
SCK Serial Clock for SPI
TOSCn Timer Oscillator pin n
XTALn Input/Output for inverting Oscil lator pin n
CLKOUT Peripheral Clock Output
EVOUT Event Channel 0 Output
RESET Reset pin
PDI_CLK Program and Debug Interface Clock pin
PDI_DATA Program and Debug Interface Data pin
TCK JTAG Test Clock
TDI JTAG Test Data In
TDO JTAG Test Data Out
TMS JTAG Test Mode Select
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29.2 Alternate Pin Functions
The tables below show the main and alternate pin functions for all pins on each port. They also
show which peripheral that makes use of or enables the alternate pin function.
Table 29-1. Port A - Alternate functions
PORT A PIN # INTERRUPT ADCA POS ADCA NEG ADAA
GAINPOS ADCA
GAINNEG ACA POS ACA NEG ACA OUT REFA
GND 60
AVCC 61
PA0 62 SYNC ADC0 ADC0 ADC0 AC0 AC0 AREFA
PA1 63 SYNC ADC1 ADC1 ADC1 AC1 AC1
PA2 64 SYNC/ASYNC ADC2 ADC2 ADC2 AC2
PA3 1 SYNC ADC3 ADC3 ADC3 AC3 AC3
PA4 2 SYNC ADC4 ADC4 ADC4 AC4
PA5 3 SYNC ADC5 ADC5 ADC5 AC5 AC5
PA6 4 SYNC ADC6 ADC6 ADC6 AC6
PA7 5 SYNC A DC7 ADC7 ADC7 AC7 AC0 OUT
Table 29-2. Port B - Alternate functions
PORT B PIN # INTERRUPT ADCB
POS ADCB
NEG ADCB
GAINPOS ADCB
GAINNEG ACB POS ACB NEG ACB OUT DACB REFB JTAG
PB0 6 SYNC ADC0 ADC0 ADC0 AC0 AC0 AREFB
PB1 7 SYNC ADC1 ADC1 ADC1 AC1 AC1
PB2 8 SYNC/ASYNC ADC2 ADC2 ADC2 AC2 DAC0
PB3 9 SYNC ADC3 ADC3 ADC3 AC3 AC3 DAC1
PB4 10 SYNC ADC4 ADC4 ADC4 AC4 TMS
PB5 11 SYNC ADC5 ADC5 ADC5 AC5 AC5 TDI
PB6 12 SYNC ADC6 ADC6 ADC6 AC6 TCK
PB7 13 SYNC ADC7 ADC7 ADC7 AC7 AC0 OUT TDO
GND 14
VCC 15
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Table 29-3. Port C - Alternate functions
PORT C PIN # INTERRUPT TCC0 AWEXC TCC1 USARTC0 USARTC1 SPIC TWIC CLOCKOUT EVENTOUT
PC0 16 SYNC OC0A OC0A SDA
PC1 17 SYNC OC0B OC0A XCK0 SCL
PC2 18 SYNC/ASYNC OC0C OC0B RXD0
PC3 19 SYNC OC0D OC0B TXD0
PC4 20 SYNC OC0C OC1A SS
PC5 21 SYNC OC0C OC1B XCK1 MOSI
PC6 22 SYNC OC0D RXD1 MISO
PC7 23 SYNC OC0D TXD1 SCK CLKOUT EVOUT
GND 24
VCC 25
Table 29-4. Port D - Alternate functions
PORT D PIN # INTERRUPT TCD0 TCD1 USARTD0 USARTD1 SPID CLOCKOUT EVENTOUT
PD0 26 SYNC OC0A
PD1 27 SYNC OC0B XCK0
PD2 28 SYNC/ASYNC OC0C RXD0
PD3 29 SYNC OC0D TXD0
PD4 30 SYNC OC1A SS
PD5 31 SYNC OC1B XCK1 MOSI
PD6 32 SYNC RXD1 MISO
PD7 33 SYNC TXD1 SCK CLKOUT EVOUT
GND 34
VCC 35
Table 29-5. Port E - Alternate functions
PORT E PIN # INTERRUPT TCE0 TCE1 USARTE0 USARTE1 SPIE TWIE CLOCKOUT EVENTOUT TOSC
PE0 36 SYNC OC0A SDA
PE1 37 SYNC OC0B XCK0 SCL
PE2 38 SYNC/ASYNC OC0C RXD0
PE3 39 SYNC OC0D TXD0
PE4 40 SYNC OC1A SS
PE5 41 SYNC OC1B XCK1 MOSI
PE6 42 SYNC RXD1 MISO TOSC2
PE7 43 SYNC TXD1 SCK CLKOUT EVOUT TOSC1
GND 44
VCC 45
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Table 29-7. Port R - Alternate functions
Table 29-6. Port F - Alternate functions
PORT F PIN # INTERRUPT TCF0 USARTF0
PF0 46 SYNC OC0A
PF1 47 SYNC OC0B XCK0
PF2 48 SYNC/ASYNC OC0C RXD0
PF3 49 SYNC OC0D TXD0
PF4 50 SYNC
PF5 51 SYNC
PF6 54 SYNC
PF7 55 SYNC
GND 52
VCC 53
PORT R PIN # INTERRUPT PROGR XTAL
PDI 56 PDI_DATA
RESET 57 PDI_CLOCK
PRO 58 SYNC XTAL2
PR1 59 SYNC XTAL1
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30. Peripheral Module Address Map
The address maps sh ow the base address for each peripheral and module in XMEG A A3. For
complete regist er description and sum mary for each peripher al module, refer to the XM EGA A
Manual.
Base Address Name Description
0x0000 GPI O General Purpose IO Registers
0x0010 VPORT0 Virtual Port 0
0x0014 VPORT1 Virtual Port 1
0x0018 VPORT2 Virtual Port 2
0x001C VPORT3 Virtual Port 2
0x0030 CPU CPU
0x0040 CLK Clock Control
0x0048 SLEEP Sleep Controller
0x0050 OSC Oscillator Control
0x0060 DFLLRC32M DFLL for the 32 MHz Internal RC Oscillator
0x0068 DFLLRC2M DFLL for the 2 MHz RC Oscillator
0x0070 PR Power Reduction
0x0078 RST Reset Controller
0x0080 WDT Watch-Dog Timer
0x0090 MCU MCU Control
0x00A0 PMIC Programmable MUltilevel Interrupt Controller
0x00B0 PORTCFG Port Configuration
0x00C0 AES AES Module
0x0100 DMA DMA Controller
0x0180 E VSYS Event System
0x01C0 NVM Non Volatile Memory (NVM) Controller
0x0200 ADCA Analog to Digital Converter on port A
0x0240 ADCB Analog to Digital Converter on port B
0x0320 DACB Digital to Analog Converter on port B
0x0380 AC A Analog Comparator pair on port A
0x0390 AC B Analog Comparator pair on port B
0x0400 RTC Real Time Counter
0x0480 TWIC Two Wire Interface on port C
0x04A0 TWIE Two Wire Interfaceon port E
0x0600 PORTA Port A
0x0620 PORTB Port B
0x0640 PORTC Port C
0x0660 PORTD Port D
0x0680 PORTE Port E
0x06A0 PORTF Port F
0x07E0 PORTR Port R
0x0800 TCC0 Timer/Counter 0 on port C
0x0840 TCC1 Timer/Counter 1 on port C
0x0880 AWEXC Advanced Waveform Extensi on on port C
0x0890 HIRESC High Resolution Extension on port C
0x08A0 USARTC0 USART 0 on port C
0x08B0 USARTC1 USART 1 on port C
0x08C0 SPIC Serial Peripheral Interface on port C
0x08F8 IRCOM Infrared Communication Module
0x0900 TCD0 Timer/Counter 0 on port D
0x0940 TCD1 Timer/Counter 1 on port D
0x0990 HIRESD High Resolution Extension on port D
0x09A0 USARTD0 USART 0 on port D
0x09B0 USARTD1 USART 1 on port D
0x09C0 SPID Serial Peripheral Interface on port D
0x0A00 TCE0 Timer/Counter 0 on port E
0x0A40 TCE1 Timer/Counter 1 on port E
0x0A80 AWEXE Advanced Waveform Extensionon port E
0x0A90 HIRESE High Resolution Extension on port E
0x0AA0 USARTE0 USART 0 on port E
0x0AB0 USARTE1 USART 1 on oirt E
0x0AC0 SPIE Serial Peripheral Interface on port E
0x0B00 TCF0 Timer/Counter 0 on port F
0x0B90 HIRESF High Resolution Extension on port F
0x0BA0 USARTF0 USART 0 on port F
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31. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
Arithmetic and Logic Instructions
ADD Rd, Rr Add without Carry Rd ←Rd + Rr Z,C,N,V,S,H 1
ADC Rd, Rr Add with Ca rr y Rd ←Rd + Rr + C Z,C,N,V,S,H 1
ADIW Rd, K Add Immediate to Word Rd ←Rd + 1:Rd + K Z,C,N,V,S 2
SUB Rd, Rr Subtract without Carry Rd ←Rd - Rr Z,C,N,V,S,H 1
SUBI Rd, K Subtract Immediate Rd ←Rd - K Z,C,N,V,S,H 1
SBC Rd, Rr Su btract with Ca r ry Rd ←Rd - Rr - C Z,C,N,V,S,H 1
SBCI Rd, K Subtract Immediate with Carry Rd ←Rd - K - C Z,C,N,V,S,H 1
SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd ←Rd + 1:Rd - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Rd ←Rd • Rr Z,N,V,S 1
ANDI Rd, K Logical AND with Immediate Rd ←Rd • K Z,N,V,S 1
OR Rd, Rr Logical OR Rd ←Rd v Rr Z,N,V,S 1
ORI Rd, K Logical OR with Immediate Rd ←Rd v K Z,N,V,S 1
EOR Rd, Rr Exclusive OR Rd ←Rd ⊕ Rr Z,N,V,S 1
COM Rd One’s Complement Rd ←$FF - Rd Z,C,N,V,S 1
NEG Rd Two’s Complement Rd ←$00 - Rd Z,C,N,V,S,H 1
SBR Rd,K Set Bit(s) in Register Rd ←Rd v K Z,N,V,S 1
CBR Rd,K Clear Bit(s) in Register Rd ←Rd • ($FFh - K) Z,N,V,S 1
INC Rd Increment Rd ←Rd + 1 Z,N,V,S 1
DEC Rd Decrement Rd ←Rd - 1 Z,N,V,S 1
TST Rd Test for Zero or Minus Rd ←Rd • Rd Z,N,V,S 1
CLR Rd Clear Register Rd ←Rd ⊕ Rd Z,N,V,S 1
SER Rd Set Register Rd ←$FF None 1
MUL Rd,Rr Multiply Unsigned R1:R0 ←Rd x Rr (UU) Z,C 2
MULS Rd,Rr Multiply Signed R1:R0 ←Rd x Rr (SS) Z,C 2
MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 ←Rd x Rr (SU) Z,C 2
FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 ←Rd x Rr<<1 (UU) Z,C 2
FMULS Rd,Rr F ractional Multiply Signed R1:R0 ←Rd x Rr<<1 (SS) Z,C 2
FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 ←Rd x Rr<< 1 (SU) Z,C 2
DES K Data Encryption if (H = 0) then R15:R0
else if (H = 1) then R15:R0 ←
←
Encr ypt (R15:R 0 , K)
Decrypt(R15:R0, K) 1/2
Branch Instructions
RJMP k Relative Jump PC ←PC + k + 1 None 2
IJMP Indirec t Jump to (Z) PC(15:0 )
PC(21:16) ←
←
Z,
0None 2
EIJMP Extended Indirect Jump to (Z) PC(15:0)
PC(21:16) ←
←
Z,
EIND None 2
JMP k Jump PC ←k None 3
RCALL k Relative Call Subroutine PC ←PC + k + 1 None 2 / 3(1)
ICALL Indirect Call to (Z) PC(15:0)
PC(21:16) ←
←
Z,
0None 2 / 3(1)
EICALL Extended Indirect Call to (Z) PC(15:0)
PC(21:16) ←
←
Z,
EIND None 3(1)
55
8068K–AVR–02/09
XMEGA A3
CALL k call Subroutine PC ←k None 3 / 4(1)
RET Subroutine Return PC ←STACK None 4 / 5(1)
RETI Interrupt Return PC ←STACK I 4 / 5(1)
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ←PC + 2 or 3 None 1 / 2 / 3
CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1
CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1
CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ←PC + 2 or 3 None 1 / 2 / 3
SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC ←PC + 2 or 3 None 1 / 2 / 3
SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC ←PC + 2 or 3 None 2 / 3 / 4
SBIS A, b Skip if Bit in I/O Regis ter Set If (I /O( A,b) =1) PC ←PC + 2 or 3 None 2 / 3 / 4
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ←PC + k + 1 None 1 / 2
BRBC s , k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ←PC + k + 1 None 1 / 2
BREQ k Branch if Equal if (Z = 1) then PC ←PC + k + 1 None 1 / 2
BRNE k Branch if Not Equal if (Z = 0) then PC ←PC + k + 1 None 1 / 2
BRCS k Branch if Carry Set if (C = 1) then PC ←PC + k + 1 None 1 / 2
BRCC k Branch if Carry Cleared if (C = 0) then PC ←PC + k + 1 None 1 / 2
BRSH k Branch if Same or Higher if (C = 0) then PC ←PC + k + 1 None 1 / 2
BRLO k Branch if Lower if (C = 1) then PC ←PC + k + 1 None 1 / 2
BRMI k Branch if Minus if (N = 1) then PC ←PC + k + 1 None 1 / 2
BRPL k Branch if Plus if (N = 0) then PC ←PC + k + 1 None 1 / 2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ←PC + k + 1 None 1 / 2
BRLT k Branch if Less Than , Signed if (N ⊕ V= 1) then PC ←PC + k + 1 None 1 / 2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ←PC + k + 1 None 1 / 2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ←PC + k + 1 None 1 / 2
BRTS k Branch if T Flag Set if (T = 1) then PC ←PC + k + 1 None 1 / 2
BRTC k Branch if T Flag Cleared if (T = 0) then PC ←PC + k + 1 None 1 / 2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ←PC + k + 1 None 1 / 2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ←PC + k + 1 None 1 / 2
BRIE k Branch if Interrupt Enabled if (I = 1) then PC ←PC + k + 1 None 1 / 2
BRID k Branch if Interrupt Disabled if (I = 0) then PC ←PC + k + 1 None 1 / 2
Data Transfer Instructions
MOV Rd, Rr Copy Register Rd ←Rr None 1
MOVW Rd, Rr Copy Register Pair Rd+1:Rd ←Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd ←K None 1
LDS Rd, k Load Direct from data space Rd ←(k) None 2(1)(2)
LD Rd, X Load Indirect Rd ←(X) None 1(1)(2)
LD Rd, X+ Load Indirect and Post-Increment Rd
X←
←
(X)
X + 1 None 1(1)(2)
LD Rd, -X Load Indirect and Pre-Decrement X ← X - 1,
Rd ← (X) ←
←
X - 1
(X) None 2(1)(2)
LD Rd, Y Load Indirect Rd ← (Y) ←(Y) None 1(1)(2)
LD Rd, Y+ Load Indirect and Post-Increment Rd
Y←
←
(Y)
Y + 1 None 1(1)(2)
Mnemonics Operands Description Operation Flags #Clocks
56
8068K–AVR–02/09
XMEGA A3
LD Rd, -Y Load Indirect and Pre-Decrement Y
Rd ←
←
Y - 1
(Y) None 2(1)(2)
LDD Rd, Y+q Load Indirect with Displacement Rd ←(Y + q) None 2(1)(2)
LD Rd, Z Load Indirect Rd ←(Z) None 1(1)(2)
LD Rd, Z+ Load Indirect and Post-Increment Rd
Z←
←
(Z),
Z+1 None 1(1)(2)
LD Rd, -Z Load Indirect and Pre-Decrement Z
Rd ←
←
Z - 1,
(Z) None 2(1)(2)
LDD Rd, Z+q Load Indirect with Displacement Rd ←(Z + q) None 2(1)(2)
STS k, Rr Store Direct to Data Space (k) ←Rd None 2(1)
ST X, Rr Store Indirect (X) ←Rr None 1(1)
ST X+, Rr Store Indirect and Post-Increment (X)
X←
←
Rr,
X + 1 None 1(1)
ST -X, Rr Store Indirect and Pre-Decrement X
(X) ←
←
X - 1,
Rr None 2(1)
ST Y, Rr Store Indirect (Y) ←Rr None 1(1)
ST Y+, Rr Store Indirect and Post-Increment (Y)
Y←
←
Rr,
Y + 1 None 1(1)
ST -Y, Rr Store Indirect and Pre-Decrement Y
(Y) ←
←
Y - 1,
Rr None 2(1)
STD Y+q, Rr Store Indirect with Displacement (Y + q) ←Rr None 2(1)
ST Z, Rr Store Indirect (Z) ←Rr None 1(1)
ST Z+, Rr Store Indirect and Post-Increment (Z)
Z←
←
Rr
Z + 1 None 1(1)
ST -Z, Rr Store Indirect and Pre-Decrement Z ←Z - 1 None 2(1)
STD Z+q,Rr Store Indirect wi th Di spl a cement (Z + q) ←Rr None 2(1)
LPM Load Program Memory R0 ←(Z) None 3
LPM Rd, Z Load Program Memory Rd ←(Z) None 3
LPM Rd, Z+ Load Prog ram Memory and Post-Increment Rd
Z←
←
(Z),
Z + 1 None 3
ELPM Extended Load Program Memor y R0 ←(RAMPZ:Z) None 3
ELPM Rd, Z Extended Load Program Memory Rd ←(RAMPZ:Z) None 3
ELPM Rd, Z+ Extended Load Program Memory and Post-
Increment Rd
Z←
←
(RAMPZ:Z),
Z + 1 None 3
SPM Store Program Memory (RAMPZ:Z) ←R1:R0 None -
SPM Z+ Store Progr am Memory and Post- Inc rement
by 2 (RAMPZ:Z)
Z←
←
R1:R0,
Z + 2 None -
IN Rd, A In From I/O Location Rd ←I/O(A) None 1
OUT A, Rr Out To I/O Location I/O(A) ←Rr None 1
PUSH Rr Push Register on Stack STACK ←Rr None 1(1)
POP Rd Pop Register from Stack Rd ←STACK None 2(1)
Bit and Bit-test Instructions
LSL Rd Logical Shift Left Rd(n+1)
Rd(0)
C
←
←
←
Rd(n),
0,
Rd(7)
Z,C,N,V,H 1
LSR Rd Logical Shift Right Rd(n)
Rd(7)
C
←
←
←
Rd(n+1),
0,
Rd(0)
Z,C,N,V 1
Mnemonics Operands Description Operation Flags #Clocks
57
8068K–AVR–02/09
XMEGA A3
Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid
for accesses via the external RAM interface.
2. One extra cycle must be added when ac cessing Internal SRAM.
ROL Rd Rotate Left Through Carry Rd(0)
Rd(n+1)
C
←
←
←
C,
Rd(n),
Rd(7)
Z,C,N,V,H 1
ROR Rd Rotate Right Through Carry Rd(7)
Rd(n)
C
←
←
←
C,
Rd(n+1),
Rd(0)
Z,C,N,V 1
ASR Rd Arithmetic Shift Ri ght Rd(n) ←Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0) ↔Rd(7..4) None 1
BSET s Flag Set SREG(s) ←1SREG(s)1
BCLR s Flag Clear SREG(s) ←0SREG(s)1
SBI A, b Set Bit in I/O Register I/O(A, b) ←1 None 1
CBI A, b Clear Bit in I/O Register I/O(A, b) ←0 None 1
BST Rr, b Bit Store from Register to T T ←Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ←T None 1
SEC Set Carry C ←1C1
CLC Clear Carry C ←0C1
SEN Set Negative Flag N ←1N1
CLN Clear Negative Flag N ←0N1
SEZ Set Zero Flag Z ←1Z1
CLZ Clear Zero Flag Z ←0Z1
SEI Global Interrupt Enable I ←1I1
CLI Global Interrupt Disable I ←0I1
SES Set Signed Test Flag S ←1S1
CLS Clear Signed Test Flag S ←0S1
SEV Set Two’s Complement Overflo w V ←1V1
CLV Clear Two’s Complement Overflow V ←0V1
SET Set T in SREG T ←1T1
CLT Clear T in SREG T ←0T1
SEH Set Half Carry Flag in SREG H ←1H1
CLH Clear Half Carry Flag in SREG H ←0H1
MCU Control Instructions
BREAK Break (See specific descr. for BREAK) None 1
NOP No Operat ion None 1
SLEEP Sleep (see specific descr. for Sleep) None 1
WDR Watchdog Reset (see specific descr. for WDR) None 1
Mnemonics Operands Description Operation Flags #Clocks
58
8068K–AVR–02/09
XMEGA A3
32. Electrical Characteristics - TBD
32.1 Absolute Maximu m Ratings*
32.2 DC Characteristics
Note: 1. “Max” means the highest value where the pin is guaranteed to be read as low
2. “Min” means the lowest value where the pin is guaranteed to be read as high
Operating Temperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on any Pin with respect to Ground..-0.5V to VCC+0.5V
Maximum Operating Voltage ............................................ 3.6V
DC Current per I/O Pin............................................... 20.0 mA
DC Current VCC and GND Pins................................ 200.0 mA
TA = -40°C to 85°C, VCC = 1.6V to 3.6V (unless o therwise noted)
Symbol Parameter Condition Min. Typ. Max. Units
VIL Input Low Voltage, except XTAL1 pin V
VIL1 Input Low Voltage, XTAL1 pins V
VIH Input High Voltage, excep t XTAL1 pin V
VIH1 Input High Voltage, XTAL1 pin V
VOL Output Low Voltage
VOH Output High Voltage
IIL Input Leakage
Current I/O Pin µA
IIH Input Leakage
Current I/O Pin µA
RRST Reset Pull-up Resistor kΩ
RPU I/O Pin Pull-up Resistor kΩ
ICC
Power Supply Current
Active 32 MHz mA
Active 20 MHz mA
Active 8MHz mA
Idle 32 MHz mA
Idle 20 MHz mA
Power-dow n mode
WDT disabled µA
WDT slow sampling µA
WDT fast sampling
59
8068K–AVR–02/09
XMEGA A3
32.3 Speed
The maximum freque ncy of the XMEGA A3 devices is depending on VCC. As shown in Figure
32-1 on page 59 the Fr eque n cy vs. VCC curve is linear be twe e n 1.8 V < VCC < 2.7V.
Figure 32-1. Maximum Frequency vs. Vcc
1.8
12
32
MHz
V
2.7 3.6
1.6
Safe Operating Area
60
8068K–AVR–02/09
XMEGA A3
32.4 ADC Characteristics – TBD
Table 32-1. ADC Characteristics
Symbol Parameter Condition Min Typ Max Units
Resolution LSB
Integral Non-Linearity (INL) LSB
Differential Non - Linearity (DNL) LSB
Gain Error LSB
Offset Error LSB
Conversion Time µs
ADC Clock Frequency MHz
DC Supply Voltage mA
Source Impedance Ω
Start-up time µs
AVCC Analog Supply Voltage VCC - 0.3 VCC + 0.3 V
Table 32-2. ADC Gain Stage Characteristics
Symbol Parameter Condition Min Typ Max Units
Gain
Input Capacitance pF
Offset Error mV
Gain Error %
Signal Range V
DC Supply Current mA
Start-up time # clk
cycles
61
8068K–AVR–02/09
XMEGA A3
32.5 DAC Characteristics – TBD
32.6 Analog Comparator Characteristics – TBD
Table 32-3. DAC Characteristics
Symbol Parameter Condition Min Typ Max Units
Resolution LSB
Integral Non-Linearity (INL) LSB
Differential Non-Linearity (DNL) LSB
Gain Error LSB
Offset Error LSB
Calibrated Gain/Offset Error LSB
Output Range V
Output Settling Time µs
Output Capacitance nF
Output Resistance kΩ
Reference Input Voltage V
Reference Input Capacitance pF
Reference Input Resistance kΩ
Current Consumption mA
Start-up time µs
Table 32-4. Analog Comparator Characteristics
Symbol Parameter Condition Min Typ Max Units
Offset mV
Hysteresis
No
mVLow
High
Propagation Delay High Speed mode ns
Low power mode
Current Consumption High Speed mode µA
Low power mode
Start-up time µs
62
8068K–AVR–02/09
XMEGA A3
33. Typical Characteristics - TBD
63
8068K–AVR–02/09
XMEGA A3
34. Packaging information
34.1 64A
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B
64A
10/5/2001
PIN 1 IDENTIFIER
0°~7°
PIN 1
L
C
A1 A2 A
D1
D
eE1 E
B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes:
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 15.75 16.00 16.25
D1 13.90 14.00 14.10 Note 2
E 15.75 16.00 16.25
E1 13.90 14.00 14.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
64
8068K–AVR–02/09
XMEGA A3
34.2 64M2
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
64M2, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, D
64M2
5/25/06
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.80 0.90 1.00
A1 – 0.02 0.05
b 0.18 0.25 0.30
D
D2 7.50 7.65 7.80
8.90 9.00 9.10
8.90 9.00 9.10
E
E2 7.50 7.65 7.80
e 0.50 BSC
L 0.35 0.40 0.45
TOP VIEW
SIDE VIEW
BOTTOM VIEW
D
E
Marked Pin# 1 ID
SEATING PLANE
A1
C
A
C
0.08
1
2
3
K 0.20 0.27 0.40
2. Dimension and tolerance conform to ASMEY14.5M-1994.
E2
D2
be
Pin #1 Corner
L
Pin #1
Triangle
Pin #1
Chamfer
(C 0.30)
Option A
Option B
Pin #1
Notch
(0.20 R)
Option C
K
K
Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
7.65 mm Exposed Pad, Micro Lead Frame Package (MLF)
65
8068K–AVR–02/09
XMEGA A3
35. Errata
35.1 ATxmega256A3
35.1.1 rev. B
•Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
•DAC is nonlinear and inaccura t e if the external reference is above 2.4V or VCC - 0.6V
•ADC gain stage output range is limited to 2.4V
•Sampled BOD in Active mode will cause noise when bandgap is used as reference
•Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
•BOD will be enabled after any reset
•Writing EEPROM or Flash while reading any of them will not work
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs
simultaneously
If the bandgap voltage is selected as input for one Analog Comparator (AC) and then
selected/deselected as input for the another AC, the first comparator will be affected for up
to 1 us and could potentially give a wrong comparison result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection fo r both
ACs before enablin g an y of th em .
2. DAC is nonlinear and inaccurate if the external reference is above 2.4V or Vcc-0.6V
Using the DAC with a reference voltage above 2.4V or Vcc-0.6V give inaccurate output in
the top 25% of the output range:
– ±30 LSB for continuous mo de
– ±200 LSB for Sample and Hold mode
Problem fix/Workaround
None, avoid using a voltage reference above 2.4V or Vcc-0.6V.
3. ADC gain stage output range is limited to 2.4 V
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential
input will only give correct output when below 2.4 V/gain. For the available gain settings, this
gives a differential input range of:
– 1x gain: 2.4 V
– 2x gain: 1.2 V
– 4x gain: 0.6 V
– 8x gain: 300 mV
– 16x gain: 150 mV
– 32x gain: 75 mV
– 64x gain: 38 mV
66
8068K–AVR–02/09
XMEGA A3
Problem fix/Workaround
Keep the amplified voltag e output from t he ADC gain stage below 2.4 V in order to get a cor-
rect result, or keep ADC voltage reference below 2.4 V.
4. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add
noise on the bandgap reference for ADC, DAC and Analog Comparator.
Problem fix/Workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the
BOD must not be set in sampled mode.
5. Bandgap measurement with t he ADC is non-functional when VCC is below 2.7V
The ADC cannot be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/Workaround
If internal voltages must be measured when VCC is below 2.7V, me asure the internal 1. 00V
reference instead of the bandgap.
6. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
7. Writing EEPROM or Flash while reading any of them will not work
The EEPROM and Flash cannot be written while read ing EEPROM or Flash, or while exe-
cuting code in Active mode.
Problem fix/Workaround
Enter IDLE sleep mode within 2. 5 uS (Five 2 MHz clock cycles and 80 32 MHz clock cycles)
after starting an EEPROM or flash write operation. Wake-up source must either be
EEPROM ready or NVM ready interrupt. Alternatively set up a Timer/Counter to give an
overflow interrupt 5 mS after the erase or write operation has started, or 9 mS after atomic
erase-and-write operation has started, and then enter IDLE sleep mode.
67
8068K–AVR–02/09
XMEGA A3
35.1.2 rev. A
•Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
•DAC is nonlinear and inaccura t e if the external reference is above 2.4V or VCC - 0.6V
•ADC gain stage output range is limited to 2.4V
•Sampled BOD in Active mode will cause noise when bandgap is used as reference
•Flash Power Reduction Mode can not be enabled when entering sleep mode
•JTAG enable does not override Analog Comparator B output
•Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
•DAC refresh may be blocked in S/H mode
•BOD will be enabled after any reset
•Both DFLLs and both oscillators has to be enabled for one to work
•Operating frequnecy and voltag e limitations
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs
simultaneously
If the bandgap voltage is selected as input for one Analog Comparator (AC) and then
selected/deselected as input for the another AC, the first comparator will be affected for up
to 1 us and could potentially give a wrong comparison result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection fo r both
ACs before enablin g an y of th em .
2. DAC is nonlinear and inaccurate if the external reference is above 2.4V or Vcc-0.6V
Using the DAC with a reference voltage above 2.4V or Vcc-0.6V give inaccurate output in
the top 25% of the output range:
– ±30 LSB for continuous mo de
– ±200 LSB for Sample and Hold mode
Problem fix/Workaround
None, avoid using a voltage reference above 2.4V or Vcc-0.6V.
3. ADC gain stage output range is limited to 2.4 V
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential
input will only give correct output when below 2.4 V/gain. For the available gain settings, this
gives a differential input range of:
– 1x gain: 2.4 V
– 2x gain: 1.2 V
– 4x gain: 0.6 V
– 8x gain: 300 mV
– 16x gain: 150 mV
– 32x gain: 75 mV
– 64x gain: 38 mV
68
8068K–AVR–02/09
XMEGA A3
Problem fix/Workaround
Keep the amplified voltag e output from t he ADC gain stage below 2.4 V in order to get a cor-
rect result, or keep ADC voltage reference below 2.4 V.
4. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add
noise on the bandgap reference for ADC, DAC and Analog Comparator.
Problem fix/Workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the
BOD must not be set in sampled mode.
5. Flash Power Reduction Mode can not be enabled when entering sleep mode
If Flash Power Reduction Mode is enabled when a deep sleep mode, the device will only
wake up on every fourth wake-up request.
If Flash Power Reduct ion Mode is enabled wh en entering Idle slee p mode, the wake-up time
will vary with up to 16 CPU clock cycles.
Problem fix/Workaround
Disable Flash Power Reduction mode before entering sleep mode.
6. JTAG enable does not override Analog Comparator B output
When JTAG is enabled this will not override the Anlog Comparator B (ACB)ouput, AC0OUT
on pin 7 if this is enabled.
Problem fix/Workaround
AC0OUT for ACB should not be enabled when JTAG is used. Use only analog comparator
output for ACA when JTAG is used, or use the PDI as debug interface.
7. Bandgap measurement with t he ADC is non-functional when VCC is below 2.7V
The ADC cannot be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/Workaround
If internal voltages must be measured when VCC is below 2.7V, me asure the internal 1. 00V
reference instead of the bandgap.
8. DAC refresh may be blocked in S/H mode
If the DAC is running in Sample an d Hold (S/H) mode and conversion for one channel is
done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this
will block refresh signals to the second channel.
Problem fix/Workarund
When using the DAC in S/H mode, ensure that none of the channels is running at maximum
conversion rate, or ensure that the conversion rate of both channels is high enough to not
require refresh.
9 BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
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8068K–AVR–02/09
XMEGA A3
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
10 Both DFLLs and both oscillators has to be enabled for one to work
In order to use the automatic runtime calibration for the 2 MHz or the 32MHz internal oscilla-
tors, the DFLL for both oscillators and both oscillators has to be enabled for one to work.
Problem fix/Workaround
Enabled both the DFLLs and both oscillators when using automtics runtime calibartion for
one of the internal oscillators.
11 Operating Frequancy and Voltage Limitati on
To ensure correct operation, there is a limit on operating frequnecy and voltage. Figure 35-1
on page 69 shows the safe operating area.
Figure 35-1. Operating Freq unecy and Voltage Limitation
Problem fix/Workaround
None, avoid using the device outside these frequnecy and voltage limitations.
MHz
V
3.6
2.4
30
15 Safe operating
area
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8068K–AVR–02/09
XMEGA A3
36. Datasheet Revision History
36.1 8068K – 02/09
36.2 8068J – 12/08
36.3 8068I – 11/08
36.4 8068H – 10/08
36.5 8068G – 09/08
1. Added ”Errata” on page 65 for ATxmega256A3 rev B.
1. Added ”Errata” on page 65 for ATxmega256A3 rev A.
1. Updated F eaturelist in ”Memories” on page 8.
1. Updated Table 13-1 on page 24.
1. Updated ”Features” on page 1.
2. Updated ”Ordering Information” on page 2.
3. Updated ”Features” on page 8 by removing “External Memory...”.
4. Updated Figure 7-1 on page 9 and Figure 7-2 on page 10.
5. Updated Table 7-2 on page 13 and Table 7-3 on page 13.
6. Updated ”Features” on page 40 and ”Overview” on page 40.
7 Removed “Interrupt Vector Summary” section from datasheet.
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XMEGA A3
36.6 8068F – 08/08
36.7 8068E – 08/08
36.8 8068D – 06/08
36.9 8068C – 06/08
36.10 8068B – 06/08
1. Changed Figure 2-1’s title to “Block diagram and pinout.”
2. Changed Package Type to “64M2” in ”Ordering Information” on page 2 and in ”Packaging
information” on page 63.
3. Updated Table 29-5 on page 51.
4. Inserted a correct “64A” TQFP drawing on page 63.
1. Updated ”Block Diagram” on page 4.
2. Inserted “Interrupt Vector Summary” on page 54.
1. References to External Bus Inte rface (EBI) removed from ”Features” on page 1.
1. Updated ”Features” on page 1.
2. Updated Figure 2-1 on page 2.
3. Updated ”Overview” on page 3.
4. Updated Table 7-2 on page 13.
5. Replaced Figure 24-1 on page 41 by a correct on e.
6. Updated “Features” and ”Overview” on page 42.
7. Updated all tables in section ”Alternate Pin Fu nctions” on page 50.
1. Updated ”Features” on page 1.
2. Updated ”For packaging information, see ”Packaging information” on page 63.” on page 2 and
”Pinout and Pin Functions” on page 48.
3. Updated ”Ordering Information” on page 2.
4. Updated ”Overview” on page 3, included the XMEGA A3 explanation text on page 6.
5. Added XMEGA A3 Block Diagram, Figure 3-1 on page 4.
6. Updated AVR CPU ”Overview” on page 6 and Updated Figure 6-1 on page 6.
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8068K–AVR–02/09
XMEGA A3
36.11 8068A – 02/08
7. Updated Event System block diagram, Figure 9-1 on page 16.
8. Updated ”PMIC - Programmable Multi-level Interrupt Controller” on page 24.
9. Updated ”AC - Analog Comparator” on page 43.
10. Updated ”I/O configurati on” on page 26.
11. Inserted a new Figure 15-1 on page 31.
12. Updated ”Peripheral Module Address Map” on page 53.
13. Inserted ”Instruction Set Summary” on page 54.
14. Added Speed grades in ”Speed” on page 59.
1. Initial revisi on.
i
8068K–AVR–02/09
XMEGA A3
Table of Contents
Features.....................................................................................................1
Typical Applications ................................................................................1
1 Ordering Information ...............................................................................2
2 Pinout/Block Diagram ..............................................................................2
3 Overview ...................................................................................................3
3.1Block Diagram ...........................................................................................................4
4 Resources .................................................................................................5
4.1Recommended reading .............................................................................................5
5 Disclaimer .................................................................................................5
6 AVR CPU ...................................................................................................6
6.1Features ....................................................................................................................6
6.2Overv iew .... ....... ......... .......... .......... .......... ......... .......... ...... .......... .......... ......... .......... ..6
6.3Register File ..............................................................................................................7
6.4ALU - Arithm et ic Lo gic Un it ..................... ... ... ... ................ .... ... ... ................ ... .... ... .....7
6.5Program Flow ............................................................................................................7
7 Memories ..................................................................................................8
7.1Features ....................................................................................................................8
7.2Overv iew .... ....... ......... .......... .......... .......... ......... .......... ...... .......... .......... ......... .......... ..8
7.3In-Sys te m Pro gram m a ble Flash Pro g ra m Mem o ry ........................... ... ... ... ... ............9
7.4Data Me m or y ............. ................. ... ................ ... ... ................. ... ... ................ ... .... ......10
7.5Production Signature Row .......................................................................................12
7.6User Signature Row ................................................................................................12
7.7Flash and EEPROM Page Size ...............................................................................13
8 DMAC - Direct Memory Access Controller ..........................................14
8.1Features ..................................................................................................................14
8.2Overv iew .... ....... ......... .......... .......... .......... ......... .......... ...... .......... .......... ......... ..........14
9 Event System .......................................................................................... 15
9.1Features ..................................................................................................................15
9.2Overv iew .... ....... ......... .......... .......... .......... ......... .......... ...... .......... .......... ......... ..........15
10 System Clock and Clock options .........................................................17
10.1Features ................................................................................................................17
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XMEGA A3
10.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...17
10.3Clock Options ........................................................................................................18
11 Power Management and Sleep Modes .................................................20
11.1Features ................................................................................................................20
11.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...20
11.3Sleep Modes ..........................................................................................................20
12 System Control and Reset ....................................................................22
12.1Features ................................................................................................................22
12.2Resetting the AVR .................................................................................................22
12.3Reset Sourc es ............. ................ ... ... ................ .... ... ... ................ .... ... ... ................22
12.4WDT - Watc h dog Time r ............ ... ... ................ ... ................. ... ... ................ ... ..........23
13 PMIC - Programmable Multi-level Interrupt Controller .......................24
13.1Features ................................................................................................................24
13.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...24
13.3Interru pt ve cto rs .... ... ................. ... ... ................ ... .... ................ ... ... ................ .... ......24
14 I/O Ports ..................................................................................................26
14.1Features ................................................................................................................26
14.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...26
14.3I/O config u ratio n ............. ... ... .... ................ ... ... ................ .... ... ................ ... .............2 6
14.4Input sensing .........................................................................................................29
14.5Port Interrupt ..........................................................................................................29
14.6Alternate Port Functions ........................................................................................29
15 T/C - 16-bits Timer/Counter with PWM .................................................30
15.1Features ................................................................................................................30
15.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...30
16 AWEX - Advanced Waveform Extension .............................................32
16.1Features ................................................................................................................32
16.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...32
17 Hi-Res - High Resolution Extension .....................................................33
17.1Features ................................................................................................................33
17.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...33
18 RTC - Real-Time Counter .......................................................................34
18.1Features ................................................................................................................34
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XMEGA A3
18.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...34
19 TWI - Two Wire Interface .......................................................................35
19.1Features ................................................................................................................35
19.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...35
20 SPI - Serial Peripheral Interface ............ ................................................36
20.1Features ................................................................................................................36
20.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...36
21 USART .....................................................................................................37
21.1Features ................................................................................................................37
21.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...37
22 IRCOM - IR Communication Module .....................................................38
22.1Features ................................................................................................................38
22.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...38
23 Crypto Engine .........................................................................................39
23.1Features ................................................................................................................39
23.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...39
24 ADC - 12-bit Analog to Digital Converter .............................................40
24.1Features ................................................................................................................40
24.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...40
25 DAC - 12-bit Digital to Analog Converter .............................................42
25.1Features ................................................................................................................42
25.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...42
26 AC - Analog Comparator .......................................................................43
26.1Features ................................................................................................................43
26.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...43
26.3Input Selection .......................................................................................................45
26.4Window Functio n ............... ... ................. ... ... ... ................ .... ... ................ ... ... .... ......45
27 OCD - On-chip Debug ............................................................................46
27.1Features ................................................................................................................46
27.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...46
28 Program and Debug Interfaces .............................................................47
28.1Features ................................................................................................................47
28.2Overvie w ............... ................ ................. ................ ............. ................ ................ ...47
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XMEGA A3
28.3JTAG interface .......................................................................................................47
28.4PDI - Program and Debug Interface ......................................................................47
29 Pinout and Pin Functions ......................................................................48
29.1Alternate Pin Function Description ........................................................................48
29.2Alternate Pin Functions .........................................................................................50
30 Peripheral Module Address Map ..........................................................53
31 Instruction Set Summary .......................................................................54
32 Electrical Characteristics - TBD ............................................................58
32.1Absolute Ma xim u m Ra ting s* ................. ... ................ ... ... .... ................ ... ... .............5 8
32.2DC Characteristics .................................................................................................58
32.3Speed ....................................................................................................................59
32.4ADC Characteristics – TBD ...................................................................................60
32.5DAC Characteristics – TBD ...................................................................................61
32.6Analog Comparator Characteristics – TBD ...........................................................61
33 Typical Characteristics - TBD ...............................................................62
34 Packaging information ..........................................................................63
34.164A ........................................................................................................................63
34.264M2 .. ............. ......... ............. ............. ............. ............. ............. ............. ............. ...64
35 Errata .......................................................................................................65
35.1ATxmega256A3 ..................................................................................................... 65
36 Datasheet Revision History ...................................................................70
36.18068K – 02/09 .......................................................................................................70
36.28068J – 12/08 ........................................................................................................70
36.38068I – 11/08 .........................................................................................................70
36.48068H – 10/08 .......................................................................................................70
36.58068G – 09/08 .......................................................................................................70
36.68068F – 08 /0 8 ... ................ ... ................. ... ... ................ ... .... ................ ... ... .............7 1
36.78068E – 08/08 .......................................................................................................71
36.88068D – 06/08 .......................................................................................................71
36.98068C – 06/08 .......................................................................................................71
36.108068B – 06 /0 8 .............................. ... ................ .... ... ................ ... .... ................ ... ...71
36.118068A – 02 /0 8 .............................. ... ................ .... ... ................ ... .... ................ ... ...72
Table of Contents.......................................................................................i
8068K–AVR–02/09
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