EVAL-ADF4150EB1Z - Analog Devices

Fractional-N/Integer-N PLL Synthesizer

Data Sheet

ADF4150

Rev. A Document Feedback

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FEATURES

Fractional-N synthesizer and integer-N synthesizer

Programmable divide-by-1/-2/-4/-8/-16 output

5.0 GHz RF bandwidth

3.0 V to 3.6 V power supply

1.8 V logic compatibility

Separate charge pump supply (VP) allows extended tuning

voltage in 3 V systems

Programmable dual-modulus prescaler of 4/5 or 8/9

Programmable output power level

RF output mute function

3-wire serial interface

Analog and digital lock detect

Switched bandwidth fast-lock mode

Cycle slip reduction

APPLICATIONS

Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM,

PCS, DCS, DECT)

Test equipment

Wireless LANs, CATV equipment

Clock generation

GENERAL DESCRIPTION

The ADF4150 allows implementation of fractional-N or

integer-N phase-locked loop (PLL) frequency synthesizers

if used with an external voltage-controlled oscillator (VCO),

loop filter, and external reference frequency.

The ADF4150 is for use with external VCO parts and is

software compatible with the ADF4350. The VCO frequency

can be divided by 1/2/4/8/16 to allow the user to generate RF

output frequencies as low as 31.25 MHz. For applications that

require isolation the RF output stage can be muted. The mute

function is both pin and software controllable.

Control of all the on-chip registers is through a simple 3-wire

interface. The device operates with a power supply ranging

from 3.0 V to 3.6 V and can be powered down when not in use.

The ADF4150 is available in a 4 mm × 4 mm package.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

MUXOUT

OUT

REF

CLK

DATA

SDV

GND

CE CP

GND

SET

OUT

–

PHASE

COMPARATOR

SWITCH

CHARGE

PUMP

OUTPUT

STAGE

INPUT

PDB

MULTIPLEXER

10-BI T R

COUNTER ÷2

DIVIDER

×2

DOUBLER

FUNCTION

LATCH

DATA RE GIS TER

INTEGER

REG

N COUNTER

FRACTION

REG

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

MODULUS

REG

MULTIPLEXER

LOCK

DETECT

ADF4150

08226-001

DIVIDE-BY-1/

-2/-4/-8/-16

ADF4150 Data Sheet

Rev. A | Page 2 of 28

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6

Transistor Count ........................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 9

Circuit Description ......................................................................... 11

Reference Input Section ............................................................. 11

RF N Divider ............................................................................... 11

INT, FRAC, MOD, and R Counter Relationship.................... 11

INT N Mode ................................................................................ 11

R Counter .................................................................................... 11

Phase Frequency Detector (PFD) and Charge Pump ............ 11

MUXOUT and Lock Detect ...................................................... 12

Input Shift Registers ................................................................... 12

Program Modes .......................................................................... 12

Output Stage ................................................................................ 12

Initialization Sequence .............................................................. 20

RF Synthesizer—A Worked Example ...................................... 21

Modulus ....................................................................................... 21

Reference Doubler and Reference Divider ............................. 21

12-Bit Programmable Modulus ................................................ 21

Cycle Slip Reduction for Faster Lock Times ........................... 22

Spurious Optimization and Fast lock ...................................... 22

Fast Lock Timer and Register Sequences ................................ 22

Fast Lock—An Example ............................................................ 23

Fast Lock—Loop Filter Topology............................................. 23

Spur Mechanisms ....................................................................... 23

Spur Consistency and Fractional Spur Optimization ........... 24

Phase Resync ............................................................................... 24

Applications Information .............................................................. 25

Direct Conversion Modulator .................................................. 25

Interfacing ................................................................................... 26

PCB Design Guidelines for Chip Scale Package .................... 26

Output Matching ........................................................................ 27

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 28

REVISION HISTORY

11/13—Rev. 0 to Rev. A

Changes to Pin 24, Table 4................................................................ 8

7/11—Revision 0: Initial Version

Data Sheet ADF4150

Rev. A | Page 3 of 28

SPECIFICATIONS

AVDD = DVDD = SDVDD = 3.3 V ± 10%; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. The

operating temperature range is −40°C to +85°C.

Table 1.

Parameter

B Version

Unit Conditions/Comments Min Typ Max

REFIN CHARACTERISTICS

Input Frequency 10 250 MHz For f < 10 MHz ensure slew rate > 21 V/µs

Input Sensitivity 0.7 AVDD V p-p Biased at AVDD/21

Input Capacitance 5.0 pF

Input Current ±60 µA

RF INPUT CHARACTERISTICS

RF Input Frequency (RFIN), RF Output

Buffer Disabled

0.5 4.0 GHz −10 dBm ≤ RF input power ≤ +5 dBm

RF Input Frequency (RFIN), RF Output

Buffer Disabled

0.5 5.0 GHz −5 dBm ≤ RF input power ≤ +5 dBm

RF Input Frequency (RFIN) RF Output

Buffer Enabled

0.5 3.5 GHz −10 dBm ≤ RF input power ≤ +5 dBm

RF Input Frequency (RF

) RF Output

Buffer and Dividers Enabled

0.5

3.0

GHz

−10 dBm ≤ RF input power ≤ +5 dBm

Prescaler Output Frequency 750 MHz

MAXIMUM PFD FREQUENCY

Fractional-N (Low Spur Mode) 26 MHz

Fractional-N Mode (Low Noise Mode) 32 MHz

Integer-N Mode 32 MHz

CHARGE PUMP

ICP Sink/Source RSET = 5.1 kΩ

High Value 4.65 mA

Low Value 0.29 mA

SET

Range

2.7

kΩ

ICP Leakage 1 nA VCP = VP/2

Sink and Source Current Matching 2 % 0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. VCP 1 % 0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. Temperature 2 % VCP = VP/2

LOGIC INPUTS

Input High Voltage, VINH 1.5 V

Input Low Voltage, VINL 0.6 V

Input Current, IINH/IINL ±1 µA

Input Capacitance, CIN 3.0 pF

LOGIC OUTPUTS

Output High Voltage, V

− 0.4

CMOS output chosen

Output High Current, IOH 500 µA

Output Low Voltage, VO 0.4 V IOL = 500 µA

POWER SUPPLIES

AVDD 3.0 3.6 V

DVDD, SDVDD AVDD

VP AVDD 5.5 V

DIDD + AIDD 2 50 60 mA

Output Dividers 6 to 24 mA Each output divide by two consumes 6 mA

RFOUT2

RF output stage is programmable

Low Power Sleep Mode 1 µA

ADF4150 Data Sheet

Rev. A | Page 4 of 28

Parameter

B Version

Unit Conditions/Comments Min Typ Max

RF OUTPUT CHARACTERISTICS

Minimum Output Frequency Using RF

Output Dividers

31.25 MHz 500 MHz VCO input and divide-by-16 selected

Maximum RFIN Frequency Using RF

Output Dividers

4400 MHz

Harmonic Content (Second) −19 dBc Fundamental VCO output

Harmonic Content (Third) −13 dBc Fundamental VCO output

Harmonic Content (Second)

−20

dBc

Divided VCO output

Harmonic Content (Third)

−10

dBc

Divided VCO output

Output Power 3 −4 dBm Maximum setting

+5 dBm Minimum setting

Output Power Variation ±1 dB

Level of Signal With RF Mute Enabled −40 dBm

NOISE CHARACTERISTICS

Normalized Phase Noise Floor

(PNSYNTH)4

−223 dBc/Hz PLL loop BW = 500 kHz (ABP = 3 ns)

Normalized 1/f Noise (PN

1_f

)

−123

dBc/Hz

10 kHz offset. Normalized to 1 GHz. (ABP = 3 ns)

Normalized Phase Noise Floor

(PNSYNTH)4

−222 dBc/Hz PLL loop BW = 500 kHz (ABP = 6 ns); low noise

mode selected

Normalized 1/f Noise (PN1_f)5 −119 dBc/Hz 10 kHz offset; normalized to 1 GHz; (ABP = 6 ns);

low noise mode selected

Spurious Signals Due to PFD

Frequency6

−90 dBc VCO output

−75 dBc RF output buffers

1 AC coupling ensures AVDD/2 bias.

2 TA = 25°C; AVDD = DVDD = 3.3 V; prescaler = 8/9; fREFIN = 100 MHz; fPFD = 26 MHz; fRF = 1.7422 GHz.

3 Using a tuned load.

4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider

value) and 10 log FPFD. PNSYNTH = PNTOT − 10logFPFD − 20logN.

5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (FRF)

and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.

6 Spurious measured on EVAL-ADF4150EB1Z, using a Rohde & Schwarz FSUP signal source analyzer.

Data Sheet ADF4150

Rev. A | Page 5 of 28

TIMING CHARACTERISTICS

AVDD = DVDD = SDVDD = 3.3 V ± 10%; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating

temperature range is −40°C to +85°C.

Table 2.

Parameter Limit (B Version) Unit Test Conditions/Comments

t1 20 ns min LE setup time

t2 10 ns min DATA to CLK setup time

t3 10 ns min DATA to CLK hold time

t4 25 ns min CLK high duration

t5 25 ns min CLK low duration

t6 10 ns min CLK to LE setup time

t7 20 ns min LE pulse width

Figure 2. Timing Diagram

CLK

DATA

DB31 (MSB) DB30 DB1

(CONTROL BIT C2)

DB2

(CONTROL BIT C3)

DB0 (LSB)

(CONTROL BIT C1)

08226-002

ADF4150 Data Sheet

Rev. A | Page 6 of 28

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to +3.9 V

AVDD to DVDD −0.3 V to +0.3 V

VP to AVDD −0.3 V to +5.8 V

Digital I/O Voltage to GND1 −0.3 V to VDD + 0.3 V

Analog I/O Voltage to GND1 −0.3 V to VDD + 0.3 V

REFIN to GND1 −0.3 V to VDD + 0.3 V

Operating Temperature Range −40°C to +85°C

Storage Temperature Range −65°C to +125°C

Maximum Junction Temperature 150°C

LFCSP θJA Thermal Impedance

(Paddle-Soldered) 27.3°C/W

Reflow Soldering

Peak Temperature

260°C

Time at Peak Temperature 40 sec

1 GND = AGND = DGND = 0 V.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

TRANSISTOR COUNT

23380 (CMOS) and 809 (bipolar)

ESD CAUTION

Data Sheet ADF4150

Rev. A | Page 7 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

CLK

Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

2 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high

impedance CMOS input.

3 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register

that is selected by the three LSBs.

4 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state

mode. Taking the pin high powers up the device depending on the status of the power-down bits.

5 SW Fastlock Switch. Make a connection to this pin from the loop filter when using the fastlock mode.

6 VP Charge Pump Power Supply. This pin should be greater than or equal to AVDD. In systems where AVDD is 3 V, it

can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.

7 CPOUT Charge Pump Output. When enabled, this provides ±ICP to the external loop filter. The output of the loop filter

is connected to VTUNE to drive the external VCO.

8 CPGND Charge Pump Ground. This is the ground return pin for CPOUT.

9 AVDD1 Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

are to be placed as close as possible to this pin. AVDD must have the same value as DVDD.

10 RFIN+ Input to the RF Input. This small signal input is ac-coupled to the external VCO.

11 RFIN− Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small bypass

capacitor, typically 100 p F.

12, 13 AGND Analog Ground. This is a ground return pin for AVDD1 and AVDD2.

14 RFOUT− Complementary RF Output. The output level is programmable. The VCO fundamental output or a divided

down version is available.

15 RFOUT+ RF Output. The output level is programmable. The VCO fundamental output or a divided down version is

available.

16 AVDD2 Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

are to be placed as close as possible to this pin. AVDD2 must have the same value as DVDD.

17 PDBRF RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.

18 DVDD Digital Power Supply. This pin should be the same voltage as AVDD. Place decoupling capacitors to the ground

plane as close as possible to this pin.

19 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance

of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

20 LD Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock; a logic low output indicates loss of

PLL lock.

21 MUXOUT

Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference

frequency to be accessed externally.

GND

REF

SDV

GND

MUXOUT

SET

OUT

−

PDB

NOTES

1. THE L FCSP HAS AN E X P OSE D P ADDLE

THAT MUST BE CONNECTED TO GND.

PIN 1

INDICATOR

CLK 2

DATA3LE 4CE 5

SW 6

7CP

OUT

GND

–12A

GND

+21

ADF4150

TOP VIEW

(No t t o Scal e)

08226-003

ADF4150 Data Sheet

Rev. A | Page 8 of 28

Pin No. Mnemonic Description

22 SDVDD Power Supply Pin for the Digital Sigma-Delta (Σ-Δ) Modulator. This pin should be the same voltage as AVDD.

Decoupling capacitors to the ground plane are to be placed as close as possible to this pin.

23 SDGND Digital Σ-Δ Modulator Ground. Ground return path for the Σ-Δ modulator.

24 RSET Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage

bias at the RSET pin is 0.48 V. The relationship between ICP and RSET is

SET

I23.7

where:

RSET = 5.1 kΩ.

ICP = 4.65 mA.

25 EP The exposed pad must be connected to GND.

Data Sheet ADF4150

Rev. A | Page 9 of 28

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. RF Input Sensitivity; RF Output Enabled; Output Divide-by-1

Selected

Figure 5. RF Input Sensitivity; RF Output Disabled

Figure 6. RF Sensitivity; RF Output Enabled (RF Dividers-by-2/-4/-8/-16

Enabled)

Figure 7. Integer-N Phase Noise and Spur Performance; Low Noise Mode;

VCOOUT = 1750 MHz, REFIN = 100 MHz, PFD = 25 MHz, Loop Filter

Bandwidth= 50 kHz

Figure 8. Fractional-N Phase Noise and Spur Performance; Low Noise Mode;

VCOOUT = 1750 MHz, REFIN = 100 MHz, PFD = 25 MHz, Loop Filter

Bandwidth= 15 kHz, Channel Spacing = 200 kHz. FRAC = 26, MOD = 125

Figure 9. Fractional-N Phase Noise and Spur Performance; Low Spur Mode;

VCOOUT = 1750 MHz, REFIN = 100 MHz, PFD = 25 MHz, Loop Filter

Bandwidth= 50 kHz, Channel Spacing = 200 kHz. FRAC = 26, MOD = 125

–50 05.0

PO WER (dBm)

FRE QUENCY ( GHz)

08226-042

–45

–40

–35

–30

–25

–20

–15

–10

–5

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

+25°C

+85°C

–40°C

–50 0 6

PO WER (dBm)

FREQUENCY (MHz)

08226-043

–40

–30

–20

–10

12345

+25°C

+85°C

–40°C

–40 04.0

PO WER (dBm)

FRE QUENCY ( GHz)

08226-044

–35

–30

–25

–20

–15

–10

–5

0.5 1.0 1.5 2.0 3.02.5 3.5

+25°C

+85°C

–40°C

–180

–160

–140

–120

–100

–80

–60

PO WER (dBc)

08226-045

1k 10k 100k 1M 10M

FREQUENCY (Hz)

1M 10M 100M 1G 10G

FREQUENCY (Hz)

–180

–160

–140

–120

–100

–80

–60

PO WER (dBc)

08226-046

1k 10k 100k 1M 10M

FREQUENCY (Hz)

–180

–160

–140

–120

–100

–80

–60

PO WER (dBc)

08226-047

ADF4150 Data Sheet

Rev. A | Page 10 of 28

Figure 10. RF Output Phase Noise RF Dividers Used; Integer-N; Low Noise

Mode; VCOOUT = 1750 MHz, REFIN = 100 MHz, PFD = 25 MHz, Loop Filter

Bandwidth = 50 kHz

Figure 11. RF Buffer Output Fractional-N Phase Noise and Spur Performance;

Low Noise Mode; VCOOUT = 1750 MHz, REFIN = 100 MHz, PFD = 25 MHz,

Loop Filter Bandwidth = 15 kHz, Channel Spacing = 200 kHz; FRAC = 1,

MOD = 5; Output Divider = 1

Figure 12. RF Buffer Output Fractional-N Phase Noise and Spur Performance;

Low Noise Mode; VCOOUT = 1750 MHz, REFIN = 100 MHz, PFD = 25 MHz,

Loop Filter Bandwidth = 15 kHz, Channel Spacing = 200 kHz; FRAC = 1,

MOD = 5; Output Divider = 2

Figure 13. RF Buffer Output Fractional-N Phase Noise and Spur Performance;

Low Noise Mode; VCOOUT = 1750 MHz, REFIN = 100 MHz, PFD = 25 MHz,

Loop Filter Bandwidth = 15 kHz, Channel Spacing = 200 kHz. FRAC = 1,

MOD = 5. Output divider = 4

–180

–160

–140

–120

–100

–80

–60

1k 10k 100k 1M 10M

PO WER (dBc)

FREQUENCY (Hz)

08226-038

1k 10k 100k 1M 10M

FREQUENCY (Hz)

–180

–160

–140

–120

–100

–80

–60

PO WER (dBc)

08226-039

1k 10k 100k 1M 10M

FREQUENCY (Hz)

–180

–160

–140

–120

–100

–80

–60

PO WER (dBc)

08226-040

1k 10k 100k 1M 10M

FREQUENCY (Hz)

–180

–160

–140

–120

–100

–80

–60

PO WER (dBc)

08226-041

Data Sheet ADF4150

Rev. A | Page 11 of 28

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 14. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REFIN pin

on power-down.

Figure 14. Reference Input Stage

RF N DIVIDER

The RF N divider allows a division ratio in the PLL feedback

path. Division ratio is determined by IN T, F RAC, and MOD

values, which build up this divider.

INT, FRAC, MOD, AND R COUNTER RELATIONSHIP

The INT, FRAC, and MOD values, in conjunction with the R

counter, make it possible to generate output frequencies that

are spaced by fractions of the PFD frequency. See the RF

Synthesizer—A Worked Example section for more informa-

tion. The RF VCO frequency (RFOUT) equation is

RFOUT = fPFD × (INT + (FRAC/MOD)) (1)

where:

RFOUT is the output frequency of external voltage controlled

oscillator (VCO).

INT is the preset divide ratio of the binary 16–bit counter

(23 to 65535 for 4/5 prescaler, 75 to 65535 for 8/9 prescaler).

MOD is the preset fractional modulus (2 to 4095).

FRAC is the numerator of the fractional division (0 to MOD − 1).

fPFD = REFIN × [(1 + D)/(R × (1 + T))] (2)

where:

REFIN is the reference input frequency.

D is the REFIN doubler bit.

T is the REFIN divide-by-2 bit (0 or 1).

R is the preset divide ratio of the binary 10-bit programmable

reference counter (1 to 1023).

Figure 15. RF INT Divider

INT N MODE

If the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the

synthesizer operates in integer-N mode. The DB8 in Register 2

(LDF) should be set to 1 to get integer-N digital lock detect.

Additionally, lower phase noise is possible if the anti-backlash

pulse width is reduced to 3 ns. This mode is not valid for

fractional-N applications.

R COUNTER

The 10–bit R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock

to the PFD. Division ratios from 1 to 1023 are allowed.

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The phase frequency detector (PFD) takes inputs from the R

counter and N counter and produces an output proportional to

the phase and frequency difference between them. Figure 16 is

a simplified schematic of the phase frequency detector. The

PFD includes a programmable delay element that sets the width

of the antibacklash pulse, which can be either 6 ns (default, for

fractional-N applications) or 3 ns (for integer-N mode). This

pulse ensures there is no dead zone in the PFD transfer function,

and gives a consistent reference spur level.

Figure 16. PFD Simplified Schematic

BUFFER TO R COUNT E R

REF

100kΩ

SW2

SW3

SW1

POWER-DOWN

CONTROL

08226-010

THIRD ORDE R

FRACTIONAL

INTERPOLATOR

FRAC

VALUE

MOD

REG

INT

REG

RF N DIVI DE R

N = INT + FRAC/ M OD

FROM

VCO OUTPUT/

OUTPUT DIVIDERS TO PFD

N COUNTER

08226-011

CLR2

Q2D2 U2

DOWN

HIGH

–IN

+IN

CHARGE

PUMP

DELAY

CLR1

08226-012

ADF4150 Data Sheet

Rev. A | Page 12 of 28

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4150 allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 (for details, see

Figure 22). Figure 17 shows the MUXOUT section in block

diagram form.

Figure 17. MUXOUT Schematic

INPUT SHIFT REGISTERS

The ADF4150 digital section includes a 10-bit RF R counter,

a 16-bit RF N counter, a 12-bit FRAC counter, and a 12-bit

modulus counter. Data is clocked into the 32-bit shift register

on each rising edge of CLK. The data is clocked in MSB first.

Data is transferred from the shift register to one of six latches

on the rising edge of LE. The destination latch is determined

by the state of the three control bits (C3, C2, and C1) in the

shift register. These are the 3 LSBs, DB2, DB1, and DB0, as

shown in Figure 2. The truth table for these bits is shown in

Table 5. Figure 19 shows a summary of how the latches are

programmed.

Table 5. C3, C2, and C1 Truth Table

Control Bits

C3 C2 C1 Register

0 0 0 Register 0 (R0)

0 0 1 Register 1 (R1)

0 1 0 Register 2 (R2)

0 1 1 Register 3 (R3)

1 0 0 Register 4 (R4)

1 0 1 Register 5 (R5)

PROGRAM MODES

Figure 20 through Figure 25 show how the program modes are

to be set up in the ADF4150.

A number of settings in the ADF4150 are double buffered.

These include the modulus value, phase value, R counter

value, reference doubler, reference divide-by-2, and current

setting. This means that two events have to occur before the

part uses a new value of any of the double-buffered settings.

First, the new value is latched into the device by writing to the

appropriate register. Second, a new write must be performed

on Register R0. For example, any time the modulus value is

updated, Register R0 must be written to, thus ensuring the

modulus value is loaded correctly. Divider select in Register 4

(R4) is also double buffered, but only if DB13 of Register 2 (R2)

is high.

OUTPUT STAGE

The RFOUT+ and RFOUT− pins of the ADF4150 are connected

to the collectors of an NPN differential pair driven by buffered

outputs of the VCO, as shown in Figure 18. To allow the user

to optimize the power dissipation vs. the output power require-

ments, the tail current of the differential pair is programmable

by Bit D2 and Bit D1 in Register 4 (R4). Four current levels may

be set. These levels give output power levels of −4 dBm, −1 dBm,

+2 dBm, and +5 dBm, respectively, using a 50 Ω resistor to

AVDD and ac coupling into a 50 Ω load. Alternatively, both

outputs can be combined in a 1 + 1:1 transformer or a 180°

microstrip coupler (see the Output Matching section). If the

outputs are used individually, the optimum output stage

consists of a shunt inductor to AVDD.

Another feature of the ADF4150 is that the supply current

to the RF output stage can be shut down until the part

achieves lock as measured by the digital lock detect circuitr y.

This is enabled by the mute-till-lock detect (MTLD) bit in

Figure 18. Output Stage

GND

CONTROL

MUX MUXOUT

ANALOG LO CK DE TECT

DIGITAL LOCK DETECT

R COUNTER O UTPUT

N COUNTER O UTPUT

DGND

RESERVED

THREE-STATE-OUTPUT

R COUNTER I NP UT

08226-013

VCO

OUT

+RF

OUT

–

BUFFER/

DIVIDE-BY-1/

-2/-4/-8/-16

08226-014

Data Sheet ADF4150

Rev. A | Page 13 of 28

Figure 19. Register Summary

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0N16 N15 N14 N13 N12 N11 N10 N9

RESERVED

16- BIT INTEGER VAL UE (I NT ) 12- BIT FRACT IO NAL VALUE ( F RAC) CONTROL

BITS

N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3(0) C2(0) C1(0)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0PR1 P12 P11 P10 P9

12- BI T PHASE VALUE (PHASE) 12- BIT M ODUL US VALUE ( MOD) CONTROL

BITS

P8 P7 P6 P5 P4 P3 P2 P1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3(0) C2(0) C1(1)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0L2 L1 M3 M2 M1 RD2 RD1 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 D1 CP4 CP3 CP2 CP1 U6 U5 U4 U3 U2 U1 C3(0) C2(1) C1(0)

CSR

RDIV2

REFERENCE

DOUBLER

CHARGE

PUMP

CURRENT

SETTING

10- BIT R COUNTER CONTROL

BITS

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 F3 F2 0 0 F1 0C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(0) C2(1) C1(1)

CONTROL

BITS

12- BIT CLOCK DIVIDER VALUE

LDP

POLARITY

POWER-DOWN

CP THREE-

STATE

COUNTER

RESET

OUTPUT

POW ER

CLK

DIV

MODE

DBR 1

DBR = DOUBLE BUFF E RE D RE GI S TER— BUFF E RE D BY THE WRI TE TO RE GI S TER 0.

DBB = DOUBLE BUFF E RE D BIT S — BUFF E RE D BY THE WRI TE TO RE GI S TER 0, I F AND O NLY I F DB13 O F REGI S TER 2 IS HIG H.

RESERVED

LDF

RESERVED

ABP

CHARGE

CANCEL

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(1) C2(0) C1(0)

CONTROL

BITS

RESERVED RESERVED

RF O UTPUT

ENABLE

LD PI N

MODE

MTLD

DIVIDER

SELECT

FEEDBACK

SELECT

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 D15 D14 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(1) C2(0) C1(1)

CONTROL

BITS

RESERVED

DBB 2

DOUBL E BUFF

RESERVED

DBR

RESERVED

PRESCALER

LOW

NOISE AND

LOW SPUR

MODES MUXOUT

08226-015

ADF4150 Data Sheet

Rev. A | Page 14 of 28

Figure 20. Register 0 (R0)

Figure 21. Register 1 (R1)

N16 N15 ... N5 N4 N3 N2 N1 INTEG ER VAL UE (I NT )

00... 0 0 0 0 0 NOT ALLOW ED

0 0 ... 0 0 00 1 NOT ALLOW ED

00... 00 0 1 0 NOT ALLOW ED

. . ... . . . . . ...

00... 10 1 10NOT ALLOW ED

00... 1 0 11 1 23

00... 11 0 0 0 24

. . ... . . . . ....

11... 11 1 0165533

1 1 ... 1 1 1 1 0 65534

1 1 ... 111 1 165535

F12 F11 .......... F2 F1 FRACTIO NAL VAL UE (FRAC)

0 0 .......... 0 0 0

00.......... 01 1

00.......... 1 0 2

00.......... 1 1 3

. . .......... . . .

............ . . .

. . .......... . . .

11.......... 004092

1 1 .......... 0 1 4093

1 1 .......... 1 0 4094

1 1 ......... 1 1 4095

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0N16 N15 N14 N13 N12 N11 N10 N9

RESERVED

16- BIT INTEGER VALUE ( INT ) 12- BIT FRACT IO NAL VALUE ( F RAC) CONTROL

BITS

N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3(0) C2(0) C1(0)

INTmi n = 75 with prescal er = 8/ 9

08226-016

P12 P11 .......... P2 P1 PHASE VALUE ( PHASE)

0 0 .......... 00 0

00.......... 0 1 1 ( RECOM MENDED)

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

11.......... 0 0 4092

1 1 .......... 0 1 4093

1 1 .......... 1 0 4094

1 1 .......... 114095

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

00 0 0 PR1 P12 P11 P10 P9

12- BI T PHASE VALUE (PHASE) 12- BIT M ODULUS VALUE ( MOD) CONTROL

BITS

P8 P7 P6 P5 P4 P3 P2 P1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3(0) C2(0) C1(1)

RESERVED

M12 M11 ..........

..........

M2 M1 I NTERP OLATOR MO DUL US (M OD)

0 0 1 0 2

0 0 1 1 3

.. . . .

. . . . .

1 1 0 0 4092

11 0 14093

1 1 1 04094

1 1 1 14095

PRESCALER

P1 PRESCALER

04/5

18/9

DBRDBR

08226-017

Data Sheet ADF4150

Rev. A | Page 15 of 28

Figure 22. Register 2 (R2)

RD2REFERENCE

DOUBLER

0DISABLED

1 ENABLED

RD1REFERENCEDIVIDEBY 2

0DISABLED

1ENABLED

CP4 CP3 CP2 CP1 ICP(mA)

4.7kΩ

0 0 0 0 0.31

0 0 0 1 0.63

0010 0.94

00 1 1 1.25

0 1 0 0 1.56

0 1 0 1 1.88

01102.19

01 1 1 2.50

10 0 0 2.81

100 1 3.13

10 1 0 3.44

10 1 1 3.75

11 0 0 4.06

1 1 0 1 4.38

11 1 0 4.69

1 1 1 1 5.00

R10 R9 ..........

..........

R2 R1R DIVIDER (R)

00 0 1 1

0 0 1 0 2

.....

.. . . .

. . . . .

11 0 0 1020

11 0 11021

11 1 0 1022

1 1 1 1 1023

DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0

0 L2 L1 M3 M2 M1 RD2RD1R10 R9R8 R7 R6 R5R4 R3 R2R1D1 CP4 CP3 CP2 CP1 U6 U5 U4 U3 U2 U1 C3(0) C2(1) C1(0)

RDIV2 DBR

REFERENCE

DOUBLER DBR

CHARGE

PUMP

CURRENT

SETTING

10-BIT R COUNTER DBRCONTROL

BITS

LDP

POLARITY

POWER-DOWN

CP THREE-

STATE

COUNTER

RESET

LDF

MUXOUT

DOUBL E BUFF

U5LDP

010ns

1 6ns

U4PDPOLARITY

0 NEGATIVE

1POSITIVE

U3 POWER-DOWN

0 DISABLED

1 ENABLED

U2 CP

THREE-STATE

0DISABLED

1ENABLED

U1 COUNTER

RESET

0DISABLED

1ENABLED

D1DOUBLEBUFFER

R4 DB22:DB20

0DISABLED

1 ENABLED

U6 LDF

0FRAC-N

1 INT-N

RESERVED

M3 M2 M1 OUTPUT

0 0 0 THREE-STATE OUTPUT

00 1 DV

0 1 0 DGND

0 1 1 R DIVIDER OUTPUT

10 0 N DIVIDER OUTPUT

10 1 ANALOG LOCK DETECT

1 1 0 DIGITAL LO CK DETECT

1 1 1 RESERVED

L1 L2 NOISE MODE

0 0 LOW NOISE MODE

0 1 RESERVED

1 0 RESERVED

1 1 LOW SPUR MODE

LOW

NOISE AND

LOW SPUR

MODES

08226-018

ADF4150 Data Sheet

Rev. A | Page 16 of 28

Figure 23. Register 3 (R3)

Figure 24. Register 4 (R4)

C2 C1 CL OCK DIVI DE R M ODE

00CLO CK DIVIDER O F F

0 1 FAST LOCK ENABLE

10RESYNC ENABLE

11RESERVED

D12 D11 .......... D2 D1 CLOCK DI VIDER V ALUE

00.......... 0 0 0

00.......... 01 1

0 0 .......... 1 0 2

00.......... 11 3

............ ...

............ .. .

. . .......... . . .

11.......... 0 0 4092

11.......... 014093

11.......... 104094

11.......... 114095

CSR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

00 0 0 0 00 0 0F1 0C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(0) C2(1) C1(1)

CONTROL

BITS

12- BIT CLOCK DIVI DE R VALUE

CLK

DIV

MODE

RESERVED

F1 CYCLE SLIP

REDUCTION

0DISABLED

1ENABLED

RESERVED

08226-019

F3 F2

F2 CHARGE

CANCELLATION

0 DISABLED

1 ENABLED

F3 ANTIBACKLASH

PULSE WIDTH

0 6ns (FRAC-N)

1 3ns (INT_N)

CHARGE

CANCEL

ABP

D3 RF O UT

0DISABLED

1ENABLED

D2 D1 OUTPUT POWER

0 0 –4

0 1 –1

1 0 +2

1 1 +5

D8 MUTE TILL

LO CK DETE CT

0MUTE DISABLED

1MUTE ENABLE D

D12 D11 RF DIV IDER SEL ECT

0 0 ÷1

0 0 ÷2

0 1 ÷4

0 1 ÷8

D10

1 0 ÷160

D13 FEEDBACK

SELECT

0FUNDAMENTAL

1DIVIDED

08226-020

OUTPUT

POW ER

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(1) C2(0) C1(0)

CONTROL

BITS

RESERVED RESERVED

RF O UTPUT

ENABLE

MTLD

DIVIDER

SELECT

FEEDBACK

SELECT

RESERVED

DBB 2

Data Sheet ADF4150

Rev. A | Page 17 of 28

Figure 25. Register 5 (R5)

LD PIN

MODE

DB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0

0 0 0 0 0 0 0 0 D15D14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(1) C2(0) C1(1)

CONTROL

BITSRESERVEDRESERVED

RESERVED

D15 D14 LOCK DETECT PIN OPERATION

0 0 LOW

0 1 DIGITAL LO CK DETECT

1 0 LOW

1 1 HIGH

RESERVED

08226-021

ADF4150 Data Sheet

Rev. A | Page 18 of 28

Control Bits

With Bits[C3:C1] set to 0, 0, 0, Register 0 is programmed.

Figure 20 shows the input data format for programming this

16-Bit Integer Value (INT)

These 16 bits set the INT value, which determines the integer

part of the feedback division factor. They are used in Equation 1

(see the INT, FRAC, MOD, and R Counter Relationship section).

All integer values from 23 to 65,535 are allowed for 4/5 prescaler.

For 8/9 prescaler, the minimum integer value is 75.

12-Bit Fractional Value(FRAC)

The 12 FRAC bits set the numerator of the fraction that is input

to the Σ-Δ modulator. This, along with INT, specifies the new

frequency channel that the synthesizer locks to, as shown in the

RF Synthesizer—A Worked Example section. FRAC values from

0 to MOD − 1 cover channels over a frequency range equal to

the PFD reference frequency.

Control Bits

With Bits[C3:C1] set to 0, 0, 1, Register 1 is programmed.

Figure 21 shows the input data format for programming

this register.

Prescaler Value

The dual modulus prescaler (P/P + 1), along with the INT,

FRAC, and MOD counters, determines the overall division

ratio from the VCO output to the PFD input.

Operating at CML levels, it takes the clock from the VCO

output and divides it down for the counters. It is based on a

synchronous 4/5 core. When set to 4/5, the maximum RF

frequency allowed is 3 GHz. Therefore, when operating the

ADF4150 above 3 GHz, this must be set to 8/9. The prescaler

limits the INT value, where:

P = 4/5, NMIN = 23

P = 8/9, NMIN = 75

In the ADF4150, P1 in Register 1 sets the prescaler values.

12-Bit Phase Value (Phase)

These bits control what is loaded as the phase word. The word

must be less than the MOD value programmed in Register 1.

The word is used to program the RF output phase from 0° to

360° with a resolution of 360°/MOD. See the Phase Resync

section for more information. In most applications, the phase

relationship between the RF signal and the reference is not

important. In such applications, the PHASE value can be used

to optimize the fractional and subfractional spur levels. See the

Spur Consistency and Fractional Spur Optimization section for

more information.

If neither the PHASE resync nor the spurious optimization

functions are being used, it is recommended that the PHASE

word be set to 1.

12-Bit Modulus Value (MOD)

This programmable register sets the fractional modulus. This

is the ratio of the PFD frequency to the channel step resolution

on the RF output. See the RF Synthesizer—A Worked Example

section for more information.

Control Bits

With Bits[C3:C1] set to 0, 1, 0, Register 2 is programmed.

Figure 22 shows the input data format for programming

this register.

Low Noise and Spur Modes

The noise modes on the ADF4150 are controlled by DB30 and

DB29 in Register 2 (see Figure 22). The noise modes allow the

user to optimize a design either for improved spurious perfor-

mance or for improved phase noise performance.

When the lowest spur setting is chosen, dither is enabled. This

randomizes the fractional quantization noise so it resembles

white noise rather than spurious noise. As a result, the part is

optimized for improved spurious performance. This operation

would normally be used when the PLL closed-loop bandwidth

is wide, for fast-locking applications. (Wide loop bandwidth is

seen as a loop bandwidth greater than 1/10 of the RFOUT channel

step resolution (fRES)). A wide loop filter does not attenuate the

spurs to the same level as a narrow loop bandwidth.

For best noise performance, use the lowest noise setting option.

As well as disabling the dither, it also ensures that the charge

pump is operating in an optimum region for noise performance.

This setting is extremely useful where a narrow loop filter band-

width is available. The synthesizer ensures extremely low noise

and the filter attenuates the spurs. The typical performance

characteristics give the user an idea of the trade-off in a typical

W-CDMA setup for the different noise and spur settings.

Data Sheet ADF4150

Rev. A | Page 19 of 28

MUXOUT

The on-chip multiplexer is controlled by Bits[DB28:DB26] (see

Figure 22).

Reference Doubler

Setting DB25 to 0 feeds the REFIN signal directly to the 10-bit

R counter, disabling the doubler. Setting this bit to 1 multiplies

the REFIN frequency by a factor of 2 before feeding into the

10-bit R counter. When the doubler is disabled, the REFIN

falling edge is the active edge at the PFD input to the fractional

synthesizer. When the doubler is enabled, both the rising and

falling edges of REFIN become active edges at the PFD input.

When the doubler is enabled and the lowest spur mode is

chosen, the in-band phase noise performance is sensitive to the

REFIN duty cycle. The phase noise degradation can be as much

as 5 dB for the REFIN duty cycles outside a 45% to 55% range.

The phase noise is insensitive to the REFIN duty cycle in the

lowest noise mode. The phase noise is insensitive to the REFIN

duty cycle when the doubler is disabled.

The maximum allowable REFIN frequency when the doubler is

enabled is 30 MHz.

RDIV2

Setting the DB24 bit to 1 inserts a divide-by-2 toggle flip-flop

between the R counter and PFD, which extends the maximum

REFIN input rate. This function allows a 50% duty cycle signal

to appear at the PFD input, which is necessary for cycle slip

reduction.

10-Bit R Counter

The 10-bit R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock to

the PFD. Division ratios from 1 to 1023 are allowed.

Double Buffer

DB13 enables or disables double buffering of Bits[DB22:DB20]

in Register 4. The Divider Select section explains how double

buffering works.

Current Setting

Bits[DB12:DB9] set the charge pump current setting. This

should be set to the charge pump current that the loop filter

is designed with (see Figure 22).

LDF

Setting DB8 to 1 enables integer-N digital lock detect, when

the FRAC part of the divider is zero; setting DB8 to 0 enables

fractional-N digital lock detect.

Lock Detect Precision (LDP)

When DB7 is set to 0, the fractional-N digital lock detect is

activated. In this case after setting DB7 to 0, 40 consecutive PFD

cycles of 10 ns must occur before digital lock detect is set. When

DB7 is programmed to 1, 40 consecutive reference cycles of 6 ns

must occur before digital lock detect goes high. Setting DB8 to 1

causes the activation of the integer-N digital lock detect. In this

case, after setting DB7 to 0, 5 consecutive cycles of 10 ns must

occur before digital lock detect is set. When DB7 is set to 1, five

consecutive cycles of 6 ns must occur.

Phase Detector Polarity

DB6 sets the phase detector polarity. When a passive loop filter,

or noninverting active loop filter is used, set this bit to 1. If an

active filter with an inverting characteristic is used, this bit

should be set to 0.

Power-Down (PD)

DB5 provides the programmable power-down mode. Setting this

bit to 1 performs a power-down. Setting this bit to 0 returns the

synthesizer to normal operation. When in software power-down

mode, the part retains all information in its registers. Only if the

supply voltages are removed are the register contents lost.

When a power-down is activated, the following events occur:

• The synthesizer counters are forced to their load state

conditions.

• The charge pump is forced into three-state mode.

• The digital lock detect circuitry is reset.

• The RFOUT buffers are disabled.

• The input register remains active and capable of loading

and latching data.

Charge Pump (CP) Three-State

DB4 puts the charge pump into three-state mode when

programmed to 1. It should be set to 0 for normal operation.

Counter Reset

DB3 is the R counter and N counter reset bit for the ADF4150.

When this bit is 1, the RF synthesizer N counter and R counter

are held in reset. For normal operation, this bit should be set to 0.

ADF4150 Data Sheet

Rev. A | Page 20 of 28

Control Bits

With Bits[C3:C1] set to 0, 1, 1, Register 3 is programmed.

Figure 23 shows the input data format for programming

this register.

Antibacklash Pulse Width

Setting DB22 to 0 sets the PFD antibacklash pulse width to 6 ns.

This is the recommended mode for fractional-N use. By setting

this bit to 1, the 3 ns pulse width is used and results in a phase

noise and spur improvement in integer-N operation. For

fractional-N mode it is not recommended to use this smaller

setting.

Charge Cancellation Mode Pulse Width

Setting DB21 to 1 enables charge pump charge cancellation.

This has the effect of reducing PFD spurs in integer-N mode.

In fractional-N mode, this bit should not be used and the

relevant result in a phase noise and spur improvement. For

fractional-N mode, it is not recommended to use this smaller

setting.

Cycle Slip Reduction (CSR) Enable

Setting DB18 to 1 enables cycle slip reduction. This is a method

for improving lock times. Note that the signal at the phase fre-

quency detector (PFD) must have a 50% duty cycle for cycle slip

reduction to work. The charge pump current setting must also

be set to a minimum. See the Cycle Slip Reduction for Faster

Lock Times section for more information.

Clock Divider Mode

Bits[DB16:DB15] must be set to 1, 0 to activate PHASE resync

or 0, 1 to activate fast lock. Setting Bits[DB16:DB15] to 0, 0

disables the clock divider. See Figure 23.

12-Bit Clock Divider Value

The 12-bit clock divider value sets the timeout counter for

activation of PHASE resync. See the Phase Resync section for

more information. It also sets the timeout counter for fast lock.

See the Fast Lock Timer and Register Sequences section for

more information.

Control Bits

With Bits[C3: C1] set to 1, 0, 0, Register 4 is programmed.

Figure 24 shows the input data format for programming this

Feedback Select

DB23 selects the feedback from VCO output to the N-counter.

When this bit is set to 1, the signal is taken from the VCO directly.

When this bit is set to 0, it is taken from the output of the output

dividers. The dividers enable covering of the wide frequency band

(137.5 MHz to 4.4 GHz). When the divider is enabled and the

feedback signal is taken from the output, the RF output signals

of two separately configured PLLs are in phase. This is useful in

some applications where the positive interference of signals is

required to increase the power.

Divider Select

Bits[DB22:DB20] select the value of the output divider (see

Figure 24).

Mute-Till-Lock Detect

If DB10 is set to 1, the supply current to the RF output stage is shut

down until the part achieves lock as measured by the digital lock

detect circuitry.

RF Output Enable

DB5 enables or disables primary RF output, depending on the

chosen value.

Output Power

DB4 and DB3 set the value of the primary RF output power

level (see Figure 24).

Control Bits

With Bits[C3:C1] set to 1, 0, 1, Register 5 is programmed.

Figure 25 shows the input data form for programming this

Lock Detect PIN Operation

Bits[DB23:DB22] set the operation of the lock detect pin (see

Figure 25).

INITIALIZATION SEQUENCE

The following sequence of registers is the correct sequence for

initial power up of the ADF4150 after the correct application

of voltages to the supply pins:

• Register 5

• Register 4

• Register 3

• Register 2

• Register 1

• Register 0

Data Sheet ADF4150

Rev. A | Page 21 of 28

RF SYNTHESIZER—A WORKED EXAMPLE

The following is an example how to program the ADF4150

synthesizer:

RFOUT = [INT + (FRAC/MOD)] × [fPFD]/RF Divider (3)

where:

RFOUT is the RF frequency output.

INT is the integer division factor.

FRAC is the fractionality.

MOD is the modulus.

RF Divider is the output divider that divides down the VCO

frequency.

fPFD = REFIN × [(1 + D)/(R × (1 + T))] (4)

where:

REFIN is the reference frequency input.

D is the RF REFIN doubler bit.

T is the reference divide-by-2 bit (0 or 1).

R is the RF reference division factor.

For example, in a UMTS system, where 2112.6 MHz RF

frequency output (RFOUT) is required, a 10 MHz reference

frequency input (REFIN) is available, and a 200 kHz channel

resolution (fRESOUT) is required, on the RF output. A 2.1 GHz

VCO would be suitable, but a 4.2 GHz VCO would also be

suitable. In the second case, the RF divider of 2 should be used

(VCO frequency = 4225.2 MHz, RFOUT = VCO frequency/RF

divider = 4225.2 MHz/2 = 2112.6 MHz).

It is also important where the loop is closed. In this example, the

loop is closed as depicted in Figure 26 (from the out divider).

Figure 26. Loop Closed Before Output Divider

A channel resolution (fRESOUT) of 200 kHz is required at the

output of the RF divider. Therefore, channel resolution at

the output of the VCO (fRES) is to be twice the fRESOUT, that

is, 400 kHz.

MOD = REFIN/fRES

MOD = 10 MHz/400 kHz = 25

From Equation 4

fPFD = [10 MHz × (1 + 0)/1] = 10 MHz (5)

2112.6 MHz = 10 MHz × (INT + FRAC/25)/2 (6)

where:

INT = 422

FRAC = 13

MODULUS

The choice of modulus (MOD) depends on the reference signal

(REFIN) available and the channel resolution (fRES) required at

the RF output. For example, a GSM system with 13 MHz REFIN

sets the modulus to 65. This means the RF output resolution (fRES)

is the 200 kHz (13 MHz/65) necessary for GSM. With dither off,

the fractional spur interval depends on the modulus values chosen

(see Table 6).

REFERENCE DOUBLER AND REFERENCE DIVIDER

The reference doubler on-chip allows the input reference signal

to be doubled. This is useful for increasing the PFD comparison

frequency. Making the PFD frequency higher improves the

noise performance of the system. Doubling the PFD frequency

usually improves noise performance by 3 dB. It is important

to note that the PFD cannot operate above 32 MHz due to a

limitation in the speed of the Σ-Δ circuit of the N-divider.

The reference divide-by-2 divides the reference signal by 2,

resulting in a 50% duty cycle PFD frequency. This is necessary

for the correct operation of the cycle slip reduction (CSR)

function. See the Cycle Slip Reduction for Faster Lock Times

section for more information.

12-BIT PROGRAMMABLE MODULUS

Unlike most other fractional-N PLLs, the ADF4150 allows the

user to program the modulus over a 12-bit range. This means

the user can set up the part in many different configurations for

the application, when combined with the reference doubler and

the 10-bit R counter.

For example, consider an application that requires 1.75 GHz RF

and 200 kHz channel step resolution. The system has a 13 MHz

reference signal.

One possible setup is feeding the 13 MHz directly to the PFD

and programming the modulus to divide by 65. This results in

the required 200 kHz resolution.

Another possible setup is using the reference doubler to create

26 MHz from the 13 MHz input signal. The 26 MHz is then fed

into the PFD programming the modulus to divide by 130. This

also results in 200 kHz resolution and offers superior phase

noise performance over the previous setup.

The programmable modulus is also very useful for multi-

standard applications. If a dual-mode phone requires PDC

and GSM 1800 standards, the programmable modulus is a

great benefit. PDC requires 25 kHz channel step resolution,

whereas GSM 1800 requires 200 kHz channel step resolution.

PFD

PFD VCO

DIVIDER

÷2 RF

OUT

08226-022

ADF4150 Data Sheet

Rev. A | Page 22 of 28

A 13 MHz reference signal can be fed directly to the PFD, and

the modulus can be programmed to 520 when in PDC mode

(13 MHz/520 = 25 kHz).

The modulus needs to be reprogrammed to 65 for GSM 1800

operation (13 MHz/65 = 200 kHz).

It is important that the PFD frequency remain constant (13 MHz).

This allows the user to design one loop filter for both setups

without running into stability issues. It is important to remem-

ber that the ratio of the RF frequency to the PFD frequency

principally affects the loop filter design, not the actual channel

spacing.

CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES

As outlined in the Low Noise and Spur Mode section, the

ADF4150 contains a number of features that allow optimization

for noise performance. However, in fast locking applications,

the loop bandwidth generally needs to be wide, and therefore,

the filter does not provide much attenuation of the spurs. If

the cycle slip reduction feature is enabled, the narrow loop

bandwidth is maintained for spur attenuation but faster lock

times are still possible.

Cycle Slips

Cycle slips occur in integer-N/fractional-N synthesizers when

the loop bandwidth is narrow compared to the PFD frequency.

The phase error at the PFD inputs accumulates too fast for the

PLL to correct, and the charge pump temporarily pumps in the

wrong direction. This slows down the lock time dramatically.

The ADF4150 contains a cycle slip reduction feature that

extends the linear range of the PFD, allowing faster lock

times without modifications to the loop filter circuitry.

When the circuitry detects that a cycle slip is about to occur,

it turns on an extra charge pump current cell. This outputs a

constant current to the loop filter, or removes a constant

current from the loop filter (depending on whether the VCO

tuning voltage needs to increase or decrease to acquire the

new frequency). The effect is that the linear range of the PFD

is increased. Loop stability is maintained because the current

is constant and is not a pulsed current.

If the phase error increases again to a point where another cycle

slip is likely, the ADF4150 turns on another charge pump cell.

This continues until the ADF4150 detects the VCO frequency

has gone past the desired frequency. The extra charge pump

cells are turned off one by one until all the extra charge pump

cells have been disabled and the frequency is settled with the

original loop filter bandwidth.

Up to seven extra charge pump cells can be turned on. In most

applications, it is enough to eliminate cycle slips altogether,

giving much faster lock times.

Setting Bit DB18 in Register 3 to 1 enables cycle slip reduction.

Note that the PFD requires a 45% to 55% duty

cycle for CSR to operate correctly.

SPURIOUS OPTIMIZATION AND FAST LOCK

Narrow loop bandwidths can filter unwanted spurious signals,

but these usually have a long lock time. A wider loop bandwidth

achieves faster lock times, but a wider loop bandwidth may lead

to increased spurious signals inside the loop bandwidth.

The fast lock feature can achieve the same fast lock time as the

wider bandwidth, but with the advantage of a narrow final loop

bandwidth to keep spurs low.

FAST LOCK TIMER AND REGISTER SEQUENCES

If the fast lock mode is used, a timer value is to be loaded into

the PLL to determine the duration of the wide bandwidth mode.

When Bits[DB16:DB15] in Register 3 are set to 0, 1 (fast

lock enable), the timer value is loaded by the 12-bit clock

divider value. The following sequence must be programmed

to use fast lock:

1. Initialization sequence (see the Initialization Sequence

section); occurs only once after powering up the part.

2. Load Register 3 by setting Bits[DB16:DB15] to 0, 1 and

the chosen fast lock timer value [DB14:DB3]. Note that

the duration the PLL remains in wide bandwidth is equal

to the fast lock timer/fPFD.

Data Sheet ADF4150

Rev. A | Page 23 of 28

FAST LOCK—AN EXAMPLE

If a PLL has a reference frequency of 13 MHz, fPFD of 13 MHz

and a required lock time of 50 µs, the PLL is set to wide bandwidth

for 40 µs. This example assumes a modulus of 65 for channel

spacing of 200 kHz.

If the time period set for the wide bandwidth is 40 µs, then

Fast Lock Timer Value = Time In Wide Bandwidth × fPFD/MOD

Fast Lock Timer Value = 40 µs × 13 MHz/65 = 8

Therefore, 8 must be loaded into the clock divider value in

Timer and Register Sequences section.

FAST LOCK—LOOP FILTER TOPOLOGY

To use fast lock mode, the damping resistor in the loop filter

is reduced to ¼ of its value while in wide bandwidth mode. To

achieve the wider loop filter bandwidth, the charge pump

current increases by a factor of 16. To maintain loop stability,

the damping resistor must be reduced a factor of ¼. To enable

fast lock, the SW pin is shorted to the GND pin by settings

Bits[DB16:DB15] in Register 3 to 0, 1. The following two

topologies are available:

• The damping resistor (R1) is divided into two values (R1

and R1A) that have a ratio of 1:3 (see Figure 27).

• An extra resistor (R1A) is connected directly from SW,

as shown in Figure 28. The extra resistor is calculated

such that the parallel combination of an extra resistor

and the damping resistor (R1) is reduced to ¼ of the

original value of R1 (see Figure 28).

Figure 27. Fast Lock Loop Filter Topology—Topology 1

Figure 28. Fast Lock Loop Filter Topology—Topology 2

SPUR MECHANISMS

This section describes the three different spur mechanisms that

arise with a fractional-N synthesizer and how to minimize them

in the ADF4150.

Fractional Spurs

The fractional interpolator in the ADF4150 is a third-order Σ-Δ

modulator (SDM) with a modulus (MOD) that is programmable

to any integer value from 2 to 4095. In low spur mode (dither

enabled), the minimum allowable value of MOD is 50. The

SDM is clocked at the PFD reference rate (fPFD) that allows PLL

output frequencies to be synthesized at a channel step resolution

of fPFD/MOD.

In low noise mode (dither off), the quantization noise from the

Σ-Δ modulator appears as fractional spurs. The interval between

spurs is fPFD/L, where L is the repeat length of the code sequence

in the digital Σ-Δ modulator. For the third-order modulator

used in the ADF4150, the repeat length depends on the value

of MOD, as listed in Table 6.

Table 6. Fractional Spurs with Dither Off

Condition (Dither Off)

Repeat

Length Spur Interval

If MOD is divisible by 2 but not 3

2 × MOD

Channel step/2

If MOD is divisible by 3 but not 2

3 × MOD

Channel step/3

If MOD is divisible by 6 6 × MOD Channel step/6

Otherwise MOD Channel step

In low spur mode (dither on), the repeat length is extended to

221 cycles, regardless of the value of MOD, which makes the

quantization error spectrum look like broadband noise. This

may degrade the in-band phase noise at the PLL output by as

much as 10 dB. For lowest noise, dither off is a better choice,

particularly when the final loop bandwidth is low enough to

attenuate even the lowest frequency fractional spur.

Integer Boundary Spurs

Another mechanism for fractional spur creation is the inte-

ractions between the RF VCO frequency and the reference

frequency. When these frequencies are not integer related (the

point of a fractional-N synthesizer) spur sidebands appear on

the VCO output spectrum at an offset frequency that corres-

ponds to the beat note or difference frequency between an

integer multiple of the reference and the VCO frequency. These

spurs are attenuated by the loop filter and are more noticeable

on channels close to integer multiples of the reference where

the difference frequency can be inside the loop bandwidth,

therefore the name integer boundary spurs.

ADF4150

C1 C2

R1A

VCO

08226-023

ADF4150 CP

C1 C2

R1A

VCO

08226-024

ADF4150 Data Sheet

Rev. A | Page 24 of 28

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypasses the loop can cause a problem. Feedthrough of low

levels of on-chip reference switching noise, through the RFIN

pin back to the VCO, can result in reference spur levels as high

as −90 dBc. PCB layout needs to ensure adequate isolation

between VCO traces and the input reference to avoid a possible

feedthrough path on the board.

SPUR CONSISTENCY AND FRACTIONAL SPUR

OPTIMIZATION

With dither off, the fractional spur pattern due to the quanti-

zation noise of the SDM also depends on the particular phase

word with which the modulator is seeded.

The phase word can be varied to optimize the fractional and

subfractional spur levels on any particular frequency. Thus, a

look-up table of phase values corresponding to each frequency

can be constructed for use when programming the ADF4150.

If a look-up table is not used, keep the phase word at a constant

value to ensure consistent spur levels on any particular frequency.

PHASE RESYNC

The output of a fractional-N PLL can settle to any one of the

MOD phase offsets with respect to the input reference, where

MOD is the fractional modulus. The phase resync feature in the

ADF4150 produces a consistent output phase offset with respect

to the input reference. This is necessary in applications where the

output phase and frequency are important, such as digital beam

forming. See the Phase Programmability section for how to

program a specific RF output phase when using phase resync.

Phase resync is enabled by setting Bit DB16, Bit DB15 in

timer generates sync signals at intervals of tSYNC given by the

following formula:

tSYNC = CLK_DIV_VALUE × MOD × tPFD

where:

tPFD is the PFD reference period.

CLK_DIV_VALUE is the decimal value programmed in

Bits[DB14:DB3] of Register 3 and can be any integer in the

range of 1 to 4095.

MOD is the modulus value programmed in Bits[DB14:DB3] of

When a new frequency is programmed, the second sync pulse

after the LE rising edge is used to resynchronize the output

phase to the reference. The tSYNC time is to be programmed to

a value that is at least as long as the worst-case lock time. This

guarantees that the PHASE resync occurs after the last cycle slip

in the PLL settling transient.

In the example shown in Figure 29, the PFD reference is 25 MHz

and MOD is 125 for a 200 kHz channel spacing. tSYNC is set to

400 µs by programming CLK_DIV_VALUE to 80.

Figure 29. Phase Resync Example

Phase Programmability

The phase word in Register 1 controls the RF output phase. As

this word is swept from 0 to MOD, the RF output phase sweeps

over a 360° range in steps of 360°/MOD.

PHASE

FREQUENCY

SYNC

(INTERNAL)

–100 0100 200 1000

300 400 500 600 700 800 900

TIME (µs)

PLL SETTLES TO

CORRE CT PHAS E

AFTER RE S Y NC

SYNC

LAST CYCLE SLIP

PLL SETTLES TO

INCORRECT PHASE

08226-025

Data Sheet ADF4150

Rev. A | Page 25 of 28

APPLICATIONS INFORMATION

DIRECT CONVERSION MODULATOR

Direct conversion architectures are increasingly being used to

implement base station transmitters. Figure 30 shows how Analog

Devices, Inc., parts can be used to implement such a system.

The circuit block diagram shows the AD9788 TxDAC® being

used with the ADL5375. The use of dual integrated DACs, such

as the AD9788 with its specified ±0.02 dB and ±0.004 dB gain

and offset matching characteristics, ensures minimum error

contribution (over temperature) from this portion of the

signal chain.

The local oscillator (LO) is implemented using the ADF4150.

The low-pass filter was designed using ADIsimPLL™ for a channel

spacing of 200 kHz and a closed-loop bandwidth of 35 kHz.

The LO ports of the ADL5375 can be driven differentially from

the RFOUT+ and RFOUT− outputs of the ADF4150. This gives

better performance than a single-ended LO driver and

eliminates the use of a balun to convert from a single-ended LO

input to the more desirable differential LO inputs for the

ADL5375. The typical rms phase noise (100 Hz to 5 MHz) of

the LO in this configuration is 0.61°rms.

The ADL5375 accepts LO drive levels from −10 dBm to 0 dBm.

The optimum LO power can be software programmed on the

ADF4150, which allows levels from −4 dBm to +5 dBm from

each output.

The RF output is designed to drive a 50 Ω load but must be

ac-coupled, as shown in Figure 30. If the I and Q inputs are

driven in quadrature by 2 V p-p signals, the resulting output

power from the modulator is approximately 2 dBm.

Figure 30. Direct Conversion Modulator

AD9788

TxDAC

REFIO

FSADJ

MODULATED

DIGITAL

DATA

QOUTB

IOUTA

IOUTB

QOUTA

2kΩ

LOW-PASS

FILTER

LOW-PASS

FILTER

2700pF 1200pF

39nF

680Ω

360Ω

IBBP

IBBN

QBBP

QBBN

LOIP

LOIN

SPI - COMPATIBLE SERIAL BUS

ADF4150

GND

OUT

–

OUT

1nF1nF

4.7kΩ

SET

DATA

CLK

REF

FREF

CE MUXOUT

VCO

OUT

VCO

TUNE

1618

812 13 23

LOCK

DETECT

51Ω

51Ω51Ω

PDB

17 622

SDV

ADL5375

RFOUT

QUADRATURE

PHASE

SPLITTER

DSOP

–

VCO

3.9nH 3.9nH

1nF

100pF

VCO

08226-026

ADF4150 Data Sheet

Rev. A | Page 26 of 28

INTERFACING

The ADF4150 has a simple SPI-compatible serial interface

for writing to the device. CLK, DATA, and LE control the data

transfer. When LE goes high, the 32 bits that have been clocked

into the appropriate register on each rising edge of CLK are

transferred to the appropriate latch. See Figure 2 for the timing

diagram and Table 5 for the register address table.

ADuC812 Interface

Figure 31 shows the interface between the ADF4150 and the

ADuC812 MicroConverter®. Because the ADuC812 is based

on an 8051 core, this interface can be used with any 8051-based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4150 needs a

32-bit word, which is accomplished by writing four 8-bit bytes

from the MicroConverter to the device. When the fourth byte

has been written, the LE input should be brought high to

complete the transfer.

Figure 31. ADuC812 to ADF4150 Interface

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and detect lock (MUXOUT configured as

lock detect and polled by the port input). When operating in

the described mode, the maximum SCLOCK rate of the

ADuC812 is 4 MHz. This means that the maximum rate at

which the output frequency can be changed is 125 kHz.

ADSP-21xx Interface

Figure 32 shows the interface between the ADF4150 and a

ADSP-21xx digital signal processor. The ADF4150 needs a

32-bit serial word for each latch write. The easiest way to

accomplish this using the ADSP-21xx family is to use the

autobuffered transmit mode of operation with alternate

framing. This provides a means for transmitting an entire

block of serial data before an interrupt is generated.

Figure 32. ADSP-21xx to ADF4150 Interface

Set up the word length for 8 bits and use four memory locations

for each 32-bit word. To program each 32-bit latch, store the 8-bit

bytes, enable the autobuffered mode, and write to the transmit

transfer.

PCB DESIGN GUIDELINES FOR CHIP SCALE

PACKAGE

The lands on the chip scale package (CP-24-7) are rectangular.

The PCB pad for these is to be 0.1 mm longer than the package

land length and 0.05 mm wider than the package land width.

The land is to be centered on the pad. This ensures the solder

joint size is maximized. The bottom of the chip scale package

has a central thermal pad.

The thermal pad on the PCB is to be at least as large as the

exposed pad. On the PCB, there is to be a minimum clearance

of 0.25 mm between the thermal pad and the inner edges of the

pad pattern. This ensures that shorting is avoided.

Thermal vias can be used on the PCB thermal pad to improve

the thermal performance of the package. If vias are used, they

are to be incorporated in the thermal pad at 1.2 mm pitch grid.

The via diameter is to be between 0.3 mm and 0.33 mm, and the

via barrel is to be plated with one ounce copper to plug the via.

ADuC812

ADF4150

CLK

SDATA

MUXOUT

(LOCK DETECT)

SCLOCK

MOSI

I/O PORTS

08226-027

ADSP-21xx

ADF4150

CLK

SDATA

MUXOUT

(LOCK DETECT)

SCLK

MOSI

TFS

I/O PORTS

08226-028

Data Sheet ADF4150

Rev. A | Page 27 of 28

OUTPUT MATCHING

There are a number of ways to match the output of the ADF4150

for optimum operation; the most basic is to use a 50 Ω resistor to

AVDD. A dc bypass capacitor of 100 pF is connected in series as

shown in Figure 33. Because the resistor is not frequency

dependent, this provides a good broadband match. The output

power in this circuit into a 50 Ω load typically gives values

chosen by Bits[DB4:DB3] in Register 4 (R4).

Figure 33. Simple ADF4150 Output Stage

A better solution is to use a shunt inductor (acting as an RF

choke) to AVDD. This gives a better match and, therefore, more

output power.

Experiments indicate that the circuit shown in Figure 34

provides an excellent match to 50 Ω for the W-CDMA UMTS

Band 1 (2110 MHz to 2170 MHz). The maximum output power

in that case is about 7 dBm. Both single-ended architectures can

be examined using the EVAL-ADF4150EB1Z evaluation board.

Figure 34. Optimum ADF4150 Output Stage

If differential outputs are not needed, the unused output can be

terminated or combined with both outputs using a balun.

08226-029

50Ω

100pF

OUT

50Ω

3.9nH

1nF

OUT

50Ω

08226-030

ADF4150 Data Sheet

Rev. A | Page 28 of 28

OUTLINE DIMENSIONS

Figure 35. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm ×4 mm Body, Very Very Thin Quad

(CP-24-7)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADF4150BCPZ −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-7

ADF4150BCPZ-RL7 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-24-7

EVAL-ADF4150EB1Z Evaluation Board

1 Z = RoHS Compliant Part.

0.50

BSC

0.50

0.40

0.30

0.25

0.18

COMPLIANT

JEDEC S TANDARDS MO-220- WG GD.

04-12-2012-A

BOTTOM VIEWTOP VI EW

EXPOSED

PAD

PI N 1

INDICATOR

4.10

4.00 S Q

3.90

SEATING

PLANE

0.80

0.75

0.70

0.20 RE F

0.25 M IN

COPLANARITY

0.08

PI N 1

INDICATOR

2.65

2.50 S Q

2.45

1819

FOR PRO P E R CONNECTI ON O F

THE EXPOSED PAD, REFER TO

THE P IN CONFI GURAT IO N AND

FUNCTION DES CRIPTI ONS

SECTION OF THIS DATA SHEET.

0.05 M AX

0.02 NOM

registered trademarks are the property of their respective owners.

D08226-0-11/13(A)

Mouser Electronics

Authorized Distributor

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