SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
PIN CONFIGURATION (TOP VIEW)
DESCRIPTION
M66850/851/852/853 are very high-speed and clock synchronous
FIFO(First-In,First-Out) memories fabricated by high-speed CMOS
technology.
These FIFOs are applicable for a data buffer as networks and
communications.
The write operation is controlled by a write clock pin(WCLK) and
two write enable pins(WEN1,WEN2).
Data present at the data input pins(D0-D8) is written into the
Synchronous FIFO on every rising write clock edge when the
device is enabled for writing.
The read operation is controlled by a read clock pin(RCLK) and
two read enable pins(REN1,REN2).
Data is read from the Synchronous FIFO on every rising read clock
edge when the device is enabled for reading. An output enable
pin(OE) controls the states of the data output pins(Q0-Q8).
MITSUBISHI FIFOs have four flags (EF,FF,PAE,PAF). The empty
flag EF and the full flag FF are fixed flags. The almost empty flag
PAE and the almost full flag PAF are programmable flags. The
programmable flag offset is initiated by the load pin(LD).
FEATURES
• Memory configuration 64words x 9bits (M66850J/FP)
256words x 9bits (M66851J/FP)
512words x 9bits (M66852J/FP)
1024words x 9bits (M66853J/FP)
• Write and Read Clocks can be independent
• Advanced CMOS technology
• Programmable Almost-Empty and Almost-Full flags
• High-speed : 25ns cycle time
• Package Available :
32-pin Pastic Leaded Chip Carrier(PLCC)
32-pin Low profile Quad Flat Package(LQFP)
APPLICATION
• Data Buffer for networks communications.
Outline 32P0(M66850 – 853J)
4
3
2
1
32
31
30
29
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
5
6
7
8
9
10
11
12
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
OE
EF
FF
Q0
Q1
Q2
Q3
Q4
RS
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
D2
D3
D4
D5
D6
D7
D8
Outline 32P6B(M66850 – 853FP)
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
OE
Q0
Q1
Q2
Q3
Q4
EF
FF
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
RS
D2
D3
D4
D5
D6
D7
D8
BLOCK DIAGRAM
RESET
LOGIC
WRITE
CONTROL
WRITE
POINTER
INPUT
REGISTER
OUTPUT
REGISTER
READ
POINTER
READ
CONTROL
OFFSET
REGISTER
FLAG
LOGIC
WCLK
Q0-Q8
RCLK
WEN1
WEN2
RS
OE
REN1
REN2
EF
PAE
FF
PAF
LD
MEMORY
ARRAY
D0-D8
1
–
–
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
PIN and SIGNAL DESCRIPTIONS
•VCC
One+5 volt power supply pin.
• GND
One 0 volt ground pin.
• RS : Reset(INPUT)
When RS is set LOW, internal read and write pointers are set to
the first physical location,the output register is initialized to LOW,
FF and PAF are set HIGH, EF and PAE are set LOW.
A reset is required after power-up before a write operation.
• WCLK : Write Clock(INPUT)
Data present on D0-D8 is written into the FIFO on the rising edge
of WCLK when the FIFO is enabled for writing.
• RCLK : Read Clock(INPUT)
Data is read from the FIFO on the rising edge of RCLK when the
FIFO is enabled for reading.
• WEN1 : Write Enable1(INPUT)
If the FIFO is configured to allow loading of the offset registers,
WEN1 is the only the write enable. When WEN1 is LOW, data on
D0-D8 is written to the FIFO on the rising edge of WCLK.
If the FIFO is configured to have two writeenables, data on D0-
D8 is written to the FIFO on the rising edge of WCLK when
WEN1 is LOW and WEN2 is High. But if the FF is LOW, data on
D0-D8 will not be written to the FIFO.
• WEN2/LD : Write Enable2/Load(INPUT)
The function of this signal is defined at reset.
If WEN2/LD is HIGH at reset, this signal functions as a second
write enable(WEN2). If WEN2/LD is LOW at reset, this signal
functions as a control to load and read the offset register.
If the FIFO is configured to have two write enables, data on D0-
D8 is written to the FIFO on the rising edge of WCLK when
WEN1 is LOW and WEN2 is High. But if the FF is LOW, data on
D0-D8 will not be written to the FIFO.
If the FIFO is configured to have programmable flags, it is
possible to write and read from the offset registers. There are
four 9-bit offset registers. Two are used to control the
programmable Almost-Empty Flag
and
two are used to control the
programmable Almost-Full Flag.
Data on D0-D8 is written to an offset register on the rising edge
of WCLK when WEN1 is LOW and LD is LOW. Data on D0 – D8
is written to the offset registers in the following order :
PAE LSB, PAE MSB, PAF LSB, PAF MSB.
• REN1, REN2 : Read Enable(INPUT)
Data is read from the FIFO and presented Q0-8 on the rising
edge of RCLK, when REN1 and REN2 are LOW and output port
is enabled.
If either Read Enable is HIGH,the output register holds the
previous data.
When the FIFO is empty, the Read Enable signals are ignored.
• OE : Output Enable(INPUT)
When OE is LOW, the output port Q0-8 is enabled for output.
When OE is HIGH, the output port Q0-8 is placed in a high
impedance state.
• D0-8 : Data Input(INPUT)
D0-8 is the 9-bit data input port.
• Q0-8 : Data Output(OUTPUT)
Q0-8 is the 9-bit data Output port.
• EF : Empty Flag(OUTPUT)
The Empty flag goes LOW when the read pointer is equal to the
write pointer.
When EF is LOW, the FIFO is empty and further data reads from
the data output are inhibited.
EF is synchronized to the rising edge of RCLK.
• PAE : Programmable Almost-Empty Flag(OUTPUT)
When PAE is LOW, the FIFO is almost empty based on the
offset. The default offset is Empty+7. PAE is synchronized to the
rising edge of RCLK.
• FF : Full Flag(OUTPUT)
When FF is LOW, the FIFO is full and further data writes into the
data input are inhibited.
The Full Flag goes LOW when the FIFO is full of data.
FF is synchronized to the rising edge of WCLK.
• PAF : Programmable Almost-Full Flag(OUTPUT)
When PAF is LOW, the FIFO is almost full based on the offset.
The default offset is Full-7. PAF is synchronized to the rising
edge of WCLK.
2
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
OFFSET FLAG
Figure 1. Write Offset Register
Figure 2. Read Offset Register
LD WEN1 WCLK SELECTION
0 0 Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0 1 No Operation
1 0 Write into FIFO
1 1 No Operation
Figure 3. Offset Regigter Location
M66850J(64X9-bit) OFFSET REGISTERS
E0/F0 are the least significant bits.
X=Don't Care.
LD REN1 REN2 RCLK SELECTION
0 0 0 Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0 0 1
1 0 No Operation
1 1
1 1 0 Read from FIFO
1 0 1
1 0 No Operation
1 1
876543210
X X X E5E4E3E2E1E0
Default Value 007H
XXXXXXXXX
X X X F5F4F3F2F1F0
Default Value 007H
XXXXXXXXX
PAE LSB
PAE MSB
PAF LSB
PAF MSB
M66851J(256X9-bit) OFFSET REGISTERS
876543210
XE7E6E5E4E3E2E1E0
Default Value 007H
XXXXXXXXX
XF7F6F5F4F3F2F1F0
Default Value 007H
XXXXXXXXX
PAE LSB
PAE MSB
PAF LSB
PAF MSB
M66852J(512X9-bit) OFFSET REGISTERS
876543210
XE7E6E5E4E3E2E1E0
Default Value 007H
XXXXXXXXE8
Default Value 0
XF7F6F5F4F3F2F1F0
Default Value 007H
XXXXXXXXF8
Default Value 0
PAE LSB
PAE MSB
PAF LSB
PAF MSB
M66853J(1024X9-bit) OFFSET REGISTERS
876543210
XE7E6E5E4E3E2E1E0
Default Value 007H
XXXXXXXE9E8
Default Value 0 0
XF7F6F5F4F3F2F1F0
Default Value 007H
XXXXXXXF9F8
Default Value 0 0
PAE LSB
PAE MSB
PAF LSB
PAF MSB
3
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
"H"input voltage
"L"input voltage
IOZH
IOZL
0
COOff state output capacitance
V
V
V
V
µ
A
ICC1
IIL
"L"output voltage
"H"input current
Supply voltage
Input voltage
Output voltage
Vcc
ABSOLUTE MAXIMUM RATINGS
Symbol Ratings Unit
Parameter Conditions
VI
VO
Pd
Tstg Maximum power dissipation
Storage temperature
A value based on GND pin -0.5 – +7.0
-0.3 – VCC+0.5
-0.3 – VCC+0.5
Note
-65 – 150 ˚C
mW
V
V
V
RECOMMENDED OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS (Ta=0 – 70˚C, Vcc=5V±10%, GND=0V)
V
V
Limits
Min. Typ. Max.
Symbol UnitParameter
Vcc Supply voltage 4.5 5.5
˚C
GND
Topr Supply voltage
Operating ambient temperature
Limits
Min. Typ. Max.
Symbol Test conditions UnitParameter
VIH 2.0 0.8
"H"output voltage 2.4 0.4
"L"input current -1.0
µ
A
Off state "H"output current
µ
A
µ
A
70 mA
10 pF
pF
VIL
VOH
VOL
IIH
CI
Off state "L"output current
Operating power supply current
Input capacitance
IOH =-1mA
IOL =8mA
VI =VCC, Any input
VI =GND, Any input
VO =VCC
VO =GND
VI =VCC or GND, f=40MHz, Outputs are open
f = 1MHz
f = 1MHz
1.0
5.0
-5.0
15
070
Ta=70˚C
5
4
Note : 450mW(32P6B), 550mW(32P0)
ICC2 500
µ
A
Power supply current (Static) VI =VCC or GND, Outputs are open
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
Write Clock to Almost-Full Flag
tREF
tPAF
Read Clock to Empty Flag
25
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
ns
ns
ns
ns
SWITCHING CHARACTERISTICS (Ta=0 – 70˚C, Vcc=5V±10%, GND=0V)
Limits
Min. Typ. Max.
Symbol UnitParameter
tAC 15
tWFF
Data Access Time
Write Clock to Full Flag 3
0
3
ns
TIMING CONDITIONS (Ta=0 – 70˚C, Vcc=5V±10%, GND=0V)
Limits
Min. Typ. Max.
Symbol UnitParameter
tDH
tENS
tENH
tRS
tRSS
tRSR
tSKEW1
tSKEW2
Clock Pulse Width HIGH
Clock Pulse Width LOW
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width
Reset Setup Time
Skew time between Read Clock and Write Clock for Empty Flag and Full Flag
Skew time between Read Clock and Write Clock for Almost-Empty Flag and Almost-Full
Flag
10
10
6
1
6
1
25
25
25
10
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPAE
tOE
tOLZ
tOHZ
tRSF
Read Clock to Almost-Empty Flag
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Enable to Output in High-Z
Reset to Flag and Output Valid time
ns
ns
ns
ns
ns
3
15
15
15
15
13
13
25
Reset Recovery Time
AC TEST CONDITIONS
In Pulse Levels GND – 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 4
D.U.T.
1.1kΩ
30pF
680Ω
5.0V
Figure 4. Output Load
Including Test board and scope capacitances.
5
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
•Reset Timing
RS
tRSF
tRSF
tRSS
tRSR
NOTE :
1. If during reset WEN2/LD is HIGH,this signal functions as a second enable(WEN2).
If during reset WEN2/LD is LOW,this signal functions as an offset register.
REN1
REN2
WEN1
WEN2/LD (1)
EF, PAE
FF, PAE
Q0-8
tRSF
OE=1
OE=0
tRSR
tRSR
tRSS
tRSS
tRS
6
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
NOTE :
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle.
If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state untill
the next WCLK edge.
•Write Cycle Timing
WCLK
WEN2/(if Applicable)
tWFF
tCLK
tCLKH tCLKL
DATA IN VALID
tDS tDH
tENS tENH
NO OPERATION
tSKEW1 (1)
D0-D8
WEN1
FF
RCLK
REN1
REN2
tWFF
NO OPERATION
7
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
NOTE :
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for EF to change during the current clock
cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not
change state untill the next RCLK edge.
•Read Cycle Timing
RCLK
EF
REN1
REN2
WEN1
Q0-8
WCLK
tREF
tCLK
OE
tCLKH tCLKL
tENS tENH
NO OPERATION
tOHZ
tSKEW1(1)
tREF
tAC
tOE
VALID DATA
tOLZ
WEN2
8
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
•First Data Word Latency Timing
tDS
D0 (First Valid)
D1 D2 D3
tFRL (1)
tSKEW1
tREF
D1
D0
tAC tAC
tOE
tOLZ
tENS
WCLK
WEN2
(If Applicable)
D0-D8
WEN1
EF
RCLK
REN1
REN2
Q0-Q8
OE
NOTE :
1. When tSKEW1≥minimum specification, tFRL maximum=tCLK+tSKEW1.
When tSKEW1≤minimum specification, tFRL maximum=2tCLK+tSKEW1 or tCLK+tSKEW1.
9
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
•Full Flag Timing
DATA WRITE
tDS
tDS
tSKEW1
tSKEW1
NO WRITE NO WRITE
tWFF tWFF tWFF
tENS
tENS tENH tENH
LOW
tAC
tAC
DATA IN OUTPUT REGISTER DATA READ NEXT DATA READ
WCLK
WEN2
(If Applicable)
D0-D8
WEN1
FF
RCLK
REN1
REN2
Q<8:0>
OE
10
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
•Empty Flag Timing
tDS
tFRL (1)
tSKEW1
tREF
tAC
tENH tENH
tENS tENS
tENS tENH
tREF tREF
tFRL (1)
LOW
DATA IN OUTPUT REGISTER DATA READ
tDS
DATA WRITE1 DATA WRITE2
tSKEW1
WCLK
WEN2
(If Applicable)
D0-D8
WEN1
EF
RCLK
REN1
REN2
Q0-Q8
OE
tENH
tENS
NOTE :
1. When tSKEW1≥minimum specification, tFRL maximum=tCLK+tSKEW1.
When tSKEW1≤minimum specification, tFRL maximum=2tCLK+tSKEW1 or tCLK+tSKEW1.
11
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
•Programmable Full Flag Timing
tCLKH tCLKL
tENS tENH
tENS tENH
tENS tENH
tPAF
tPAF
Full-(m+1) words in FIFO(1) Full-m words
in FIFO(2)
tSKEW2(3)
(4)
WCLK
WEN1
RCLK
REN1
REN2
WEN2
(If Applicable)
PAF
NOTES :
1. PAF offset=m.
2. 64-m words in for M66850, 256-m words in for M66851,512-m words in for M66852, 1024-m words in for M66853.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle.
If the time between the rising edge of RCLK and the rising edge of WCLK is less than t SKEW2, then PAF may not change state
untill the next rising edge of WCLK.
4. If a write is performed on this rising edge of the write clock,there will be Full-(m-1) words in the FIFO when PAF goes LOW.
12
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
•Programmable Empty Flag Timing
tCLKH tCLKL
tENS
tPAE
n words in FIFO(1)
tSKEW2 (2)
tENS tENH
n+1 words in FIFO
tENH
tPAE
(3)
WCLK
WEN1
RCLK
REN1
REN2
WEN2
(If Applicable)
PAE
tENS tENH
NOTES :
1. PAF offset=m.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle.
If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then PAE may not change state
untill the next rising edge of RCLK.
3. If a read is performed on this rising edge of the read clock, there will be Empty+(n-1) words in the FIFO when PAE goes LOW.
13
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
•Write Offset Registers Timing
PAE OFFSET
(LSB)
tCLKH tCLKL
tCLK
tENS tENH
tENS
tDS tDH
PAE OFFSET
(MSB) PAF OFFSET
(LSB) PAF OFFSET
(MSB)
tCLKH tCLKL
tCLK
tENS tENH
tENS
PAE OFFSET
(LSB) PAE OFFSET
(MSB) PAF OFFSET
(LSB)
DATA IN OUTPUT REGISTER
tAC
PAF OFFSET
(MSB)
WCLK
WEN1
D0-7
LD
•Read Offset Registers Timing
RCLK
Q0-7
LD
REN1
REN2
14
NOTE :
A read and write should not be performed simultaneously to the offset registers.
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
tPLZ Close Open
tPHZ Open Close
tPZL Close Open
1.5 V 3.0 V
GND
1.5 V
Qn
1.5 V
1.5 V VOH
VOL
tAC
High-Level
Input 1.5 V 3.0 V
GND
1.5 V
tW
1.5 V 1.5 V 3.0 V
GND
OE
tPHZ
1.5V 3V
GND
90%
tPZH
VOH
tPLZ
10%
tPZL
VOL
Qn
Qn
1.5V
1.5V
1.5V
PARAMETER MEASURMENT INFORMATION
Qn
680ΩCL = 30pF : tAC, tOEN, tODIS
1.1KΩ
SW1
SW2
3V
Item
tAC
SW1
Close
SW2
Close
tPZH Open Close
Input Pulus Level : 0 – 3V
Input Pulus Rising time and Falling time : 3 ns
Threshold voltage of Input / Output : 1.5V
But tPLZ is decided at 10% of output pulse. tPHZ is decided at 90% of output pulse.
Output Load : Including Test board and scope capacitances.
VOLTAGE WAVEFORM
PROPAGATION DELAY TIMES VOLTAGE WAVEFORM
PULSE DURATION TIMES
RCK
tAC
VOLTAGE WAVEFORM ENABLE AND DISABLE TIMES
Low-Level
Input
15
