Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
http://www.cirrus.com
Evaluation Board for CS4385
Features
Demonstrates recommended layout and
grounding arrangements
CS8416 receives S/PDIF, & EIAJ-340
compatible digital audio
Headers for external audio input for either PCM
or DSD®
Requires only a digital signal source and power
supplies for a complete digital-to-analog
converter system
Description
The CDB4385 evaluation board is an excellent means
for quickly evaluating the CS4385 24-bit, 48-pin, 8-
channel D/A converter. Evaluation requires an analog
signal analyzer, a digital signal source, a PC for control-
ling the CS4385 (only required for control port mode),
and a power supply. Analog line-level outputs are pro-
vided via RCA phono jacks.
The CS8416 digital audio receiver IC provides the sys-
tem timing necessary to operate the digital-to-analog
converter and will accept S/PDIF and EIAJ-340-com-
patible audio data. The evaluation board may also be
configured to accept external timing and data signals for
operation in a user application during system
development.
ORDERING INFORMATION
CDB4385 Evaluation Board
CS4385 Analog Outputs
and Filtering
Inputs for PCM
Clocks and Data
CS8416
Digital Audio
Interface
Hardware or
Software Board
Control
Inputs for DSD
Clocks and Data
MAY '08
DS671DB4
CDB4385
2DS671DB4
CDB4385
TABLE OF CONTENTS
1. CS4385 DIGITAL-TO-ANALOG CONVERTER ..................................................................................... 4
2. CS8416 DIGITAL AUDIO RECEIVER .................................................................................................... 4
3. INPUT FOR CLOCKS AND DATA ......................................................................................................... 4
4. INPUT FOR CONTROL DATA ............................................................................................................... 4
5. POWER SUPPLY CIRCUITRY ............................................................................................................... 5
6. GROUNDING AND POWER SUPPLY DECOUPLING .......................................................................... 5
7. ANALOG OUTPUT FILTERING .............. ... ... ......................................................................................... 5
8. PERFORMANCE PLOTS ....................................................................................................................... 7
9. SCHEMATICS ..................................................................................................................................... 17
10. ERRATA ............................................................................................................................................. 31
11. REVISION HISTORY ......................................................................................................................... 31
LIST OF FIGURES
Figure 1.FFT (48 kHz, 0 dB) ..... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ................... ... .... ................... ... ..................... 7
Figure 2.FFT (48 kHz, -60 dB) ............... ... ... ... ... .... ... ... ... .................... ... ... .................... ... ... ........................ 7
Figure 3.FFT (48 kHz, No Input) ................................................................................................................. 7
Figure 4.FFT (48 kHz Out-of-Band, No Input) ............................................................................................. 7
Figure 5.FFT (48 kHz, -60 dB Wideband) .............. ... ... ... .... ... ... ... .... ... ... ... ... .... ... ................... ... .... .............. 8
Figure 6.FFT (IMD 48 kHz) ......................................................................................................................... 8
Figure 7.48 kHz, THD+N vs. Input Freq .................... ... ... .... ... ... ... .... ................... ................... ..................... 8
Figure 8.48 kHz, THD+N vs. Level .............. ... ... ......................................................................................... 8
Figure 9.48 kHz, Fade-to-Noise Linearity . ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... .............................. 8
Figure 10.48 kHz, Frequency Response ... ... ... ... .... ... ... ... .... ... ... ... .................... ... ... ................... .... ... ........... 8
Figure 11.48 kHz, Crosstalk ................... ... .................................................................................................. 9
Figure 12.48 kHz, Impulse Response ......................................................................................................... 9
Figure 13.48 kHz, Impulse Prefilter .............. ... ... .... ... ... .................... ... ... ................... .... ... ........................... 9
Figure 14.Dynamic Range 48 kHz ............................................................................................................ 10
Figure 15.FFT (96 kHz, 0 dB) ................................................................................................................... 10
Figure 16.FFT (96 kHz, -60 dB) ................................................................................................................ 10
Figure 17.FFT (96 kHz, No Input) ............................................................................................................. 11
Figure 18.FFT (96 kHz Out-of-Band, No Input) ......................................................................................... 11
Figure 19.FFT (96 kHz, -60 dB Wideband) ............................................................................................... 11
Figure 20.FFT (IMD 96 kHz) ..................................................................................................................... 11
Figure 21.96 kHz, THD+N vs. Input Freq .................................................................................................. 11
Figure 22.96 kHz, THD+N vs. Level ...... ... ... ... .......................................................................................... 11
Figure 23.96 kHz, Fade-to-Noise Linearity ............... ... ... .... ... ... ... .... ......................................................... 12
Figure 24.96 kHz, Frequency Response ... ... ... ... .... ... ... ... .... ... ... ... .................... ... ... ................... .... ... ......... 12
Figure 25.96 kHz, Crosstalk ................... ... ................................................................................................ 12
Figure 26.96 kHz, Impulse Response ....................................................................................................... 12
Figure 27.96 kHz, Impulse Prefilter .............. ... ... .... ... ... .................... ... ... ................... .... ... ......................... 12
Figure 28.Dynamic Range 96 kHz ............................................................................................................ 13
Figure 29.FFT (192 kHz, 0 dB) ................................................................................................................. 13
Figure 30.FFT (192 kHz, -60 dB) .............................................................................................................. 13
Figure 31.FFT (192 kHz, No Input) ........................................................................................................... 14
Figure 32.FFT (192 kHz Out-of-Band, No Input) ....................................................................................... 14
Figure 33.FFT (192 kHz, -60 dB Wideband) ............................................................................................. 14
Figure 34.FFT (IMD 192 kHz) ................................................................................................................... 14
Figure 35.192 kHz, THD+N vs. Input Freq ................................................................................................ 14
Figure 36.192 kHz, THD+N vs. Level ....................................................................................................... 14
Figure 37.192 kHz, Fade-to-Noise Linearity ............................................................................................. 15
Figure 38.192 kHz, Frequency Response .......... .......... .......... .......... ......... .......... .......... ......... .......... ......... 15
DS671DB4 3
CDB4385
Figure 39.192 kHz, Crosstalk .................................................................................................................... 15
Figure 40.192 kHz, Impulse Response ..................................................................................................... 15
Figure 41.192 kHz, Impulse Prefilter ......................................................................................................... 15
Figure 42.Dynamic Range 192 kHz .......................................................................................................... 16
Figure 43.System Block Diagram and Signal Flow ................................................................................... 17
Figure 44.CS4385 ..................................................................................................................................... 18
Figure 45.Analog Outputs A1 - B1 ............................................................................................................ 19
Figure 46.Analog Outputs A2 - B2 ............................................................................................................ 20
Figure 47.Analog Outputs A3 - B3 ............................................................................................................ 21
Figure 48.Analog Outputs A4 - B4 ............................................................................................................ 22
Figure 49.CS8416 S/PDIF Input ............................................................................................................... 23
Figure 50.PCM Input Header and Muxing ................................................................................................. 24
Figure 51.DSD Input Header ..................................................................................................................... 25
Figure 52.Control Input ............................................................................................................................. 26
Figure 53.Power Inputs ............................................................................................................................. 27
Figure 54.Silkscreen Top .......................................................................................................................... 28
Figure 55.Top Side .................................................................................................................................... 29
Figure 56.Bottom Side .............................................................................................................................. 30
LIST OF TABLES
Table 1. System Connections .................................................................................................................... 5
Table 2. CDB4385 Jumper Settings ............................................................................................................ 6
4DS671DB4
CDB4385
CDB4385 SYSTEM OVERVIEW
The CDB4385 evaluation board is an excellent means of quickly evaluating the CS4385. The CS8416 digital au dio
interface receiver provide s an easy interface to digital au dio signal sources including the majority of digital a udio test
equipment. The eval uation board also allows the user to sup ply external PCM or DSD clocks and data throug h PCB
headers for system develop ment.
The CDB4385 schematic has been partitioned into 10 schematics shown in Figures 44 through 53. Each partitioned
schematic is re pres ente d in the sys tem diagra m sho wn in Figure 43. Notice that the system diagram also includes
the interconnections between the partitioned schematics.
1. CS4385 DIGITAL-TO-ANALOG CONVERTER
A description of the CS4385 is included in the CS4385 datasheet.
2. CS8416 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8416 digital audio receiver
(Figure 49). The outputs of the CS8416 include a serial bit clock, serial data, left-right clock, and a 128/256 Fs mas-
ter clock. The CS8416 data format is fixed to I2S. The operation of the CS8416 and a discussion of the digital audio
interface are included in the CS8416 datasheet.
The evaluation board has been designed such that the input can be either optical or coaxial, see Figure 49. How-
ever, both inputs cannot be dr iven simultaneously.
Switch position 7 of S1 sets the output MCLK-to-LRCK ratio of the CS8416. This switch should be set to 256 (closed)
for inputs Fs≤96 kHz and 128 (open) for Fs≥64 kHz. The 8416 must be manually reset using ‘HW RST’ (S2) or
through the software when this switch is changed.
3. INPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to ex ternal systems via headers J11 and J7. Header
J11 allows the evaluation board to accept externally generated PCM clocks and data. The schematic for the
clock/data input is shown in Figure 50. Switch position 6 of S1 selects the source as either CS8416 (open) or header
J11 (closed).
Header J7 allows the evaluation board to accept externally generated DSD data and clocks. The schematic for the
clock/data input is shown in Figure 50. A synchronous MCLK must still be provided via Header J11. Switch position
8 of S1 selects either PCM (open) or DSD (closed).
Please see the CS 43 8 5 data sh ee t for mo re info rm at ion .
4. INPUT FOR CONTROL DATA
The evaluation board can b e run in eith er a stand-alon e mode o r with a PC. Stand-alone mode uses the CS4385 in
hardware mode a nd the mode pins are configured u sing switch positions 1 through 5 of S1. PC mode uses software
to setup the CS4385 thr ou gh I²C ® using the PC’s serial or USB ports. PC mode is automatically selected when the
serial or USB port is attached and the CDB4385 software is running.
Header J15 offers the option for external input of RST and SPI™/I²C clocks and data. The board is setup from the
factory to use the on-board microcontroller in conjunction with the supplied software. To use an external control
source, remove the shunts on J15 and place a ribbon cable so the signal lines are on the center r ow and the grounds
are on the right side. R116 and R119 should be populated with 2-kΩ resistors when using an external I2C source
which does not already provide pull-ups.
DS671DB4 5
CDB4385
5. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by four binding posts (GND, +5V, +12V, and -12V), see Figure 53. The
‘+5V’ terminal supplies VA and the rest of the +5-V circuitry on the board. The +3.3-V circuitry is powered from a
regulator. Th e +2.5 volts required fo r VD is also provide d from an on-board r egulator. The +5- V supply should be
set within the recommended values for VA stated in the CS4385 datasheet.
WARNING:Refer to the CS4385 datasheet for maximum allowable voltage levels. Operation outside of this range
can cause permanent damage to the device.
6. GROUNDING AND POWER SUPPLY DECOUPLING
As with any high-performance converter, the CS4385 requires careful attention to power supply and grounding ar-
rangements to optimize performance. Figure 44 details the connections to the CS4385 and Figures 54, 55, and 56
show the component placement and top and bottom layout. The decoupling capacitors are located as close to the
CS4385 as possible. Extensive use of ground plane fill in the eval uation board yields large reductions in radiated
noise.
7. ANALOG OUTPUT FILTERING
The analog output on the CDB4385 has been designed according to the CS4385 datasheet. This output circuit in-
cludes an active 2-pole, 50-kHz filter which utilizes the multiple-feedback topology.
Table 1. System Connections
CONNECTOR INPUT/OUTPUT SIGNAL PRESENT
+5V Input + 5 V power
GND Input Ground connection from power supply
+12V Input +12 V positive supply for the on-board filtering
-12V Input -12 V negative supply for the on-board filtering
S/PDIF IN - J9 Input Digital audio interface input via coax
S/PDIF IN - OPT1 Input Digital audio interface input via optical
PCM INPUT - J11 Input Input for master, serial, left/right clocks and serial data
DSD INPUT - J7 Input Input for DSD serial clock and DSD data
OUTA1-B4 Output RCA li ne level analog outputs
6DS671DB4
CDB4385
Table 2. CDB4385 Jumper Settings
JUMPER /
SWITCH PURPOSE POSITION FUNCTION SELECTED
J15 Selects source of control data *shunts on Left
shunts removed *Control from PC and on-board microcontrolle r
External control input using center and right column s
J16 JTAG micro programming - Reserved for factory use only
S2 Resets CS8416 and CS4385 The CS8416 must be reset if switch S1 is changed
S1
CS4385 mode settings M0-M4 1-5 Default: M0, M4 open (HI)
M1, M2, M3 closed (LO)
Sets clock source 6 Sets clock source for CS4385
*open = RX(CS8416), closed = EXT(J11)
Sets MCLK ratio of CS8416 7 Selects 128x (open) or 256x (*closed) MCLK/LRCK ratio
output for CS8416
Selects PCM or DSD mode 8 For PCM input set to *Open, for DSD set to Closed
*Default Factory Settings
DS671DB4 7
CDB4385
8. PERFORMANCE PLOTS
The plots in the following section were ache ived using an Audio Precision System 2700 and a randomly chosen p ro-
duction CDB4385. In some cases the per formance may be limited by the CDB4385. All measurements we re taken
at room temp using the standard AP filter options (20 Hz to 22 kHz) with default board settings and nominal
datasheet voltag e s ap plie d unle ss oth e rwis e no te d.
The impulse response plots were taken both pre-and post filtering as the off-chip filter was degrading the perfor-
mance at higher sample rates. The pre-filter impulse response plots were taken directly at the output pins of the
DAC (with the analog filter still connected) to show the effect of the CDB’s analog filtering on the impulse response
(as the analog filtering adds its own signature to the impulse response of the DAC, and in the case of the higher
sampling rates it was band-limiting it).
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Hz
Figure 1. FFT (48 kHz, 0 dB) Figure 2. FFT (48 kHz, -60 dB)
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Hz
Figure 3. FFT (48 kHz, No Input) Figure 4. FFT (48 kHz Out-of-Band, No Input)
8DS671DB4
CDB4385
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Hz
Figure 5. FFT (48 kHz, -60 dB Wideband) Figure 6. FFT (IMD 48 kHz)
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Hz
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dBFS
Figure 7. 48 kHz, THD+N vs. Input Freq Figure 8. 48 kHz, THD+N vs. Level
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d
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dBFS
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+0
+1
+2
+3
+4
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 9. 48 kHz, Fade-to-Noise Linearity Figure 10. 48 kHz, Frequency Response
DS671DB4 9
CDB4385
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d
B
20 20k50 100 200 500 1k 2k 5k 10k
Hz
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3
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-1.5
-1
-500m
0
500m
1
1.5
2
2.5
V
03m500u 1m 1.5m 2m 2.5m
sec
Figure 11. 48 kHz, Crosstalk Figure 12 . 48 kHz, Impulse Response
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3
-2.5
-2
-1.5
-1
-500m
0
500m
1
1.5
2
2.5
V
03m500u 1m 1.5m 2m 2.5m
sec
Figure 13. 48 kHz, Impulse Prefilter
DS671DB4 11
CDB4385
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Hz
Figure 17. FFT (96 kHz, No Input) Figure 18. FFT (96 kHz Out-of-Band, No Input)
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Hz
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2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
Figure 19. FFT (96 kHz, -60 dB Wideband) Figure 20. FFT (IMD 96 kHz)
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Hz
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dBFS
Figure 21. 96 kHz, THD+N vs. Input Freq Figure 22. 96 kHz, THD+N vs. Level
12 DS671DB4
CDB4385
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+5
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d
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Hz
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+0
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d
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r
A
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dBFS
Figure 23. 96 kHz, Fade-to-Noise Linearity Figure 24. 96 kHz, Frequency Response
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d
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Hz
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3
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-1.5
-1
-500m
0
500m
1
1.5
2
2.5
V
01.5m250u 500u 750u 1m 1.25m
sec
Figure 25. 96 kHz, Crosstalk Figure 26. 96 kHz, Impulse Response
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-1
-500m
0
500m
1
1.5
2
2.5
V
01.5m250u 500u 750u 1m 1.25m
sec
Figure 27. 96 kHz, Impulse Prefilter
14 DS671DB4
CDB4385
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Hz
Figure 31. FFT (192 kHz, No Input) Figure 32. FFT (1 92 kHz Out-of-Band, No Input)
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Figure 33. FFT (192 kHz, -60 dB Wideband) Figure 34. FFT (IMD 192 kHz)
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Figure 35. 192 kHz, THD+N vs. Input Freq Figure 36. 192 kHz, THD+N vs. Level
DS671DB4 15
CDB4385
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dBFS
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Hz
Figure 37. 192 kHz, Fade-to-Noise Linearity Figure 38. 192 kHz, Frequency Response
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d
B
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-1.5
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-500m
0
500m
1
1.5
2
2.5
V
0600u200u 400u
sec
Figure 39. 192 kHz, Crosstalk Figure 40. 192 kHz, Impulse Response
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-1.5
-1
-500m
0
500m
1
1.5
2
2.5
V
0600u200u 400u
sec
Figure 41. 192 kHz, Impu lse Prefilter
DS671DB4 17
CDB4385
9. SCHEMATICS
Figure 43. System Block Diagram and Signal Flow
CS4385
CS8416
S/PDIF
Input
Serial Control Port
PCM mux
PCM Clocks/Data
PCM Clocks/Data
I2C/SPI Header
Power
DSD Clocks/
Data
DSD HEADER
2
2
DSD clk_enable
PCM Clocks/Data
DSD input enable
M0 - M4 switches
(for stand-alone mode)
PCM source select
CS8416 clock setting
Hardware Control
Switches
PCM HEADER
2
2
A1, B1
A2, B2
A3, B3
A4, B4
Differential to Single-Ended
Analog Outputs
32 DS671DB4
CDB4385
11.REVISION HISTORY
Release Changes
DB1 Initial Release
DB2 Updated for revision C of CDB
DB3 Added Performance Plots
DB4 Added USB support to Section 4. Input for Control Data
Contacting Cirrus Logic Support
For all product questions and inq uiries, contact a Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without not ice and is pr ovided "AS IS" witho ut warr anty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
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supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by C irrus
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