Features * Atmel Advanced System Bus (ASB) Arbitration * Customized Options - Number of Masters (2 to 7) - Priority of Masters - Possibility of Inserting Master Hand-over Cycle for Each Master * Atmel AMBATM Master Compliant * Fully Scan Testable up to 96% Fault Coverage Description The Advanced System Bus (ASB), part of the Advanced Microcontroller Bus Architecture (AMBA), supports the connection of multiple processors. Therefore, it requires an arbiter to ensure that only one bus master has write access to the ASB at any particular point in time. Each bus master can request the bus; the Arbiter decides which master has the highest priority and issues a grant accordingly. A hand-over cycle is inserted if required. Arbiter Each master is connected to the Arbiter via two signals: * A request signal areq: output from the master, input to the arbiter * A grant signal agnt: input to the master, output from the arbiter 32-bit Embedded Core Peripheral For further information on the AMBA structure, Master Signals Manager and Read Data Manager, refer to the ARM7TDMITM System Architecture datasheet, Literature Number 1353. Figure 1. Arbiter Symbol nreset_f AMBA Bus Inputs nclock agnt[N-1:0] blok[N-1:0] areq[N-1:0] AMBA Bus Output Arbiter scan_test_mode Scan Test test_si test_so test_se Scan Test Configuration The coverage is maximum if all non-scan inputs can be controlled and all non-scan outputs can be observed. In order to achieve this, the ATPG vectors must be generated on the entire circuit (top level) which includes the Arbiter or all Arbiter I/Os must have a top-level access and ATPG vectors must be applied to these pins. Rev. 1284D-03/01 1 Table 1. Pin Description Name Type Source/Destination Description AMBA Bus Inputs nreset_f Input nclock Input (1) From Reset Controller System reset for parts synchronized on the falling edge of the ASB clock (nclock). Active low. ASB system clock. blok[N -1:0] Input From Masters Locked transfers. Active high. areq[N(1)-1:0] Input From Masters Bus request. Each master has a corresponding areq signal. Active high. agnt[N(1)-1:0] Output To Masters Bus grant. Each master has a corresponding agnt signal. Active high. Scan Test scan_test_mode Input For scan test only. This input must be set to 1 only during scan test. Must be set to 0 in normal operating mode. test_se Input Test scan shift enabled when tied to 1. Input Test scan input (input of the scan chain). (2) test_si (2) Output test_so Notes: 2 Test scan output (output of the scan chain). 1. N = Number of masters 2. The scan chain uses the clock nclock. Arbiter 1284D-03/01 Arbiter Operating in an AMBA System Figure 2. AMBA Data Buses pdc_sel_bridge Read Data Manager ARM7TDMI Core and Wrapper ARM Memory Controller (including Decoder, EBI and ARAM Controller) bwait_from_APB wait_1C APB Peripherals dsel_bridge BDout brdata (DIN on ARM Core) BD_from_APB BD_from_masters bwait_to_ASB areq agnt bwait_in (DOUT on ARM Core) bwdata bridge_sel data_to_master pdc_data Master Signals Manager data_from_masters Bridge bwait_in bwdata Arbiter (N masters) brdata Master[i] agnt agnt[i] areq areq[i] agnt[N-1] areq[N-1] Advanced System Bus (ASB) Advanced Peripheral Bus (APB) 3 1284D-03/01 Figure 3. Master Control Signals ARM Memory Controller (including Decoder, EBI and ARAM Controller) ARM7TDMI Core and Wrapper bwrite mabe btran[1:0] ba blok bsize ba bprot bsize btran BusEnable_(N-1) bwrite ba_(N-1) APB Peripherals Master Signals Manager 2 bprot_(N-1) 2 bsize_(N-1) agnt[N-1] areq[N-1] 2 btran_(N-1) bwrite_(N-1) bwrite_(i) 2 write_ master bwriteout 2 btranout bsizeout bprotout 2 not used in this configuration address baout btran_(i) 2 bsize_(i) 2 bprot_(i) Bridge bwrite ba_(i) btran BusEnable_(i) bsize agnt[i] agnt[N-1] bprot blok ba BusEnable blok[N-1:0] Arbiter (N masters) agnt agnt[i] areq areq[i] Master agnt[N-1] areq[N-1] 4 Arbiter 1284D-03/01 Arbiter Functional Description The configuration described below is an example in which the arbiter manages six masters. The waveforms which follow use the same configuration. The arbitration scheme of this implementation is a simple priority encoded scheme where the highest priority master requesting the ASB is granted. Note: Priority The priority order is defined differently during reset. In operational mode (reset inactive), the priority order is defined Table 2 from the highest priority to the lowest priority. If no request is present, the default master is granted and is in charge of driving BTRAN to a valid value. Table 2. Priority Level Priority Level Connection Example of Master 1 areq[0] and agnt[0] Default master 2 areq[1] and agnt[1] Debug 3 areq[2] and agnt[2] DMA 4 areq[3] and agnt[3] PDC 5 areq[4] and agnt[4] Coprocessor core 6 areq[5] and agnt[5] ARM(R) Core Note: During reset (active low), only the default master can be granted control of the bus. Therefore, whatever the value of areq, agnt[5:0] is 000001. Table 3. Arbitration Examples Request Granted Response areq[5:0] = UUUUU1 agnt [5:0] = 000001 areq[5:0] = UUUU10 agnt [5:0] = 000010 areq[5:0] = UUU100 agnt [5:0] = 000100 areq[5:0] = UU1000 agnt [5:0] = 001000 areq[5:0] = U10000 agnt [5:0] = 010000 areq[5:0] = 100000 agnt [5:0] = 100000 areq[5:0] = 000000 agnt [5:0] = 000001 Therefore: areq[5:0] = 000101 agnt [5:0] = 000001 areq[5:0] = 011101 agnt [5:0] = 000001 areq[5:0] = 111110 agnt [5:0] = 000010 Note: U takes the place of 0 or 1. 5 1284D-03/01 Timing Diagrams The timing diagrams take into account the priority order described in Table 2. During System Reset and at the End of System Reset The master which has the lowest priority is always requesting the bus (typically the ARM core). Figure 4. Inputs nclock nreset_f blok[5:0] 000000 areq[5:0] 100000 Outputs agnt[5:0] 000001 100000 During system reset, Master[0](default master) is granted the bus. agnt is negative-edge triggered. 6 Arbiter 1284D-03/01 Arbiter Figure 5. Master [5] and Master [3] Requesting the Bus, Master [3] Granted After the End of Reset Inputs nclock nreset_f blok[5:0] 000000 areq[5:0] 101000 Outputs agnt[5:0] 000001 001000 Figure 6. Master Change [5] to [3] Inputs nclock nreset_f blok[5:0] areq[5:0] 000000 100000 111000 Outputs agnt[5:0] 000001 100000 001000 7 1284D-03/01 Normal Operating Mode Figure 7. Master Change Between the Masters [5] and [4]: [5], [4], [5], [4], [5], [4] Inputs nclock nreset_f 1 blok[5:0] areq[5:0] 000000 100000 110000 100000 010000 100000 010000 Outputs 100000 agnt[5:0] 010000 100000 010000 100000 010000 Figure 8. Master Change Between the Masters [5] and [3]: [5], [3], [5], [3], [5], [3] Inputs nclock nreset_f 1 blok[5:0] areq[5:0] 000000 100000 111000 100000 001000 100000 001000 Outputs agnt[5:0] 8 100000 001000 100000 001000 100000 001000 Arbiter 1284D-03/01 Arbiter Figure 9. Master Change Between the Masters [4] and [2]: [4], [2], [4], [2], [4], [2] Inputs nclock nreset_f 1 blok[5:0] areq[5:0] 000000 110000 111100 010000 000100 010000 000100 Outputs agnt[5:0] 010000 000100 010000 000100 010000 000100 Figure 10. Master Change Between the Masters [3] and [2]: [3], [2], [3], [2], [3] Inputs nclock nreset_f 1 000000 blok[5:0] areq[5:0] 111000 111100 001000 000100 001000 Outputs agnt[5:0] 001000 000100 001000 000100 001000 9 1284D-03/01 Figure 11. Master Changes with All Masters Inputs nclock nreset_f 1 blok[5:0] areq[5:0] 000000 100000 110000 111000 101000 110000 000011 000001 000010 Outputs agnt[5:0] 100000 010000 001000 010000 000001 000010 Figure 12. Timing Data Inputs nclock nreset_f tHOLD_BLOK blok[5:0] 000000 100000 tSU_AREQ areq[5:0] 101000 agnt[5:0] 10 000001 010000 tPD_AGNT 001000 000000 tHOLD_AREQ 100000 tPD_AGNT Outputs tSU_BLOK 100000 tPD_AGNT 010000 Arbiter 1284D-03/01 Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 1150 E. Cheyenne Mtn. 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