February 2006 Rev1 1/19
19
General features
■Excelle nt thermal stability
■Comm on source con figuration
■POUT =3W mith 17dB gain@5 00M Hz/12.5V
■New leadless plast ic package
■Esd prote ction
■Supp lied in tape & reel of 3K units
■In compliance with 2002/ 95/EC europe an
directive
Description
The PD5 5003L-E is a common source N-
Channel, enhancement-mode lateral Field-Effec t
RF power transistor. It is designed for high gain,
broadband c ommerc ial and industrial application.
It operates at 12V in common source mode at
frequencies of up to 1GHz. PD5500L-E boasts
the excellent gain, linearity and reliability of
STH1LV latest LD-MOS technology mounted in
the innovative lead less SMD plastic package,
PowerFLAT™.
PD5500L-E’s superior linearity performances
makes it an ideal sol ution for car mobile radio.
PIN co nf ig ur at i o n
PowerFLAT™(5x5)
TO P VIEW
PD55003L-E
RF POWER TRAN SISTOR
The LdmoST Plastic FAMILY
www.st.com
Or de r co de s
Sales Type Marking P ackage Pack aging
PD55003L-E 55003 PowerFLAT™(5x5) TAPE & REEL
Contents: PD55003L-E
2/19 Rev1
Contents:
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Typical performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. 2 Typical pe rformance (broadband) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Test circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Test circuit photomaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PD55003L-E Electrical da ta
Rev1 3/19
1 Electrical data
1.1 Maximum Ratings
1.2 Thermal data
Table 1. Absolute maximum ratings (TCASE=25°C)
Symbol Parameter Value Unit
V(BR)DSS Drain-Source Voltage 40 V
VGS Gate-Sour ce Volatge -0.5 to +15 V
IDDrain Current 2.5 A
PDISS Power Dissi pation (@TC = 70°C) 14 W
Tstg Storage Temperature – 65 to +150 °C
TjOperating Junction Temperature 150 °C
Table 2. Th erm al data
Symbol Parameter Value Unit
Rth(j-c) Junction-Case Thermal Resistance 5.7 °C/W
Electri cal speci fication PD55003 L-E
4/19 Rev1
2 Electrical specification
(TCASE=25°C)
Table 3. Static
Symbol Test Condict ions Min. Typ. Max. Unit
IDSS VGS=0V, VDS=28V 1 µA
IGSS VGS=20V, VDS=0V 1 µA
VGS(Q) VDS=10V, ID=50mA 2.0 5.0 V
VDS(ON) VGS=10V, ID=0.5A 0.36 V
gfs VDS=10V, ID=1A 1.0 mho
Ciss
Coss
Crss
VGS=0V, VDS=12.5V, f=1MHz 34
23
1.8
pF
pF
pF
Table 4. Dyna m ic
Symbol Test Condictions Min. Typ. Max. Unit
P1dB VDD=12.5V, IDQ=50mA, f=500MHz 3 W
GPVDD=12.5V, IDQ=50mA, POUT=3W, f=500MHz 17 19 dB
ηDV
DD=12.5V, IDQ=50mA, POUT=3W, f=500MHz 50 52 %
Load
mismatch VDD=12.5V, IDQ=50mA, POUT=3W, f=500MHz 20:1 VSWR
Ta bl e 5 . Switch in g on/of f (ind uc tive loa d)
Test Condi ctions Class
Human Body Model 2
Machine Model M3
Table 6. Sw itching en ergy (inductive load)
Tes t Methodology Rating
J-STD-020B MSL 3
PD550 03L-E El ectrical speci fication
Rev1 5/19
Figure 1. Typical Input/Drain load Impedances
Typical Input
Impedance Typical Drain
Load Impedance
G
D
S
ZDL
Zin
Table 7. Imp edance Data
FREQ. MHz ZIN(Ω)Z
DL(Ω)
480 1.79 - j 4.96 10.68 + j 7.45
500 1.88 - j 5.93 10.28 + j 8.92
520 2.10 - j 7.03 9.86 + j 10.18
Electri cal speci fication PD55003 L-E
6/19 Rev1
2.1 Typical performances
Figure 2. Capacitance Vs supply Voltage Figure 3. Output Power Vs Input Power
Figure 4. Pow er Gai n Vs Output Power Fig ure 5. Efficiency Vs Outp ut Power
Figure 6. Input Return Loss Vs Output Power Figure 7. Output Power Vs Bias Current
1
10
100
1000
0246810121416
Vds (V)
C (pF)
Coss
Ciss
Crss
f = 1 MH z
0
1
2
3
4
5
6
0 25 50 75 100 125
Pin (mW)
Pout (W)
I dq = 50 mA
V ds = 12.5 V
f = 500 MHz
Idq = 70 mA
10
12
14
16
18
20
22
24
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Pout (W)
G
p (d
B)
I dq = 50 mA
Idq = 20 mA
I dq = 30 mA
Vds = 12.5 V
f = 500 M Hz
I dq = 70mA
0
10
20
30
40
50
60
70
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Pout (W)
N
d (%
)
Idq = 50 mA
Vd s = 12 .5 V
f = 500 MHz
Idq = 70 mA
-30
-25
-20
-15
-10
-5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Pout (W)
RL (dB)
Idq = 50 mA
V ds = 12.5 V
f = 500 MHz
Idq = 70 mA
0
1
2
3
4
5
6
7
0 50 100 150 200 250 300 350 400 450 500
Idq (mA)
Pout (W)
Pin = 20 dB m
f = 500 MHz
Vdd = 12.5 V
PD550 03L-E El ectrical speci fication
Rev1 7/19
Figure 8. Efficiency Vs Bias Current Figure 9. Output Power Vs Supply Voltage
Figu re 10. Ou tput Pow er Vs Gate- So urce
Voltage
0
10
20
30
40
50
60
70
80
0 50 100 150 200 250 300 350 400 450 500
I dq (mA )
N
d (%
)
Pin = 20 dBm
f = 500 M Hz
Vdd = 12.5 V
0
1
2
3
4
5
6
7
8
5 6 7 8 9101112131415
Vds (V)
Pout (W )
Idq = 50 mA
Pin = 20 dBm
f = 500 MHz
0
1
2
3
4
5
6
7
0.00.51.01.52.02.53.03.54.0
Vg s (V)
Pout (W)
Pin = 20 dBm
Vdd = 12. 5 V
f = 500 MHz
Electri cal speci fication PD55003 L-E
8/19 Rev1
2.2 Typical performance (broadband)
Figure 11. Power Gain Vs Frequency Figure 12. Efficiency Vs Frequency
Figu re 13 . Retu r n Lo s s Vs Frequ ency
0
2
4
6
8
10
12
14
16
18
20
470 480 490 500 510 520 530 540
f (MHz)
Gp (dB)
Vds = 12.5 V
Id q = 50 mA
Po ut = 3 W 0
10
20
30
40
50
60
470 480 490 500 510 520 530 540
f (M H z )
Nd (%)
Vds = 12.5 V
Idq = 50 mA
P out = 3 W
-30
-25
-20
-15
-10
-5
0
470 480 490 500 510 520 530 540
f (MHz)
RL (dB)
Vds = 12.5 V
Idq = 50 m A
Pout = 3 W
PD55003L-E Test circuit schematic
Rev1 9/19
3 Test circuit schematic
Q
R4
R3R1
B1
L
C12
C1
C5
C6
B2
C13
1
2
VDD
1
2
VGG
RF ou
t
N2
RF in
N1
C7
+
C8
Z1 Z2
Z5
Z3
C2 C3
Z6
Z7
C10
Z8
C14 C15 C16
Z4
Z10
C4
C9 C11
Z9
Z1 0.709” X 0.08”
Z2 0.551” X 0.08”
Z3 0.217” X 0.08”
Z4 0.059” X 0.08”
Z5 0.452” X 0.223”
Z6 0.260” X 0.223”
Z7 0.118” X 0.08”
Z8 0.315” X 0.08”
Z9 0.866” X 0.08”
Z10 0.512” X 0.08”
Table 8. Test Circuit Component List
Component Description
B1, B2 FERRIDE BEAD
C1, C12 3000Pf, 100B ATC CHI P CAPACITOR
C2, C3 15pF, 100B ATC CHIP CAPACITOR
C4, C9 0 -:- 20 pF VARIABLE CAPACITO R JOHANSON
C5, C13 120pF 100B ACT CHIP CAPACITOR
C6, C14 0.1mF 100B ACT CAPACITOR
C7, C15 1200pF 100B ACT CAPACITOR
C8, C16 10µF, 35V, SMD ELECTROLYTIC CAPACITOR
C10 0.5 -:- 5pF VARIABLE CAPACITO R JOHANSON
C11 0.8 -:- 10pF VARIABLE CAPACITOR JOHANSON
R1 33KΩ CHIP RESISTOR 1W
R2, R3 15Ω MELF RESISTOR 1W
R4 1KΩ CHIP RESISTOR 1W
N1, N2 TYPE N FLANGE MOUNT
BOARD ROGER ULTRA LAM 2000 THK 0.030” εr = 2.55 2OZ ED Cu BOTH SIDES
Test circuit schematic PD55003L-E
10/19 Rev1
3.1 Test Circuit
3.2 Test circuit photomaster
6.4 inches
4 inches
PD55003L-E Test circuit schematic
Rev1 11/19
Tab le 9. S-P arameter (PD55003L)
(VDS=12.5V, IDS=0.15A)
FREQ IS11IS
11∠Φ IS21IS
21∠Φ IS12IS
12∠Φ IS22IS
22∠Φ
(MHz)
50 0.808 -110 20.14 112 0.039 22 0.672 -109
100 0.772 -141 11.77 93 0.042 5 0.633 -138
150 0.771 -152 7.86 82 0.041 -5 0.642 -147
200 0.779 -157 5.80 73 0.040 -11 0.665 -151
250 0.794 -161 4.50 66 0.038 -17 0.694 -154
300 0.809 -163 3.62 60 0.035 -22 0.721 -155
350 0.824 -165 2.98 54 0.033 -26 0.750 -157
400 0.839 -166 2.50 49 0.031 -30 0.774 -159
450 0.853 -168 2.13 44 0.028 -32 0.796 -160
500 0.865 -169 1.83 40 0.025 -34 0.818 -161
550 0.874 -171 1.59 36 0.023 -36 0.837 -163
600 0.885 -172 1.39 33 0.021 -36 0.852 -164
650 0.894 -173 1.23 29 0.018 -37 0.867 -165
700 0.901 -174 1.10 26 0.016 -37 0.880 -166
750 0.906 -175 0.97 23 0.015 -36 0.890 -167
800 0.911 -176 0.88 20 0.012 -32 0.902 -169
850 0.916 -177 0.79 18 0.011 -28 0.909 -169
900 0.918 -178 0.72 15 0.010 -22 0.918 -171
950 0.922 -179 0.65 13 0.008 -13 0.922 -171
1000 0.925 180 0.59 11 0.007 -7 0.928 -172
1050 0.925 179 0.54 9 0.007 8 0.934 -173
1100 0.928 178 0.50 7 0.006 21 0.938 -174
1150 0.927 177 0.46 5 0.007 38 0.941 -175
1200 0.928 176 0.43 4 0.008 51 0.944 -176
1250 0.929 175 0.40 2 0.010 56 0.947 -176
1300 0.927 175 0.37 1 0.011 61 0.953 -177
1350 0.927 174 0.34 -1 0.011 65 0.951 -178
1400 0.925 173 0.32 -2 0.012 68 0.952 -178
1450 0.922 172 0.30 -4 0.014 72 0.954 -179
1500
0.922
172
0.28
-5
0.016
73
0.957
-180
Test circuit schematic PD55003L-E
12/19 Rev1
Table 10. S-Parameter (PD 55003L)
(VDS=12.5V, IDS=0.8A)
FREQ IS11IS
11∠Φ IS21IS
21∠Φ IS12IS
12∠Φ IS22IS
22∠Φ
(MHz)
50 0.841 -124 22.20 107 0.029 21 0.651 -130
100 0.800 -150 12.84 92 0.031 6 0.654 -153
150 0.800 -159 8.59 83 0.031 -2 0.666 -159
200 0.803 -163 6.38 76 0.030 -8 0.684 -161
250 0.812 -166 5.00 70 0.028 -11 0.702 -163
300 0.822 -168 4.07 64 0.027 -15 0.721 -163
350 0.830 -169 3.39 59 0.025 -17 0.740 -164
400 0.837 -170 2.87 55 0.024 -20 0.760 -165
450 0.848 -172 2.47 50 0.022 -23 0.777 -166
500 0.857 -172 2.15 46 0.020 -23 0.795 -166
550 0.866 -174 1.89 42 0.018 -25 0.813 -167
600 0.874 -174 1.67 39 0.017 -23 0.825 -168
650 0.882 -175 1.49 35 0.015 -24 0.839 -168
700 0.887 -176 1.33 32 0.013 -22 0.853 -169
750 0.893 -177 1.19 29 0.012 -16 0.863 -170
800 0.898 -178 1.08 26 0.011 -15 0.875 -171
850 0.903 -179 0.98 23 0.010 -11 0.885 -172
900 0.904 -180 0.89 21 0.009 -1 0.893 -173
950 0.909 179 0.82 19 0.008 7 0.901 -173
1000 0.911 179 0.75 16 0.008 16 0.904 -174
1050 0.914 178 0.69 14 0.008 27 0.911 -175
1100 0.916 177 0.64 12 0.008 35 0.916 -175
1150 0.917 176 0.59 10 0.009 43 0.919 -176
1200 0.917 176 0.55 8 0.010 48 0.923 -177
1250 0.918 175 0.51 6 0.010 57 0.929 -177
1300 0.917 174 0.47 5 0.012 62 0.929 -178
1350 0.917 173 0.44 3 0.013 63 0.934 -179
1400 0.914 173 0.42 1 0.013 67 0.936 -179
1450 0.912 172 0.39 0 0.015 71 0.938 -180
1500
0.911
171
0.36
-2
0.016
72
0.941
179
PD55003L-E Test circuit schematic
Rev1 13/19
Table 11. S-Parameter (PD 55003L )
(VDS=12.5V, IDS=1.5A)
FREQ IS11IS
11∠Φ IS21IS
21∠Φ IS12IS
12∠Φ IS22IS
22∠Φ
(MHz)
50 0.837 -114 18.43 111 0.030 24 0.588 -132
100 0.799 -143 10.49 93 0.033 6 0.632 -152
150 0.801 -154 6.99 82 0.032 -3 0.656 -158
200 0.809 -159 5.15 74 0.031 -9 0.680 -160
250 0.823 -163 4.00 67 0.029 -14 0.701 -162
300 0.835 -165 3.22 61 0.028 -18 0.726 -163
350 0.845 -167 2.66 56 0.025 -20 0.750 -164
400 0.855 -169 2.23 52 0.024 -24 0.768 -165
450 0.866 -170 1.91 47 0.022 -26 0.789 -166
500 0.876 -171 1.65 43 0.020 -24 0.812 -167
550 0.882 -173 1.44 39 0.018 -25 0.828 -167
600 0.892 -174 1.26 36 0.016 -25 0.836 -168
650 0.898 -175 1.12 33 0.015 -25 0.844 -169
700 0.903 -176 1.00 29 0.013 -20 0.857 -170
750 0.907 -177 0.90 27 0.011 -17 0.868 -171
800 0.909 -178 0.81 24 0.010 -10 0.883 -171
850 0.912 -179 0.73 21 0.009 -6 0.889 -172
900 0.915 -180 0.67 19 0.009 1 0.894 -173
950 0.917 179 0.61 17 0.008 17 0.905 -174
1000 0.917 178 0.56 15 0.008 24 0.907 -174
1050 0.918 178 0.51 13 0.008 32 0.908 -175
1100 0.920 177 0.47 11 0.009 40 0.912 -176
1150 0.920 176 0.44 9 0.010 48 0.919 -177
1200 0.920 175 0.41 7 0.010 57 0.922 -177
1250 0.919 174 0.38 6 0.012 59 0.926 -178
1300 0.919 174 0.35 4 0.013 61 0.931 -179
1350 0.918 173 0.33 3 0.014 63 0.928 -179
1400 0.917 172 0.31 1 0.015 68 0.929 -180
1450 0.914 172 0.29 0 0.016 70 0.933 180
1500 0.912 171 0.27 -1 0.018 71 0.935 179
Pack age mech ani cal data PD55003 L-E
14/19 Rev1
4 Package mechanical data
In order to meet environ men tal re quirem ents, ST offers these dev ices in ECOPACK ®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the in ner box label, in
compliance with JEDEC Standard JESD97. The maximum rat ings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK sp ecifications are available at: www.st.com
PD550 03L-E Package mecha nical data
Rev1 15/19
Tabl e 12. PowerFLAT™ Mech anical Data
Dim. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 0.90 1.00 0.035 0.039
A1 0.02 0.05 0.001 0.002
A3 0.24 0.009
AA 0.15 0.25 0.35 0.006 0.01 0.014
b 0.43 0.51 0.58 0.017 0.020 0.023
c 0.64 0.71 0.79 0.025 0.028 0.031
D 5.00 0.197
d 0.30 0.011
E 5.00 0.197
E2 2.49 2.57 2.64 0.098 0.101 0.104
e 1.27 0.050
f 3.37 0.132
g 0.74 0.03
h 0.21 0.008
Figure 14. PowerFLAT™ Package Dimensions
Pack age mech ani cal data PD55003 L-E
16/19 Rev1
Table 13. PowerFLAT™ Tape & Reel Dimensions
DIM. mm.
MIN. TYP MAX.
Ao 5.15 5.25 5.35
Bo 5.15 5.25 5.35
Ko 1.0 1.1 1.2
Fi gure 15 . Pow e rFLAT™ Tape & Reel
PD550 03L-E Package mecha nical data
Rev1 17/19
Table 14. Recomm end ed FOOT PRINT
Revision hi stor y PD55003L-E
18/19 Rev1
5 Revision history
Table 15. Document revision history
Date Revision Changes
14-Feb-2006 1Fi rst Issue
PD55003L-E
Rev1 19/19
I
nformation furnished is believed to b e accurate and reliable . However, STMi croelectronics assumes no re sponsibilit y for the consequence
s
o
f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grante
d
b
y impli catio n or ot herw ise under any patent o r patent rights of S TM i croelectro ni cs. Specific ations mentioned in th is publicat i on are subjec
t
t
o change without notice. This publication supersedes and replaces all informati on previously supplied. STMicroelectronics products are no
t
authoriz ed for use as critic al components in lif e supp ort devices or sy stem s w ithout ex press wri tten approval of STM i croel ectronics.
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