IS46TR81280A-125JBLA2 - Integrated Silicon Solution, Inc.

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 1

Rev. 00B

12/5/2012

128MX8, 64MX16 1Gb DDR3 SDRAM ADVANCED INFORMATION

DECEMBER 2012

FEATURES

• Standard Volta ge: VDD and VDDQ = 1.5V ± 0.075V

Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V

• High speed data transfer rates wi th system

frequency up to 933 MHz

• 8 internal banks for concurrent operation

• 8n-bit pre-fetch architecture

• Programmable CAS Latency

• Programmable Additive Latency: 0, CL-1,CL-2

• Programmable CAS WRITE latency (C WL) based

on tCK

• Programmable Burst Length: 4 and 8

• Programmable Burst Sequence: Sequential or

Interleave

• BL switch on the fly

• Auto Self Refresh(ASR)

• Self Refresh Temperature(SRT)

• Refresh Interval:

7.8 us (8192 cycles/64 ms) Tc= -40°C to 85°C

3.9 us (8192 cycles/32 ms) Tc= 85°C to 105°C

• Partial Array Self Refresh

• Asynchronous RESET pin

• TDQS (Termination Data Strobe) supported (x8

only)

• OCD (Off-Chip Driver Impedance Adjustment)

• Dynamic ODT (On-Die Termination)

• Driver strength : RZQ/7, RZQ/6 (RZQ = 240 Ω )

• Write Leveling

• Operating temperature:

Commercial (TC = 0°C to +95°C)

Industrial (TC = -40°C to +95°C)

Automotive, A1 (TC = -40°C to +95°C)

Automotive, A2 (TC = -40°C to +105°C)

OPTIONS

• Configuration:

128Mx8

64Mx16

• Package:

96-ball FBGA (9mm x 13mm) for x16

78-ball FBGA (8mm x 10.5mm) for x8

ADDRESS TABLE

Parameter 128Mx8 64Mx16

Row Addressing A0-A13 A0-A12

Column Addressing

A0-A9

Bank Addressing BA0-2 BA0-2

Page size 1KB 2KB

Auto Prec h ar ge Ad dres s ing

A10/AP

BL switch on the fly A12/BC# A12/BC#

SPEED BIN

Speed Option 187F 15G 15H 125J 107L Units

JEDEC Speed Grade

DDR3-

1066F

DDR3-

1333G

DDR3-

1333H

DDR3-

1600J

DDR3-

1866L

CL-nRCD-nRP

7-7-7

8-8-8

9-9-9

10-10-10

12-12-12

tCK

tRCD,tRP(min)

13.125

12.0

13.5

12.5

12.84

Note: Faster speed options are backward compatibl e to slower speed opti ons.

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised

to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product

can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use

in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 2

Rev. 00B

12/5/2012

1. DDR3 P ACKAGE BALLOUT

1.1 DDR3 SDRAM package ballout 78-ball FBGA – x8

1 2 3 4 5 6 7 8 9

VSS VDD NC NU/TDQS# VSS VDD

VSS VSSQ DQ0 DM/TDQS VSSQ VDDQ

VDDQ DQ2 DQS DQ1 DQ3 VSSQ

VSSQ DQ6 DQS# VDD VSS VSSQ

VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ

VSS RAS# CK VSS NC

ODT VDD CAS# CK# VDD CKE

NC CS# WE# A10/AP ZQ NC

J VSS BA0 BA2 NC(A15) VREFCA VSS

VDD A3 A0 A12/BC# BA1 VDD

VSS A5 A2 A1 A4 VSS

VDD A7 A9 A11 A6 VDD

VSS RESET# A13 NC(A14) A8 VSS

Note:

NC balls have no internal connection. NC(A14) and NC(A15) are one of NC pins and reserved for higher densi ties .

1.2 DDR3 SDRAM package ballout 96-ball FBGA – x16

1 2 3 4 5 6 7 8 9

VDDQ DQU5 DQU7 DQU4 VDDQ VSS

VSSQ VDD VSS DQSU# DQU6 VSSQ

VDDQ DQU3 DQU1 DQSU DQU2 VDDQ

VSSQ VDDQ DMU DQU0 VSSQ VDD

VSS VSSQ DQL0 DML VSSQ VDDQ

VDDQ DQL2 DQSL DQL1 DQL3 VSSQ

VSSQ DQL6 DQSL# VDD VSS VSSQ

H VREFDQ VDDQ DQL4 DQL7 DQL5 VDDQ

NC VSS RAS# CK VSS NC

ODT VDD CAS# CK# VDD CKE

NC CS# WE# A10/AP ZQ NC

VSS BA0 BA2 NC(A15) VREFCA VSS

VDD A3 A0 A12/BC# BA1 VDD

VSS A5 A2 A1 A4 VSS

VDD A7 A9 A11 A6 VDD

VSS RESET# NC(A13) NC(A14) A8 VSS

Note:

NC balls have no internal c onnect ion. NC(A13), NC(A14) and NC(A15) are one of NC pins and reserved for higher densities.

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 3

Rev. 00B

12/5/2012

1.3 Pinout Description - JEDEC Standard

Symbol

Type

Function

CK, CK#

Input

Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled

on the crossing of the positive edge of CK and negative edge of CK#.

CKE

Input

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device

input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-

Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is

asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during the

power on and initialization sequence, they must be maintained during all operations (including

Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers,

excluding CK, CK#, ODT and CKE, are disabled during power-down. Input buffers, excluding

CKE, are disabled during Self-Refresh.

CS#

Input

Chip Select: All commands are masked when CS# is registered HIGH. CS# provides for external

Rank selection on systems with multiple Ranks. CS# is considered part of the command code.

ODT Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3

SDRAM. When enabled, ODT is only applied to each DQ, DQSU, DQSU#, DQSL, DQSL#, DMU,

and DML signal. The ODT pin will be ignored if MR1 and MR2 are programmed to disable RTT.

RAS#. CAS#.

WE#

Input

Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being entered.

DM, (DMU),

(DML)

Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH coincident with that input data during a Write access. DM is sampled on both

edges of DQS. For x8 device, the function of DM or TDQS/TDQS# is enabled by Mode Register

A11 setting in MR1.

BA0 - BA2

Input

Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write, or Precharge

command is being applied. Bank address also determines which mode register is to be accessed

during a MRS cycle.

A0 - A13

Input

Address Inputs: Provide the row address for Active commands and the column address for Read/

Write commands to select one location out of the memory array in the respective bank. (A10/AP

and A12/BC# have additional functions; see below). The address inputs also provide the op-code

during Mode Register Set commands.

A10 / AP Input Auto-precharge: A10 is sampled during Read/Write commands to determine whether

Autoprechar ge shou ld be performed to the accessed bank after the Read/Write operation. (HIGH:

Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge command to

determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If

only one bank is to be precharged, the bank is selected by bank addresses.

A12 / BC#

Input

Burst Chop: A12 / BC# is sampled during Read and Write commands to determine if burst chop

(on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth

table for details.

RESET#

Input

Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive when

RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a CMOS rail- to-

rail signal with DC high and low at 80% and 20% of VDD, i.e., 1.20V for DC high and 0.30V for

DC low.

DQ(DQL, DQU)

Input / Output

Data Input/ Output: Bi-directional data bus.

DQS,

DQS#, DQSU,

DQSU#, DQSL,

DQSL#

Input / Output

Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered

in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to

the data on DQU0-DQU7. The data strobes DQS, DQSL, and DQSU are paired with differential

signals DQS#, DQSL#, and DQSU#, respectively, to provide differential pair signaling to the

system during reads and writes. DDR3 SDRAM supports differential data strobe only and does

not support single-ended.

TDQS, TD QS #

Output

Termination Data Strobe: TDQS/TDQS# is applicable for x8 DRAMs only. When enabled via

Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function

on TDQS/TDQS# that is applied to DQS/DQS#. When disabled via mode register A11 = 0 in

MR1, DM/TDQS will provide the data mask function and TDQS# is not used. x16 DRAMs must

disable the TDQS function via mode register A11 = 0 in MR1.

No Connect: No internal electrical connection is present.

VDDQ

Supply

DQ Power Supply: 1.5 V +/- 0.075 V for standard voltage or 1.35V +0.1V, -0.067V for low voltage

VSSQ Supply DQ Ground

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 4

Rev. 00B

12/5/2012

VDD

Supply

Power Supply: 1.5 V +/- 0.075 V for standard voltage or 1.35V +0.1V, -0.067V for low voltage

VSS

Supply

Ground

VREFDQ

Supply

Reference voltage for DQ

VREFCA

Supply

Reference voltage for CA

Supply

Reference Pin for ZQ calibration Input only pins (BA0-BA2, A0-A13, RAS#, CAS#, WE#, CS#,

CKE, ODT, and RESET#) do not supply termination.

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 5

Rev. 00B

12/5/2012

2. FUNCTION DESCRIPTION

2.1 Simplified State Diagram

Abbreviation

Function

Abbreviation

Function

Abbreviation

Function

ACT Active Read RD, RDS4, RDS8 PDE Enter Power-down

PRE Precharge Read A RDA, RDAS4, RDAS8 PDX Exit Power-down

PREA Precharge All Write WR, WRS4, WRS8 SRE Self-Refr e sh entry

MRS Mode Register Set Write A WRA, WRAS4, WRAS8 SRX Self-Refresh ex it

REF Refresh RESET Start RESET Procedure MPR Multi-Purpose Register

ZQCL

ZQ Calibrati on Long

ZQCS

ZQ Calibration Short

Power

applied

RESET

From

Any state

Reset

Procedure Initialization

ZQCL

Calibration

ZQCL

ZQCS

Idle

MRS,MPR,

Write

Leveling

Self

Refresh

SRE

SRX

REF

Refreshing

Precharge

Power

Down

PDX

PDE

ACT

Activating

Bank

Active

Power

Down

PDE

PDX

Reading Writing

Writing

Reading

Precharging Automatic

Sequence

Command

Sequence

Write

Write A

Write

Write A

PRE,PREA

Read

Read A

Read

Read A

PRE,PREA

Read A

Read

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 6

Rev. 00B

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2.2 RESET and Initialization Procedure

2.2.1 Power-up Initialization Sequence

The following sequence is required for POWER UP and Initialization.

1. Apply power (RESET# is recommended to be maintained below 0.2 x VDD; all other inputs may be undefined).

RESET# needs to be maintained for minimum 200 us with stable power. CKE is pulled “Low” anytime before

RESET# being de-asserted (min. time 10 ns). The power voltage ramp time between 300mV to VDD(min) must be

no greater than 200 ms; and during the ramp, VDD > VDDQ and (VDD - VDDQ) < 0.3 volts .

• VDD and VDDQ are driven from a single power converter output, AND

• The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD

on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to

0.95 V max once power ramp is finished, AND

• Vref tracks VDDQ/2.

• Apply VDD without any slope reversal before or at the same time as VDDQ.

• Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.

• The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD

on one side and must be larger than or equal to VSSQ and VSS on the other side.

2. After RESET# is de-asserted, wait for another 500 us until CKE becomes active. During this time, the DRAM will

start internal state initialization; this will be done independently of external clocks.

3. Clocks (CK, CK#) need to be started and stabilized for at least 10 ns or 5 tCK (which is larger) before CKE goes

active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be met. Also, a NOP or

Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE is

registered “High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence is

finished, including expiration of tDLLK and tZQinit.

4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as RESET# is asserted. Further,

the SDRAM keeps its on-die termination in high impedance state after RESET# deassertion until CKE is registered

HIGH. The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is

registered HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled

in MR1, the ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the

power up initialization sequence is finished, including the expiration of tDLLK and tZQinit.

5. After CKE is being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS

command to load mode register. (tXPR=max (tXS ; 5 x tCK)

6. Issue MRS Command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to

BA0 and BA2, “High” to BA1.)

7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to

BA2, “High” to BA0 and BA1.)

8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue "DLL Enable" command,

provide "Low" to A0, "High" to BA0 and "Low" to BA1 – BA2).

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 7

Rev. 00B

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9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command,

provide "High" to A8 and "Low" to BA0-2).

10. Issue ZQCL command to starting ZQ calibration.

11. Wait for both tDLLK and tZQinit completed.

12. The DDR3 SDRAM is now ready for normal operation.

Figure2.1.1 Reset and Initialization Sequence at Power-on Ramping

2.2.2 Reset Initialization with Stable Power

The following sequence is required for RESET at no power interruption initialization.

1. Asserted RESET below 0.2 * VDD anytime when reset is needed (all other inputs may be undefined). RESET needs

to be maintained for minimum 100 ns. CKE is pulled “LOW” before RESET being de-asserted (min. time 10 ns).

2. Fol low Power-up Initialization Sequence steps 2 to 11.

3. The Reset sequence is now completed; DDR3 SDRAM is ready for normal operation.

CK,CK#

VDD,VDDQ

RESET#

CKE

CMMAND

ODT

RTT

T=200µS

Tmin=10nS

T=500µS

tCKSRX

tIS

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tXPR

tMRD

tMOD

tZQinit

tDLLK

tIS

Valid

MRD MRD MRD MRD ZQCL 1)

MR2 MR3 MR1 MR0

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Note1. From time point “Td” until “Tk” NOP or DES commands must be

applied between MRS and ZQCL commands.

Time

Break

DON’T

CARE

Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 8

Rev. 00B

12/5/2012

Figure2.1.2 Reset Procedure at Pow er Stable Condition

2.3 Register Definition

2.3.1 Programming the Mode Registers

For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by

the DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command.

As the default values of the Mode Registers (MR#) are not defined, contents of Mode Registers must be fully initialized

and/or re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers

can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even

if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must

be redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which

means these commands can be executed any time after power-up without affecting the array contents The mode register

set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time

required between two MRS commands shown as below.

CK,CK#

VDD,VDDQ

RESET#

CKE

CMMAND

ODT

RTT

T=100nS

Tmin=10nS

T=500µS

tCKSRX

tIS

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tXPR

tMRD

tMOD

tZQinit

tDLLK

tIS

Valid

MRD

ZQCL

MR2 MR3 MR1 MR0

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Te Tf Tg Th Ti Tj Tk

Note1. From time point “Td” until “Tk” NOP or DES commands must be

applied between MRS and ZQCL commands.

Time

Break

DON’T

CARE

Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 9

Rev. 00B

12/5/2012

Figure2.3.1a tMRD Timing

The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except DLL

reset, and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DES shown

as the following figure.

Figure 2.3.1b tMOD Timing

The mode register contents can be changed using the same command and timing requirements during normal operation

as long as the DRAM is in idle state, i.e., all banks are in the precharged state with tRP satisfied, all data bursts are

completed and CKE is high prior to writing into the mode register. If the RTT_NOM Feature is enabled in the Mode

an off State prior to the MRS command. The ODT Signal maybe registered high after tMOD has expired. If the RTT_NOM

Feature is disabled in the Mode Register prior and after an MRS command, the ODT Signal can be registered either LOW

or HIGH before, during and after the MRS command. The mode registers are divided into various fields depending on the

functionality and/or modes.

Command

Address

CKE

Settings

ODT

RTT_Nom ENABLED prior and/or after MRS command

RTT_Nom D IS ABLED prior and after MRS command

ODTLoff + 1

Old Settings

( (

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Time

Break

DON’T

CARE

Valid

MRS

Valid

NOP/

DEC

Valid

MRS

Valid

NOP/

DEC

NOP/

DEC

NOP/

DEC

tMRD

New Settings

CK#

Command

Address

CKE

Settings

ODT

RTT_Nom ENABLED prior and/or after MRS command

RTT_Nom D IS ABLED prior and after MRS command

ODTLoff + 1

Old Settings

( (

) )

Time

Break

DON’T

CARE

Valid

MRS

Valid

NOP/

DEC

Valid

NOP/

DEC

NOP/

DEC

NOP/

DEC

tMOD

New Settings

NOP/

DEC

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2.3.2 Mode Register MR0

The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls burst length,

read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge Power-Dow n, which include

vendor specific options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting

low on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2, while controlling the states of address pins according to the

following figure.

1. A13 must be programmed to 0 during MRS.

2. WR (write recovery for autoprecharge)m i n in clock cycles is calculated by dividi ng tWR(in ns) by tCK (in ns) and roundi ng up to the next integer:

WRmin[cycles] = Roundup(tWR[ns] / tCK[ns]). The WR value in the m ode register must be programmed to be equal or larger than WRm in. T he

programmed WR value is used with tRP to determine t DAL.

3. The table only shows the encodi ngs for a given Cas Latency. For actual supported Cas Latency, please refer to speedbin tables for each

frequency

4. The table only shows the encodi ngs for Writ e Recovery. For actual W rite recovery timing, pl eas e refer to AC timing table.

Figure 2.3.2 — MR0 Definition

2.3.2.1 Burst Length, Type and Order

Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3

as shown in Figure 2.3.2. The ordering of accesses within a burst is determined by the burst length, burst type, and the

starting column address as shown in Table below. The burst length is defined by bits A0-A1. Burst length options include

BA2

BA1

BA0

A13

A12

A11

A10

Address Field

PPD

DLL

CAS Latency

RBT

Mode Register 0

DLL Reset

mode

Read Burst Type

Nomal

Nibble Sequential

8 (Fixed)

Yes

Test

Interleave

BC4 or 8 (on the fly)

BC4 (Fixed)

A12

DLL Control for

Write recov ery for aut oprecharge

Reserved

Precharge PD

A11

A10

WR(cycles)

Slow exit (DLL of f)

CAS Latency

Fast exit (DLL on)

Reserved

BA1

BA0

MR Select

MR0

MR1

MR2

MR3

Reserved

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fixed BC4, fixed BL8, and ‘on the fly’ which allows BC4 or BL8 to be selected coincident with the registration of a Read or

Write command via A12/BC#.

Burst

Length READ/

WRITE

Starting

Column

ADDRESS

(A2,A1,A0)

burst type = Sequential

(decimal)

A3 = 0

burst type = Interleaved

(decimal)

A3 = 1 Notes

Chop

READ

0,1,2,3,T,T,T,T

1, 2, 3

1,2,3,0,T,T,T,T

1,0,3,2,T,T,T,T

1, 2, 3

2,3,0,1,T,T,T,T

1, 2, 3

3,0,1,2,T,T,T,T

3,2,1,0,T,T,T,T

1, 2, 3

100

4,5,6,7,T,T,T,T

1, 2, 3

101

5,6,7,4,T,T,T,T

5,4,7,6,T,T,T,T

1, 2, 3

110

6,7,4,5,T,T,T,T

1, 2, 3

111

7,4,5,6,T,T,T,T

7,6,5,4,T,T,T,T

1, 2, 3

WRITE 0,V,V 0,1,2,3,X,X,X,X 0,1,2,3,X,X,X,X 1, 2, 4, 5

1,V,V

4,5,6,7,X,X,X,X

1, 2, 4, 5

8 READ

0,1,2,3,4,5,6,7

1 1,2,3,0,5,6,7,4 1,0,3,2,5,4,7,6 2

2,3,0,1,6,7,4,5

11 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4 2

100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 2

101 5,6,7,4,1,2,3,0 5,4,7,6,1,0,3,2 2

110 6,7,4,5,2,3,0,1 6,7,4,5,2,3,0,1 2

111 7,4,5,6,3,0,1,2 7,6,5,4,3,2,1,0 2

WRITE V,V,V 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 2, 4

Notes:

1. In case of burst length bei ng fixed to 4 by MR0 setting, the internal write operati on st arts two clock cycles earli er than for the BL8 mode. This means

that the st arting poi nt f or tWR and tWTR will be pulled in by two clocks. In case of burst length being selected on-the-fly via A12/BC#, the internal

write operation st arts at the sam e point in time like a burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR

and tWTR will not be pulled in by two clocks.

2. 0...7 bit num ber is value of CA[2:0] that causes t his bit to be the first read during a burst.

3. T: Output driver for dat a and strobes are in high impedance.

4. V: a valid logic level (0 or 1), but respective buffer input ignores level on i nput pins.

5. X: Don’t Care.

2.3.2.2 CAS Latency

The CAS Latency is defined by MR0 (bits A9-A11) as shown in Figure 2.3.2. CAS Latency is the delay, in clock cycles,

between the internal Read command and the availability of the first bit of output data. DDR3 SDRAM does n ot supp ort

any half-clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL); RL = AL

+ CL. For more information on the supported CL and AL settings based on the operating clock frequency, refer to

“Standard Spe ed Bi ns ”.

2.3.2.3 Test Mode

The normal operating mode is selected by MR0 (bit A7 = 0) and all other bits set to the desired values shown in Figure

2.3.2. Programming bit A7 to a ‘1’ places the DDR3 SDRAM into a test mode that is only used by the DRAM Manufactur er

and should NOT be used. No operations or functionality is specified if A7 = 1.

2.3.2.4 DLL Reset

The DLL Reset bit is self-clearing, meaning that it returns back to the value of ‘0’ after the DLL reset function has been

issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Any time that the DLL reset function is

used, tDLLK must be met before any functions that require the DLL can be used (i.e., Read commands or ODT

synchronous operations).

2.3.2.5 Write Recovery

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The programmed WR value MR0 (bits A9, A10, and A11) is used for the auto precharge feature along with tRP to

determine tDAL. WR (write recovery for auto-precharge) min in clock cycles is calculated by divi ding tWR (in ns) by tCK

(in ns) and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to

be equal to or larger than tWR(min).

2.3.2.6 Precharge PD DLL

MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12 = 0), or ‘s lo w-exit’,

the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be

met prior to the next valid command. When MR0 (A12 = 1), or ‘fast-exit’, the DLL is maintained after entering precharge

power-down and upon exiting power-down requires tXP to be met prior to the next valid command.

2.3.3 Mode Register MR1

The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, Rtt_Nom impedance,

additive latency, Write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by asserting low on CS#,

RAS#, CAS#, WE#, high on BA0 and low on BA1 and BA2, while controlling the states of address pins according to

Figure 2.3.3.

* 1 : A8, A10, and A13 must be programmed to 0 during MRS.

* TDQS must be disabled for x16 option. Figure 2.3.3 MR1 Definition

2.3.3.1 DLL Enable/Disable

BA2

BA1

BA0

A13

A12

A11

A10

Address Field

Qoff

TDQS

Rtt

Level

Rtt

D.I.C

Rtt

D.I.C

DLL

Mode Register 1

A11

TDQS enable

Write leveling enable

Rtt_Nom

DLL Enable

Disabled

ODT disabled

Enable

Enabled

RZQ/4

Disable

RZQ/2

Additive Latency

RZQ/6

0 (AL disabled)

RZQ/12

CL-1

RZQ/8

CL-2

Reserved

Note: RZQ = 240 Ω

A12

Qoff

*3:In Write leveling Mode (MR1[bit7] = 1) with

Out pu t buffer enable d

MR1[bit12]=1, all RTT_Nom settings are allowed; in

Out pu t buffer dis abled

Write Leveling Mode (MR1[bit7] = 1) with

*2: Output s di s a bled - DQs, DQSs, DQS# s.

MR1[bit12]=0, only RTT_Nom settings of RZQ/2,

RZQ/4 and RZQ/6 are allowed.

BA1

BA0

MR Select

*4:If RTT_Nom is used during Writes, only the

MR0

values RZQ/2, RZQ/4 and RZQ/6 are allowed.

MR1

MR2

Output Driver Impedance Control

MR3

RZQ/6

RZQ/7

RZQ/TBD

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The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning

to normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0 = 0), the DLL is

automatically disabled when entering Self-Refresh operation and is automatically re-enabled upon exit of Self-Refresh

operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a Read or

synchronous ODT co mmand can be issued to allow time for the internal clock to be synchron i zed with the e xter nal cloc k.

Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON or tAOF parameters. During

tDLLK, CKE must continuously be registered high. DDR3 SDRAM does not require DLL for any Write operation, except

when RTT_WR is enabled and the DLL is required for proper ODT operation. For more detailed information on DLL

Disable operation refer to “DLL-off Mode”.

The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by

continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode

The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set Rtt_WR, MR2 {A10,

A9} = {0,0}, to disable Dynamic ODT externally.

2.3.3.2 Output Driver Impedance Control

The output driver impedance of the DDR3 SDRAM device is selected by MR1 (bits A1 and A5) as shown in Figure 2.3.3.

2.3.3.3 ODT Rtt Values

DDR3 SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal termination

value Rtt_Nom is programmed in MR1. A separate value (Rtt_WR) may be programmed in MR2 to enable a unique RTT

value when ODT is enabled during writes. The Rtt_WR value can be applied during writes even when Rtt_Nom is

disabled.

2.3.3.4 Additive Latency (AL)

Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable bandwidths in

DDR3 SDRAM. In this operation, the DDR3 SDRAM allows a read or write command (either with or without auto-

precharge) to be issued immediately after the active command. The command is held for the time of the Additive Latency

(AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL)

register settings. Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A

summary of the AL register options are shown in Table below.

Additive Latency (AL) Settings

0 (AL Disabled)

CL - 1

CL - 2

Reserved

NOTE: AL has a value of CL - 1 or CL - 2 as per the CL values programmed in the MR0 register.

2.3.3.5 Write leveling

For better signal integrity, DDR3 memory module adopted fly-by topology for the commands, addresses, control signals,

and clocks. The fly-by topology has the benefit of reducing the number of stubs and their length, but it also causes flight

time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the Controller to maintain

tDQSS, tDSS, and tDSH specification. Therefore, the DDR3 SDRAM supports a ‘write leveling’ feature to allow the

controller to compensate for skew.

2.3.3.6 Output Disable

The DDR3 SDRAM outputs may be enabled/disabled by MR1 (bit A12) as shown in Figure 2.3.3. When this feature is

enabled (A12 = 1), all output pins (DQs, DQS, DQS#, etc.) are disconnected from the device, thus rem ovin g an y loading

of the output drivers. This feature may be useful when measuring module power, for example. For normal operation, A12

should be set to ‘0’.

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2.3.3.7 TDQS, TDQS#

TDQS (Termination Data Strobe) is a feature of X8 DDR3 SDRAM that provides additional termination resistance outputs

that may be useful in some system configurations. The TDQS function is available in X8 DDR3 SDRAM only and must be

disabled via the mode register A11=0 in MR1 for X16 configuration.

2.3.4 Mode Register MR2

The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write

latency. The Mode Register 2 is written by asserting low on CS#, RAS#, CAS#, WE#, high on BA1 and low on BA0 and

BA2, while controlling the states of address pins according to the below.

* 1 : A5, A8, A11 ~ A13 must be programmed to 0 during MRS.

* 2 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not available.

Figure 2.3.4 MR2 Definition

2.3.4.1 Partial Array Self-Refresh (PASR)

If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address range

shown in Figure 2.3.4 will be lost if Self-Refresh is entered. Data integrity will be maintained if tREFI conditions are met

and no Self-Refresh command is issued.

2.3.4.2 CAS Write Latency (CWL)

The CAS Write Latency is defined by MR2 (bits A3-A5), as show n in Figure 2.3.4. CAS Write Latency is the delay, in clock

cycles, between the internal Write command and the availability of the first bit of input data. DDR3 SDRAM does not

support any half-clock latencies. The overall Write Latency ( WL) is defined as Additive Latency (AL) + CAS Write Latency

BA2

BA1

BA0

A13

A12

A11

A10

Address Field

Rtt_WR

SRT

ASR

CWL

PASR

Mode Register 2

Self-Refresh Tempera ture (SRT) Rang e

Partial Array Self-Refresh (Opti o n al)

Normal operating temperature range

Full Arra y

Extended operating temperature range

HalfArray (BA[2:0]=000,001,010, &011)

Quarter Arra y (BA[2 :0]=000, & 001)

1/8th Array (BA[2:0] = 000)

Auto Self-R efresh ( ASR)

3/4 Array (BA[2:0] = 010,011,100,101,110, & 111)

Man u al SR Reference (SRT)

Hal fArray (BA[2: 0] = 100, 101, 1 10, &111)

ASR enable

Quarter Arra y (BA[2 :0]=110, &111)

1/8th Array (B A[2:0]=111)

A10

Rtt_WR

CAS write Latency (CWL)

Dynamic ODT off (Write does not affect Rtt value)

5 (tCK(avg) ≥ 2.5 ns)

RZQ/4

6 (2.5 ns > tC K(avg) ≥ 1.875 ns)

RZQ/2

7 (1.875 ns > tCK(avg) ≥ 1.5 ns)

Reserved

8 (1.5 ns > tC K(avg) ≥ 1.25 ns)

9 (1.25 ns > tCK(avg) ≥ 1.07ns)

BA1

BA0

MR Select

10 (1.07 ns > tCK(avg) ≥ 0.935 ns)

MR0

11 (0.935 ns > tCK(avg) ≥ 0.83 3 ns )

MR1

12 (0.833 ns > tCK(avg) ≥ 0.75 ns )

MR2

MR3

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(CWL); WL = AL + CWL. For more information on the supported CWL and AL settings based on the operating clock

frequency, refer to “Standard Speed Bins”.

2.3.4.3 Auto Self-Ref r esh (AS R) and Self -Refresh Temperature (SRT)

For more details refer to “Extended Temperature Usage”. DDR3 SDRAMs support Self-Refresh operation at all supported

temperatures. Applic ati ons requir ing Se lf -Refresh operation in the Extended Temperature Range must use the ASR

function or program the SRT bit appropriately.

2.3.4.4 Dy namic ODT (Rtt_WR)

DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal

integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing

an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT setings. In Write leveling mode, only

RTT_Nom is available. For details on Dynamic ODT operation, refer to “Dynamic ODT”.

2.3.5 Mode Register MR3

The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on CS#, RA S#,

CAS#, WE#, high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the below.

* 1 : A3 - A13 must be programmed to 0 during MRS.

* 2 : The predefined pattern will be used for read synchronization.

* 3 : When MPR control is set for normal operation (MR3 A[2] = 0) then MR3 A[ 1:0] will be ignored.

Figure 2.3.5 MR3 Definition

2.3.5.1 Multi-Purpose Register (MPR)

The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. To

enable the MPR, a Mode Register Set (MRS) command must be issued to MR3 register with bit A2=1. Prior to issuing the

MRS command, all banks mu st be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any

subsequent RD or RDA commands will be redirected to the Multi Purpose Register. When the MPR is enabled, only RD

or RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2=0).

Power down mode, Self-Refresh and an y other non-RD/RDA command is not allowed during MPR enable mode. The

RESET function is supported during MPR enable mode.

The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. The

basic concept of the MPR is shown in Figure 2.3.5.1.

BA2

BA1

BA0

A13

A12

A11

A10

Address Field

MPR

MPR Loc

Mode Register 3

MRP Op erat ion

MPR Address

MPR

MPR location

Normal operation

Predefined pattern

Dataflow from MPR

RFU

BA1

BA0

MR Select

MR0

MR1

MR2

MR3

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Figure 2.3.5.1 MP R Block Diagram

To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1. Prior to

issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is

enabled, any subsequent RD or RDA commands will be redirected to the Multi Purpose Register.

The resulting operation, when a RD or RDA command is issued, is defined by MR3 bits A[1:0] when the MPR is enabled.

When the MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is issued with the

MPR disabled (MR3 bit A2 = 0).

Note that in MPR mode RDA has the same functionality as a READ command which means the auto precharge part of

RDA is ignored. Power-Down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR

enable mode. The RESET function is supported during MPR enable mode.

MPR MR3 Register Definition

MR 3 A[2]

MR 3 A[1:0]

Function

MPR

MPR-Loc

0b don’t care (0b or 1b)

Normal operation, no MPR transaction. All subsequent Reads will come from DRAM

array. All subsequent Write will go to DRAM array.

1b See Table 13 Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0].

Memory Core

(all banks

precharged)

Multipurpose

data for read

MR3[A2]

DQ, DM, DQS, DQS#

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MPR Register Address Definition

The following Table provides an overview of the available data locations, how they are addres sed b y MR3 A[1:0] dur ing a

MRS to MR3, and how their individual bits are mapped into the burst order bits during a Multi Purpose Register Read.

MPR MR3 Register Definition

MR3

A[2]

MR3

A[1:0]

Function

Burst

Length

Read Addres s

A[2:0]

Burst Order and Data Pattern

1b 00b R ead pred efined pattern

for system Calibration

BL8 000b

Burst order 0,1,2,3,4,5,6,7

Pre-defined Data Pattern [0,1,0,1,0,1,0,1]

BC4 000b

Burst order 0,1,2,3

Pre-defined Data Pattern [0,1,0,1]

BC4 100b

Burst order 4,5,6,7

Pre-defined Data Pattern [0,1,0,1]

1b 01b RFU

BL8

000b

Burst order 0,1,2,3,4,5,6,7

BC4

000b

Burst order 0,1,2,3

BC4

100b

Burst order 4,5,6,7

1b 10b RFU

BL8

000b

Burst order 0,1,2,3,4,5,6,7

BC4

000b

Burst order 0,1,2,3

BC4

100b

Burst order 4,5,6,7

1b 11b RFU

BL8

000b

Burst order 0,1,2,3,4,5,6,7

BC4

000b

Burst order 0,1,2,3

BC4

100b

Burst order 4,5,6,7

NOTE: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent

MPR Functional Description

• One bit wide logical interface via all DQ pins during READ operation.

• Register Read on x16:

o DQL[0] and DQU[ 0] dri ve information from MPR.

o DQL[7:1] and DQU[7:1] either drive the same information as DQL[0], or they drive 0b.

• Addressing during for Multi Purpose Register reads for all MPR agents:

o BA[2:0]: don’t care

o A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed

o A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst Chop 4

cases, the burst order is switched on nibble base A[2]=0b, Burst order: 0,1,2,3 *) A[2]=1b, Burst order:

4,5,6,7 *)

o A[9:3]: don’t care

o A10/AP: don’t care

o A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0.

o A11, A13: don’t care

• Regular interface functionality during register reads:

o Support two Burst Ordering which are switched with A2 and A[1:0]=00b.

o Support of read burst chop (MRS and on-the-fly via A12/BC)

o All other address bits (remaining column address bits including A10, all bank address bits) will be ignored

by the DDR3 SDRAM.

o Regular read latencies and AC timings apply.

o DLL must be locked prior to MPR Reads.

NOTE: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.

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NOTE: Good reference for the example of MPR feature is the J E DEC standard No.93-3D, 4.10.4 Protocol example.

Relevant Timing Parameters

AC timing parameters are important for operating the Multi Purpose Register: tRP, tMRD, tMOD, and tMPRR. For more

details refer to “Electrical Characteristics & AC Timing”

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2.4 DDR3 SDRAM Command Descrip tion and Operation

2.4.1 Command Truth Table

[BA=Bank Address, RA=Row Address, CA=Column Address, BC#=Burst Chop, X=Don’t Care, V=Valid]

Function Abbrevia

tion

CKE

CS# RAS

# CAS

# WE

# BA

0-2 A11,

A13 A12/

BC# A10/

AP A0-

A9 Notes

Cycle

Current

Cycle

Mode Register Set

MRS

OP Code

Refresh

REF

Self Refresh Entry

SRE

7,9,12

Self Refresh Exit SRX L H

7,8,9,

Single Bank Precharge

PRE

Precharge all Banks

PREA

Bank Activate

ACT

H H L L H H BA

Row Address(RA)

Write (Fixed BL8 or BC4)

RFU

Write (BC4, on the Fly)

WRS4

RFU

Write (BL8, on the Fly)

WRS8

RFU

Write with Auto Precharge (Fixed BL8 or BC4)

WRA

RFU

Write with Auto Precharge (BC4, on the Fly)

WRAS4

H H L H L L BA RFU L H CA

Write with Auto Precharge (BL8, on the Fly)

WRAS8

H H L H L L BA RFU H H CA

Read (Fixed BL8 or BC4)

RFU

Read (BC4, on the Fly)

RDS4

RFU

Read (BL8, on the Fly)

RDS8

RFU

Read with Auto Precharge (Fixed BL8 or BC4)

RDA

RFU

Read with Auto Precharge (BC4, on the Fly)

RDAS4

H H L H L H BA RFU L H CA

Read with Auto Precharge (BL8, on the Fly)

RDAS8

H H L H L H BA RFU H H CA

No Operation

NOP

Device Deselected

DES

Power Down Entry PDE H L

6,12

Power Down Exit PDX L H

6,12

ZQ Calibration Long

ZQCL

ZQ Calibration Short

ZQCS

H H L H H L X X X L X

Notes:

1. All DDR3 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock. The MSB of BA, RA and CA

are device density and configuration dependant.

2. RESET# is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function.

3. Bank address es (BA) determi ne which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.

4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.

5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly B L will be defined by MRS.

6. The Power Down Mode does not perform any refresh operation.

7. The state of ODT does not affect the states described in this table. The ODT function is not availabl e during Self Refresh.

8. Self Refresh Exit is asynchronous.

9. VREF(Bot h VrefDQ and Vref CA) must be maintained during Self Refresh operation. VrefDQ supply may be turned OFF and VREFDQ may take any

value between VSS and VDD during Self Refresh operation, provided t hat V ref DQ is valid and stable prior to CKE going back High and that first

Write operation or first Writ e Leveling Act i vity may not occur earl i er than 512 nCK after exit from Self Refresh.

10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait st ate. T he purpose of the No Operation command

(NOP) is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A No Operation command will not terminate a

pervious operation t hat is stil l executing, such as a burst read or write cycle.

11. The Deselect command performs the same function as No Operation comm and.

12. Refer to the CKE Truth Table for more detail with CKE transition.

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2.4.1. CKE Truth Table

Current State2 CKE

Command (N)3

RAS#, CAS#, WE#,

CS#

Action (N)3 Notes

Previous Cycle1 (N-1) Current Cyc l e1(N)

Power-Down L L X Maintain Power-Down 14,15

L H DESELECT or NOP Power-Down Exit 11,14

Self-Refresh L L X Maintain Self-Refresh 15,16

L H DESELECT or NOP Self-Refresh Exit 8,12,16

Bank(s) Active H L DESELECT or NOP Active Power-Down Entry 11,13,14

Reading H L DESELECT or NOP Power-Down Entry 11,13,14,17

Writing H L DESELECT or NOP Power-Down Entry 11,13,14,17

Precharging H L DESELECT or NOP Power-Down Entry 11,13,14,17

Refreshing H L DESELECT or NOP Precharge Power-Down Entry 11

All Bank Idle H L DESELECT or NOP Precharge Power-Down Entry 11,13,14,18

H L REFRESH Self-Refresh 9.13.18

Notes:

1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.

2. Current st ate is defined as the state of the DDR3 SDRAM immediately prior to clock edge N.

3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not included here.

4. All stat es and sequences not shown are illegal or reserved unless explicitl y desc ri bed elsewhere in this document.

5. The state of ODT does not affect the states described in this table. The ODT function is not availabl e during Self-Refresh.

6. CKE must be registered with the sam e value on tCKEmin consecutive positive clock edges. CKE must remain at the valid input level the entire time it

takes to achieve the tCKEmin clocks of registerat i on. Thus, after any CKE transition, CKE m ay not transition f rom its valid l evel duri ng the time

period of tIS + tCKEmin + tIH.

7. DESELECT and NOP are defined in the Command Truth Table.

8. On Self-Refres h Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period. Read or ODT commands

may be issued only after tXSDLL is satisfied.

9. Self-Refre sh mode can only be entered from the All Banks Idle state.

10. Must be a legal command as defined in the Command Truth Table.

11. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.

12. Valid commands for Self-Refresh Exit are NOP and DESELECT only.

13. Self-Refresh cannot be entered during Read or Write operations.

14. The Power-Down does not perform any refres h operations.

15. “X” means “don’t care“ (i ncludi ng floati ng around V REF) in Self-Refresh and Power-Down. It also applies to Address pins.

16. VREF (Bot h Vref_DQ and Vref_CA) must be maintained during Self-Refresh operation.VrefDQ supply may be turned OFF and VREFDQ may take

any value between VSS and VDD during Self Refresh operation, provided t hat Vref DQ is valid and stable prior to CKE going back High and that first

Write operation or first Writ e Leveling Act i vity may not occur earl i er than 512 nCK after exit from Self Refresh.

17. If all banks are clos ed at the conclusion of the read, write or precharge command, then Precharge Power-Down is ent ered, ot herwise Ac t i ve Power-

Down is entered.

18. ‘Idl e st ate’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all timings f rom previous

operations are satisfi ed (t MRD, tMOD, t RFC, tZQinit, tZQoper, tZQ CS, et c.) as well as a ll Self-Refresh exit and Power-Down Exit parameters are

satisfied (tXS, tXP, tXPDLL, etc).

2.4.2 No Operation (NOP) Command

The No operation (NOP) command is used to instruct the selected DDR3 SDRAM to perform a NOP ( CS# low and

RAS#,CAS#,WE# high). This prevents unwanted commands from being registered during idle or wait states. Operations

alrea d y in progress are not affected.

2.4.3 Deselect(DES) Command

The Deselect function (CS# HIGH) prevents new commands from being executed by the DDR3 SDRAM. The DDR3

SDRAM is effectively deselected. Operations already in progress are not affected.

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2.4.4 DLL-off Mode

DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations until A0 bit

set back to “0”. The MR1 A0 bit for DLL control can be switched either during initialization or later. The DLL-off Mode

operations listed below are an optional feature for DDR3. The maximum clock frequency for DLL-off Mode is specif ied b y

the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the refresh interval, tREFI.

Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS Write Latency (CWL)

in MR2 are supported. The DLL-off mode is only required to support setting of both CL=6 and CWL=6. DLL-off mode will

affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the data Strobe to Data relati onshi p ( tDQ SQ,

tQH). Special attention is needed to line up Read data to controller time domain.

Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after the Read command,

the DLL-off mode tDQSCK starts (AL+CL-1) cycles after the read command. Another difference is that tDQSCK may not

be small compared to tCK (it might even be larger than tCK) and the difference between tDQSCKmin and tDQSCKmax is

significantly larger than in DLL-on mode. The timing relations on DLL-off mode READ operation have shown at the

following Timing Diagram (CL=6, BL=8)

Note: The tDQSCK is used here for DQS, DQS, and DQ to have a simplified diagram; the DLL_off shift will affect both timings in the same way and the

skew between all DQ, DQS, and DQS# signals will still be tD QS Q .

Figure 2.4.4 DLL-off mode READ Timing Operation

CK#

Command

Address

DQS,DQS#(DLL_on)

DQ(DLL_on)

DQS,DQS#(DLL_off)

DQ(DLL_off)

DQS,DQS#(DLL_off)

DQ(DLL_off)

tDQSCK(DLL_off)_min

tDQSCK(DLL_off)_max

RL (DLL_off) = AL+(CL-1) = 5

RL (DLL_on) = AL+CL =6 (CL= 6,AL=0)

CL=6

T10

READ

NOP

Don’t Care

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2.4.5 DLL on/off switching procedure

DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operation until A0 bit

set back to “0”.

2.4.5.1 DLL “on” to DLL “off” Procedure

To switch from DLL “on” to DLL “off” requires te frequency to be changed during Self-Refresh outlined in the following

procedure:

1. Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT,

must be in high impedance state before MRS to MR1 to disable the DLL).

2. Set MR1 Bit A0 to “1” to disable the DLL.

3. Wait tMOD.

4. Enter Self Refresh Mode; wait until (tCKSRE) satisfied.

5. Change frequency, in guidance with “Input Clock Frequency Change” section.

6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.

7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings from

any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when Self

Refresh mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any

MRS command are satisfied. If both ODT features were disabled in the mode registers when Self Refresh mode was

entered, ODT signal can be registered LOW or HIGH.

8. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may be

necessary. A ZQCL command may also be issued after tXS).

9. Wait for tMOD, and then DRAM is ready for next command.

2.4.5.2 DLL “off” to DLL “on” Procedure

To switch from DLL “off” to DLL “on” (with required frequency change) during Self-Refresh:

1. Starting from Idle state (All banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT)

must be in high impedance state before Self-Refresh mode is entered.)

2. Enter Self Refresh Mode, wait until tCKSRE satisfied.

3. Change freque ncy, in guidance with "Input clock frequency change".

4. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.

5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from

subsequent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers

when Self Refresh mode was entered, the ODT signal must continuously be registered LOW until tDLLK timings from

subsequent DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self

Refresh mode was entered, ODT signal can be registered LOW or HIGH.

6. Wait tXS, then set MR1 bit A0 to “0” to enable the DLL.

7. Wait tMRD, then set MR0 bit A8 to “1” to start DLL Reset.

8. Wait tMRD, then set Mode Registers with appropriate values (especially an update of CL, CWL and WR may be

necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued during

or after tDLLK.)

9. Wait for tMOD, then DRAM is ready for next command (Remember to wait tDLLK after DLL Reset before applying

command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued.

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2.4.6. Input clock freq u ency change

Once the DDR3 SDRAM is initialized, the DDR3 SDRAM requires the clock to be “stable” during almost all states of

normal operation. This means that, once the clock frequency has been set and is t o be in the “stable state”, the clock

period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (spread spectrum clocking)

specifications.

The input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions:

(1) Self-Refresh mode and (2) Precharge Power-down mode. Outside of these two modes, it is illegal to change the clock

frequency.

For the first condition, once the DDR3 SDRAM has been successfully placed in to Self-Refresh mode and tCKSRE has

been satisfied, the state of the clock becomes a don’t care. Once a don’t care, changing the clock frequency is

permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode

for the sole purpose of changing the clock frequency, the Self-Refresh entry and exit specifications must still be met.

The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating

frequency specified for the particular speed grade. Any frequency change below the minimum operating frequency would

require the use of DLL_on- mode -> DLL_off -mode transition sequence, refer to “DLL on/off switching procedure”.

The second condition is when the DDR3 SDRAM is in Precharge Power-down mode (either fast exit mode or slow exit

mode). If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the

ODT signal must continuously be registered LOW ensuring RTT is in an off state. If the RTT_NOM feature was disabled in

the mode register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be

registered either LOW or HIGH in this case. A minimum of tCKSRE must occur after CKE goes LOW before the clock

frequency may change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and

maximum operating frequency specified for the particular speed grade. During the input clock frequency change, ODT

and CKE must be held at stable LOW levels. Once the input clock frequency is changed, stable new clocks must be

provided to the DRAM tCKSRX before Precharge Power-down may be exited; after Precharge Power-down is exited and

tXP has expired, the DLL must be RESET via MRS. Depending on the new clock frequency, additional MRS commands

may need to be issued to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL re-

lock period, ODT must remain LOW and CKE must remain HIGH. After the DLL lock time, the DRAM is ready to op erate

with new clock frequency.

2.4.7 Write leveling

For better signal integrity, the DDR3 memory module adopted fly-by topology for the commands, addresses, control

signals, and clocks. The fly-by topology has benefits from reducing number of stubs and their length, but it also causes

flight time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the Controller to

maintain tDQSS, tDSS, and tDSH specification. Therefore, the DDR3 SDRAM supports a ‘write leveling’ feature to allow

the controller to compensate for skew.

The memory controller can use the ‘write leveling’ feature and feedback from the DDR3 SDRAM to adjust the DQS -

DQS# to CK - CK# relationship. The memory controller involved in the leveling must have adjustable delay setting on

DQS - DQS# to align the rising edge of DQS - DQS# with that of the clock at the DRAM pin. The DRAM asynchronously

feeds back CK - CK#, sampled with the rising edge of DQS - DQS#, through the DQ bus. The controller repeatedly delays

DQS - DQS# until a transition from 0 to 1 is detected. The DQS - DQS# delay established though this exercise would

ensure tDQSS specification.

Besides tDQSS, tDSS and tDSH specification also needs to be fulfilled. One way to achieve this is to combine the actual

tDQSS in the application with an appropriate duty cycle and jitter on the DQS - DQS# signals. Depending on the actual

tDQSS in the application, the actual values for tDQSL and tDQSH may have to be better than the absolute limits provided

in the chapter "AC Timing Parameters" in order to satisfy tDSS and tDSH specification. A conceptual timing of this

scheme is shown in Figure 2.4.7.

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Figure 2.4.7 Write Leveling Concept

DQS - DQS# driven by the controller during leveling mode must be terminated by the DRAM based on ranks populated.

Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.

One or more data bits should carry the leveling feedback to the controller across the DRAM configurations X8 and X16.

On a X16 device, both byte lanes should be leveled independently.

Therefore, a separate feedback mechanism should be available for each byte lane. The upper data bits should provide

the feedback of the upper diff_DQS(diff_UDQS) to clock relationship whereas the lower data bits would indicate the lower

diff_DQS(diff_LDQS) to clock relationship.

2.4.7.1 DRAM setting for write leveling & DRAM termination function in that mode

DRAM enters into Write leveling mode if A7 in MR1 set ’High’ and after finishing leveling, DRAM exits from write leveling

mode if A7 in MR1 set ’Low’. Note that in write leveling mode, only DQS/DQS# terminations are activated and deactivated

via ODT pin, unlike normal operation.

MR setting involved in the leveli n g p rocedure

Function MR1 Enable Disable

Write leveli ng enabl e

Output buffer mode (Qoff) A12 0 1

DRAM termination function in the leveling mode

ODT pin @DRAM DQS/DQS# termination DQs termination

De-asserted

Off

Asserted

Off

NOTE: In Write Leveling Mode with its output buffer disabl ed (MR1[bit7] = 1 with MR1[bit12] = 1) all RTT_Nom settings are allowed; in Write Leveling

Mode with its output buffer enabled (MR1[bit7] = 1 with MR1[bit12] = 0) only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed.

CK#

diff_DQS

Source

Destination

CK#

diff_DQS

Pus h D QS to capture

0-1 transition

0 or 1

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2.4.7.2 Procedure Description

The Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. When entering write leveling

mode, the DQ pins are in undefined driving mode. During write leveling mode, only NOP or DESELECT commands are

allowed, as well as an MRS command to exit write leveling mode. Since the controller levels one rank at a time, the output

of other ranks must be disabled by setting MR1 bit A12 to 1.

The Controller may assert ODT after tMOD, at which time the DRAM is ready to accept the ODT signal.

The Controller may drive DQS low and DQS# high after a delay of tWLDQSEN, at which time the DRAM has applied on-

die termination on these signals. After tDQSL and tWLMRD, the controller provides a single DQS, DQS# edge which is

used by the DRAM to sample CK - CK# driven from controller. tWLMRD(max) timing is controller dependent.

DRAM samples CK - CK# status with rising edge of DQS - DQS# and provides feedback on all the DQ bits

asynchronously after tWLO timing. Either one or all data bits ("prime DQ bit(s)") provide the leveling feedback. The

DRAM's remaining DQ bits are driven Low statically after the first sampling procedure. There is a DQ output uncertainty of

tWLOE defined to allow mismatch on DQ bits. The tWLOE period is defined from the transition of the earliest DQ bit to the

corresponding transition of the latest DQ bit. There are no read strobes (DQS/DQS#) needed for these DQs. Controller

samples incoming DQ and decides to increment or decre ment DQS - DQS# delay setting and launches the next

DQS/DQS# pulse after some time, which is controller dependent. Once a 0 to 1 transition is detected, the controller locks

DQS - DQS# delay setting and write leveling is achieved for the device. Figure 2.4.7.2 describes the timing diagram and

parameters for the overall Write Leveling procedure.

Notes:

1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs . If feedback is driven only on one DQ, the remaining DQs must be driven

low, as shown in above Figure, and maintai ned at this state throughout t he leveling procedure.

2. MRS: Load MR1 to enter write leveling mode.

3. NOP: NOP o r Desel ect.

4. diff _DQS is the diff erent i al data strobe (DQS, DQS#). Timing reference points are the zero crossi ngs. DQS is shown with solid line, DQS# is shown

with dotted line.

5. CK, CK# : CK is shown wit h solid dark line, where as CK# is drawn with dot t ed l i ne.

6. DQS, DQS# needs to fulfill minim um pulse width requirem ents tDQSH(m i n) and tDQSL(min) as defined for regular Writes; the max puls e width is

system dependent.

CK#(5)

CMD

MRS

NOP

tMOD

NOP

tWLH

tWLS

tWLH

tWLS

NOP

DON’T CARE

Undefined

Driving Mode

Time Break

ODT

diff_DQS(4)

One Prime DQ:

Prime DQ

(1)

Late Remain i ng DQs

Early Rem ainin g D Qs

Late Remain i ng DQs

(1)

Early Rem ainin g D Qs

(1)

All DQs are Prime:

(2)

(3)

tWLDQSEN

tDQSL(6)

tDQSH(6)

tDQSL(6)

tDQSH(6)

tWLMRD

tWLO

tWLOE

tWLO tWLO

tWLO tWLO tWLOE

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Figure 2.4.7.2 Write leveling sequence [DQS - DQS# is capturing CK-CK# low at T1 and CK-CK# high at T2]

2.4.7.3 Write Leveling Mode Exit

The following sequence describes how the Write Leveling Mode should be exited:

1. After the last rising strobe edge, stop driving the strobe signals. Note: From now on, DQ pins are in undefined driving

mode, and will remain undefined, until tMOD after the respective MR command.

2. Drive ODT pin low (tIS must be satisfied) and continue registering low.

3. After the RTT is switched off, disable Write Level Mode via MRS command.

4. After tMOD is satisfied, any valid command may be registered. (MR commands may be issued after tMRD ).

2.4.8 Extended Temperature Usage

a. Auto Self -refresh supported

b. Extended Temperature Range supported

c. Double refresh required for operation in the Extended Temperature Range (applies only for devices supporting the

Extended Temperature Range)

Mode Register Description

Field Bits Description

Auto Self-Refresh (ASR)

when enabled, DDR3 SDRAM automatically provides Self-Refresh power management functions for all

supported operating temperature values. If not enabled, the SRT bit must be programmed to indicate TOPER

ASR

MR2 (A6)

during subsequent Self-Refresh operation

0 = Manual SR Reference (SRT)

1 = ASR enable

Self-Refresh Temperature (SRT) Range

If ASR = 0, the SRT bit must be programmed to indicate TOPER during subsequent Self-Refresh opera tion

SRT MR2 (A7) If ASR = 1, SRT bit must be set to 0b

0 = Normal operating temperature range

1 = Extended operating temperature range

2.4.8 1 Auto Self-Refresh mode - ASR Mode

DDR3 SDRAM provides an Auto Self-Refresh mode (ASR) for application ease. ASR mode is enabled by setting MR2 bit

A6 = 1b and MR2 bit A7 = 0b. The DRAM will manage Self-Refresh entry in either the Normal or Extended (optional)

Temperature Ranges. In this mode, the DRAM will also manage Self-Refresh power consumption when the DRAM

operating temperature changes, lower at low temperatures and higher at high temperatures.

If the ASR option is not supported by the DRAM, MR2 bit A6 must be set to 0b.

If the ASR mode is not enabled (MR2 bit.A6 = 0b), the SRT bit (MR2 A7) must be manually programmed with the

operating temperature range required during Self-Refresh operation.

Support of the ASR option does not automatically imply support of the Extended Temperature Range.

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3. ABSOL UTE MAXI MUM RATINGS AND AC & DC OPERATING CONDITIONS

3.1 Absolute Maximum DC Ratings.

Symbol Parameter Rating Units Note

VDD Voltage on VDD pin relative to Vss -0.4 V ~ 1.975 V V 1,3

VDDQ Voltage on VDDQ pin relative to Vss -0.4 V ~ 1.975 V V 1,3

VIN, VOUT Voltage on any pin relative to Vss -0.4 V ~ 1.975 V V 1

TSTG Storage Temperature -55 to +100 °C 1,2

Notes:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operat i on of the device at these or any other conditions above those indicated in the operat i onal sect i ons of this specification is not

implied. Exposure to absol ut e maximum rating condit i ons for extended periods may affect reli abi lit y .

2. Storage T emperature is the case surfac e temperat ure on the center/top si de of the DRAM. For the measurement conditions.

3. VDD and VDDQ must be within 300 mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less

than 500 mV; VREF may be equal to or less than 300 mV

3.2 Component Operating Temperature Range

Symbol

Parameter

Rating

Units

Notes

Toper for Commercial

Normal Operating Temperature Range

0 to 85

°C

1,2

Extended Temperature Range

85 to 95

°C

1,3

Toper for Industrial and

Automotive

Normal Operating Temperature Range -40 to 0 °C 1

Toper for Automotive

(A2 only)

Normal Operating Temperature Range 95 to 105 °C 1,3

Notes:

1. Operating Temperature TOPER is the case surface te mperature on the center / top side o f the DRAM.

2. The Normal Temperature Range specif i es the temperat ures where all DRAM specificat i ons will be supported. During operation, the DRAM case

temperature m ust be maintained between 0 to 85°C under all operating conditions

3. Some appl ications require operation of the DRAM in the Extended Temperature Range above 85°C case temperature. Ful l specifications are

supported in this range, but the following additional conditions apply:

a ) Refresh commands must be doubled in frequency, therefore reduci ng the Refresh interval t REFI to 3.9 µs.

b) If Self-Refresh operation is required in the Extended Temperat ure Range, then it is mandatory to either use the Manual Self-Refresh mode with

Extended Temperat ure Range capabilit y (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2

A7 = 0b).

3.3 Recommended DC Operatin g Conditions(SSTL_1.5)

Symbol Parameter

Rating

Unit Notes

Min

Typ

Max

VDD

Supply Voltage

1.425

1.5

1.575

1,2

VDDQ

Supply Voltage for Output

1.425

1.5

1.575

1,2

Notes:

1. Under all conditi ons V DDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

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4. AC & DC INPUT MEASUREMENT LEVELS

4.1. AC and DC Logi c Input Levels for Sing le-Ended Signals

4.1.1 AC and DC Input Levels for Single-Ended Command and Address Signals

Symbol Parameter

DDR3-800/1066/1333/1600

Unit Note

Min

Max

VIH.DQ(DC100) DC input logic high Vref + 0.100 VDD V 1

VIL.DQ(DC100) DC input logic low VSS Vref - 0.100 V 1

VIH.DQ(AC175) AC input logic hig h Vref + 0.175 Note 2 V 1,2

VIL.DQ(AC175) AC input logic low Note 2 Vref - 0.175 V 1,2

VIH.CA(AC150)

AC input logic high

Vref + 0.150

Note2

1,2

VIL.CA(AC150)

AC input logic low

Note2

Vref - 0.150

1,2

VREFCA(DC)

Reference Voltage for ADD, CMD inputs

0.49 * VDD

0.51 * VDD

3,4

Symbol Parameter

DDR3L-800/1066/1333/1600

Unit Note

Min

Max

VIH.DQ(DC90) DC input logic high Vref + 0.09 VDD V 1

VIL.DQ(DC90) DC input logic low VSS Vref - 0.09 V 1

VIH.DQ(AC160) AC input logic hig h Vref + 0.160 Note 2 V 1,2

VIL.DQ(AC160)

AC input logic low

Note 2

Vref - 0.160 V 1,2

VIH.CA(AC135)

AC input logic high

Vref + 0.135

Note2

1,2

VIL.CA(AC135)

AC input logic low

Note2

Vref - 0.135

1,2

VREFCA(DC)

Reference Voltage for ADD, CMD inputs

0.49 * VDD

0.51 * VDD

3,4

Notes:

1. For input only pins except RESET.Vref=VrefCA(DC)

2. See "Overshoot and Undershoot Specificat i ons"

3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than +/ - 0.1% VDD.

4. For reference: DDR3 has approx. VDD/2 +/- 15mV, DDR3L has approx VDD/2 +/- 13.5mV.

5. To allow VREFCA margining, all DRAM Command and Address Input Buffers MUST use external VREF (provided by syst em) as the input for their

VREFCA pins. All VIH/L input level MUST be compared with the external VRE F level at the 1st stage of the Command and Address input buffer

4.1.2 AC and DC Logic Input Le vels for Single-Ended Signals & DQ and DM

Symbol Parameter DDR3-800/1066 DDR3-1333/1600 DDR3-1866 Unit Note

Min.

Max.

Min.

Max.

Min.

Max.

VIH.DQ(DC100) DC input logic high

Vref

+0.100

VDD

Vref

+0.100

VDD

Vref

+0.100

VDD V 1

VIL.DQ(DC100) DC input logic low VSS

Vref -

0.100

VSS

Vref -

0.100

VSS

Vref -

0.100

V 1

VIH.DQ(AC175) AC input logic hig h

Vref

+0.175

Note2 - - - - V 1,2,5

VIL.DQ(AC175) AC input logic low Note2

Vref -

0.175

- - - - V 1,2,5

VIH.DQ(AC150) AC input logic hig h

Vref

+0.150

Note2

Vref

+0.150

Note2 - - V 1,2,5

VIL.DQ(AC150) AC input logic low Note2

Vref -

0.150

Note2

Vref -

0.150

- - V 1,2,5

VREFDQ(DC)

Reference Voltage for

DQ, DM inputs

0.49

*VDD

0.51 *VDD

0.49

*VDD

0.51 *VDD 0.49 *VDD

0.51

*VDD

V 3,4

VREFDQ_t(DC) Reference Voltage for

trained DQ, DM inputs

0.45

*VDD

0.55 *VDD 0.45

*VDD

0.55 *VDD 0.45 *VDD 0.55

*VDD

V 3,4,

6,7

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Symbol Parameter DDR3L-800/1066 DDR3L-1333/1600 Unit Note

Min.

Max.

Min.

Max.

VIH.DQ(DC90)

DC input logic high

Vref +0.09

VDD

Vref +0.09

VDD

VIL.DQ(DC90)

DC input logic low

VSS

Vref -0.09

VSS

Vref -0.09

VIH.DQ(AC160)

AC input logic high

Vref +0.175

Note2

1,2,5

VIL.DQ(AC160)

AC input logic low

Note2

Vref -0.160

1,2,5

VIH.DQ(AC135)

AC input logic high

Vref +0.150

Note2

Vref +0.135

Note2

1,2,5

VIL.DQ(AC135)

AC input logic low

Note2

Vref -0.135

Note2

Vref -0.135

1,2,5

VREFDQ(DC)

Reference Voltage for DQ,

DM inputs

0.49 *VDD 0.51 *VDD 0.49 *VDD 0.51 *VDD V 3,4

VREFDQ_t(DC)

Reference Voltage for

trained DQ, DM inputs 0.45 *VDD 0.55 *VDD 0.45 *VDD 0.55 *VDD V

3,4,

6,7

Notes:

1. For input only pins except RESET#. Vref = VrefDQ(DC)

2. See "Overshoot and Undershoot Specificat i ons"

3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than ± 0.1% VDD.

4. For reference: DDR3 has approx. VDD/2 ±15mV , and DDR3L has approx. VDD/2 ± 13.5mV .

5. Single-ended swing requirem ent f or DQS-DQS#, is 350mV (peak to peak). Different i al swing requirem ent for DQS -DQS#, is 700mV (peak to peak)

6. VRefDQ training is perform ed only during system boot. Once the training is complet ed and an optimal VRefDQ_t(DC) voltage l evel is identif i ed, the

optimal VRefDQ_t(DC) volt age l evel will be used during system runtime. During VRefDQ training, VRefDQ is swept f rom 40% of VDD to 60% of V DD to

find the optimal VRefDQ_t (DC) voltage level; and onc e the optim al VRefDQ_t(DC) is set, it must stay within ±1% of its set value as well as not be less

than 45% of VDD or exceed 55% of VDD. VIH.DQ(AC)min/VIL.DQ(AC)max = Optimal VRefDQ_t(DC) ±AC Level, where "AC Level" is the actual AC

voltage level per DDR3 speed bins as specified in JESD79-3 specificati on. After VRefDQ training is com pleted and the optimal V RefDQ _t(DC) i s set, the

Memory Controller provides t he DRAM device a valid write window. Through DQS pl acem ent optimi zation and V RefDQ centeri ng, t he valid write window

is optimized for both input voltage m argi n and tDS+tDH window for the DRAM receiver. The DRAM device supports the use of the above techniques to

optimize the write timi ng and voltage margin, as long as the technique does not create any DIMM failures due to DRAM input voltage and/or timing spec

violations as defined in JESD79-3 specification.

7. To allow VREFDQ margining, all DRAM Data Input Buffers MUST use external VREF (provided by system) as the input for their VREFDQ pins. All

VIH/L input level MUST be compared with the external VREF level at the 1st stage of the Data input buffer.

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4.2 Vref Tolerances

The dc-tolerance limits and ac-moist limits for the reference voltages VrefCA and VrefDQ are illustrated in the following

figure. It shows a valid reference voltage Vref(t) as a function of time. (Vref stands for VrefCA and VrefDQ likewise).

Vref(DC) is the linear average of Vref(t) over a very long period of time (e.g.,1 sec). This average has to meet the min/max

requirement in previous page. Furthermore Vref(t) may temporarily deviate from Vref(DC) by no more than ±1% VDD.

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on

Vref. “Vref” shall be understood as Vref(DC). The clarifies that dc-variations of Vref affect the absolute voltage a signal

has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System

timing and voltage budgets need to account for Vref(DC) deviations from the optimum position within the data-eye of the

input signals.

This also clarifies that the DRAM setup/hold specification and de-rating values need to include time and voltage

associated with Vref ac-noise. Timing and voltage effects due to ac-noise on Vref up to the specified limit (±1% of VDD)

are included in DRAM timing and their associated de-ratings.

Figure 4.2 Illustration of Vref(DC) tolerance and Vrefac-noise limits

Voltage

Vref(D

Vref ac-noise

Vref(t)

Vref(DC)

VDD

VSS

time

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4.3. AC and DC Logi c Input Levels for Differe n tial Signals

4.3.1 Differential signal definition

Figure 4.3.1 Definition of differential ac-s wing and “time above ac-level”

4.3.2 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#)

1. Differe n tial AC and DC Input Levels

Symbol Parameter

DDR3-800, 1066, 1333, & 1600

unit Notes

Min

Max

VIHdiff Differential input logic high +0.200 Note3 V 1

VILdiff Differential input logic low Note3 -0.200 V 1

VIHdiff(ac) Differential input high ac 2 x ( VIH(ac) – Vref ) Note3 V 2

VILdiff(ac) Differential input low ac Note3 2 x ( Vref - VIL(ac) ) V 2

Symbol Parameter

DDR3L-800, 1066, 1333, & 1600

unit Notes

Min

Max

VIHdiff Differential input logic high +0.180 Note3 V 1

VILdiff Differential input logic low Note3 -0.180 V 1

VIHdiff(ac) Differential input high ac 2 x ( VIH(ac) – Vref ) Note3 V 2

VILdiff(ac) Differential input low ac Note3 2 x ( Vref - VIL(ac) ) V 2

Notes:

1. Used to define a different i al signal slew-rate.

2. For CK - CK# use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - DQS#, DQSL, DQSL#, DQSU, DQSU# use VIH/VIL(ac ) of DQs and VREFDQ; if

a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.

3. These values are not defined; however, the single-ended signal s CK, CK#, DQS, DQS#, DQSL, DQSL#, DQSU, DQSU# need to be within the

respective limits (VI H(dc ) max, VIL(dc)mi n) for singl e-ended s i gnals as well as the limitations f or overs hoot and unders hoot.

tDVAC

VIH.DIFF.AC.MIN

VIH.DIFF.MIN

VIH.DIFF.MAX

VIH.DIFF.AC.MAX

Half cycle

tDVAC

time

Differential Input Voltage (i.e. DQS–DQS#, CK–CK#)

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4.3.2.2 A llowed time before ringback (tDVAC) for CK - CK# and DQS - DQS#

Slew Rate [V/ns]

tDVAC [ps] @IVIH/Ldiff(ac)I = 350mV

tDVAC [ps] @IVIH/Ldiff(ac)I = 300mV

min

max

min

max

> 4.0

175

4.0

170

3.0

167

2.0

163

1.8

162

1.6

161

1.4

159

1.2

155

1.0

150

< 1.0

150

4.3.3. Single-ended requirements for di ffer ential signals

Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK#, DQS#, DQSL#, or DQSU#) has also to

comply with certain requirements for single-ended signals.

CK and CK# have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH(ac) / VIL(ac) )

for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, DQS#, DQSL# have to reach VSEHmin / VSELmax

(approximately the ac-levels (VIH(ac) / VIL(ac) ) for DQ signals) in every half-cycle preceding and following a valid

transition.

4.3.3.1. Single-ended levels for CK, DQS, DQSL, DQSU, CK#, DQS#, DQSL# or DQSU#

Symbol Parameter

DDR3/DDR3L-800, 1066, 1333, & 1600

Unit Notes

Min

Max

VSEH

Single-ended high-level for strobes

(VDDQ/2) + 0.175

note3

1, 2

Single-ended high-level for CK, CK

(VDDQ/2) + 0.175

note3

1, 2

VSEL

Single-ended low-level for stro bes

note3

(VDDQ/2) - 0.175

1, 2

Single-ended Low-level for CK, CK

note3

(VDDQ/2) - 0.175

1, 2

Notes:

1. For CK, CK# use VIH/VIL(ac) of ADD/CMD; for strobes (DQS, DQS#, DQSL, DQSL#, DQS U, DQSU#) use VI H/VIL(ac) of DQs.

2. VIH(ac )/VIL(ac) for DQs is based on VREFDQ; VIH(ac)/ VIL(ac) for ADD/ CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a

signal group, then the reduced level applies also here

3. These values are not defined, however the single-ended signals CK, CK#, DQS, DQS#, DQSL, DQSL#, DQSU, DQSU# need to be within the

respective limits (VI H(dc ) max, VIL(dc)mi n) for singl e-ended s i gnals as well as the limitations f or overs hoot and unders hoot.

Figure 4.3.3 Single-ended requirement for differential signals.

VSS or VSSQ

VSELmax

VDD/2 or VDDQ/2

VSEHmin

VSEL

VSEH

CK or DQS

time

VDD or VDDQ

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4.4 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross

point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in the following table. The

differential input cross point voltage Vix is measured from the actual cross point of true and completement signal to the

midlevel between of VDD and VSS.

Figure 4.4. Vix Definition

4.4.1 Cross point voltage for differential input signals (CK, DQS)

Symbol Parameter

DDR3-800, 1066, 1333, & 1600

Unit Note

Min.

Max.

Vix

Differential Input Cross Point Voltage relative to VDD/2 for

CK, CK

-150 150 mV

-175 175 mV 1

Differential Input Cross Point Voltage relative to VDD/2 for

DQS, DQS

-150 150 mV

Note:

1. Extended range for Vi x is only allowed for clock and if single-ended clock i nput signals CK and CK# are monotonic with a single-ended swing VSEL /

VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK - CK# is larger than 3 V/ns.

4.5 Slew Rate Definitions for Single-Ended Input Signals

See “Address / Command Setup, Hold and Derating” for single-ended slew rate definitions for address and command

signals.

See “Data Setup, Hold and Slew Rate Derating” for single-ended slew rate definitions for data signals.

VDD

CK#,DQS#

VDD/2

CK,DQS

VSS

VIX

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4.6. Slew Rate Definition for Differential I n p u t Signals

4.6.1 Differential Inpu t Slew Rate Definition

Description

Measured

Defined by

From

Differential input slew rate for rising edge (CK-CK# & DQS-

DQS#)

VILdiffmax VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff

Differential input slew rate for falling edge (CK-CK# & DQS-

DQS#)

VIHdiffmin VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff

Note : The differential signal (i.e., CK-CK# & DQS-DQS#) must be linear between these thresholds.

Figure 4.6.1 Input Nominal Slew Rate Definition for DQS, DQS# and CK, CK#

Differential Input Voltage(i.e.

DQS-DQS#, CK-CK#)

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4.9.1 Self-Refresh Temperature Range - SRT

SRT applies to devices supporting Extended Temperature Range only. If ASR = 0b, the Self-Refresh Temperature (SRT)

Range bit must be programmed to guarantee proper self-refresh operation. If SRT = 0b, then the DRAM will set an

appropriate refresh rate for Self-Refresh operation in the Normal Te mperature Range. If SRT = 1b then the DRAM will set

an appropriate, potentially different, refresh rate to allow Self-Refresh operation in either the Normal or Extended

Temperature Ranges. The value of the SRT bit can effect self-refresh power consumption, please refer to the IDD table

for details.

For parts that do not support the Extended Temperature Range, MR2 bit A7 must be set to 0b and the DRAM should not

be operated outside the Normal Temperature Range.

Self-Refresh mode summary

MR2

A[6] MR2

A[7] Self-Refresh operatio n Allowed Operating Temperature Range for

Self-Refresh Mode

0 0 Self-refresh rate appropriate for the Normal Temperature Range Normal (0 - 85 oC)

0 1

Self-refresh rate appropriate for either the Normal or Extended

Temperature Ranges. The DRAM must support Extended

Temperature Range. The value of the SRT bit can effect self -

refresh power consumption, please refer to the IDD table for

details.

Normal and Extended (0 - 95 oC)

1 0 ASR enabled (for devices supporting ASR and Normal

Temperature Range). Self-Refresh power consumption is

temperature dependent Normal (0 - 85 oC)

1 0 ASR enabled (for devices supporting ASR and Extended

Temperature Range). Self-Refresh power consumption is

temperature dependent Normal and Extended (0 - 95 oC)

1 1 Illegal

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5. AC AND DC OUTPUT M EASUREMENT LEVELS

5.1 Single Ended AC and DC Output Levels

Symbol

Parameter

Value

Unit

Notes

VOH(DC)

DC output high measurement level (for IV curve linearity)

0.8xVDDQ

VOM(DC)

DC output mid measurement level (for IV curve linearity)

0.5xVDDQ

VOL(DC)

DC output low measurement level (fro IV curve linearity)

0.2xVDDQ

VOH(AC)

AC output high measurement level (for output SR)

VTT+0.1xVDDQ

VOL(AC)

AC output low measurement level (for output SR)

VTT-0.1xVDDQ

NOTE 1. The swing of ± 0.1 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a driver impedance of 40Ω

and an effective test load of 25Ω to VTT = VDDQ/2.

5.2 Differential AC and DC Output Levels

Symbol

Parameter

Value

Unit

Notes

VOHdiff(AC)

AC differential output high measurement level (for output SR)

+0.2 x VDDQ

VOLdiff(AC)

AC differential output low measurement level (for output SR)

-0.2 x VDDQ

NOTE 1. The swing of ± 0.2 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a driver impedance of 40Ω

and an effective test load of 25Ω to VTT = VDDQ/2 at each of the differential outputs.

5.3 Single Ended Output Slew Rate

5.3.1 Single Ended Output Slew Rate Definition

Description

Measured

Defined by

From

Single ended output slew rate for rising edge

VOL(AC)

VOH(AC)

[VOH(AC)-VOL(AC)] / DeltaTRse

Single ended output slew rate for falling edge

VOH(AC)

VOL(AC)

[VOH(AC)-VOL(AC)] / DeltaTFse

Figure 5.3.1 Single Ended Output Slew Rate Definition

5.3.2 Output Slew Rate (single-ended)

Parameter Symbol

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

Unit

Min.

Max.

Min.

Max.

Single-ended Output Slew Rate

SRQse

2.5

TBD

V/ns

Note: SR: Slew Rate. Q: Query Output (like in DQ, which stands for Data-in, Query -Output). se: Single-ended si gnal s. F or Ron = RZQ/7 setting.

Single Ended Output Voltage(i.e. DQ)

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5.4 Differential Output Slew Rate

5.4.1 Differential Output Slew Rate Definition

Description

Measured

Defined by

From

Differential output slew rate for rising

VOLdiff(AC)

VOHdiff(AC)

[VOHdiff(AC)-VOLdiff(AC)]/DeltaTRdiff

Differential output slew rate for falling

VOHdiff(AC)

VOLdiff(AC)

[VOHdiff(AC)-VOLdiff(AC)]/DeltaTFdiff

Note: Output slew rate is verified by design and characterizati on, and not 100% tested in product i on.

Figure 5.4.1 Differential Output Slew Rate Definition

5.4.2 Differential Output Slew Rate

Parameter Symbol

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

Unit

Min.

Max.

Min.

Max.

Differential Output Slew Rate

SRQdiff

TBD

V/ns

Description: SR: Slew Rate, Q: Query Output (like in DQ, which stands for Data-in, Query-Output), diff: Differential Signals, For Ron = RZQ/7 setting

5.5 Reference Load for AC Timing and Outp u t Slew Rate

The following figure represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters

of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular

system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS

or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their

production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.

Figure 5.5 Reference Load for AC Timing and Output Slew Rate

CK,CK#

DUT

DQ,

DQS,

DQS#

VDDQ

25ohm

VTT=VDDQ/2

Timing Re ference Point

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5.6 Overshoot and Un dershoot Specifications

5.6.1 AC Overshoot/Undersh o o t Specification for Address and Control Pins

Item

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

Units

Maximum peak amplitude allowed for overshoot area

0.4

Maximum peak amplitude allowed for undershoot area

0.4

Maximum overshoot area above VDD

0.67

0.5

0.4

0.33

V-ns

undershoot area below VSS

0.67

0.5

0.4

0.33

V-ns

Note : A0-A13, BA0-BA2, CS#, RAS#, CAS#, WE#, CKE, ODT

5.6.2 AC Overshoot/Undersh o o t Specification for Clock, Data, Strobe, and Mask

Item

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

Units

Maximum peak amplitude allowed for overshoot area

0.4

Maximum peak amplitude allowed for undershoot area

0.4

Maximum overshoot area above VDD

0.25

0.19

0.15

0.13

V-ns

undershoot area below VSS

0.25

0.19

0.15

0.13

V-ns

Note : CK, CK#, DQ, DQS, DQS#, DM

5.7 34Ohm Output Driver DC Electrical Characteristics

A Functional representation of the output buffer is shown as below. Output driver impedance RON is defined by the value

ofthe external reference resistor RZQ as follows:

RON34 = RZQ / 7 (nominal 34.4ohms +/-10% with nominal RZQ=240ohms)

The individual pull-up and pull-dow n resistors (RONPu and RONPd) are defined as follows:

RONPu = [VDDQ-Vout] / | Iout | ------------------- under the condition that RONPd is turned off (1)

RONPd = Vou t / | Iout | -------------------------------under the condition that RONPu is turned off (2)

Maximum Amplitude

Overshoot Area

Undershoot Area

Maximum Amplitude

VDD

VSS

Volts(V)

Time(ns)

Maximum Amplitude

VDDQ

VSSQ

Volts(V)

Time(ns)

Maximum Amplitude

Overshoot Area

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Figure 5.7 Output Driver : Definition of Voltages and Currents

5.7.1 Output Driver DC Electrical Characteristics

DDR3 (assuming 1.5V, RZQ = 240ohms; entire operating temperature range; after proper ZQ calibration)

RONNom

Resistor

Vout

Min

Nom

Max

Unit

Notes

34 ohms

RON34Pd VOLdc=0.2xVDDQ 0.6 1 1.1 RZQ/7 1,2,3

VOMdc=0.5xVDDQ 0.9 1 1.1 RZQ/7 1,2,3

VOHdc =0. 8xVDDQ 0.9 1 1.4 RZQ/7 1,2,3

RON34Pu VOLdc=0.2xVDDQ 0.9 1 1.4 RZQ/7 1,2,3

VOMdc=0.5xVDDQ 0.9 1 1.1 RZQ/7 1,2,3

VOHdc=0.8xVDDQ 0.6 1 1.1 RZQ/7 1,2,3

40 ohms

RON40Pd VOLdc=0.2xVDDQ 0.6 1 1.1 RZQ/6 1,2,3

VOMdc=0.5xVDDQ 0.9 1 1.1 RZQ/6 1,2,3

VOHdc =0. 8xVDDQ 0.9 1 1.4 RZQ/6 1,2,3

RON40Pu VOLdc=0.2xVDDQ 0.9 1 1.4 RZQ/6 1,2,3

VOMdc=0.5xVDDQ 0.9 1 1.1 RZQ/6 1,2,3

VOHdc=0.8xVDDQ 0.6 1 1.1 RZQ/6 1,2,3

Mismatch betw een pull-up and pull-down, MMPuPd VOMdc= 0.5xVDDQ -10 +10 % 1,2,4

DDR3L (assuming 1.35V, RZQ = 240ohms; entire operating temperature range; after proper ZQ calibration)

RONNom

Resistor

Vout

Min

Nom

Max

Unit

Notes

34 ohms

RON34Pd

VOLdc=0.2xVDDQ

0.6

1.15

RZQ/7

1,2,3

VOMdc=0.5xVDDQ 0.9 1 1.15 RZQ/7 1,2,3

VOHdc =0. 8xVDDQ

0.9

1.45

RZQ/7

1,2,3

RON34Pu VOLdc=0.2xVDDQ 0.9 1 1.45 RZQ/7 1,2,3

VOMdc=0.5xVDDQ

0.9

1.15

RZQ/7

1,2,3

VOHdc=0.8xVDDQ 0.6 1 1.15 RZQ/7 1,2,3

40 ohms RON40Pd VOLdc=0.2xVDDQ 0.6 1 1.15 RZQ/6 1,2,3

VOMdc=0.5xVDDQ 0.9 1 1.15 RZQ/6 1,2,3

VOHdc =0. 8xVDDQ 0.9 1 1.45 RZQ/6 1,2,3

40 ohms RON40Pu VOLdc=0.2xVDDQ 0.9 1 1.45 RZQ/6 1,2,3

VDDQ

VSSQ

To other circuitry

RONPu

RONPd

IPd

Output

Driver

Chip in Drive Mode

Iout

Vout

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VOMdc=0.5xVDDQ 0.9 1 1.1 RZQ/6 1,2,3

VOHdc=0.8xVDDQ 0.6 1 1.1 RZQ/6 1,2,3

Mismatch betw een pull-up and pull-down, MMPuPd VOMdc= 0.5xVDDQ -10 +10 % 1,2,4

Notes:

1. The tolerance limits are spec i fied aft er cali brat i on with stable volt age and temperature. F or the behavior of the tolerance limits if t emperature or

voltage changes after calibration, see following section on voltage and temperature sensitivity.

2. The tolerance limits are spec i fied under the condit i on that VDDQ=VDD and that VSSQ=VSS.

3. Pull-down and pull-up output dri ver impedanc es are recommended to be calibrated at 0. 5xVDDQ. Other calibration schemes may be used to

achieve the linearit y spec shown above, e.g. calibration at 0. 2 * VDDQ and 0.8 x VDDQ.

4. Measurem ent def i niti on for mismatch between pull -up and pull-down, MMPuPd:

Measure RONPu and RONPd, both at 0.5 x VDDQ:

MMPuPd = [RONPu - RONPd] / RONNom x 100

5.7.2 Output Driver Temperature and Voltage sensitivity

If temperature and/or voltage after calibration, the tolerance limits widen according to the following table below.

Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@c alibr ati on); VDD = VD DQ

5.7.2.1 Output Driver Sensitivity Definition

Items Min. Max. Unit

RONPU@VOHdc 0.6 - dRONdTH*lDelta Tl - dRONdVH*l Delta Vl 1.1 + dRONdTH*lDelta Tl - dRONdVH*lDelta Vl RZQ/7

RON@VOMdc 0.9 - d RONd TM*lDelta Tl - dRONdVM*lDelta Vl 1.1 + dRONdTM*lDelta Tl - dRONd VM*lDelta Vl RZQ/7

RONPD@VOLdc 0.6 - dRONdTL*lDelta Tl - dRONdVL*lDelta Vl 1.1 + dRONdTL*lD elta Tl - dRONdVL*lDelta Vl RZQ/7

Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization.

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5.7.2.2 Output Driver Voltage and Temperature Sensitivity

Speed Bin

DDR3-800/1066/1333

DDR3-1600

Unit

Items

Min.

Max

Min.

Max

dRONdTM

1.5

%/°C

dRONdVM

0.15

0.13

%/mV

dRONdTL

1.5

%/°C

dRONdVL

0.15

0.13

%/mV

dRONdTH

1.5

%/°C

dRONdVH

0.15

0.13

%/mV

Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization.

5.8 On-Die Termination (OD T) Levels and I-V Characteri stics

5.8.1 On-Die Termination (ODT) Level s and I-V Characteristics

On-Die Termination effective resistance RTT is defined by bits A9, A6, and A2 of the MR1 Register.

ODT is applied to the DQ, DM, DQS/DQS, and TDQS/TDQS (x8 devices only) pins.

A functional representation of the on-die termination is shown in the following figure. The individual pull-up and pull-down

resistors (RTTPu and RTTPd) are defined as follows:

RTTPu = [VDDQ - Vout] / | Iout | ------------------ under the condition that RTTPd is turned off (3)

RTTPd = Vout / | Iout | ------------------------------ under the condition that RTTPu is turned off (4)

Figure 5.8.1 On-Die Termination : Definition of Voltages and Currents

5.8.2 ODT DC Electrical Characteristics

The following table provides an overview of the ODT DC electrical characteristics. The values for RTT60Pd120,

RTT60Pu120, RTT120Pd240, RTT120Pu240, RTT40Pd80, RTT40Pu80, RTT30Pd60, RTT30Pu60, RTT20Pd40,

RTT20Pu40 are not specification requirements, but can be used as design guide lines:

VDDQ

VSSQ

To other circuitry

RTTPu

RTTPd

IPu

IPd

ODT

Chip in Termination Mode

Iout

Vout

Iout = Ipd -Ipu

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ODT DC Electrical Characteristics

(assuming RZQ = 240ohms +/- 1% entire operating temperature range; after proper ZQ calibration)

MR1 A9, A6, A2 RTT Resistor Vout Min Nom Max Unit Notes

0,1,0 120Ω

RTT120Pd240 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ 1,2,3,4

0.5 x VDDQ 0.9 1 1.1 RZQ 1,2,3,4

VOHdc = 0. 8 x VDDQ 0.9 1 1.4 RZQ 1,2,3,4

RTT120Pu240 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ 1,2,3,4

0.5 x VDDQ 0.9 1 1.1 RZQ 1,2,3,4

VOHdc = 0. 8 x VDDQ 0.9 1 1.4 RZQ 1,2,3,4

RTT120 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/2 1,2,5

0,0,1 60Ω

RTT60Pd120 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/2 1,2,3,4

0.5 x VDDQ 0.9 1 1.1 RZQ/2 1,2,3,4

VOHdc = 0. 8 x VDDQ 0.9 1 1.4 RZQ/2 1,2,3,4

RTT60Pu120 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/2 1,2,3,4

0.5 x VDDQ

0.9

1.1

RZQ/2

1,2,3,4

VOHdc = 0. 8 x VDDQ 0.9 1 1.4 RZQ/2 1,2,3,4

RTT60 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/4 1,2,5

0,1,1 40Ω

RTT40Pd80 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/3 1,2,3,4

0.5 x VDDQ 0.9 1 1.1 RZQ/3 1,2,3,4

VOHdc = 0. 8 x VDDQ 0.9 1 1.4 RZQ/3 1,2,3,4

RTT40Pu80 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/3 1,2,3,4

0.5 x VDDQ 0.9 1 1.1 RZQ/3 1,2,3,4

VOHdc = 0. 8 x VDDQ 0.9 1 1.4 RZQ/3 1,2,3,4

RTT40 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/6 1,2,5

1,0,1 30Ω

RTT30Pd60 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/4 1,2,3,4

0.5 x VDDQ 0.9 1 1.1 RZQ/4 1,2,3,4

VOHdc = 0. 8 x VDDQ 0.9 1 1.4 RZQ/4 1,2,3,4

RTT30Pu60 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/4 1,2,3,4

0.5 x VDDQ

0.9

1.1

RZQ/4

1,2,3,4

VOHdc = 0. 8 x VDDQ 0.9 1 1.4 RZQ/4 1,2,3,4

RTT30

VIL(ac) to VIH(ac)

0.9

1.6

RZQ/8

1,2,5

1,0,0 20Ω

RTT20Pd40 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/6 1,2,3,4

0.5 x VDDQ 0.9 1 1.1 RZQ/6 1,2,3,4

VOHdc = 0. 8 x VDDQ 0.9 1 1.4 RZQ/6 1,2,3,4

RTT20Pu40 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/6 1,2,3,4

0.5 x VDDQ 0.9 1 1.1 RZQ/6 1,2,3,4

VOHdc = 0. 8 x VDDQ 0.9 1 1.4 RZQ/6 1,2,3,4

RTT20 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/12 1,2,5

Notes:

1. The tolerance limits are spec i fied aft er cali bration with st abl e voltage and temperature. For the behavior of the tolerance limits if temperature or

voltage changes after calibration, see following section on voltage and temperature sensitivity.

2. The tolerance limits are spec i fied under the c onditi on that VDDQ = VDD and that VSSQ = VSS.

3. Pull-down and pull-up ODT resistors are rec ommended to be calibrated at 0.5 x VDDQ. Other cal i bration schemes may be used t o achieve the

linearity s pec shown above.

4. Not a specificat i on requirement , but a design guide line.

5. Measurem ent def i niti on for RTT:

Apply VIH(ac) to pin under test and measure current I(VIH(ac )), then apply VIL(ac ) to pin under test and measure current I(VIL(ac)) respectively.

RTT = [VIH(ac) - VIL(ac)] / [I(VIH(ac)) - I(VIL(ac))]

6. Measurem ent def i niti on for VM and DVM:

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Measure voltage (VM) at test pin (mi dpoi nt) wit h no load:

Delta VM = [2VM / VDDQ -1] x 100

5.8.3 ODT Temperature and Voltag e sensitivity

If temperature and/or voltage after calibration, the tolerance limits widen according to the following table.

Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibr ati on); VDD = VD DQ

5.8.3.1 ODT Sensitivity Definition

min

max

Unit

RTT

0.9 - dRTTdT*lDelta Tl - dRTTdV*lDelta Vl

1.6 + dRTTdT*lDelta Tl + dRTTdV*lDelta Vl

RZQ/2,4,6,8,12

5.8.3.2 ODT Voltage and Temperature Sensitivity

Min

Max

Unit

dRTTdT

1.5

%/°C

dRTTdV

0.15

%/mV

Note: These parameters may not be subject to producti on test. They are verified by design and characterization

5.9 ODT Timing D efinitions

5.9.1 Test Load for ODT Timings

Different than for timing measurements, the reference load for ODT timings is defined in the following figure.

Figure 5.9.1 ODT Timing Reference Load

5.9.2 ODT Timing Defin itions

Definitions for tAON, tAONPD, tAOF, tAOFPD, and tADC are provided in the following table and subsequent figures.

Symbol

Begin Point Definition

End Point Definition

tAON Rising edge of CK - CK defined by the end point of ODTLon Extrapolated point at VSSQ

AONPD

Rising edge of CK - CK with ODT being first registered high Extrapolated point at VSSQ

tAOF Rising edge of CK - CK defined by the end point of ODTLoff End point: Extrapolated point at VRTT_Nom

AOFPD

Rising edge of CK - CK with ODT being first registered low End point: Extrapolated point at V

RTT_Nom

tADC

Rising edge of CK - CK defined by the end point of ODTLcnw,

ODTLcwn4, or ODTLcwn8

End point: Extrapolated point at V

RTT_Wr

and

VRTT_Nom respectively

Reference Settings for ODT Timing Measurements

Measured Parameter

RTT_Nom Setting

RTT_Wr Setting

VSW1[V]

VSW2[V]

tAON

RZQ/4

0.05

0.10

RZQ/12

0.10

0.20

tAONPD

RZQ/4

0.05

0.10

RZQ/12

0.10

0.20

tAOFPD

RZQ/4

0.05

0.10

CK,CK#

DUT

DQ,DM

DQS,

DQS#,

TDQS,

TDQS#

25ohm

VTT=VSSQ

Timing Re ference Point

VDDQ

VSSQ

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RZQ/12

0.10

0.20

tADC

RZQ/12

RZQ/2

0.20

0.30

Figure 5.9.2.1 Definition of tAON

Figure 5.9.2.2 Definiti o n of tAONPD

Begin Point : Rising edge of CK-CK# with

ODT being first register high

End Point : Extrapolated point at VSSQ

CK#

VTT

Vsw2

DQ,DM,DQS,

DQS#,TDQS,

TDQS#

VSSQ

AONPD

Vsw1

Tsw1

Tsw2

Begin Point : Rising edge of CK-CK#

defined by the end of ODTLon

End Point : Extrapolated point at VSSQ

CK#

VTT

Vsw2

DQ,DM,DQS,

DQS#,TDQS,

TDQS#

VSSQ

AON

Vsw1

Tsw1

Tsw2

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Figure 5.9.2.3 Definition of tAOF

Figure 5.9.2.4 Definiti o n of tAOFPD

Begin Point : Rising edge of CK-CK# with

defined by the end point of ODTLoff

End Point : Extrapolated point at V

RTT_NOM

CK#

VTT

Vsw2

DQ,DM,DQS,

DQS#,TDQS,

TDQS#

VSSQ

AOF

Vsw1

Tsw1

Tsw2

VRTT NOM

Begin Point : Rising edge of CK-CK# with

ODT being first registered low

End Point : Extrapolated point at V

RTT_NOM

CK#

VTT

Vsw2

DQ,DM,DQS,

DQS#,TDQS,

TDQS#

VSSQ

tAOFPD

Vsw1

Tsw1

Tsw2

VRTT NOM

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Figure 5.9.2.5 Definiti o n of tADC

Begin Point : Rising edge of CK-CK#

defined by the end point of ODTLcn w

Begin Point : Rising edge of CK-CK# defined by

the end point of ODTLcwn4 or ODTLcwn8

tADC tADC

End Point : Extrapolated point at V

RTT_Wr

End Point : Extrapolated

point at VRTT_NOM

DQ,DM,DQS,

DQS#,TDQS,

TDQS#

CK#

VTT

VSSQ

RTT_NOM

Tsw11

Tsw21

Tsw22

Tsw12

Vsw2

Vsw1

VRTT_Wr

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6. INPUT / OUTP UT CAPACITANCE

Symbol Parameter

DDR3/DDR3

L-800

DDR3/DDR3

L -1066

DDR3/DDR3

L -1333

DDR3/DDR

3L -1600

Units Notes

Min Max Min Max Min Max Min

CIO Input/output capacitance (DQ,

DM, DQS,DQS#,TDQS,TDS#)

DDR3 1.5 3 1.5 3 1.5 2.5 1.5 2.3 pF 1,2,3

DDR3L 1.5 2.5 1.5 2.5 1.5 2.3 1.5 2.3

CCK Input capacitan ce, CK and CK# 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 pF 2,3

CDCK Input capacitance delta, CK and CK# 0 0.2 0 0.2 0 0.2 0 0.2 pF 2,3,4

CDDQS Input/output capacitance delta, DQS and

DQS#

0 0.2 0 0.2 0 0.2 0 0.2 pF 2,3,5

CI Input capacit an ce, CTR L,

ADD, command input-only

pins

DDR3 0.75 1.35 0.75 1.35 0.75 1.3 0.75 1.3 pF 2,3,7,8

DDR3L 0.75 1.3 0.7 1.3 0.75 1.3 0.75 1.3

CDI_CTRL

Input capacitance delta, all CTRL input-

only pins

-0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 pF 2,3,7,8

DI_ADD_

CMD

Input capacitance delta, all ADD/CMD

input-only pins

-0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 pF

2,3,9,1

CDIO Input/output capacitance delta, DQ, DM,

DQS, DQS# TDQS,TDQS# TDQS -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11

CZQ Input/output capacitance of ZQ pin - 3 - 3 - 3 - 3 pF 2,3,12

Notes:

1. Alt hough the DM, TDQS and TDQS# pins have different functions, the loading m atc hes DQ and DQS

2. This paramet er is not subject to producti on test. It is verifi ed by design and charact erizat i on. V DD=VDDQ=1.5V, VBIAS=VDD/2 and on-die

terminat i on off.

3. This paramet er appl i es to monolithic devices only; stacked/ dual-die devices are not covered here

4. Absol ute value of CCK-CCK#

5. Absol ute value of CIO(DQS)-CIO(DQS#)

6. CI applies to ODT, CS#, CKE, A0-A13, BA0-BA2, RAS#,CAS#,WE#.

7. CDI_CTRL applies to ODT, CS# and CKE

8. CDI_CTRL=CI(CTRL)-0.5*(CI(CK)+CI(CK#))

9. CDI_ADD_CMD applies to A0-A13, BA0-BA2, RAS#, CAS# and WE#

10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CK)+CI(CK#))

11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS#))

12. Maximum external load c apacitance on ZQ pi n: 5 pF.

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7. IDD SPECI F ICATIONS AND MEASUREMENT CONDITIONS

IDD Specifications (x8), 1.5 Operation Voltage

Symbol Parameter/Condition

DDR3-1066

DDR3-1333

DDR3-1600

DDR3-1866

Unit

Max.

Typ.

IDD0

Operating Current 0

-> One Bank Activate-> Precharge

IDD1

Operating Current 1

-> One Bank Activate-> Read->

Precharge

IDD2P0

Precharge Power-Down Current

Slow Exit - MR0 bit A12 = 0

IDD2P1

Precharge Power-Down Current

Fast Exit - MR0 bit A12 = 1

IDD2PQ

Precharge Quiet Standby Current

IDD2N

Precharge Standby Current

IDD3P

Active Power-Down Current

Always Fast Exit

IDD3N

Active Standby Current

IDD4R

Operating Current B urst Read

106

122

139

159

IDD4W

Operating Current B urst Write

104

119

134

150

IDD5B

Burst Refresh Current

IDD6

Self-Refresh Current Norm al

Temperature Range (0-85°C)

IDD6ET

Self-Refresh Current : extended

temperature range

IDD6TC

Auto Self-Refresh Current

IDD7

All Bank Interleave Read Current

184

220

227

375

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IDD Specifications (x16), 1.5 Operation Voltage

Symbol Parameter/Condition

DDR3-1066

DDR3-1333

DDR3-1600

DDR3-1866

Unit

Max.

Typ.

IDD0

Operating Current 0

-> One Bank Activate-> Precharge

IDD1

Operating Current 1

-> One Bank Activate-> Read->

Precharge

106

112

119

120

IDD2P0

Precharge Power-Down Current

Slow E xit - MR0 bit A12 = 0

IDD2P1

Precharge Power-Down Current

Fast Exit - MR0 bit A12 = 1

IDD2PQ

Precharge Quiet Standby Current

IDD2N

Precharge Standby Current

IDD3P

Active Power-Down Current

Always Fast Exit

IDD3N

Active Standby Current

IDD4R

Operating Current B urst Read

165

195

224

IDD4W

Operating Current B urst Write

162

189

216

218

IDD5B

Burst Refresh Current

IDD6

Self-Refresh Current Normal

Temperature Range (0-85°C)

IDD6ET

Self-Refresh Current: extended

temperature range

IDD6TC

Auto Self-Refresh Current

IDD7

All Bank Interleave Read Current

266

297

332

403

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IDD Specifications (x8), 1.35 Operation Voltage

Symbol Parameter/Condition

DDR3-1066

DDR3-1333

DDR3-1600

Unit

Max.

Typ.

IDD0

Operating Current 0

-> One Bank Activate->

Precharge

TBD

IDD1

Operating Current 1

-> One Bank Activate-> Read->

Precharge

TBD

IDD2P0

Precharge Power-Down Current

Slow Exit - MR0 bit A12 = 0

TBD

IDD2P1

Precharge Power-Down Current

Fast Exit - MR0 bit A12 = 1

TBD

IDD2PQ

Precharge Quiet Standby

Current

TBD

IDD2N

Precharge Standby Current

TBD

IDD3P

Active Power-Down Current

Always Fast Exit

TBD

IDD3N

Active Standby Current

TBD

IDD4R

Operating Current B urst Read

TBD

IDD4W

Operating Current B urst Write

TBD

IDD5B

Burst Refresh Current

TBD

IDD6

Self-Refresh Current Norm al

Temperature Range (0-85°C)

TBD

IDD6ET

Self-Refresh Current: extended

temperature range

TBD

IDD6TC

Auto Self-Refresh Current

TBD

IDD7

All Bank Interleave Read Current

TBD

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IDD Specifications (x16), 1.35 Operation Voltage

Symbol Parameter/Condition

DDR3-1066

DDR3-1333

DDR3-1600

Unit

Max.

Typ.

IDD0

Operating Current 0

-> One Bank Activate-> Precharge

IDD1

Operating Current 1

-> One Bank Activate-> Read->

Precharge

100

106

IDD2P0

Precharge Power-Down Current

Slow Exit - MR0 bit A12 = 0

IDD2P1

Precharge Power-Down Current

Fast Exit - MR0 bit A12 = 1

IDD2PQ

Precharge Quiet Standby Current

IDD2N

Precharge Standby Current

IDD3P

Active Power-Down Current

Always Fast Exit

IDD3N

Active Standby Current

IDD4R

Operating Current B urst Read

133

158

182

IDD4W

Operating Current B urst Write

129

154

176

IDD5B

Burst Refre s h Current

IDD6

Self-Refresh Current Norm al

Temperature Range (0-85°C)

IDD6ET

Self-Refresh Current: extended

temperature range

IDD6TC

Auto Self-Refresh Current

IDD7

All Bank Interleave Read Current

230

267

298

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8. ELEC TRICAL CHARACTE RISTICS AND AC TIMING FOR DDR3-800 TO DDR3 -1600

8.1 Clock Speci fi cat ion

The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result

in malfunction of the DDR3 SDRAM device.

8.1.1 Definition for tCK(avg)

tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is

calculated from rising edge to rising edge.

Where N=200

8.1.2 Definition for tCK(abs)

tCK(abs) is defind as the absolute clock period, as measured from one rising edge to the next consecutive rising edge.

tCK(abs) is not subject to production test.

8.1.3 Definition for tCH(avg) and tCL(avg)

tCH(avg) is defined as the average high pulse wid th, as calculated acr oss any consec uti ve 200 high puls es:

Where N=200

tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses:

Where N=200

8.1.4 Definition for note for tJIT(per), tJIT(per, Ick)

tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg).

tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200}

tJIT(per) defines the single period jitter when the DLL is already locked.

tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.

tJIT(per) and tJIT(per,lck) are not subject to production test.

8.1.5 Definition for tJIT(cc), tJIT(cc , Ick)

tCK(avg) = ( tCKj ) / N

tCH(avg) = ( tCHj ) / (N x tCK(avg)

tCL(avg) = ( tCLj ) / (N x tCK(avg)

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tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of

{tCKi+1-tCKi}

tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.

tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.

tJIT(cc) and tJIT(cc,lck) are not subject to production test.

8.1.6 Definition for tERR(nper)

tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to

production test.

8.2 Refresh Parameters

Refresh parameters(1)

Parameter Symbol Units

All Bank Refresh to active/refresh cmd time tRFC 110 ns

Average periodic refresh interval tREFI -40°C < TCASE < 85°C 7.8 µs

85°C < TCASE < 105°C

3.9

µs

Notes:

1. The permiss i ble Tcase operating temperature is s pecified by temperature grade. The maximum Tcase is 95 C unless A2 grade, for which the

maximum is 105 C.

8.3 Spee d Bins and CL, tRCD, tRP, tRC and tRAS for corr esponding Bin

DDR3-1066MT/s

Speed Bin

DDR3/DDR3L-1066

Unit

CL-nRCD-nRP

7-7-7 (-187F)

Parameter

Symbol

Min

Max

Internal read com man d to first dat a

tAA

13.125

20.000

ACT to internal read or write delay time

tRCD

13.125

PRE command period

tRP

13.125

ACT to ACT or REF command period

tRC

50.625

ACT to PRE command period

tRAS

37.500

9*tREFI

CL=5

CWL =5

tCK(AVG)

3.000

3.300

CWL=6

tCK(AVG)

Reserved

CL=6

CWL =5

tCK(AVG)

2.500

3.300

CWL=6

tCK(AVG)

Reserved

CL=7

CWL =5

tCK(AVG)

Reserved

CWL=6

tCK(AVG)

1.875

<2.5

CL=8

CWL =5

tCK(AVG)

Reserved

CWL=6

tCK(AVG)

1.875

<2.5

Supported CL Settings

5,6,7,8

nCK

Supported CWL Settings

5,6

nCK

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DDR3-1333MT/s Speed Bin DDR3/DDR3L-1333 Unit

CL-nRCD-nRP

9-9-9 (-15H)

Parameter

Symbol

Min

Max

Internal read com man d to first dat a tAA 13.125 20 ns

ACT to internal read or write delay tRCD 13.125 - ns

PRE command period tRP 13.125 - ns

ACT to ACT or REF period tRC 49.125 - ns

ACT to PRE command period tRAS 36.0 9*tREFI ns

CL=5

CWL =5

tCK(AVG)

3.0

3.3

CWL=6 tCK(AVG) Reserved ns

CWL=7 tCK(AVG) Reserved ns

CL=6 CWL =5 tCK(AVG) 2.5 3.3 ns

CWL=6 tCK(AVG) Reserved ns

CWL=7 tCK(AVG) Reserved ns

CL=7

CWL =5

tCK(AVG)

Reserved

CWL=6

tCK(AVG)

1.875

<2.5

CWL=7 tCK(AVG) Reserved ns

CL=8 CWL =5 tCK(AVG) Reserved ns

CWL=6 tCK(AVG) 1.875 <2.5 ns

CWL=7 tCK(AVG) Reserved ns

CL=9 CWL=5 tCK(AVG) Reserved ns

CWL=6

tCK(AVG)

Reserved

CWL=7

tCK(AVG)

1.5

<1.875

CL=10 CWL =5 tCK(AVG) Reserved ns

CWL=6 tCK(AVG) Reserved ns

CWL=7 tCK(AVG) 1.5 <1.875 ns

Supported CL Settings 5,6,7,8,9,10 nCK

Supported CWL Settings

5,6,7

nCK

Note : *: Opti onal

DDR3-1333MT/s Speed Bin DDR3/DDR3L-1333 Unit

CL-nRCD-nRP 8-8-8 (-15G)

Parameter Symbol Min Max

Internal read com man d to first dat a tAA 12.0 20 ns

ACT to internal read or write delay tRCD 12.0 - ns

PRE command period

tRP

12.0

ACT to ACT or REF period

tRC

48.0

ACT to PRE command period tRAS 36.0 9*tREFI ns

CL=5 CWL =5 tCK(AVG) 2.5 3.3 ns

CWL=6 tCK(AVG) Reserved ns

CWL=7 tCK(AVG) Reserved ns

CL=6 CWL =5 tCK(AVG) 2.5 3.3 ns

CWL=6

tCK(AVG)

Reserved

CWL=7 tCK(AVG) Reserved ns

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CL=7 CWL =5 tCK(AVG) Reserved ns

CWL=6

tCK(AVG)

1.875

<2.5

CWL=7

tCK(AVG)

Reserved

CL=8 CWL =5 tCK(AVG) Reserved ns

CWL=6 tCK(AVG) 1.875 <2.5 ns

CWL=7 tCK(AVG) 1.5 1.875 ns

CL=9 CWL=5 tCK(AVG) Reserved ns

CWL=6 tCK(AVG) Reserved ns

CWL=7

tCK(AVG)

1.5

<1.875

CL=10 CWL =5 tCK(AVG) Reserved ns

CWL=6 tCK(AVG) Reserved ns

CWL=7 tCK(AVG) 1.5 <1.875 ns

Supported CL Settings 5,6,7,8,9,10 nCK

Supported CWL Settings 5,6,7 nCK

Note : *: Opti onal

DDR3-1600MT/s

Speed Bin

DDR3/DDR3L-1600

Unit CL-nRCD-nRP 10-10-10 (-125J)

Parameter Symbol Min Max

Internal read com man d to first dat a tAA 12.5 20 ns

ACT to internal read or write delay tRCD 12.5 - ns

PRE command period tRP 12.5 - ns

ACT to ACT or REF period

tRC

47.5

ACT to PRE command period

tRAS

9*tREFI

CL=5

CWL =5 tCK(AVG) 2.5 3.3 ns

CWL=6 tCK(AVG) Reserved ns

CWL=7 tCK(AVG) Reserved ns

CWL=8 tCK(AVG) Reserved ns

CL=6

CWL =5

tCK(AVG)

2.5

3.3

CWL=6

tCK(AVG)

Reserved

CWL=7

tCK(AVG)

Reserved

CWL=8 tCK(AVG) Reserved ns

CL=7

CWL =5 tCK(AVG) Reserved ns

CWL=6 tCK(AVG) 1.875 <2.5 ns

CWL=7 tCK(AVG) Reserved ns

CWL=8

tCK(AVG)

Reserved

CL=8

CWL =5

tCK(AVG)

Reserved

CWL=6 tCK(AVG) 1.875 <2.5 ns

CWL=7 tCK(AVG) Reserved ns

CWL=8 tCK(AVG) Reserved ns

CL=9

CWL =5 tCK(AVG) Reserved ns

CWL=6 tCK(AVG) Reserved ns

CWL=7

tCK(AVG)

1.5

<1.875

CWL=8

tCK(AVG)

Reserved

CL=10

CWL =5 tCK(AVG) Reserved ns

CWL=6 tCK(AVG) Reserved ns

CWL=7 tCK(AVG) 1.5 <1.875 ns

CWL =8 tCK(AVG) 1.25 <1.5 ns

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CL=11

CWL =5 tCK(AVG) Reserved ns

CWL= 6

tCK(AVG)

Reserved

CWL= 7

tCK(AVG)

Reserved

CWL =8 tCK(AVG) 1.25 <1.5 ns

Supported CL Settings 5,6,7,8,9,10,11 nCK

Supported CWL Settings 5,6,7,8 nCK

Note : *: Opti onal

DDR3-1866MT/s Speed Bin DDR3/DDR3L-1866 Unit

CL-nRCD-nRP 12-12-12 (-107L)

Parameter Symbol Min Max

Internal read com man d to first dat a tAA 12.84 20 ns

ACT to internal read or write delay

tRCD

12.84

PRE command period

tRP

12.84

ACT to ACT or REF period tRC 46.84 - ns

ACT to PRE command period tRAS 34 9*tREFI ns

CL=5

CWL =5 tCK(AVG) Reserved ns

CWL=6 tCK(AVG) Reserved ns

CWL=7 tCK(AVG) Reserved ns

CWL=8

tCK(AVG)

Reserved

CL=6

CWL =5

tCK(AVG)

2.5

3.3

CWL=6 tCK(AVG) Reserved ns

CWL=7 tCK(AVG) Reserved ns

CWL=8 tCK(AVG) Reserved ns

CL=7

CWL =5 tCK(AVG) Reserved ns

CWL=6

tCK(AVG)

Reserved

CWL=7

tCK(AVG)

Reserved

CWL=8

tCK(AVG)

Reserved

CL=8

CWL =5 tCK(AVG) Reserved ns

CWL=6 tCK(AVG) 1.875 <2.5 ns

CWL=7 tCK(AVG) Reserved ns

CWL=8 tCK(AVG) Reserved ns

CL=9

CWL =5

tCK(AVG)

Reserved

CWL=6

tCK(AVG)

Reserved

CWL=7 tCK(AVG) Reserved ns

CWL=8 tCK(AVG) Reserved ns

CL=10

CWL =5 tCK(AVG) Reserved ns

CWL=6 tCK(AVG) Reserved ns

CWL=7

tCK(AVG)

1.5

<1.875

CWL =8

tCK(AVG)

Reserved

CL=11

CWL

=5,6,7,8

tCK(AVG) Reserved ns

CL=12,13

CWL=5,6,

7,8

tCK(AVG) Reserved ns

CWL =9 tCK(AVG) 1.07 <1.25 ns

Supported CL Settings

5,6,7,8,9,10,11,12,13

nCK

Supported CWL Settings

5,6,7,8,9

nCK

Note :In these tables in secti on 8.3, grey shading is for readabilit y purposes only.

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9 . ELECTRICAL CHARACTERISTICS & AC TIMING

9.1 Timing Parameter by Speed Bin (DDR3-800, DDR3-1066)

Parameter Symbol

DDR3/DDR3L-800

DDR3/DDR3L-1066

Units

Notes

Min.

Max.

Min.

Max.

Clock Timing

Minimum Clock Cycle Time (DLL off mode) tCK(DLL_OFF) 8 - 8 - ns 6

Average Clock Period tCK(avg) Refer to Standard Speed Bins ps

Average high pulse width

tCH(avg)

0.47

0.53

0.47

0.53

tCK(avg)

Average low pulse width

tCL(avg)

0.47

0.53

0.47

0.53

tCK(avg)

Absolute Clock Period tCK(abs)

Min.: tCK(avg)min + tJIT(per)min

Max.: tCK(avg)max + tJIT(per)max

Absolute clock HIGH pulse width tCH(abs) 0.43 - 0.43 - tCK(avg) 25

Absolute clock LOW puls e width

tCL(abs)

0.43

tCK(avg)

Clock Period Jitter

JIT(per)

-100

100

-90

Clock Period Jitter during DLL locking period

JIT(per, lck)

-90

-80

Cycle to Cycle Period Jitter tJIT(cc) 200 200 180 180 ps

Cycle to Cycle Period Jitter during DLL locking

period

JIT( cc, lck) 180 180 160 160 ps

Duty Cycle Jitter

tJIT(duty)

Cumulative error across 2 cycles

tERR(2per)

-147

147

-132

132

Cumulative error across 3 cycles

tERR(3per)

-175

175

-157

157

Cumulative error across 4 cycles

tERR(4per)

-194

194

-175

175

Cumulative error across 5 cycles tERR(5per) -209 209 -188 188 ps

Cumulative error across 6 cy cl e s

tERR(6per)

-222

222

-200

200

Cumulative error across 7 cycles

tERR(7per)

-232

232

-209

209

Cumulative error across 8 cycles

tERR(8per)

-241

241

-217

217

Cumulative error across 9 cycles tERR(9per) -249 249 -224 224 ps

Cumulative error across 10 cycles tERR(10per) -257 257 -231 231 ps

Cumulative error across 11 cycles

tERR(11per)

-263

263

-237

237

Parameter Symbol

DDR3/DDR3L-800

DDR3/DDR3L-1066

Units

Notes

Min.

Max.

Min.

Max.

Cumulative error across 12 cycles tERR(12per) -269 269 -242 242 ps

Cumulative error across n = 13, 14 . . . 49, 50

cycles tERR(nper) tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min ps 24

tERR(nper)max = (1 + 0.68ln(n)) *

tJIT(per)max

Data Timing

DQS, DQS# to DQ skew, per group, per

access

tDQSQ - 200 - 150 ps 13

DQ output hold time from DQS, DQS#

tQH

0.38

tCK(avg)

13,g

DQ low-impedance time from CK, CK# tLZ(DQ) -800 400 -600 300 ps 13,14,f

DQ high impedance time from CK, CK#

tHZ(DQ)

400

300

13,14,f

Data setup time to DQS, DQS# referenced to

Vih(ac) / Vil(ac) levels

tDS(base)

AC175

See table for Data Setup and Hold

ps d,17

Data setup time to DQS, DQS# referenced to

Vih(ac) / Vil(ac) levels

tDS(base)

AC150

ps d,17

Data hold time from DQS, DQS# referenced

to Vih(dc) / Vil(dc) levels

tDH(base)

DC100

ps d,17

DQ and DM Input pulse width for each input tDIPW 600 - 490 - ps 28

Data Strobe Timing

DQS,DQS# differential READ Preamble

tRPRE

0.9

Note

0.9

Note

13,19,g

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DQS, DQS# differential READ Postamble

tRPST

0.3

Note

0.3

Note

11,13,g

DQS, DQS# differential output high time tQSH 0.38 - 0.38 - tCK(avg) 13,g

DQS, DQS# differential output low time tQSL 0.38 - 0.38 - tCK(avg) 13,g

DQS, DQS# differential WRITE Preamble

tWPRE

0.9

tCK(avg)

DQS, DQS# differential WR ITE Postamble

tWPST

0.3

tCK(avg)

DQS, DQS# rising edge output access time

from rising CK, CK#

tDQSCK -400 400 -300 300 tCK(avg) 13,f

DQS and DQS# low-impedance time

(Referenced from RL - 1)

tLZ(DQS) -800 400 -600 300 tCK(avg) 13,14,f

DQS and DQS# high-impedance time

(Referenced from RL + BL/2)

tHZ(DQS) - 400 - 300 tCK(avg) 13,14,f

DQS, DQS# differential input low pulse width

tDQSL

0.45

0.55

0.45

0.55

tCK(avg)

29,31

DQS, DQS# differential input high pulse width

tDQSH

0.45

0.55

0.45

0.55

tCK(avg)

30,31

DQS, DQS# rising edge to CK, CK# rising

edge

tDQSS -0.25 0.25 -0.25 0.25 tCK(avg) c

DQS, DQS# falling edge setup time to CK,

CK# rising edge

tDSS 0.2 - 0.2 - tCK(avg) c,32

DQS, DQS# falling edge hold time from CK,

CK# rising edge

tDSH 0.2 - 0.2 - tCK(avg) c,32

Command and Address Timing

DLL locking time

tDLLK

512

nCK

Intern al RE A D Command to PRECHARGE

Command delay tRTP

tRTPmin.: max(4nCK, 7.5ns)

tRTPmax.: -

Delay from start of internal write transaction to

internal read com mand tWTR tWTRmin.: max (4nC K, 7.5ns) e,18

tWTRmax.:

WRITE recovery time

tWR

e,18

Mode Register Set command cycle time

tMRD

nCK

Mode Register Set command update delay tMOD tMODmin.: max(12nCK, 15ns)

tMODmax.:

ACT to internal read or write delay time

tRCD

Standard Speed Bins

PRE command period

tRP

Standard Speed Bins

ACT to ACT or REF command period

tRC

Standard Speed Bins

CAS# to CAS# command delay tCCD 4 - 4 - nCK

Parameter Symbol

DDR3/DDR3L-800

DDR3/DDR3L-1066

Units

Notes

Min.

Max.

Min.

Max.

Auto precharge write recovery + precharge

time

tDAL(min) WR + roundup(tRP / tCK(avg)) nCK

Multi-Purpose Register Recovery Time tMPRR 1 - 1 - nCK 22

ACTIVE to PRECHARGE command period tRAS Standard Speed Bins

ACTIVE to ACTIVE command period for 1KB

page size

tRRD

max(4nCK,

10ns)

max(4nCK,

7.5ns)

ACTIVE to ACTIVE command period for 2KB

page size tRRD

tRRDmin.: max(4nCK, 10ns)

tRRDmax.:

Four activate window for 1KB page size tFAW 40 - 37.5 - ns e

Four activate window for 2KB page size

tFAW

Command and Addre ss setu p time to CK,

CK# referenced to Vih(ac) / Vil(ac) levels

tIS(base)

See table for ADD/CMD setup and hold

ps b,16

Command and Address hold time from CK,

CK# referenced to Vih(dc) / Vil(dc) levels

tIH(base) ps b,16,27

Command and Addre ss setu p time to CK,

CK# referenced to Vih(ac) / Vil(ac) levels

tIS(base)

AC150

ps b,16

Control and Address Input pulse width for

each input

tIPW 900 - 780 - ps 28

Calibration Timing

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Power-up and RESET calibration time

tZQinit

512

nCK

Normal operatio n Fu ll calibr at i on time tZQoper 256 - 256 - nCK

Normal operation Short calibration time tZQCS 64 - 64 - nCK 23

Reset Timing

Exit Reset from CKE HIGH to a valid

command tXPR

tXPRmin.: max(5nCK, tRFC(min) + 10ns)

tXPRmax.: -

Self Refresh Timings

Exit Self Refresh to commands not requiring a

locked DLL tXS tXSmin.: max(5nCK, tRFC(min) + 10ns)

tXSmax.: -

Exit Self Refresh to commands requiring a

locked DLL tXSDLL

tXSDLLmin.: tDLLK(min)

nCK 2

tXSDLLmax.: -

Minimum CKE low width for Self Refresh entry

to exit timing tCKESR tCKESRmin.: tCKE(min) + 1 nCK

tCKESRmax.: -

Valid Clock Requirement after Self Refresh

Entry (SRE) or Power-Down Entry (PDE) tCKSRE

tCKSREmin.: max(5 nCK, 10 ns)

tCKSREmax.: -

Valid Clock Requirement before Self Refresh

Exit (SRX) or Power-Down Exit (PDX) or

Reset Exit

tCKSRX

tCKSRXmin.: max(5 nCK, 10 ns)

tCKSRXmax.: -

Power Down Timings

Exit Power Down with DLL on to any valid

command; Exit Precharge Power Down with

DLL frozen to commands not requiring a

locked DLL

tXP

tXPmin.: max(3nCK, 7.5ns)

tXPmax.: -

Exit Precharge Power Down with DLL frozen

to commands requiring a locked DLL tXPDLL

tXPD LLmin.: max(10nCK, 24ns)

tXPDLLmax.: -

CKE minimum pulse width tCKE

tCKEmin.: max(3nCK

7.5ns)

tCKEmin.: max(3nCK

5.625ns)

tCKEmax.: - tCKEmax.: -

Command pass disable delay tCPDED tCPDEDmin.: 1 nCK

tCPDEDmax.: -

Power Down Entry to Exit Timing tPD tPDmin.: tCKE(min) 15

tPDmax.: 9*tREFI

Parameter Symbol

DDR3/DDR3L-800

DDR3/DDR3L-1066

Units

Notes

Min.

Max.

Min.

Max.

Timing of ACT command to Power Down

entry tACTPDEN

tACTPDENmin.: 1

nCK 20

tACTPDENmax.: -

Timing of PRE or PREA command to Power

Down entry tPRPDEN tPRPDENmin.: 1 nCK 20

tPRPDENmax.: -

Parameter Symbol

DDR3-800

DDR3-1066

Units

Notes

Min.

Max.

Min.

Max.

Timing of RD/RDA command to Power Down

entry tRDPDEN tRDPDENmin.: RL+4+1 nCK

tRDPDENmax.: -

Timing of WR command to Power Down entry

(BL8OTF, BL8MRS, BC4OTF) tWRPDEN

tWRPDENmin.: WL + 4 + (tWR / tCK(avg))

nCK 9

tWRPDENmax.: -

Timing of WRA command to Power Down

entry (BL8OTF, BL8MRS, BC4OTF) tWRAPDEN

tWRAPDENmin.: WL+4+WR+1

nCK 10

tWRAPDENmax.: -

Timing of WR command to Power Down entry

(BC4MRS)

tWRPDEN

tWRPDENmin.: WL + 2 + (tWR / tCK(avg))

nCK 9

tWRPDENmax.: -

Timing of WRA command to Power Down

entry (BC4MRS) tWRAPDEN tWRAPDENmin .: WL + 2 +WR + 1 nCK 10

tWRAPDENmax.: -

Timing of REF command to Power Down

entry tREFPDEN

tREFPDENmin.: 1

nCK 20,21

tREFPDENmax.: -

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Timing of MRS command to Power Down

entry tMRSPDEN

tMRSPDENmin.: tMOD(min)

tMRSPDENmax.: -

ODT Ti m i n g s

ODT high time without write command or with

write command and BC4 ODTH4

ODTH4min.: 4

nCK

ODTH4max.: -

ODT high time with Write command and BL8 ODTH8

ODTH8min.: 6

nCK

ODTH8max.: -

Asynchronous RTT turn-on delay (Power-

Down with DLL frozen)

tAONPD 2 8.5 2 8.5 ns

Asynchronous RTT turn-off delay (Power-

Down with DLL frozen)

tAOFPD 2 8.5 2 8.5 ns

RTT turn-on

tAON

-400

400

-300

300

7,f

RTT_Nom and RTT_WR turn-off time from

ODTLoff reference

tAOF 0.3 0.7 0.3 0.7 tCK(avg) 8,f

RTT dynamic change sk ew tADC 0.3 0.7 0.3 0.7 tCK(avg) f

Write Leveling Timings

First DQS/DQS# rising edge after write

leveling mode is progr am med

tWLMRD 40 - 40 - nCK 3

DQS/DQS# delay after write leveling mode is

programmed

tWLDQSEN 25 - 25 - nCK 3

Write leveli ng setup time from rising CK, CK#

crossing to rising DQS, DQS# crossing

tWLS 325 - 245 - ps

Write leveling hold time from rising DQS,

DQS# crossing to rising CK, CK# crossing

tWLH 325 - 245 - ps

Write leveling output delay tWLO 0 9 0 9 ns

Write leveli ng output error

tWLOE

9.2.1 Timing Parameter by Speed Bin (DDR3-13 33, D DR3-1600)

Parameter Symbol

DDR3/DDR3L-1333

DDR3/DDR3L-1600

Units

Notes

Min.

Max.

Min.

Max.

Clock Timing

Minimum Clock Cycle Time (DLL off mode)

tCK(DLL_OFF)

Average Clock Period

tCK(avg)

Refer to Standard Speed Bins

Average high pulse width

tCH(avg)

0.47

0.53

0.47

0.53

tCK(avg)

Average low pulse width

tCL(avg)

0.47

0.53

0.47

0.53

tCK(avg)

Absolute Clock Period tCK(abs)

Min.: tCK(avg)min + tJIT(per)min

Max.: tCK(avg)max + tJIT(per)max

Absolute clock HIGH pulse width

tCH(abs)

0.43

tCK(avg)

Absolute clock LOW puls e width

tCL(abs)

0.43

tCK(avg)

Clock Period Jitter

JIT(per)

-80

-70

Clock Period Jitter during DLL locking period

JIT(per, lck)

-70

-60

Cycle to Cycle Period Jitter

tJIT(cc)

160

140

Cycle to Cycle Period Jitter during DLL

locking period

JIT( cc, lck) 140 140 120 120 ps

Duty Cycle Jitter

tJIT(duty)

Cumulative error across 2 cycles

tERR(2per)

-118

118

-103

103

Cumulative error across 3 cycles

tERR(3per)

-140

140

-122

122

Cumulative error across 4 cycles

tERR(4per)

-155

155

-136

136

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Integrated Silicon Solution, Inc. – www.issi.com – 61

Rev. 00B

12/5/2012

Cumulative error across 5 cycles

tERR(5per)

-168

168

-147

147

Cumulative error across 6 cycles

tERR(6per)

-177

177

-155

155

Cumulative error across 7 cycles

tERR(7per)

-186

186

-163

163

Cumulative error across 8 cycles

tERR(8per)

-193

193

-169

169

Cumulative error across 9 cycles

tERR(9per)

-200

200

-175

175

Cumulative error across 10 cycles

tERR(10per)

-205

205

-180

180

Cumulative error across 11 cycles

tERR(11per)

-210

210

-184

184

Cumulative error across 12 cycles

tERR(12per)

-215

215

-188

188

Cumulative error across n = 13, 14 . . . 49, 50

cycles tERR(nper)

tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min

tERR(nper)max = (1 + 0.68ln(n)) *

tJIT(per)max

Data Timing

DQS, DQS# to DQ skew, per group, per

access

tDQSQ - 125 - 100 ps 13

DQ output hold time from DQS, DQS#

tQH

0.38

tCK(avg)

13,g

DQ low-impedance time from CK, CK#

tLZ(DQ)

-500

250

-450

225

13,14,f

DQ high impedance time from CK, CK#

tHZ(DQ)

250

225

13,14,f

Data setup time to DQS, DQS# referenced to

Vih(ac) / Vil(ac) levels

tDS(base)

AC175

See table for Data Setup and Hold

ps d,17

Data setup time to DQS, DQS# referenced to

Vih(ac) / Vil(ac) levels

tDS(base)

AC150

ps d,17

Data hold time from DQS, DQS# referenced

to Vih(dc) / Vil(dc) levels

tDH(base)

DC100

ps d,17

DQ and DM Input pulse width for each input

tDIPW

400

360

Data Strobe Timing

DQS,DQS# differential READ Preamble tRPRE 0.9 Note 19 0.9

Note

Note 13,19,g

DQS, DQS# differential READ Postamble tRPST 0.3 Note 11 0.3

Note

Note 11,13,g

DQS, DQS# differential output high time

tQSH

0.4

tCK(avg)

13,g

DQS, DQS# differential output low time

tQSL

0.4

tCK(avg)

13,g

DQS, DQS# differential WRITE Preamble

tWPRE

0.9

tCK(avg)

DQS, DQS# differential W RITE Postamble

tWPST

0.3

tCK(avg)

DQS, DQS# rising edge output access time

from rising CK, CK#

tDQSCK -255 255 -225 225 tCK(avg) 13,f

Parameter Symbol

DDR3/DDR3L-1333

DDR3/DDR3L-1600

Units

Notes

Min.

Max.

Min.

Max.

DQS and DQS# low-impedance time

(Referen ced from RL - 1)

tLZ(DQS) -500 250 -450 225 tCK(avg) 13,14,f

DQS and DQS# high-impedance time

(Referenced from RL + BL/2)

tHZ(DQS) - 250 - 225 tCK(avg) 13,14,f

DQS, DQS# differential input low pulse width

tDQSL

0.45

0.55

0.45

0.55

tCK(avg)

29,31

DQS, DQS# differential input high pulse width

tDQSH

0.45

0.55

0.45

0.55

tCK(avg)

30,31

DQS, DQS# rising edge to CK, CK# rising

edge

tDQSS -0.25 0.25 -0.27 0.27 tCK(avg) c

DQS, DQS# falling edge setup time to CK,

CK# rising edge

tDSS 0.2 - 0.18 - tCK(avg) c,32

DQS, DQS# falling edge hold time from CK,

CK# rising edge

tDSH 0.2 - 0.18 - tCK(avg) c,32

Command and Address Timing

DLL locking time

tDLLK

512

nCK

Intern al RE A D Command to PRECHARGE

Command delay

tRTP

tRTPmin.: max(4nCK, 7.5ns)

tRTPmax.: -

Delay from start of internal write transaction to

internal read com mand tWTR

t WTRmin.: max ( 4nCK, 7.5ns)

tWTRmax.:

WRITE recovery time

tWR

e,18

Mode Register Set command cycle time

tMRD

nCK

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Integrated Silicon Solution, Inc. – www.issi.com – 62

Rev. 00B

12/5/2012

Mode Register Set command update delay tMOD

tMODmin.: max(12nCK, 15ns)

tMODmax.:

ACT to internal read or write delay time

tRCD

Standard Speed Bins

PRE command period

tRP

Standard Speed Bins

ACT to ACT or REF command period

tRC

Standard Speed Bins

CAS# to CAS# command delay

tCCD

nCK

Auto precharge write recovery + precharge

time

tDAL(min) WR + roundup(tRP / tCK(avg)) nCK

Multi-Purpose Register Recovery Time

tMPRR

nCK

ACTIVE to PRECHARGE command period

tRAS

Standard Speed Bins

ACTIVE to ACTIVE command period for 1KB

page size

tRRD

max(4nCK,

6ns)

max(4nCK,

6ns)

ACTIVE to ACTIVE command period for 2KB

page size tRRD

tRRDmin.: max(4nCK, 7.5ns)

tRRDmax.:

Four activate window for 1KB page size

tFAW

Four activate window for 2KB page size

tFAW

Command and Addre ss setu p time to CK,

CK# referenced to Vih(ac) / Vil(ac) levels

tIS(base)

See table for ADD/CMD Setup and Hold

ps b,16

Command and Address hold tim e from CK,

CK# referenced to Vih(dc) / Vil(dc) levels

tIH(base) ps b,16,27

Command and Addre ss setu p time to CK,

CK# referenced to Vih(ac) / Vil(ac) levels

tIS(base)

AC150

ps b,16

Control and Address Input pulse width for

each input

tIPW 620 - 560 - ps 28

Calibration Timing

Power-up and RESET calibration time

tZQinit

512

nCK

Normal operatio n Fu ll calibr at i on time

tZQoper

256

nCK

Normal operation Short calibration time

tZQCS

nCK

Reset Timing

Exit Reset from CKE HIGH to a valid

command

tXPR

tXPRmin.: max(5nCK, tRFC(min) + 10ns)

tXPRmax.: -

Self Refresh Timings

Exit Self Refresh to commands not requiring a

locked DLL tXS tXSmin.: max(5nCK, tRFC(min) + 10ns)

tXSmax.: -

Parameter Symbol

DDR3/DDR3L-1333

DDR3/DDR3L-1600

Units

Notes

Min.

Max.

Min.

Max.

Exit Self Refresh to commands requiring a

locked DLL

tXSDLL

tXSDLLmin.: tDLLK(min)

nCK

tXSDLLmax.: -

Minimum CKE low width for Self Refresh entry

to exit timing tCKESR

tCKESRmin.: tCKE(min) + 1 nCK

tCKESRmax.: -

Valid Clock Requirement after Self Refresh

Entry (SRE) or Power-Down Entry (PDE)

tCKSRE

tCKSREmin.: max(5 nCK, 10 ns)

tCKSREmax.: -

Valid Clock Requirement before Self Refresh

Exit (SRX) or Power-Down Exit (PDX) or

Reset Exit

tCKSRX

tCKSRXmin.: max(5 nCK, 10 ns)

tCKSRXmax.: -

Power Down Timings

Exit Power Down with DLL on to any valid

command; Exit Precharge Power Down with

DLL frozen to commands not requiring a

locked DLL

tXP

tXPmin.: max(3nCK, 6ns)

tXPmax.: -

Exit Precharge Power Down with DLL frozen

to commands requiring a locked DLL

tXPDLL

tXPD LLmin.: max(10nCK, 24ns)

tXPDLLmax.: -

CKE minimum pulse width tCKE

tCKEmin.: max(3nCK

5.625ns)

tCKEmin.: max(3nCK

5ns)

tCKEmax.: -

Command pass disable delay

tCPDED

tCPDEDmin.: 1

nCK

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IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 63

Rev. 00B

12/5/2012

tCPDEDmax.: -

Power Down Entry to Exit Timing tPD

tPDmin.: tCKE(min)

tPDmax.: 9*tREFI

Timing of ACT command to Power Down

entry

tACTPDEN

tACTPDENmin.: 1

nCK

tACTPDENmax.: -

Timing of PRE or PREA command to Power

Down entry tPRPDEN

tPRPDENmin.: 1

nCK

tPRPDENmax.: -

Timing of RD/RDA command to Power Down

entry

tRDPDEN

tRDPDENmin.: RL+4+1

nCK

tRDPDENmax.: -

Timing of WR command to Power Down entry

(BL8OTF, BL8MRS, BC4OTF)

tWRPDEN

tWRPDENmi n.: WL + 4 + (tWR / tCK(avg))

nCK

tWRPDENmax.: -

Timing of WRA command to Power Down

entry (BL8OTF, BL8MRS, BC4OTF) tWRAPDEN

tWRAPDENmin.: WL+4+ WR+1

nCK

tWRAPDENmax.: -

Timing of WR command to Power Down entry

(BC4MRS)

tWRPDEN

tWRPDENmin.: WL + 2 + (tWR / tCK(avg))

tWRPDENmax.: -

nCK

Timing of WRA command to Power Down

entry (BC4MRS)

tWRAPDEN

tWRAPDE Nmi n.: WL + 2 +WR + 1

nCK

tWRAPDENmax.: -

Timing of REF command to Power Down

entry tREFPDEN

tREFPDENmin.: 1

nCK

tREFPDENmax.: -

Timing of MRS command to Power Down

entry

tMRSPDEN

tMRSPDENmin.: tMOD(min)

tMRSPDENmax.: -

ODT Ti m i n g s

ODT high time without write command or with

write command and BC4

ODTH4

ODTH4min.: 4

nCK

ODTH4max.: -

ODT high time with Write command and BL8 ODTH8

ODTH8min.: 6

nCK

ODTH8max.: -

Asynchronous RTT turn-on delay (Power-

Down with DLL frozen)

tAONPD 2 8.5 2 8.5 ns

Asynchronous RTT turn-off delay (Power-

Down with DLL frozen)

tAOFPD 2 8.5 2 8.5 ns

RTT turn-on

tAON

-250

250

-225

225

RTT_Nom and RTT_WR turn-off time from

ODTLoff reference

tAOF 0.3 0.7 0.3 0.7 tCK(avg) 7,f

RTT dynamic change sk ew tADC 0.3 0.7 0.3 0.7 tCK(avg) 8,f

Parameter Symbol

DDR3/DDR3L-1333

DDR3/DDR3L-1600

Units

Notes

Min.

Max.

Min.

Max.

Write Leveling Timings

First DQS/DQS# rising edge after write

leveling mode is progr am med

tWLMRD 40 - 40 - nCK

DQS/DQS# delay after write leveling mode is

programmed

tWLDQSEN 25 - 25 - nCK 3

Write leveling setup time from rising CK, CK#

crossing to rising DQS, DQS# crossing

tWLS 195 - 165 - ps

Write leveling hold time from rising DQS,

DQS# crossing to rising CK, CK# crossing

tWLH 195 - 165 - ps

Write leveling output delay

tWLO

7.5

Write leveling output error

tWLOE

9.2.2 Timing Parameter by Speed Bin (DDR3-1866)

Parameter Symbol

DDR3/DDR3L-1866

Units

Notes

Min.

Max.

Min.

Max.

Clock Timing

Minimum Clock Cycle Time (DLL off mode)

tCK(DLL_OFF)

Average Clock Period

tCK(avg)

Refer to Standard Speed Bins

Average high pulse width

tCH(avg)

0.47

0.53

tCK(avg)

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 64

Rev. 00B

12/5/2012

Average low pulse width

tCL(avg)

0.47

0.53

tCK(avg)

Absolute Clock Period tCK(abs)

Min.: tCK(avg)min + tJIT(per)min

Max.: tCK(avg)max + tJIT(per)max

Absolute clock HIGH pulse width

tCH(abs)

0.43

tCK(avg)

Absolute clock LOW puls e width

tCL(abs)

0.43

tCK(avg)

Clock Period Jitter

JIT(per)

-60

Clock Period Jitter during DLL locking period

JIT(per, lck)

-50

Cycle to Cycle Period Jitter

tJIT(cc)

120

Cycle to Cycle Period Jitter during DLL

locking period

JIT( cc, lck) 100 100

Duty Cycle Jitter

tJIT(duty)

Cumulative error across 2 cycles

tERR(2per)

-88

Cumulative error across 3 cycles

tERR(3per)

-105

105

Cumulative error across 4 cycles

tERR(4per)

-117

117

Cumulative error across 5 cycles

tERR(5per)

-126

126

Cumulative error across 6 cycles

tERR(6per)

-133

133

Cumulative error across 7 cycles

tERR(7per)

-139

139

Cumulative error across 8 cycles

tERR(8per)

-145

145

Cumulative error across 9 cycles

tERR(9per)

-150

150

Cumulative error across 10 cycles

tERR(10per)

-154

154

Cumulative error across 11 cycles

tERR(11per)

-158

158

Cumulative error across 12 cycles

tERR(12per)

-161

161

Cumulative error across n = 13, 14 . . . 49, 50

cycles tERR(nper)

tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min

tERR(nper)max = (1 + 0.68ln(n)) *

tJIT(per)max

Data Timing

DQS, DQS# to DQ skew, per group, per

access

tDQSQ - 85 -

ps 13

DQ output hold time from DQS, DQS#

tQH

0.38

tCK(avg)

13,g

DQ low-impedance time from CK, CK#

tLZ(DQ)

-390

195

13,14,f

DQ high impedance time from CK, CK#

tHZ(DQ)

195

13,14,f

Data setup time to DQS, DQS# referenced to

Vih(ac) / Vil(ac) levels

tDS(base)

AC175

See table for Data

Setup and Hold

- - ps d,17

Data setup time to DQS, DQS# referenced to

Vih(ac) / Vil(ac) levels tDS(base)

AC150 - ps d,17

Parameter Symbol

DDR3/DDR3L-1866

Units

Notes

Min.

Max.

Min.

Max.

Data hold time from DQS, DQS# referenced

to Vih(dc) / Vil(dc) levels

tDH(base)

DC100

- ps d,17

DQ and DM Input pulse width for each input tDIPW 320 -

- ps 28

Data Strobe Timing

DQS,DQS# differential READ Preamble

tRPRE

0.9

Note 19

Note

13,19,g

DQS, DQS# differential READ Postamble

tRPST

0.3

Note 11

Note

11,13,g

DQS, DQS# differential output high time

tQSH

0.4

tCK(avg)

13,g

DQS, DQS# differential output low time

tQSL

0.4

tCK(avg)

13,g

DQS, DQS# differential WRITE Preamble

tWPRE

0.9

tCK(avg)

DQS, DQS# differential W RITE Postamble

tWPST

0.3

tCK(avg)

DQS, DQS# rising edge output access time

from rising CK, CK#

tDQSCK -195 195

tCK(avg) 13,f

DQS and DQS# low-impedance time

(Referen ced from RL - 1)

tLZ(DQS) -390 195

tCK(avg) 13,14,f

DQS and DQS# high-impedance time

(Referenced from RL + BL/2)

tHZ(DQS) - 195

tCK(avg) 13,14,f

DQS, DQS# differential input low pulse width

tDQSL

0.45

0.55

tCK(avg)

29,31

DQS, DQS# differential input high pulse width

tDQSH

0.45

0.55

tCK(avg)

30,31

DQS, DQS# rising edge to CK, CK# rising

tDQSS

-0.27

0.27

tCK(avg)

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IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 65

Rev. 00B

12/5/2012

edge

DQS, DQS# falling edge setup time to CK,

CK# rising edge

tDSS 0.18 -

tCK(avg) c,32

DQS, DQS# falling edge hold time from CK,

CK# rising edge tDSH 0.18 - tCK(avg) c,32

Command and Address Timing

DLL locking time

tDLLK

512

nCK

Intern al RE A D Command to PRECHARGE

Command delay

tRTP

tRTPmin.: max(4nCK, 7.5ns)

tRTPmax.: -

Delay from start of internal write transaction to

internal read command

tWTR

t WTRmin.: max ( 4nCK, 7.5ns)

tWTRmax.:

WRITE recovery time

tWR

e,18

Mode Register Set command cycle time

tMRD

nCK

Mode Register Set command update delay tMOD

tMODmin.: max(12nCK, 15ns)

tMODmax.:

ACT to internal read or write delay time

tRCD

Standard Speed Bins

PRE command period

tRP

Standard Speed Bins

ACT to ACT or REF command period

tRC

Standard Speed Bins

CAS# to CAS# command delay

tCCD

nCK

Auto precharge write recovery + precharge

time

tDAL(min) WR + roundup(tRP / tCK(avg)) nCK

Multi-Purpose Register Recovery Time

tMPRR

nCK

ACTIVE to PRECHARGE command period

tRAS

Standard Speed Bins

ACTIVE to ACTIVE command period for 1KB

page size

tRRD

max(4nCK,

6ns)

max(4nCK,

6ns)

ACTIVE to ACTIVE command period for 2KB

page size tRRD tRR Dmin.: max(4nCK, 7.5ns)

tRRDmax.:

Four activate window for 1KB page size

tFAW

Four activate window for 2KB page size

tFAW

Command and Addre ss setu p time to CK,

CK# referenced to Vih(ac) / Vil(ac) levels

tIS(base) See table for

ADD/CMD setup and

hold

ps b,16

Command and Address hold tim e from CK,

CK# referenced to Vih(dc) / Vil(dc) levels

tIH(base)

ps b,16,27

Command and Addre ss setu p time to CK,

CK# referenced to Vih(ac) / Vil(ac) levels

tIS(base)

AC150

ps b,16

Parameter Symbol

DDR3/DDR3L-1866

Units

Notes

Min.

Max.

Min.

Max.

Control and Address Input pulse width for each

input

tIPW 535 -

ps 28

Calibration Timi ng

Power-up a nd R E SET cali bration time

tZQinit

512

nCK

Normal operation Full calibration ti m e

tZQoper

256

nCK

Normal operation Short cali bration time

tZQCS

nCK

Reset T iming

Exit Reset from C K E H IGH to a valid com m and tXPR

tXPRmin.: max(5nCK, tRFC(min) + 10ns)

tXPRmax.: -

Self Refresh Tim ings

Exit Self Refresh to commands not requiring a

locked DLL tXS

tXSmi n.: max(5nCK, tRFC(min) + 10ns)

tXSmax.: -

Exit Self Refresh to commands r equiring a

locked DLL tXSDLL

tXSDLLmin.: tDLLK(min)

nCK

tXSDLLmax.: -

Minim um C KE low width for Self Refresh entry t o

exit timing tCKESR

tCKESRmin.: tCKE(min) + 1 nCK

tCKESRmax.: -

Valid Clock Requirement after Self Refresh Entry

(SRE) or Power-Down Entry (PDE) tCKSRE

tCKSREmin.: max(5 nCK, 10 ns)

tCKSREmax.: -

Valid Clock Requirement before Self Refresh

tCKSRX

tCKSRXmin.: max(5 nC K, 10 ns)

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 66

Rev. 00B

12/5/2012

Exit (SRX) or Power -D ow n Exit (PDX) or R eset

Exit

tCKSRXmax.: -

Power Down Timings

Exit Power Down with DLL on to any valid

command; Exit Precharge Powe r Down with DLL

frozen to commands not requiring a locked DLL tXP

tXPmi n.: max(3nCK, 6ns)

tXPmax.: -

Exit Precharge Power Down with DLL f rozen to

commands requiri ng a locked DLL tXPDLL

tXPDLLmi n.: max(1 0nC K, 24ns)

tXPDLLmax.: -

CKE mini m um pulse widt h tCKE

tCKEmi n.: max(3nCK 5 ns)

tCKEmax.: -

Command pass disable delay tCPDED

tCPDEDmin.: 1

nCK

tCPDEDmax.: -

Power Down Entry to Exit Timing tPD

tPDmin.: tCKE(min)

tPDmax.: 9*tREFI

Timing of ACT command to Power D ow n entry tACTPDEN

tACTPDENmin. : 1

nCK

tACTPDENmax.: -

Timing of PRE or PREA c om m and to Power

Down ent ry tPRPDEN

tPRPDENmin. : 1

nCK

tPRPDENmax.: -

Timing of RD/RDA com m and to Power Down

entry tRDPDEN

tRDPDENmin.: RL+4+1

nCK

tRDPDENmax.: -

Timing of WR command t o P ower Down entry

(BL8OTF, BL8M RS, BC4OTF) tWRPDEN

tW R PD E Nmin.: WL + 4 + (tWR / tCK(avg))

nCK

tWRPDENmax.: -

Timing of WRA command to Power Down ent ry

(BL8OTF, BL8M RS, BC4OTF) tWRAPDEN

tWRAPDENmin.: WL+4+WR+1

nCK

tWRAPDENmax.: -

Timing of WR command t o P ower Down entry

(BC4MRS)

tWRPDEN

tW R PD E Nmin.: WL + 2 + (tWR / tCK(avg))

tWRPDENmax.: -

nCK

Timing of WRA command to Power Down ent ry

(BC4MRS) tWRAPDEN

tWRAPDENmi n. : WL + 2 +W R + 1

nCK

tWRAPDENmax.: -

Timing of REF command t o Power Down entry tREFPDEN

tREFPDENmin. : 1

nCK

tREFPDENmax.: -

Timing of MRS command t o P ower Down entry tMRSPDEN

tMRSPDENmin.: tMOD(min)

tMRSPDENmax.: -

ODT Timings

ODT high t ime without write com m and or with

write command and BC4 ODTH4

ODTH4min.: 4

nCK

ODTH4max.: -

Parameter Symbol

DDR3/DDR3L-1866

Units

Notes

Min.

Max.

Min.

Max.

ODT high time with Write command and BL8 ODTH8

ODTH8min.: 6

nCK

ODTH8max.: -

Asynchronous RTT turn-on delay (Power-

Down with DLL frozen)

tAONPD 2 8.5

Asynchronous RTT turn-off delay (Power-

Down with DLL frozen)

tAOFPD 2 8.5

RTT turn-on

tAON

-195

195

RTT_Nom and RTT_WR turn-off time from

ODTLoff reference

tAOF 0.3 0.7

tCK(avg) 7,f

RTT dynamic change sk ew

tADC

0.3

0.7

tCK(avg)

8,f

Write Leveling Timings

First DQS/DQS# rising edge after write

leveling mode is progr am med

tWLMRD 40 -

nCK

DQS/DQS# delay after write leveling mode is

programmed

tWLDQSEN 25 -

nCK 3

Write leveling setup time from rising CK, CK#

crossing to rising DQS, DQS# crossing

tWLS 140 -

Write leveling hold time from rising DQS,

DQS# crossing to rising CK, CK# crossing

tWLH 140 -

Write leveling output delay

tWLO

7.5

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Write leveling output error

tWLOE

9.3 Jitter Notes

Specific Note a

Unit “tCK(avg)” represents the actual tCK(avg) of the input clock under operation. Unit “nCK” represents one clock cycle of

the input clock, counting the actual clock edges. ex) tMRD=4 [nCK] means; if one Mode Register Set command is

registered at Tm, another Mode Register Set command may be registered at Tm+4, even if (Tm+4-Tm) is 4 x tCK(avg) +

tERR(4per), min.

Specific Note b

These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc)

transition edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock

jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the

command/address. That is, these parameters should be met whether clock jitter is present or not.

Specific Note c

These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal

(CK, CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc), as

these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or

not.

Specific Note d

These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective

data strobe signal (DQS(L/U), DQS(L/U)) crossing.

Specific Note e

For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{tPARAM[ns] / tCK(avg)[ns]}, which is in

clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP

=RU{tRP/tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-

6, of which tRP = 15ns, the device will support tnRP = RU{tRP/tCK(avg)} = 6, as long as the input clock jitter specifications

are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6-Tm) is less than 15ns due to

input clock jitter.

Specific Note f

When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper), act of

the input clock, where 2 <= m <=12. (output derating are relative to the SDRAM input clock.)

For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = -172ps and tERR(mper),act,max

= 193ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = -400ps - 193ps = -593ps and

tDQSCK,max(derated) = tDQSCK,max - ERR(mper),act,min = 400ps + 172ps = 572ps. Similarly, tLZ(DQ) for DDR3-800

derates to tLZ(DQ),min(derated) = -800ps - 193ps = -993ps and tLZ(DQ),max(derated) = 400ps + 172ps = 572ps.

(Caution on the min/max usage!)

Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <= 12, and

tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.

Specific Note g

When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the

input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800

SDRAM has tCK(avg),act=2500ps, tJIT(per),act,min = -72ps and tJIT(per),act,max = 93ps, then tRPRE,min(derated) =

tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500ps - 72ps = 2178ps. Similarly,

tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500ps - 72ps = 878ps.

(Caution on the min/max usage!)

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9.4 Timing Parameter Notes

1. Actual value dependent upon measurement level definitions.

2. Commands requiring a locked DLL are: READ ( and RAP) are synchronous ODT commands.

3. The max values are sy stem dependent.

4. WR as programmed in mode register.

5. Value must be rouned-up to next higher inte ger va lue.

6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.

7. For definition of RTT-on time tAON See “Timing Parameters”.

8. For definition of RTT-off time tAOF See “Timing Parameters”.

9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.

10. WR in clock cycles are programmed in MR0.

11. The maximum read postamble is bonded by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the

right side.

12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this

parameter needs to be derated by TBD.

13. Value is only valid for RON34.

14. Single ended signal parameter.

15. tREFI depends on TOPER.

16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew

rate. Note for DQ and DM signals, VREF(DC)=VRefDQ(DC). For input only pins except RESET,

VRef(DC)=VRefCA(DC).

17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate.

18. Note for DQ and DM signals, VREF(DC)=VRefDQ(DC). For input only pins except RESET, VRef(DC)=VRefCA(DC).

19. Start of internal write transaction is defined as follows:

20. For BL8 (fixed by MRS and on-the-fly): Rising clock edge 4 clock cycles after WL.

21. For BC4 (on-the-fly): Rising clock edge 4 clock cycles after WL.

22. For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.

19. The maximum preamble is bound by tLZ(DQS)max on the left side and tDQSCK(max) on the right side.

20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are

in progress, but power-down IDD spec will not be applied until finishing those operations.

21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there

are cases where additional time such as tXPDLL(min) is also required.

22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

23. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error

within 64 nCK for all speed bins assuming the maximum sensitivities specified in the “Output Driver Voltage and

Temperature Sensitivity” and “ODT Voltage and Temperature Sensitivity” tables. The appropriate interval between

ZQCS commands can be determined from these tables and other application-specific parameters.

23. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage

(Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. the interval could be defined by the

following formula:

ZQCorrection / [(TSens x Tdriftrate) + (VSens x Vdriftrate)]

, where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and

voltage sensitivities.

For example, if TSens = 1.5%/C, VSens = 0.15%/mV, Tdriftrate = 1 C/sec and Vdriftrate = 15mV/sec, then the interval

between ZQCS commands is calculated as

0.5 / [(1.5x1)+(0.15x15)] = 0.133 ≈ 128ms

24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.

25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following

falling edge.

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26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following

rising edge.

27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an addit ional 100 ps of

derating to accommodate for the lower altemate threshold of 150mV and another 25ps to account for the earlier

reference point [(175mV - 150mV) / 1V/ns].

28. Pulse width of a input signal is defined as the width between the first crossing of Vref(dc) and the consecutive

crossing of Vref(dc).

29. tDQSL des c ribes the instan t ane ous dif f er ential input lo w pu lse width on DQ S - DQS#, as measured from one falling

edge to the next consecutive rising edge.

30. tDQSH describes the instantaneous differential input high pulse width on DQS - DQS#, as measured from one rising

edge to the next consecutive falling edge.

31. tDQSH,act + tDQSL,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing

parameter in the application.

32. tDSH,act + tDSS,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter

in the application.

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9.5 Address / Command Setup, Hold and Derating

For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the datasheet tIS(base)

and tIH(base) value to the ∆tIS and ∆tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + ∆tIS

Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the

first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate

line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value . If the actual signal is later than

the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual

signal from the ac level to VREF (dc) level is used for derating value.

Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the

first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of Vih(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate

line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than

the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual

signal from the dc level to VREF (dc) level is used for derating value.

For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC. Although for slow slew

rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the

rising clock transition, a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in

between the values listed in Table 69, the derating values may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

9.5.1 ADD/CMD Setup and Hold Base-Values for 1V/ns

Symbol Reference DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units

tIS(base) AC175 VIH/L(ac) 200 125 65 45 ps

tIS(base) AC150 VIH/L(ac) 350 275 190 170 ps

tIH(base) DC100 VIH/L(dc) 275 200 140 120 ps

Symbol Reference DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 Units

tIS(base) AC160 VIH/L(ac) 215 140 80 60 ps

tIS(base) AC135 VIH/L(ac) 365 290 205 185 ps

tIH(base) DC90 VIH/L(dc) 285 210 150 130 ps

Notes:

1. (ac/dc ref erenced for 1V/ ns Address/ Command slew rate and 2 V/ns differential CK-CK# slew rate)

2. The tIS(base) AC150 specif ic at i ons are adj ust ed from the tIS(base) AC175 specification by addi ng an additional 125 ps for DDR3-800/1066 or

100ps for DDR3-1333/1600 of derating to accommodate for the lower alternate threshol d of 150 mV and another 25 ps to account for the earlier

reference point [(175 m v - 150 mV) / 1 V/ns].

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9.5.2 Derating values DDR3-800/1066/1333/1600 tIS/tIH - ac/dc based AC175 Threshold

”tIS, ”tIH derating in [ps] AC/DC based

AC175 Threshold -> VIH(ac)=VREF(dc)+175mV, VIL(ac)=VREF(dc)-175mV

CK,CK# Differ ential Slew Rate

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/n s 1.2 V/ns 1.0 V/n s

”tIS ” tIH ” tIS ” tIH ” tIS ” tIH ” tIS ” tIH ” tIS ” tIH ” tIS ” tIH ” tIS ” tIH ” tIS ” tIH

CMADDD/

Slew rate

V/ns

2.0

104

112

120

128

100

1.5

1.0

0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50

0.9

-2 -4 -2 -4 -2 -4 6 4 14 12 22 20 30 30 38 46

0.8 -6 -10 -6 -10 -6 -10 2 -2 10 6 18 14 26 24 34 40

0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34

0.6

-17

-26

-17

-26

-17

-26

-9

-18

-1

-10

-2

0.5

-35

-40

-35

-40

-35

-40

-27

-32

-19

-24

-11

-16

-2

-6

0.4

-62 -60 -62 -60 -62 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10

9.5.3 Derating values DDR3-800/1066/1333/1600 tIS/tIH - ac/dc based – Alternate AC150 Threshold

”

tIS,

”

tIH derating in [ps] AC/DC based

Alternate AC150 Threshold -> VIH(ac)=VREF(dc)+15 0mV, VIL(ac)=VREF(dc)-150mV

CK,CK# Differential Slew Rate

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/n s 1.4 V/ns 1.2 V/ns 1.0 V/ns

”tIS ” tIH ” tIS ” tIH ” tIS ” tIH ” tIS ” tIH ” tIS ” tIH ” tIS ” tIH ” tIS ” tIH ” tIS ” tIH

CADDMD/

Slew rate

V/ns

2.0

107

115

100

1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84

1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50

0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46

0.8 0 -10 0 -10 0 -10 8 -2 16 6 24 14 32 24 40 40

0.7 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34

0.6

-1

-26

-1

-26

-1

-26

-18

-10

-2

0.5

-10

-40

-10

-40

-10

-40

-2

-32

-24

-16

-6

0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10

9.5.4 Req u ired time tVAC above VIH(ac) {below VIL(ac)} for val id transition

Slew Rate [V/ns] tVAC @ AC175 [ps] tVAC @ AC150 [ps]

min max min max

> 2.0 75 - 175 -

2.0 57 - 170 -

1.5

167

1.0

163

0.9

162

0.8 29 - 161 -

0.7 22 - 159 -

0.6 13 - 155 -

0.5 0 - 150 -

< 0.5 0 - 150 -

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9.5.5 Address / Command Setup, Hold and Derating

9.6.5.1 Nominal slew rate and tVAC for setup time tIS(left) and hold time t DH(right) – ADD/CMD with respect to clock

9.6.5.2 Tangent line for setup time tIS(left) and hold time tIH(right) - ADD/CMD with respect to clock

VREF to AC region

VREF to DC

VREF to AC region

CK#

DDQ

VIH(ac)MIN

VIH(dc)MIN

VREF(dc)

VIL(dc)MAX

VIL(ac)MAX

Normal

slew rate

Normal

slew rate

tIS

tIH

tVAC

tIS

tIH

∆

Setup slew Rate @

Falling signal

[VREF(dc)-VIL(ac)max]

/ ΔTF

Setup slew Rate @ Rising

signal

[VIH(ac)min-VREF(dc)]

/ ΔTR

CK#

DDQ

VIH(ac)MIN

VIH(dc)MIN

VREF(dc)

VIL(dc)MAX

VIL(ac)MAX

Normal

slew rate

Normal

slew rate

tIS

tIH

tVAC

tIS

tIH

∆

Hold slew Rate @

Rising signal

[VREF(dc)-VIL(dc)max]

/ ΔTR

Hold slew Rate @

Falling signal

[VIH(dc)min-VREF(dc)]

/ ΔTF

CK#

DDQ

VIH(ac)MIN

VIH(dc)MIN

VREF(dc)

VIL(dc)MAX

VIL(ac)MAX

Normal

slew rate

Normal

slew rate

tIS

tIH

tVAC

tIS

tIH

VSS

∆

Setup slew Rate @

Rising signal

= tangent lin e

[VIH(ac)min-VREF(dc)]

/ ΔTR

Setup slew Rate @

Falling signal

= tangent lin e

[VREF(dc)-VIL(ac)max]

/ ΔTF

tangent

line

tangent

line

CK#

VDDQ

VIH(ac)MIN

VIH(dc)MIN

VREF(dc)

VIL(dc)MAX

VIL(ac)MAX

Normal

slew rate

Normal

slew rate

tIS

tIH

tIS

tIH

∆

Hold slew Rate @

Falling signal

= tangent lin e

[VIH(dc)min-VREF(dc)]

/ ΔTF

Hold slew Rate @

Rising signal

= tangent lin e

[VREF(dc)-VIL(dc)max]

/ ΔTR

tangent

line

tangent

line

∆

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9.6 Data Setup, Hold and Slew Rate Deratin g

For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet

tDS(base) and tDH(base) value (see Table 72) to the ∆tDS and ∆tDH (see Table 73) derating value respectively.

Example: tDS (total setup time) = tDS(base) + ∆tDS.

Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the

first crossing of V IH(ac) min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of VREF(dc) and the first crossing of VIL(ac) max. If the actual signal is always earlier than the nominal slew rate

line between shaded ‘VREF(dc) to ac region’, use nom inal slew rate for derating value. If the actual signal is later than the

nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual

signal from the ac level to VREF(dc ) level is used for derating value.

Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc) max and

the first crossing of VREF(dc) . Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the

last cr ossing of VIH(dc) min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew

rate line between shaded ‘dc level to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is

earlier than the nominal slew rate line anywhere between shaded ‘dc to V REF(dc) region’, the slew rate of a tangent line

to the actual signal from the dc level to VREF(dc) level is used for derating value.

For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached

VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach

VIH/IL(ac) .

For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

9.6.1 Data Setup and Hold Bas e -Values

Symbol Reference DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units

tDS(base) AC175 VIH/L(ac) 75 25 - - ps

tDS(base) AC150 VIH/L(ac) 125 75 30 10 ps

tDH(base) DC100 VIH/L(dc) 150 100 65 45 ps

NOTE: (ac/dc referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate)

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9.6.2 Derating values DDR3-800/1066 tDS/tDH - (AC175)

AtDS, ADH derating in [ps] AC/DC based1

DQS, DQS# Differential Slew Rate

4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns

AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH

Slew

rate

V/ns

2.0

1.5

1.0

0.9

-2

-4

-2

-4

0.8

-6

-10

-2

0.7

-3

-8

0.6

-1

-10

-2

0.5

-11

-16

-2

-6

0.4

-30

-26

-22

-10

NOTE 1. Cell contents shaded in red are defined as ‘not supported’.

9.6.3 Derating values for DDR3-800/1066/1333/1600 tDS/tDH - (AC150)

AtDS, ADH derating in [ps] AC/DC based1

DQS, DQS# Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH AtDS AtDH

Slew

rate

V/ns

2.0

1.5

1.0

0.9

-4

0.8

-10

-2

0.7

-8

0.6

-10

-2

0.5

-16

-6

0.4

-26

-10

NOTE 1. Cell contents shaded in red are defined as ‘not supported’.

9.6.4 Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition

Slew Rate [V/ns] DDR3-800/1066 (AC175) DDR3-800/1066/1333/1600 (AC150)

Slew Rate [V/ns] tVAC [ ps] tVAC [ps]

min max min max

> 2.0

175

2.0

170

1.5

167

1.0

163

0.9

162

0.8

161

0.7

159

0.6

155

0.5

155

< 0.5

150

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 75

Rev. 00B

12/5/2012

9.6.5 Data Setup, Hold and Slew Rate Derating

9.6.5.1 Nominal slew rate and tVAC for setup time tDS(left) and hold time t DH(right) - DQ with respect to strobe

9.6.5.2 Tangent line for setup time tDS(left) and hold time tDH(right) - DQ with respect to strobe

VREF to AC region

VREF to DC region

DQS#

DQS

DDQ

VIH(ac)MIN

VIH(dc)MIN

VREF(dc)

VIL(dc)MAX

VIL(ac)MAX

Normal

slew rate

Normal

slew rate

tDS

tDH

tVAC

tDS

tDH

VREF to AC region

∆

Setup slew Rate @

Falling signal

[VREF(dc)-VIL(ac)max]

/ ΔTF

Setup slew Rate @ Rising

signal

[VIH(ac)min-VREF(dc)]

/ ΔTR

DQS#

DQS

DDQ

VIH(ac)MIN

VIH(dc)MIN

VREF(dc)

VIL(dc)MAX

VIL(ac)MAX

Normal

slew rate

Normal

slew rate

tDS

tDH

tVAC

tDS

tDH

VSS

∆TR

∆

Hold slew Rate @

Rising signal

[VREF(dc)-VIL(dc)max]

/ ΔTR

Hold slew Rate @

Falling signal

[VIH(dc)min-VREF(dc)]

/ ΔTF

DQS#

DQS

VDDQ

VIH(ac)MIN

VIH(dc)MIN

VREF(dc)

VIL(dc)MAX

VIL(ac)MAX

Normal

slew rate

Normal

slew rate

tDS tDH

tVAC

tDS tDH

VREF to AC region

VSS

∆

Setup slew Rate @

Rising signal

= tangent lin e

[VIH(ac)min-VREF(dc)]

/ ΔTR

Setup slew Rate @

Falling signal

= tangent lin e

[VREF(dc)-VIL(ac)max]

/ ΔTF

tangent

line

tangent

line

DQS#

DQS

VDDQ

VIH(ac)MIN

VIH(dc)MIN

VREF(dc)

VIL(dc)MAX

VIL(ac)MAX

Normal

slew rate

Normal

slew rate

tDS tDH

∆

Hold slew Rate @

Falling signal

= tangent lin e

[VIH(dc)min-VREF(dc)]

/ ΔTF

Hold slew Rate @

Rising signal

= tangent lin e

[VREF(dc)-VIL(dc)max]

/ ΔTR

tangent

line

tangent

line

∆

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 76

Rev. 00B

12/5/2012

ORDERING INFORMATION, 64MX16, 1.5V

64Mx16 - Commercial Ra ng e: (0°C ≤ TC ≤ 95°C)

Data Rate CL-tRCD-tRP Order Part No. Package

1333MT/s 8-8-8 IS43TR16640A -15GBL 96-ball FBGA ,Lead -free

1600MT/s 10-10-10 IS43TR16640A -125JBL 96-ball FBGA,Lead-free

64Mx16 - Industrial Range: (–40°C ≤ TC ≤ 95°C)

Data Rate CL-tRCD-tRP Order Part No. Package

1333MT/s 8-8-8 IS43TR16640A -15GBLI 96-ball FBGA,Lead-free

1600MT/s 10-10-10 IS43TR16640A -125JBLI 96-ball FBGA,Lead-free

64Mx16 – Automotive, A1 Range: (–40°C ≤ TC ≤ 95°C)

Data Rate CL-tRCD-tRP Order Part No. Package

1066MT/s 7-7-7 IS46TR16640A -187FBLA1 96-ball FBGA,Lead-free

1333MT/s 8-8-8 IS46TR16640A -15GBLA1 96-ball FBGA,Lead-free

1333MT/s 9-9-9 IS46TR16640A -15HBLA1 96-ball FBGA,Lead-free

1600MT/s 10-10-10 IS46TR16640A -125JBLA1 96-ball FBGA,Lead-free

64Mx16 – Automotive, A2 Range: (–40°C ≤ TC ≤ 105°C)

Data Rate CL-tRCD-tRP Order Part No. Package

1066MT/s 7-7-7 IS46TR16640A -187FBLA2 96-ball FBGA,Lead-free

1333MT/s 8-8-8 IS46TR16640A -15GBLA2 96-ball FBGA,Lead-free

1333MT/s 9-9-9 IS46TR16640A -15HBLA2 96-ball FBGA,Lead-free

1600MT/s 10-10-10 IS46TR16640A -125JBLA2 96-ball FBGA,Lead-free

Note: Contact ISSI for availability of options.

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 77

Rev. 00B

12/5/2012

ORDERING INFORMATION, 256MX8, 1.5V

128Mx8 - Commercial Ra ng e: (0°C ≤ TC ≤ 95°C)

Data Rate CL-tRCD-tRP Order Part No. Package

1333MT/s 8-8-8 IS43TR81280A -15GBL 78-ball FBGA,Lead-free

1600MT/s 10-10-10 IS43TR81280A -125JBL 78-ball FBGA,Lead-free

128Mx8 - Industrial Range: (–40°C ≤ TC ≤ 95°C)

Data Rate CL-tRCD-tRP Order Part No. Package

1333MT/s 8-8-8 IS43TR81280A -15GBLI 78-ball FBGA,Lead-free

1600MT/s 10-10-10 IS43TR81280A -125JBLI 78-ball FBGA,Lead-free

128Mx8 – Automot ive, A1 Range: (–40°C ≤ TC ≤ 95°C)

Data Rate CL-tRCD-tRP Order Part No. Package

1333MT/s 8-8-8 IS46TR81280A -15GBLA1 78-ball FBGA,Lead-free

1600MT/s 10-10-10 IS46TR81280A -125JBLA1 78-ball FBGA,Lead-free

128Mx8 – Automotive, A2 Range: (–40°C ≤ TC ≤ 105°C)

Data Rate CL-tRCD-tRP Order Part No. Package

1333MT/s 8-8-8 IS46TR81280A -15GBLA2 78-ball FBGA,Lead-free

1600MT/s 10-10-10 IS46TR81280A -125JBLA2 78-ball FBGA,Lead-free

Note: Contact ISSI for availabil ity of opt i ons.

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 78

Rev. 00B

12/5/2012

IS43/46TR16640A, IS43/46TR16640AL

IS43/46TR81280A , IS43/46TR81280AL

Integrated Silicon Solution, Inc. – www.issi.com – 79

Rev. 00B

12/5/2012