1
®
FN9104.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2004, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6161
Dual Power Distribution Controller
The ISL6161 is a HOT SW AP dual supply power distribution
controller that can be used in PCI-Express applications.
Two external N-Channel MOSFETs are driven to distribute
and control power while providing load fault isolati on. At
turn-on, the gate of each external N-Channel MOSFET is
charged with a 10µA current source. Capacitors on each
gate (see the “Typical Application Diagram” on page 1),
create a programmable ramp (soft turn-on) to control in-rush
currents. A built-in charge pump supplies the gate drive for
the 12V supply N-Channel MOSFET switch.
Overcurrent protection is facilitated by two external current
sense resistors and FETs. When the current through either
resistor exceeds the user programmed value, the controlle r
enters the current regulation mode. The time-out capacitor,
CTIM, starts charging as the controller enters the time-out
period. Once CTIM charges to a 2V threshold, both the
N-Channel MOSFETs are latched off. In the event of a hard
and fast fault of at least 3x the programmed current limit
level, the N-Channel MOSFET gates are pulled low
immediately before entering the time-out period. The
controller is reset by a rising edge on the ENABLE pin.
The ISL6161 constantly monitors both output voltages and
reports either one being low on the PGOOD output as a low .
The 12V PGOOD Vth is ~10.8V and the 3.3V Vth is ~2.8V
nominally.
Pinout ISL6161
(14 LD SOIC)
TOP VIEW
Features
• HOT SWAP Dual Power Distribution and Control for
+12V and +3.3V
• Provides F aul t I sol ati on
• Programmable Current Regulation Level
• Programmable Time-Out
• Charge Pump Allows the Use of N-Channel MOSFETs
• Power-Good and Overcurrent Latch Indicators
• Adjustable Turn-On Ramp
• Protection During Turn-On
• Two Levels of Current Limit Detection Provide Fast
Response to Varying Fault Conditions
• 1µs Response Time to Dead Short
• 3µs Response Time to 200% Current Overshoot
• Pb-Free Available (R oH S compliant)
Applications
• PCI-Express Applications
• Power Distribution and Control
• Hot Plug, Hot Swap Components
Typical Application Diagram
8
9
10
11
12
14
13
7
6
5
4
3
2
1
12VS
12VG
VDD
ENABLE
3VG
3VS
12VISEN
GND
CPUMP
CTIM
RILIM
PGOOD
3VISEN
NC
Ordering Information
PART
NUMBER PART
MARKING
TEMP.
RANGE
(°C) PACKAGE PKG.
DWG. #
ISL6161IBZA*
(Note) ISL6161 IBZ -40 to +85 14 Ld SOIC
(Pb-free) M14.15
ISL6161CB* ISL6161CB 0 to +70 14 Ld SOIC M14.15
ISL6161CBZA*
(Note) 6161CBZ 0 to +70 14 Ld SOIC
(Pb-free) M14.15
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel
specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020
12VS
12VG
ENABLE
PGOOD
3VG
3VS
12VISEN
GND
C
TIM
R
ILIM
C
PUMP
3ISEN
V
DD
ISL6161
12V R
LOAD
R
ILIM
C
TIM
ENABLE
INPUT
C
PUMP
R
SENSE
3.3V
R
LOAD
R
SENSE
3.3V
OPTIONAL
R
FILTER
C
FILTER
V
DD
C
GATE
C
GATE
Data Sheet October 2, 2008
2FN9104.4
October 2, 2008
Simplified Schematic
2V
VDD
12VG
12VS 12ISEN
3VG
3VS 3ISEN
GND
NC
CTIM
PGOOD
RILIM
CPUMP
ENABLE
QPUMP
100µA
RISING
ENABLE
VDD
R
R
S
QN
Q
POR
CLIM
3X
ENABLE
OC
10µA
OPTIONAL
FALLING
EDGE
DELAY
R
2R
EDGE
RESET
RFILTER
CFILTER
CPUMP
CTIM
RILIM
12V
TO LOAD
TO LOAD
OC
OPTIONAL
LATCH
12VIN
5VIN
10μA
12V
ISL6161
CGATE
CGATE
TO VDD
+
-
12V
+
-
RSENSE
+
-
PGOOD
+
-
CLIM
3X
ENABLE
OC
10µA
FALLING
EDGE
DELAY
R
2R
18V
+
-
18V
+
-
12V
RSENSE
ISL6161
3FN9104.4
October 2, 2008
Pin Descriptions
PIN NUMBER SYMBOL FUNCTION DESCRIPTION
1 12VS 12V Source Connect to source of associated external N-Channel MOSFET switch to sense output
voltage.
2 12VG 12V Gate Connect to the gate of associated N-Channel MOSFET switch. A capacitor from this node to
ground sets the turn-on ramp. At turn-on this capacitor will be charged to ~17.4V by a 10µA
current source.
3V
DD Chip Supply Connect to 12V supply. This can be either connected directly to the +12V rail supplying the
load voltage or to a dedicated VDD +12V supply. If the former is chosen, special attention to
VDD decoupling must be paid to prevent sagging as heavy loads are switched on.
4 NC Not Connected
5 ENABLE Enable/Reset ENABLE is used to turn-on and reset the chip. Both outputs turn-on w hen this pin is driven
low . After a current limit time-out, the chip is reset by the rising edge of a reset signal applied
to the ENABLE pin. This input has 100µA pull-up capability, which is compatible with 3V and
5V open drain and standard logic.
6 3VG 3V Gate Connect to the gate of the external 3V N-Channel MOSFET. A capacitor from this node to
ground sets the turn-on ramp. At turn-on, this capacitor will be charged to ~11.4V by a 10µA
current source.
7 3VS 3 Source Connect to the source side of 3V external N-Channel MOSFET switch to sense output
voltage.
8 3VISEN 3V Current Sense Connect to the load side of the 3V sense resistor to measure the voltage drop across this
resistor between 3VS and 3VISEN pins.
9 PGOOD Power-Good indicator Indicates that all output volt ages are within specification. PGOOD is driven by an open drain
N-Channel MOSFET. It is pulled low when any output is not within specification.
10 CTIM Current Limit Timing
Capacitor Connect a capacitor from this pin to ground. This capacitor controls the time between the
onset of current limit and chip shutdown (current limit time-out). The duration of current limit
time-out (in seconds) = 200kΩ x CTIM (Farads).
11 CPUMP Charge Pump
Capacitor Connect a 0.1µF capacitor between this pin and VDD (pin 3). Provides charge storage for
12VG drive.
12 GND Chip Ground
13 RILIM Current Limit Set
Resistor A resistor connected between this pin and ground deter mines the current level at which
current limit is activated. This current is determined by the ratio of the RILIM resistor to the
sense resistor (RSENSE). The current at current limit onset is equal to
10µA x (RILIM/RSENSE). The ISL6161 is limited to a 10kΩ min. value (OC Vth = 100mV)
resistor whereas the ISL6161 can accommodate a 5kΩ resistor for a lower OC Vth (50mV).
14 12VISEN 12V Current Sense Connect to the load side of sense resistor to measure the voltage drop across this resistor .
ISL6161
4FN9104.4
October 2, 2008
Absolute Maximum Ratings TA= +25°C Thermal Information
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +16V
12VG, CPUMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 21V
12VISEN, 12VS . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to VDD + 0.3V
3VISEN, 3VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-5V to 7.5V
PGOOD, RILIM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7.5V
ENABLE, CTIM, 3VG . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV (Class 2)
Operating Conditions
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . .+10.5V to +13.2V
Temperature Range (TA)
ISL6161IB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
ISL6161CB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Thermal Resistance (Typical, Note 1) θJA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Maximum Junction Temperature (Plastic Package) . . . . . . .+150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications VDD = 12V, CVG = 0.01µF, CTIM = 0.1µF, RSENSE = 0.1Ω, CBULK = 220µF, ESR = 0.5Ω, TA = TJ = -40°C to
+85°C, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not
production tested.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
12V CONTROL SECTION
Current Limit Threshold Voltage
(Voltage Across Sense Resistor) VIL12V RILIM = 10kΩ92 100 108 mV
RILIM = 5kΩ 47 53 59 mV
3x Current Limit Threshold Voltage
(Voltage Across Sense Resistor) 3 x VIL12V RILIM = 10kΩ250 300 350 mV
RILIM = 5kΩ 100 165 210 mV
±20% Current Limit Response Time
(Current within 20% of Regulated Value) 20%iLrt 200% Current Overload, RILIM = 10kΩ,
RSHORT = 6.0Ω
-2-µs
±10% Current Limit Response Time
(Current within 10% of Regulated Value) 10%iLrt 200% Current Overload, RILIM = 10kΩ,
RSHORT = 6.0Ω
-4-µs
±1% Current Limit Response Time
(Current within 1% of Regulated Value) 1%iLrt 200% Current Overload, RILIM = 10kΩ,
RSHORT = 6.0Ω
-10-µs
Response Time to Dead Short RTSHORT C12VG = 0.01µF - 500 - ns
Gate Turn-On Time tON12V C12VG = 0.01µF - 12 - ms
Gate Turn-On Current ION12V C12VG = 0.01µF 8 10 12 µA
3x Gate Discharge Current 3XdisI 12VG = 18V - 0.75 - A
12V Undervoltage Threshold 12VVUV 10.5 10.8 11.0 V
Charge Pumped 12VG Voltage V12VG CPUMP = 0.1µF 16.8 17.3 17.9 V
3.3V CONTROL SECTION
Current Limit Threshold Voltage
(Voltage Across Sense Resistor) VIL3V RILIM = 10kΩ92 100 108 mV
RILIM = 5kΩ47 53 59 mV
3x Current Limit Threshold Voltage
(Voltage Across Sense Resistor) 3 x VIL3V RILIM = 10kΩ250 300 350 mV
RILIM = 5kΩ100 155 210 mV
±20% Current Limit Response Time
(Current within 20% of Regulated Value) 200% Current Overload, RILIM = 10kΩ,
RSHORT = 2.5Ω
-2-µs
±10% Current Limit Response Time
(Current within 10% of Regulated Value) 200% Current Overload, RILIM = 10kΩ,
RSHORT = 2.5Ω
-4-µs
ISL6161
5FN9104.4
October 2, 2008
ISL6161 Description and Operation
The ISL6161 is a multi-featured +12V and +3.3V dual power
supply distribution controller . Its features include programmable
current regulation (CR) limiting and time to latch off.
At turn-on, the gate capacitor of each external N-Channel
MOSFET is charged with a 10µA current source. These
capacitors create a programmable ramp (soft turn-on). A
charge pump supplies the gate drive for the 12V supply control
FET switch driving that gate to 17V.
The load currents pass through two external current sense
resistors. When the voltage across either resistor quickly
exceeds the user programmed Current Regulation voltage
threshold (CRVth) level, the controller enters current regulation.
The CRVth is set by the external resistor value on RILIM pin. At
this time, the time-out capacitor, CTIM, starts charging with a
10µA current source and the controller enters the time-out
period. The length of the time-out period is set by the single
external capacitor (see Table 2) placed from the CTIM pin
(pin 10) to ground and is characterized by a lowered gate drive
voltage to the appropriate external N-Channel MOSFET. Once
CTIM charges to 2V, an internal comparator is tripped resulting
in both N-Channel MOSFETs being latched off. If the voltage
across the sense resistors rises slowly in response to an OC
condition, then the CR mode is entered at ~95% of the
programmed CR level. This difference is due to the necessary
hysteresis and response time in the CR control circuitry.
Table 1 shows RSENSE and RILIM recommendations and
resulting CR level for the PCI-Express add-in card connector
sizes specified.
±1% Current Limit Response Time
(Current within 1% of Regulated Value) 200% Current Overload, RILIM = 10kΩ,
RSHORT = 2.5Ω
-10-µs
Response Time To Dead Short RTSHORT CVG = 0.01µF - 500 ns
Gate Turn-On Time tON3V CVG = 0.01µF - 5 - ms
Gate Turn-On Current ION3V CVG = 0.01µF 8 10 12 µA
3x Gate Discharge Current 3xdisI CVG = 0.01µF, ENABLE = Low 0.75 - A
3.3V Undervoltage Threshold 3.3VVUV 2.7 2.85 3.0 V
3.3VG High Voltage 3VG 11.2 11.9 - V
SUPPLY CURRENT AND IO SPECIFICATIONS
VDD Supply Current IVDD 4810mA
VDD POR Rising Threshold 9.5 10.0 10.7 V
VDD POR Falling Threshold 9.0 9.4 9.8 V
Current Limit Time-Out tILIM CTIM = 0.1µF - 20 - ms
ENABLE Pull-up Voltage PWRN_V ENABLE pin open 1.8 2.4 3.2 V
ENABLE Rising Threshold PWR_Vth 1.1 1.5 2 V
ENABLE Hysteresis PWR_hys 0.1 0.2 0.3 V
ENABLE Pull-Up Current PWRN_I 60 80 100 µA
Current Limit T ime-Out Threshold (CTIM)C
TIM_Vth 1.8 2 2.2 V
CTIM Charging Current CTIM_I 8 10 12 µA
CTIM Discharge Current CTIM_disI 1.7 2.6 3.5 mA
CTIM Pull-Up Current CTIM_disI VCTIM = 8V 3.556.5mA
RILIM Pin Current Source Output RILIM_Io 90 100 110 µA
Charge Pump Output Current Qpmp_Io CPUMP = 0.1µF, CPUMP = 16V 320 560 900 µA
Charge Pump Output Voltage Qpmp_Vo No load 17.2 17.4 - V
Charge Pump Output Voltage - Loaded Qpmp_VIo Load current = 100µA 16.2 16.7 - V
Charge Pump POR Rising Threshold Qpmp + Vth 15.6 16 16.5 V
Charge Pump POR Falling Threshold Qpmp - Vth 15.2 15.7 16.2 V
Electrical Specifications VDD = 12V, CVG = 0.01µF, CTIM = 0.1µF, RSENSE = 0.1Ω, CBULK = 220µF, ESR = 0.5Ω, TA = TJ = -40°C to
+85°C, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not
production tested. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ISL6161
6FN9104.4
October 2, 2008
.
The ISL6161 responds to a load short (defined as a curre nt
level 3x the OC set point with a fast transition) by
immediately driving the relevant N-Channel MOSFET gate to
0V in ~3µs. The gate voltage is then slowly ramped up,
soft-starting the N-Channel MOSFET to the programmed
current regulation limit level. This is the start of the time-out
period if the abnormal load condition still exists. The
program med current regulation level is hel d un ti l ei t he r th e
OC event passes or the time-out period expires. If the former
is the case, then the N-Channel MOSFET is fully enhanced
and the CTIM charging current is diverted away from the
capacitor. If the time-out period expires prior to OC
resolution, then both gates are quickly pulled to 0V turning
off both N-Channel MOSFETs simultaneously.
Upon any UV condition, the PGOOD signal will pull low
when tied high through a resistor to the logic supply. This pin
is a fault indicator but not the OC latch-off indicator. For an
OC latch-off indication, monitor CTIM, pin 10. This pin will
rise rapidly to 12V once the time-out period expires. See
“Simplified Schematic” on page 2 for OC latch-off circuit
suggestion.
The ISL6161 is reset by a rising edge on the ENABLE pin
and is turned on by the ENABLE pin being driven low.
ISL6161 Application Considerations
In a non PCI-Express, motor drive application, Current loop
stabilization is facilitated through a small value resistor in
series with the gate timing capacitor. As the ISL6161 drives
a highly inductive current load, instability characterized by
the gate voltage repeatedly ramping up and down may
appear. A simple method to enhance stability is provided by
the substitution of a larger value gate resistor. Typically, this
situation can be avoided by eliminating long point-to-point
wiring to the load.
With the ENABLE internal pull-up, the ISL6161 is well suited
for implementation on either side of the connector where a
motherboard prebiased condition or a load boa rd staggered
connection is present. In either case, the ISL6161 turns on in
a soft-start mode protecting the supply rail from sudden
current loading.
During the Time-Out delay period with the ISL6161 in
current limit mode, the VGS of the external N-Channel
MOSFETs is reduced driving the N-Channel MOSFET switch
into a high rDS(ON) state. Thus, avoid extended time-out
periods as the external N-Channel MOSFETs may be
damaged or destroyed due to ex cessive internal power
dissipation. Refer to the MOSFET manufacturers data sheet
for SOA information.
With the high levels of in-rush current e.g., highly capacitive
loads and motor start-up currents, choosing the current
regulation (CR) level is crucial to provide both protection
and still allow for this in-rush current without latching off.
Consider this in addition to the time-out delay when
choosing MOSFETs for your design.
Physical layo ut of RSENSE resistors is critical to avoid
inadvertently lowering the CR and trip levels. Ideally, trace
routing between the RSENSE resistors and the ISL6161
should be as direct and as short as possible with zero
current in the sense lines.
TABLE 1. RSENSE AND RILIM RECOMMENDATIONS
PCI-EXPRESS
ADD-IN CARD
CONNECTOR RILIM
(kΩ)
3.3V RSENSE
(mΩ),
NOMINAL
CR (A)
12V RSENSE
(mΩ),
NOMINAL
CR (A)
NOMINAL
CRVth
(mV)
X1 10 30, 3.3 150, 0.7 100
4.99 15, 3.5 90, 0.6 53
X4/X8 10 30, 3.3 40, 2.5 100
4.99 15, 3.5 20, 2.6 53
X16 10 30, 3.3 16, 6.3 100
4.99 15, 3.5 8, 6.6 53
NOTE: Nominal CR Vth = RILIM x 10µA.
TABLE 2.
CTIM CAPACITOR
(µF) NOMINAL TIME-OUT PERIOD
(ms)
0.022 4.4
0.047 9.4
0.1 20
NOTE: Nominal time-out period in seconds = CTIM x 200kΩ.
CORRECT
TO ISEN AND
CURRENT
SENSE RESISTOR
INCORRECT
FIGURE 1. SENSE RE SISTOR PCB LAYOUT
RISET
ISL6161
7FN9104.4
October 2, 2008
Open load detection can be accomplished by monitoring
the ISEN pins. Although gated off, the external FET IDSS will
cause the ISEN pin to float above ground to some voltage
when there is no attached load. If this is not desired, 5k
resistors from the xISEN pins to ground will prevent the
outputs from floating when the external switch FETs are
disabled and the outputs are open.
For PCI-Express applications, the ISL6161 and the
ISL6118 provide the fundamental hotswap function for the
+12V and +3.3V main rails and the +3.3V aux respectively,
as shown in the “PCI-Express Implementation of ISL6161
and ISL6118” on page 10.
Typical Performance Curves
FIGURE 2. SUPPLY CURRENT FIGURE 3. RILIM SOURCE CURRENT
FIGURE 4. CTIM CURRENT SOURCE FIGURE 5. CTIM OC VOLTAGE THRESHOLD
8.2
8.0
7.8
7.6
7.4
7.2
-40 -200 20406080
TEMPERATURE (°C)
8.4
SUPPLY CURRENT (mA)
-30 -10 10 30 50 70
104
103
-40 -20 0 20 40 60 80
102 70503010-10-30
105
TEMPERATURE (°C)
CURRENT (µA)
-40 -20 0 20 40 60-30 -10 10 30 50 70 80
10.7
10.6
10.5
10.4
10.3
CTIM CURRENT SOURCE (µA)
TEMPERATURE (°C) -40 -20 0 20 40 60-30 -10 10 30 50 70 80
2.04
2.02
2.00
1.98
1.96
1.94
CTIM OC VOLTAGE THRESHOLD (V)
TEMPERATURE (°C)
ISL6161
8FN9104.4
October 2, 2008
FIGURE 6. 12V UV THRESHOLD FIGURE 7. 3.3V UV THRESHOLD
FIGURE 8. 12V, 3V GATE DRIVE FIGURE 9. PUMP VOLTAGE
FIGURE 10. OC VOLTAGE THRESHOLD WITH RLIM = 5kΩFIGURE 11. O C VOLTAGE THRESHOLD WITH RLIM = 10kΩ
Typical Performance Curves (Continued)
TEMPERATURE (°C)
12V UV THRESHOLD (V)
20 40 60 80-40 -20 0
10.920
10.902
10.886
10.870 20 40 60 80-40 -20 0
2.8750
2.8725
2.8700
2.8675
2.8650
TEMPERATURE (°C)
3.3V UV THRESHOLD (V)
12V VG
20 40 60 80-40 0-20
17.36
17.34
17.32
17.30
17.28
17.26
11.935
11.930
11.925
11.920
11.915
11.910
11.905
11.900
TEMPERATU RE (°C)
3.3V GATE DRIVE (V)
12V GATE DRIVE (V)
3.3VG
20 40 60 80-40 0-20
VOLTAGE (V)
TEMPERATURE (°C)
17.6
17.4
17.2
16.8
16.6
17.0
CHARGE PUMP VOLTAGE
NO LOAD
CHARGE PUMP VOLTAGE
100µA LOAD
20 40 60 80-40 0-20
TEMPERATURE (°C)
VOLTAGE THRESHOLD (mV)
54.5
54.0
53.5
53.0
52.5
12 OC Vth
3.3 OC Vth
20 40 60 80-40 0-20
VOLTAGE THRESHOLD (mV)
12 OC VTth
3.3 OC Vth
TEMPERATURE (°C)
102.5
102.0
101.5
101.0
100.5
ISL6161
9FN9104.4
October 2, 2008
ISL6161
FIGURE 12. POWER-ON RESET VOLTAGE THRESHOLD
Typical Performance Curves (Continued)
-40 -20 0 20 40 60 80-30 -10 10 30 50 70
10.2
10.0
9.8
9.6
POWER ON RESET (V)
TEMPERATURE (°C)
VDD LOW TO HIGH
VDD HIGH TO LOW
10 FN9104.4
October 2, 2008
PCI-Express Implementation of ISL6161 and ISL6118
CONTROLLER
INTERSIL
ISL6161
12V, 3.3V
POWER CONTROLLER
INTERSIL ISL6118
DUAL 3.3VAUX
POWER CONTROLLER
3.3V GATE SWITCH
+12V GATE SWITCH
+12V
3.3V GATE SWITCH
+12V GATE SWITCH
SLOT 2 PWREN#
SLOT 2 PW R G D
PCI-EXPR E SS S L OT 1
PCI-EXPRES S SL O T 2
SLOT 1 PW R EN #
SLOT 1 PW RG D
SLOT 2 PWRFLT#
SLOT 2 PWREN#
SLOT 1 PWRFLT#
SLOT 1 PWREN#
3.3V
+12V
3.3VAUX
3.3VAUX
3.3V
+12V
INTERSIL
ISL6161
12V, 3.3V
POWER CONTROLLER
3.3V
SLOT 1 PRSNT
SLOT 2
PRSNT
3.3VSB
3.3V
12V
ISL6161
11
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reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersil or its subsidiari es.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9104.4
October 2, 2008
ISL6161
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
α
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B0.013 0.020 0.33 0.51 9
C0.0075 0.0098 0.19 0.25 -
D0.3367 0.3444 8.55 8.75 3
E0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H0.2284 0.2440 5.80 6.20 -
h0.0099 0.0196 0.25 0.50 5
L0.016 0.050 0.40 1.27 6
N14 147
α0o8o0o8o-
Rev. 0 12/93
