© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 1 1Publication Order Number:
BSR58LT1/D
BSR58LT1
JFET Chopper Transistor
N−Channel − Depletion
Features
•Pb−Free Package is Available
MAXIMUM RATINGS
Rating Symbol Value Unit
Drain−Gate Voltage VDG −40 Vdc
Gate−Source Voltage VGS −35 Vdc
Gate Current IG50 mAdc
Total Device Dissipation
@ TA = 25°C
Derate above 25°C
PD350
2.8 mW
mW/°
C
Lead Temperature TL300 °C
Operating and Storage Junction
Temperature Range TJ, Tstg −65 to +150 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Gate−Source Breakdown Voltage
(IG = −1.0 mAdc) V(BR)GSS 40 − Vdc
Gate Reverse Current
(VGS = −15 Vdc) IGSS − −1.0 nAdc
Gate Source Cutoff Voltage
(VDS = 5.0 Vdc, ID = 1.0 mAdc) VGS(off) −0.8 −4.0 Vdc
Drain−Cutoff Current
(VDS = 5.0 Vdc, VGS = −10 Vdc) ID(off) − 1.0 nAdc
ON CHARACTERISTICS
Zero−Gate−Voltage Drain Current (Note
1)
(VDS = 15 Vdc)
IDSS 8.0 80 mAdc
Static Drain−Source On Resistance
(VDS = 0.1 Vdc) rDS(on) − 60 W
Drain Gate and Source Gate
On−Capacitance
(VDS = VGS = 0, f = 1.0 MHz)
Cdg(on)
+
Csg(on)
− 28 pF
Drain Gate Off−Capacitance
(VGS = −10 Vdc, f = 1.0 MHz) Cdg(off) − 5.0 pF
Source Gate Off−Capacitance
(VGS = −10 Vdc, f = 1.0 MHz) Csg(off) − 5.0 pF
1. Pulse Width = 300 ms, Duty Cycle = 3.0%.
Device Package Shipping†
ORDERING INFORMATION
BSR58LT1 SOT−23
SOT−23
CASE 318
STYLE 10
3000/Tape & Reel
3
2
1
MARKING DIAGRAM
M6M G
G
http://onsemi.com
1 DRAIN
2 SOURCE
3
GATE
BSR58LT1G SOT−23
(Pb−Free) 3000/Tape & Reel
M6 = Device Code
M = Date Code*
G= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or overbar may
vary depending upon manufacturing location.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
BSR58LT1
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2
tf, FALL TIME (ns) tr, RISE TIME (ns)
td(on), TURN−ON DELAY TIME (ns)
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
ID, DRAIN CURRENT (mA)
Figure 1. Turn−On Delay Time
RK = 0
TJ = 25°C
J111
J112
J113
VGS(off) = 12 V
= 7.0 V
= 5.0 V
RK = RD′
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
ID, DRAIN CURRENT (mA)
Figure 2. Rise Time
RK = RD′
RK = 0
TJ = 25°C
J111
J112
J113
VGS(off) = 12 V
= 7.0 V
= 5.0 V
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
ID, DRAIN CURRENT (mA)
Figure 3. Turn−Off Delay Time
RK = RD′
RK = 0
TJ = 25°C
J111
J112
J113
VGS(off) = 12 V
= 7.0 V
= 5.0 V
td(off), TURN−OFF DELAY TIME (ns)
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
ID, DRAIN CURRENT (mA)
Figure 4. Fall Time
RK = RD′
RK = 0
TJ = 25°C
J111
J112
J113
VGS(off) = 12 V
= 7.0 V
= 5.0 V
TYPICAL SWITCHING CHARACTERISTICS
NOTE 1
The switching characteristics shown above were measured using a test
circuit similar to Figure 5. At the beginning of the switching interval, the
gate voltage is at Gate Supply Voltage (−VGG). The Drain−Source Voltage
(VDS) is slightly lower than Drain Supply Voltage (VDD) due to the
voltage divider. Thus Reverse Transfer Capacitance (Crss) or Gate−Drain
Capacitance (Cgd) is charged to VGG + VDS.
During the turn−on interval, Gate−Source Capacitance (Cgs) discharges
through the series combination of RGen and RK. Cgd must discharge to
VDS(on) through RG and RK in series with the parallel combination of
effective load impedance (R′D) and Drain−Source Resistance (rds).
During the turn−off, this charge flow is reversed.
Predicting turn−on time is somewhat difficult as the channel resistance
rds is a function of the gate−source voltage. While Cgs discharges, VGS
approaches zero and rds decreases. Since Cgd discharges through rds,
turn−on time is non−linear. During turn−off, the situation is reversed with
rds increasing as Cgd charges.
The above switching curves show two impedance conditions; 1) RK is
equal to RD, which simulates the switching behavior of cascaded stages
where the driving source impedance is normally the load impedance of
the previous stage, and 2) RK = 0 (low impedance) the driving source
impedance is that of the generator.
RGEN
50 W
VGEN
INPUT RK
50 W
RGG
VGG
50 W
OUTPUT
RD
+VDD
RT
SET VDS(off) = 10 V
INPUT PULSE
tr
tf
PULSE WIDTH
DUTY CYCLE
≤ 0.25 ns
≤ 0.5 ns
= 2.0 ms
≤ 2.0%
RGG & RK
RDȀ+ RD(RT)50)
RD)RT)50
Figure 5. Switching Time Test Circuit
BSR58LT1
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3
rds(on), DRAIN−SOURCE ON−STATE
RESISTANCE (OHMS)
NOTE 2
The Zero−Gate−Voltage Drain Current (IDSS), is the principle
determinant of other J-FET characteristics. Figure 10 shows the
relationship of Gate−Source Off Voltage (VGS(off) and Drain−
Source On Resistance (rds(on)) to IDSS. Most of the devices will
be within ±10% of the values shown in Figure 10. This data wil
l
be useful in predicting the characteristic variations for a given
part number.
For example:
Unknown
rds(on) and VGS range for an J112
The electrical characteristics table indicates that an J112 has
an IDSS range of 25 to 75 mA. Figure 10, shows rds(on) = 52 W
for IDSS = 25 mA and 30 W for IDSS = 75 mA.
The corresponding VGS values are 2.2 V and 4.8 V.
yfs, FORWARD TRANSFER ADMITTANCE (mmhos)
C, CAPACITANCE (pF)
rds(on), DRAIN−SOURCE ON−STATE
RESISTANCE (OHMS)
rds(on), DRAIN−SOURCE ON−STATE
RESISTANCE (NORMALIZED)
2.0
3.0
5.0
7.0
10
20
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
ID, DRAIN CURRENT (mA)
Figure 6. Typical Forward Transfer Admittance
1.0
1.5
2.0
3.0
5.0
7.0
10
15
0.03 0.05 0.1 0.3 0.5 1.0 3.0 5.0 10 30
VR, REVERSE VOLTAGE (VOLTS)
Figure 7. Typical Capacitance
200
160
120
80
40
00 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
VGS, GATE−SOURCE VOLTAGE (VOLTS)
Figure 8. Effect of Gate−Source Voltage
On Drain−Source Resistance
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
−70 −40 −10 20 50 80 110 140 170
Tchannel, CHANNEL TEMPERATURE (°C)
Figure 9. Effect of Temperature On
Drain−Source On−State Resistance
J113
J112
J111
Tchannel = 25°C
VDS = 15 V
Cgs
Cgd
Tchannel = 25°C
(Cds IS NEGLIGIBLE)
IDSS
= 10
mA
25
mA
50mA 75mA 100mA 125mA
Tchannel = 25°C
ID = 1.0 mA
VGS = 0
10
IDSS, ZERO−GATE−VOLTAGE DRAIN CURRENT (mA)
Figure 10. Effect of IDSS On Drain−Source
Resistance and Gate−Source Voltage
20 30 40 50 60 70 80 90 100 110 120 130 140 150
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
100
90
80
70
60
50
40
30
20
10
0
VGS, GATE−SOURCE VOLTAGE (VOLTS)
Tchannel = 25°C
rDS(on) @ VGS = 0
VGS(off)
BSR58LT1
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4
PACKAGE DIMENSIONS
bC
L
D
A
E
A1
e
3
12
DIM
AMIN NOM MAX MIN
MILLIMETERS
0.89 1.00 1.11 0.035
INCHES
A1 0.01 0.06 0.10 0.001
b0.37 0.44 0.50 0.015
c0.09 0.13 0.18 0.003
D2.80 2.90 3.04 0.110
E1.20 1.30 1.40 0.047
e1.78 1.90 2.04 0.070
L0.35 0.54 0.69 0.014
2.10 2.40 2.64 0.083
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. 318−01 THRU −07 AND −09 OBSOLETE, NEW
STANDARD 318−08.
HE
0.040 0.044
0.002 0.004
0.018 0.020
0.005 0.007
0.114 0.120
0.051 0.055
0.075 0.081
0.021 0.029
0.094 0.104
NOM MAX
HE
ǒmm
inchesǓ
SCALE 10:1
0.8
0.031
0.9
0.035
0.95
0.037
0.95
0.037
2.0
0.079
SOT−23 (TO−236)
CASE 318−08
ISSUE AL
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
STYLE 10:
PIN 1. DRAIN
2. SOURCE
3. GATE
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BSR58LT1/D
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