Mic MxX26C1000A 1M-BIT [128K x 8] CMOS MULTIPLE-TIME-PROGRAMMABLE-EPROM FEATURES * 128K x 8 organization +5V operating power supply *+12.75V prograni/erase voltage * Electric erase instead of UV light erase * Fast access time: 70/90/100/120/150 ns * Totally static operation * Completely TTL compatible GENERAL DESCRIPTION The MX26C1000A is-a 12.75V/5V, 1M-bit MTP EPROM (Muitiple Time Programmable Read Only Memory). It is organized as 128K words by 8 bits per word, operates from a + 5 volt supply, has a static standby mode, and features fast address location programming. It is designed to be reprogrammed and erased by an EPROM programmer or on-board. Ail programming/erasing signals are TTL levels, requiring a PIN CONFIGURATIONS PDIP/SOP PLCC ao o a2 QO/3 VPP i VOC < zz Sig 2 A16 PGM ! ! AIS NG 32 Ai2 2 }2 ata ar Ata A? AIS AG A13 AG Ss Ag AS Ag Ag , AS 2 Ad i Ag A4 5 A : A3 OE AS MX26C1000A Dan A a2 zs Ato Az OE Are = cE Al Alo AO: OF ao 06 AO "CE ar 1 05 co a7 Q2 i Q4 GND a3 538266568 6 TSOP AZ | 17 16 A4 A2 18 15 AS At 19 14 AG AO 20 13 a7 Qo >] ai 12 Al2 air} 22 W Ais a2 | 23 10 At6 GND 24 MX261000A 9 VPP Q3 4} 28 8 vec a4 | 268 7 4.5 PGM as ij 27 6 NC ae: | 28 5 AI4 a7 29 4 A138 CE 30 OC 3 Ag Ato 31 21" ag OE 32 1 foo at * Operating current: 30mA * Standby current: 100uA * 100 minimum erase/program cycles * Package type: - 32 pin PDIP - 32 pin SOP - 32 pin PLCC - 32 pin TSOP(| single pulse. The MX26C1000A supports an intelligent quick pulse programming algorithm which can result ina programming time of less than 30 seconds. This MTP EPROM is packaged in industry standard 32 pin dual-in-line packages, 32 pinPLCC packages or 32 pin TSOP packages and 32 pin SOP packages. BLOCK DIAGRAM CE ce ey ' ! CONTROL = OUTPUT 0-07 dE =i LOGIC BUFFERS - | 4 poses r. wet ey ~ | YDecopeR | - =! SELECT ~ AQ~A16 : ADDRESS | mer INPUTS : X-DECODER s | CELL ' fo y MAXTRIX } vec VPP GND ' PIN DESCRIPTION SYMBOL PIN NAME AO~A16 Address Input Q0~-Q7 Data Input/Output CE Chip Enable Input OE Output Enable Input VPP Program Supply Voltage NC No Internal Connection Vcc Power Supply Pin (+5V) GNO Ground Pin P/N: PM0464_ Patent#: US#5,526,307 66-1 REV.1.5, FEB 10, 1998FUNCTIONAL DESCRIPTION When the MX26C1000A is delivered, or it is erased, the chip has all 1000K bits in the "ONE", or HIGH state. "ZEROs" are loaded into the MX26C1000 through the procedure of programming. PROGRAMMING MODE PROGRAMMING ALGORITHM The MX26C1000A is programmed by an EPROM programmer or on-board. The device is set up in the programming mode when the programming voltage VPP = 12.75V is applied, with VCC = 5 V and PGM = VIH (Algorithm shown in Figure 1). Programming is achieved by applying a single TTL low level 25us pulse to the PGM input after addresses and data lines are stable. If the data is not verified, additional pulses are applied for a maximum of 20 pulses. After the data is verified, one 25us pulse is applied to overprogram the byte so that program margin is assured. This process is repeated while sequencing through each address of the device. When programming is completed, the data at all the address is verified at VCC = VPP = 5V + 10%. The VCC supply of the MXIC On-Board Programming Algorithm is designed to be 5V + 10% particularly to faciliate the programming operation under the on-board application environment. Butitcan also be implemented in an industrial-standard EPROM programmer. COMPATIBILITY WITH MX27C1000 FAST PROGRAMMING ALGORITHM Besides the On-Board Programming Algorithm, the Fast Programming Algorithm of MX27C1000 also applies to MX26C1000A. MXIC Fast Algorithm is the conventional EPROM programming algorithm and is available in industrial-standard EPROM programmers. A user of industrial-standard EPROM programmer can choose either of the algorithms base on his preference. The device is set up in the fast programming mode when the programming voltage VPP = 12.75V is applted, with VCC = 6.25V and PGM = ViL(or OE = VIH)(Algorithm is shown in Figure 2). The programming is achieved by applying a single TTL low level 25~100us pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the device. When the programming mode is completed, the data in all address is verified at VCC = VPP = 5V + 10%. MxX26C1000A ERASE MODE The MX26C1000A is erased by an EPROM programmer or in-system. The device is set up in erase mode when the AQ = VPP = 12.75V are applied, with VCC = 5V and PGM = VIL.(Algorithm shown in Figure 3). Erase time is around tsec. If the erase is not verified, an additional erase processes will be repeated for a maximum of 200 times. : PROGRAM INHIBIT MODE Programming of multiple MX26C 1000s in parallet with different data is also easily accomplished by using the Program inhibit Mode. Except for CE and OE, all like inputs of the parallel MX26C1000 may be common. A TTL low-level program pulse applied to an MX26C1000A CE input with VPP = 12.75 + 0.25 V and PGM LOW will program that MX26C 1000A. .A high- level CE input inhibits the other MX26C 1000A from being programmed. PROGRAM VERIFY MODE Verification should be performed on the programmed bits to determine that they were correctly programmed. Verification should be performed with OE and GE, at VIL, PGM at VIH, and VPP at its programming voltage. ERASE VERIFY MODE Verification should be performed on the erased chip to determine that the whole chip(all bits) was correctly erased. Verification should be performed with OE and CE at VIL, PGM at VIH, and VCC = 5V, VPP = 12.5V AUTO IDENTIFY MODE The auto identify mode allows the reading out of a binary code from an MTP that will identify its manufacturer and device type. This mode is intended for use by the programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C + 5C ambient temperature range that is required when programming the MX26C 1000A. To activate this mode, the programming equipment must force 12.75V an address line AQ of the device. Two identifier bytes may then be sequenced from the device P/N: PMO454_ Patent#: US#5,526,307 REV.1.5, FEB 10, 1998Mic. outputs by toggling address line AO from VIL to VIH. All other address lines must be held at VIL during auto identify mode. Byte 0 ( AO = VIL) represents the manufacturer code, and byte 1 (AO = VIH), the device identifier code. For the MX26C1000A, these two identifier bytes are given in the Mode Select Table. All identifiers for the manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. READ MODE The MX26C1000A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been LOW and addresses have been stabie for at least tACC - tOE. STANDBY MODE The MX26C1000A has a GMOS standby mode which reduces the maximum VCC current to 100 UA. It is placed in CMOS standby when CE is at VCC + 0.3 V. The MX26C1000A also has a TTL-standby mode which reduces the maximum VCC current to 1.5 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. TWO-LINE OUTPUT CONTROL FUNCTION To accommodate multiple memory connections, a two- line control function is provided to allow for: 1. Low memory power dissipation, 2. Assurance that output bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output MX26C4000A pins are only active when data is desired from a particular memory device. SYSTEM CONSIDERATIONS During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. Ata minimum, a0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 UF bulk electrolytic capacitor should be used between VCC and GND for each of the eight devices. The location of the capacitor should be close to where the power supply is connected to the array. P/N: PM0454 Patent#: US#5,526,307 REV.1.5, FEB 10, 1998M=Ii a MxX26C1000A MODE SELECT TABLE PINS MODE CE OE PGM AO AQ VPP OUTPUTS Read VIL. VIL x xX vec DOUT Output Disable VIL VIH x Xx voc High Z Standby (TTL) VIH x x xX vec High Z Standby (CMOS) Vcc x x x vcc High Z Program VIL VIH VIL X x VPP DIN Program Verify VIL Vit VIH xX x VPP DOUT Erase Vit VIH VIL Xx VPP VPP HIGH Z Erase Verify VIL VIL. VIH x X VPP DOUT Program Inhibit VIH x x x VPP High Z Manufacturer Code VIL VIL x VIL VH voc C2H Device Code(26C1000) = VIL ViL Xx VIH VH vcc DeH NOTES: 1. VH = 12.0V +05V 3. A1-A8 =ATO-A16 = VIL{For auto select) 2. X = Either VIH or VIL{For auto select) 4. See DC Programming Characteristics for VPP voltage during programming. FIGURE 1. PROGRAMMING FLOW CHART , ADDRESS = FIRST LOCATION vCC =5V VPP a 12.75V INTERACTIVE SECTION VERIFY SECTION DEVICE FAILED P/N: PMO454_ Patent#: US#5,526,307 REV. 1.5, FEB 10, 1998MxX26C1000A FIGURE 2. COMPATIBILITY WITH MX27C1000 FAST PROGRAMMING FLOW CHART ADDRESS = FIRST LOCATION VCC = 6.25V VPP = 12.75V INTERACTIVE SECTION VERIFY SECTION INCREMENT ADDRESS PASS LAST ADDRESS FAIL YES VCC = VPP = 5.25V VERIFY ALL BYTES DEVICE FAILED 2 PASS DEVICE PASSED PIN: PM0454_ Patent: US#5,526,307 REV.1.5, FEB10, 1998 66-5NM=Iic MxX26C1000A FIGURE 3. ERASING MODE FLOW CHART PROGRAM ALL 0 Y AQ = 12.75V VCC = 5V VPP = 12.75V t CHIP ERASE (0.5s) i AQ = VIL or VIH VCC =5V VPP = 12.75V | All Bits Verity FAIL INCREMENT X | = PASS 1 CHIP ERASE (0.58) ' DEVICE PASSED NO YES Y DEVICE FAILED P/N: PMO454_ Patent#: US#5,526,307 REV.1.5, FEB 10, 1998MIG . MxX26C1000A SWITCHING TEST CIRCUITS DEVICE a 1.8K ohm Wo UNDER <J +5V TEST cL DIODES = IN3064 6.2K ohm - OR EQUIVALENT ! J CL = 100 pF including jig capacitance(30pF for 70 ns parts) SWITCHING TEST WAVEFORMS 3.0V TEST POINTS ov INPUT OUTPUT AC TESTING: (1) Inputs are driven at 3.0V for a logic "1" and OV for a logic "0". Input pulse rise and fall times are < 10ns. (2) For MX26C1000A P/N: PM0454 Patent#: US#5,526,307 66-7 REV.1.5, FEB 10, 1998Mic ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature 0C to 70C Storage Temperature -65C to 125C Applied Input Voltage -0.5V to 7.0V Applied Output Voltage -0.5V to VCC + 0.5V VCC to Ground Potential -0.5V to 7.0V AS & Vpp -0.5V to 13.5V MxX26C4000A NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change. DC CHARACTERISTICS TA = 0C to 70C, VCC = 5V + 10% SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS VOH Output High Voltage 2.4 Vv IOH = -0.4mA VOL Output Low Voltage 0.4 Vv tOL = 2.1mMA VIH Input High Voltage 2.0 VCC + 0.5 Vv VIL Input Low Voltage -0.3 0.8 Vv Il tnput Leakage Current -10 10 uA VIN = 0 to 5.5V iLO Output Leakage Current 10 10 uA VOUT = 0 to 5.5V Icc3 VCC Power-Down Current 100 uA CE = VCC +0.3V Icc2 VCC Standby Current 15 mA CE = VIH lcci VCC Active Current 30 mA CE = VIL, f=-5MHz, lout = OmA IPP VPP Supply Current Read 100 uA CE = OF = VIL, VPP = 5.5V CAPACITANCE TA = 25C, f = 1.0 MHz (Sampled only) SYMBOL PARAMETER TYP. MAX. UNIT CONDITIONS CIN Input Capacitance 8 8 pF VIN = OV COUT Output Capacitance 8 12 pF VOUT = 0V CVPP VPP Capacitance 18 25 pF VPP = 0V PN: PM0454_ Patenti#: US#5,526,307 66-8 REV.1.5, FEB 10, 1998vic. AC CHARACTERISTICS MxX26C1000A TA = 0C to 70C, VCC = 5V+ 10% 26C1000A 26C1000A -70 ~90 SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT CONDITIONS tACC Address to Output Delay 70 90 ns CE = OE = VIL (CE Chip Enable to Output Delay 70 90 ns OE = VIL tOE Output Enable to Output Delay 35 40 ns CE = VIL tOF OE High to Output Float, 0 20 ) 25 ns or CE High to Output Float tOH Output Hold from Address, 0 0 ns CE or OE which ever occurred firs 26C1000A 26C1000A 26C1000A -10 -12 15 SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS tACC Address to Output Delay 100 120 150 ns CE = OE = VIL tCE Chip Enable to Output Delay 100 120 150 ns OE = VIL tOE Output Enable to Output Delay 45 50 65 ns CE = VIL tDF OE High to Output Float, 0 30 0 35 QO 50 ns or CE High to Output Float tOH Output Hold from Address, 0 0 0 ns GE or OF which ever occurred first DC PROGRAMMING CHARACTERISTICS TA = 25C +5C SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS VOH Output High Voltage 2.4 Vv IOH = -0.40mA VOL Output Low Voltage 0.4 v IOL = 2.1mA VIH input High Voltage 2.0 VCC + 0.5 v VIL input Low Voltage -0.3 0.8 Vv Itt Input Leakage Current -10 10 uA VIN = 0 to 5.5V VH AQ Auto Select Voltage 11.5 12.5 Vv ICC3 VCC Supply Current (Program/Erase & Verify) 50 mA IPP2 VPP Supply Current(Program)/Erase 50 mA CE = PGM = VIL, OE = VIH VCC2 Programming & Erase Supply Voitage 45 6.5 VPP2 Programming & Erase Voltage 12.5 13.0 IPP AQ AQ Auto Select Current /Erase 1 mA CE = PGM = VIL, OE = VIH P/N: PM0454 Patent: US#5,526,307 66-9 REV.1.5, FEB 10, 1998hM}IiG Mx26C1000A AC PROGRAMMING CHARACTERISTICS TA = 25C + 5C SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS tAS Address Setup Time 2.0 us tOES OE Setup Time 2.0 us tdS Data Setup Time 2.0 us tAH Address Hold Time 0 us tDH Data Hoid Time 2.0 us tDFP CE to Output Float Delay 0 130 ns tVPS VPP Setup Time 2.0 us tPW Program Pulse Width 20 105 us ives VCC Setup Time 2.0 us tDv Data Valid from CE 250 ns tcES CE Setup Time 2.0 us tOE Data valid from OE 150 ns ek tER Erase Recovery Time 0.5 s . tPR Program Recovery Time 2 us tEW Erase Pulse Width 0.5 s tEV Erase Verify Time 200 ns tPV Program Verify Time 200 ns tA9S AQ Setup Time 2.0 us tPVS Program Verify Setup 2 us tEVS Erase Verity Setup 0.5 s WAVEFORMS READ CYCLE ADDRESS INPUTS DATA ADDRESS a tacc CE [ aq (CE ~ OE oo lg (CFO ne VALID DATA << (OH PAN: PM0454 Patent#: US#5,526,307 66-10 REV.1.5, FEB 10, 1998PROGRAMMING WAVEFORMS PROGRAM PROGRAM VERIFY VIH - ri 7 ADDRESS VALID ADDRESS INPUTS vit tAS. a a at DATAINSTABLE DATA OUT VALID tos 10H i << | VPP tvPS - vec wes tPVS aaoeel 1PV ~~ - cE VILL. at tCES | VIH POM ve a (Pw ~~ pA ~ 7 VIH | OE Mb. i022 ----------0- 0-2-2 bee eee ef ERASE WAVEFORMS | | vpP SN ADDRESS) =H S INPUTS Others Not Care Oss ls Erase Erase Verity Ag vit oa oui VPP = VPP / | wes vec =a ~ tEVS | __ VIH OE VIL _ VI CE vit paw VIL P/N: PM0454_ Patent#: US#5,526,307 66-11 REV.1.5, FEB 10, 1998= | ee MxX26C1000A ORDERING INFORMATION PLASTIC PACKAGE PART NO. ACCESS TIME OPERATING CURRENT STANDBY CURRENT PACKAGE (ns) MAX.(mA) _ MAX.(UA) MX26C1000APC-70 70 30 100 32 Pin DIP MX26C1000AMG-70 70 30 100 32 Pin SOP MX26C1000AQC-70 70 30 100 32 Pin PLCC MX26C1000ATC-70 70 30 100 32 Pin TSOP MX26C1000APC-90 90 30 100 32 Pin DIP MX26C1000AMG-90 90 30 100 32 Pin SOP MX26C1000AQC-90 90 30 100 32 Pin PLCC MX26C1000ATC-90 90 30 100 32 Pin TSOP MX26C1000APC-10 100 30 100 32 Pin DIP MX26C1000AMC-10 100 30 100 32 Pin SOP MX26C1000AQC-10 100 30 100 32 Pin PLCC MX26C1000ATC-10 100 30 100 32 Pin TSOP MX26C1000APC-12 120 30 100 32 Pin DIP MX26C1000AMC-12 120 30 100 32 Pin SOP MX26C1000AQC-12 120 30 100 32 Pin PLCC MX26C1000ATC-12 120 30 100 32 Pin TSOP MX26C1000APC-15 150 30 100 32 Pin DIP MX26C1000AMC-15 150 30 100 32 Pin SOP MX26C1000AQC-15 150 30 100 32 Pin PLCC MX26C1000ATC-15 150 30 100 32 Pin TSOP P/N: PM0454 Patent#: US#5,526,307 REV.1.5, FEB 10, 1998 66-12Programming flow chart revised. Mode Select Table, Erase Mode A9=VH-->A9=VPP. Erase flow chart revised. M=Ic MxX26C 1000A Revision History Revision # Description Date 11 Eraseing mode flow chart: Chip erase(5s)---> (1s). 4/10/1997 Programming waveforms: CE changed. 1.2 MTP ROM----> MTP EPROM 5/30/1997 Chip erase(1s)---->0.5s. X = 60?--->200? Switching Test Waveforms revise. tEW Erase Pulse Width 1 sec---> 0.5sec Programming/erase waveforms modifiction. VPP: from 12.0~13V to 12.5~13V. 1.3 Erase Verify Time: 60---->200. 7/25/1997 1.4 Change Part Name: 26C1000 ---> 26C1000A 11/05/1997 1.5 Change tPW:Min. 95us --> Min. 20us 2/10/1998 P/N: PM0454_ Patent: US#5,526,307 66-13 REV.1.5, FEB 10, 1998