8-/10-/12-Bit High Bandwidth Multiplying DACs with Serial Interface AD5426/AD5432/AD5443 Data Sheet FEATURES GENERAL DESCRIPTION 2.5 V to 5.5 V supply operation 50 MHz serial interface 10 MHz multiplying bandwidth 2.5 MSPS update rate INL of 1 LSB for 12-bit DAC 10 V reference input Low glitch energy < 2 nV-s Extended temperature range -40C to +125C 10-lead MSOP Pin-compatible 8-, 10-, and 12-bit current output DACs Guaranteed monotonic 4-quadrant multiplication Power-on reset with brownout detection Daisy-chain mode Readback function 0.4 A typical power consumption The AD5426/AD5432/AD54431 are CMOS 8-, 10-, and 12-bit current output digital-to-analog converters (DACs), respectively. These devices operate from a 2.5 V to 5.5 V power supply, making them suitable for battery-powered applications and many other applications. These DACs use a double buffered, 3-wire serial interface that is compatible with SPI, QSPITM, MICROWIRE, and most DSP interface standards. In addition, a serial data out pin (SDO) allows for daisy-chaining when multiple packages are used. Data readback allows the user to read the contents of the DAC register via the SDO pin. On power-up, the internal shift register and latches are filled with 0s and the DAC outputs are at zero scale. As a result of manufacturing on a CMOS submicron process, the parts offer excellent 4-quadrant multiplication characteristics with large signal multiplying bandwidths of 10 MHz. The applied external reference input voltage, VREF, determines the full-scale output current. An integrated feedback resistor, RFB, provides temperature tracking and full-scale voltage output when combined with an external current to voltage precision amplifier. APPLICATIONS Portable battery-powered applications Waveform generators Analog processing Instrumentation Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming The AD5426/AD5432/AD5443 DACs are available in small, 10-lead MSOPs. The EV-AD5443/46/53SDZ evaluation board is available for evaluating DAC performance. For more information, see the UG-327 evaluation board user guide. FUNCTIONAL BLOCK DIAGRAM VREF VDD AD5426/ AD5432/ AD5443 R 8-/10-/12-BIT R-2R DAC RFB IOUT1 IOUT2 DAC REGISTER POWER-ON RESET CONTROL LOGIC AND INPUT SHIFT REGISTER GND SDO 03162-001 SYNC SCLK SDIN INPUT LATCH Figure 1. 1 Protected by U.S. Patent No. 5,689,257. Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2004-2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5426/AD5432/AD5443 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Operation ....................................................................... 15 Applications ....................................................................................... 1 Single-Supply Applications ....................................................... 17 General Description ......................................................................... 1 Adding Gain ................................................................................ 17 Functional Block Diagram .............................................................. 1 DACs Used as a Divider or Programmable Gain Element ... 18 Revision History ............................................................................... 2 Reference Selection .................................................................... 18 Specifications..................................................................................... 3 Amplifier Selection .................................................................... 18 Timing Characteristics ................................................................ 5 Serial Interface ............................................................................ 20 Absolute Maximum Ratings ............................................................ 6 PCB Layout and Power Supply Decoupling................................ 22 ESD Caution .................................................................................. 6 Overview of the AD5426/AD5432/AD5443 and Related DACs .. 23 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 24 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 24 Terminology .................................................................................... 14 Theory of Operation ...................................................................... 15 REVISION HISTORY 9/15--Rev. G to Rev. H Deleted Positive Output Voltage Section and Figure 45; Renumbered Sequentially.............................................................. 17 Changes to Adding Gain Section ................................................. 17 Changed Overview of AD54xx and AD55xx Devices Section to Overview of the AD5426/AD5432/AD5443 and Related DACs Section .................................................................................. 23 Changes to Ordering Guide .......................................................... 24 6/13--Rev. F to Rev. G Change to General Description Section ........................................ 1 Changes to Ordering Guide .......................................................... 24 7/12--Rev. E to Rev. F No Change to Content, Changed VDD Values in 7/12 Revision History Only ...................................................................................... 2 7/12--Rev. D to Rev. E Changed VDD = 3 V to VDD = 2.5 V ............................. Throughout Changes to Table 2 ............................................................................ 4 Changes to Table 4 ............................................................................ 7 Change to Daisy-Chain Mode Section ........................................ 20 Change to Ordering Guide ............................................................ 24 4/12--Rev. C to Rev. D Changed VDD = 2.5 V to VDD = 3 V ............................. Throughout Changes to General Description Section ...................................... 1 Deleted Microprocessor Interface Section, ADSP-21xx to AD5426/AD5432/AD5443 Interface Section, Figure 51, Figure 52, Table 11, ADSP-BF5x to AD5426/AD5432/AD5443 Interface Section, Figure 53 and Figure 54; Renumbered Sequentially ..................................................................................... 21 Deleted 80C51/80L51 to AD5426/AD5432/AD5443 Interface Section, Figure 55, MC68HC11 Interface to AD5426/AD5432/ AD5443 Interface Section, Figure 56, MICROWIRE to AD5426/AD5432/AD5443 Interface Section, Figure 57, PIC16C6x/7x to AD5426/AD5432/AD5443, and Figure 58 .... 22 Deleted Evaluation Board for the AD5426/AD5432/AD5443 Series of DACs Section, Operating the Evaluation Board Section, and Power Supplies Section ........................................... 23 Deleted Figure 59 and Figure 60................................................... 24 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 Deleted Figure 61............................................................................ 25 Deleted Figure 62............................................................................ 26 2/09--Rev. B to Rev. C Changes to Low Power Serial Interface Section and DaisyChain Mode Section....................................................................... 20 Updated Outline Dimensions ....................................................... 28 11/08--Rev. A to Rev. B Changes to Ordering Guide .......................................................... 28 5/05--Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Specifications .................................................................3 Changes to Figure 42...................................................................... 16 Change to Figure 45 ....................................................................... 17 Change to Figure 46 ....................................................................... 18 Changes to Table 7, Table 8, and Table 9 ..................................... 19 Additions to Microprocessor Interface Section.......................... 21 2/04--Revision 0: Initial Version Rev. H | Page 2 of 24 Data Sheet AD5426/AD5432/AD5443 SPECIFICATIONS VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V; temperature range for Y version: -40C to +125C; all specifications TMIN to TMAX, unless otherwise noted; dc performance measured with OP177; ac performance with AD8038, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE AD5426 Resolution Relative Accuracy Differential Nonlinearity AD5432 Resolution Relative Accuracy Differential Nonlinearity AD5443 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temperature Coefficient1 Output Leakage Current REFERENCE INPUT1 Reference Input Range VREF Input Resistance RFB Resistance Input Capacitance Code Zero Scale Code Full Scale DIGITAL INPUT/OUTPUT1 Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage, VOH Min Typ Max Unit Test Conditions/Comments 8 0.25 0.5 Bits LSB LSB Guaranteed monotonic 10 0.5 1 Bits LSB LSB Guaranteed monotonic 12 1 -1/+2 10 10 20 Bits LSB LSB mV ppm FSR/C nA nA 10 10 10 12 12 V k k 3 5 6 8 pF pF 5 8 8 1.7 0.6 VDD - 1 VDD - 0.5 Output Low Voltage, VOL Input Leakage Current, IIL Input Capacitance DYNAMIC PERFORMANCE1 Reference Multiplying Bandwidth Output Voltage Settling Time Measured to 16 mV of FS Measured to 4 mV of FS Measured to 1 mV of FS Digital Delay 10% to 90% Rise/Fall Time Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error 4 0.4 0.4 1 10 10 50 55 90 40 15 2 70 48 V V V V V V A pF MHz 100 110 160 75 30 ns ns ns ns ns nV-s dB dB Rev. H | Page 3 of 24 Guaranteed monotonic Data = 0x0000, TA = 25C, IOUT1 Data = 0x0000, T = -40C to 125C, IOUT1 Input resistance TC = -50 ppm/C Input resistance TC = -50 ppm/C VDD = 4.5 V to 5 V, ISOURCE = 200 A VDD = 2.5 V to 3.6 V, ISOURCE = 200 A VDD = 4.5 V to 5 V, ISINK = 200 A VDD = 2.5 V to 3.6 V, ISINK = 200 A VREF = 3.5 V; DAC loaded all 1s VREF = 10 V; RLOAD = 100 , DAC latch alternately loaded with 0s and 1s Interface delay time Rise and fall time, VREF = 10 V, RLOAD = 100 1 LSB change around major carry, VREF = 0 V DAC latch loaded with all 0s, VREF = 3.5 1 MHz 10 MHz AD5426/AD5432/AD5443 Parameter Output Capacitance IOUT1 Data Sheet Min IOUT2 Digital Feedthrough Analog THD Digital THD 50 kHz fOUT 20 kHz fOUT Output Noise Spectral Density SFDR Performance (Wide Band) 50 kHz fOUT 20 kHz fOUT SFDR Performance (Narrow Band) 50 kHz fOUT 20 kHz fOUT Intermodulation Distortion POWER REQUIREMENTS Power Supply Range IDD Typ Max Unit Test Conditions/Comments 12 10 22 10 0.1 17 12 25 12 pF pF pF pF nV-s All 0s loaded All 1s loaded All 0s loaded All 1s loaded Feedthrough to DAC output with SYNC high and alternate loading of all 0s and all 1s VREF = 3.5 V p-p, all 1s loaded, f = 1 kHz Clock = 1 MHz, VREF = 3.5 V, CCOMP = 1.8 pF 81 dB 73 74 25 dB dB nV/Hz 75 76 dB dB 87 87 78 dB dB dB Clock = 1 MHz, f1 = 20 kHz, f2 = 25 kHz, VREF = 3.5 V V A A %/% TA = 25C, logic inputs = 0 V or VDD T = -40C to +125C , logic inputs = 0 V or VDD VDD = 5% Clock = 1 MHz, VREF = 3.5 V 2.5 0.4 Power Supply Sensitivity1 1 @ 1 kHz Clock = 1 MHz, VREF = 3.5 V 5.5 0.6 5 0.001 Guaranteed by design and characterization, not subject to production testing. Rev. H | Page 4 of 24 Data Sheet AD5426/AD5432/AD5443 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V; temperature range for Y version: -40C to +125C; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter fSCLK t1 t2 t3 t4 1 t5 t6 t7 t8 t9 2, 3 2.5 V to 5.5 V 50 20 8 8 13 5 3 5 30 80 120 4.5 V to 5.5 V 50 20 8 8 13 5 3 5 30 45 65 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns typ ns max Test Conditions/Comments Max clock frequency SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK active edge setup time Data setup time Data hold time SYNC rising edge to SCLK active edge Minimum SYNC high time SCLK active edge to SDO valid Falling or rising edge as determined by control bits of serial word. Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with load circuit, as shown in Figure 4. 3 SDO operates with a VDD of 3.0 V to 5.5 V. 1 2 t1 SCLK t8 t2 t4 t3 t7 SYNC t6 t5 DB15 DB0 03162-002 DIN ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED. Figure 2. Standalone Mode Timing Diagram t1 SCLK t2 t4 t5 DB15 (N) t8 t6 SYNC SDIN t7 t3 t6 DB0 (N) DB15 (N + 1) DB0 (N + 1) DB15(N) DB0(N) SDO ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED. Figure 3. Daisy-Chain and Readback Modes Timing Diagram Rev. H | Page 5 of 24 03162-003 t9 AD5426/AD5432/AD5443 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VDD to GND VREF, RFB to GND IOUT1, IOUT2 to GND Logic Inputs and Output 1 Operating Temperature Range Extended Industrial (Y Version) Storage Temperature Range Junction Temperature 10-lead MSOP JA Thermal Impedance Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (<20 sec) 1 Rating -0.3 V to +7 V -12 V to +12 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 200A -40C to +125C -65C to +150C 150C 206C/W 300C 235C TO OUTPUT PIN IOL VOH (MIN) + VOL (MAX) 2 CL 20pF 200A IOH Figure 4. Load Circuit for SDO Timing Specifications Overvoltages at SCLK, SYNC, and DIN are clamped by internal diodes. ESD CAUTION Rev. H | Page 6 of 24 03162-004 Transient currents of up to 100 mA do not cause SCR latch-up. TA = 25C, unless otherwise noted. Data Sheet AD5426/AD5432/AD5443 IOUT1 1 IOUT2 2 GND 3 SCLK 4 SDIN 5 AD5426/ AD5432/ AD5443 TOP VIEW (Not to Scale) 10 RFB 9 VREF 8 VDD 7 SDO 6 SYNC 03162-005 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic IOUT1 IOUT2 GND SCLK 5 SDIN 6 SYNC 7 SDO 8 9 10 VDD VREF RFB Description DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Digital Ground Pin. Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device may be configured such that data is clocked into the shift register on the rising edge of SCLK. The device can accommodate clock rates up to 50 MHz. Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to rising edge. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the mode, the serial interface counts clocks, and data is latched to the shift register on the 16th active clock edge. Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes the DAC register contents available for readback on the SDO pin, clocked out on the opposite edges to the active clock edge. SDO operates with a VDD of 3.0 V to 5.5 V. Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. DAC Reference Voltage Input. DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output. Rev. H | Page 7 of 24 AD5426/AD5432/AD5443 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.20 0.20 0.10 0.10 0.05 0.05 TA = 25C VREF = 10V 0.15 VDD = 5V -0.05 0 -0.05 -0.10 -0.10 -0.15 -0.15 0 50 100 150 200 250 CODE -0.20 0 50 TA = 25C 0.4 VREF = 10V VDD = 5V 0.3 0.3 0.2 0.2 0.1 0.1 DNL (LSB) 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 200 400 600 800 10000 CODE -0.5 03162-007 0 0 200 800 1000 4000 Figure 10. DNL vs. Code (10-Bit DAC) 1.0 1.0 TA = 25C 0.8 VREF = 10V VDD = 5V 0.4 0.4 0.2 0.2 DNL (LSB) 0.6 TA = 25C 0.8 VREF = 10V VDD = 5V 0.6 0 -0.2 0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 1000 1500 2000 2500 CODE 3000 3500 4000 03162-008 -0.4 500 600 CODE Figure 7. INL vs. Code (10-Bit DAC) 0 400 03162-010 iNL (LSB) 250 0.5 TA = 25C 0.4 VREF = 10V VDD = 5V INL (LSB) 200 Figure 9. DNL vs. Code (8-Bit DAC) 0.5 -1.0 150 CODE Figure 6. INL vs. Code (8-Bit DAC) -0.5 100 03162-011 -0.20 03162-009 INL (LSB) 0 03162-006 INL (LSB) TA = 25C VREF = 10V 0.15 VDD = 5V Figure 8. INL vs. Code (12-Bit DAC) -1.0 0 500 1000 1500 2000 2500 CODE 3000 Figure 11. DNL vs. Code (12-Bit DAC) Rev. H | Page 8 of 24 3500 Data Sheet AD5426/AD5432/AD5443 2.0 0.6 0.5 1.5 MAX INL 0.4 TA = 25C VDD = 5V AD5443 MIN INL -1.0 MIN DNL -1.5 -0.2 3 4 5 6 7 REFERENCE VOLTAGE 8 9 10 -2.0 0.5 03162-012 2 Figure 12. INL vs. Reference Voltage -0.40 0.7 0.8 0.9 1.0 1.1 VBIAS (V) 1.2 1.3 1.4 1.5 2.0 1.5 Figure 15. Linearity vs. VBIAS Voltage Applied to IOUT2 4 TA = 25C VDD = 5V AD5443 -0.45 0.6 03162-015 MIN INL 03162-016 -0.1 TA = 25C VREF = 2.5V VDD = 3V AD5443 3 2 -0.50 MAX DNL MAX INL 1 0 -0.55 LSB DNL (LSB) MAX DNL -0.5 0 -0.3 TA = 25C 0.5 VREF = 0V VDD = 3V AD5443 0 03162-017 0.1 LSB INL (LSB) 0.3 0.2 MAX INL 1.0 -0.60 -1 MIN DNL -2 MIN INL -3 MIN DNL -0.65 -4 2 3 4 5 6 7 REFERENCE VOLTAGE 8 9 10 -5 03162-013 -0.70 Figure 13. DNL vs. Reference Voltage 5 4 0.4 0.6 0.8 1.0 1.2 VBIAS (V) 1.4 1.6 1.8 0.5 TA = 25C 0.4 VREF = 0V VDD = 3V AND 5V 3 0.3 VDD = 5V 2 0.2 0 VOLTAGE (mV) 1 VDD = 3V -1 -2 0.1 -0.2 -4 -0.4 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 140 Figure 14. Gain Error vs. Temperature OFFSET ERROR -0.1 -0.3 -40 GAIN ERROR 0 -3 03162-014 ERROR (mV) 0.2 Figure 16. Linearity vs. VBIAS Voltage Applied to IOUT2 VREF = 10V -5 -60 0 -0.5 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VBIAS (V) 1.2 1.3 1.4 Figure 17. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2 Rev. H | Page 9 of 24 AD5426/AD5432/AD5443 Data Sheet 0.5 0.7 TA = 25C 0.4 VREF = 2.5V VDD = 3V AND 5V GAIN ERROR 0.3 0.5 0.2 0.1 CURRENT (mA) VOLTAGE (mV) TA = 25C 0.6 OFFSET ERROR 0 -0.1 -0.2 VDD = 5V 0.4 0.3 0.2 -0.3 0.1 -0.4 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VBIAS (V) 0 Figure 18. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2 0 1 2 3 INPUT VOLTAGE (V) 4 5 03162-021 VDD = 3V 0 03162-018 -0.5 Figure 21. Supply Current vs. Logic Input Voltage, SYNC (SCLK), DATA = 0 3 1.6 TA = 25C VREF = 0V VDD = 5V 2 AD5443 MAX INL 1.4 1.2 IOUT LEAKAGE (nA) MAX DNL MIN INL -2 1.0 0.6 0.4 IOUT1 VDD 3V 0.2 MIN DNL -3 0.5 0.8 1.5 2.0 2.5 VBIAS (V) 0 -40 20 40 60 TEMPERATURE (C) 80 100 120 0.50 4 TA = 25C = 2.5V V 3 REF VDD = 5V AD5443 2 0.45 0.40 CURRENT (A) 0 MAX INL MIN DNL -1 -2 -3 1.5 VBIAS (V) ALL 1s 0.25 0.20 VDD = 3V 0.15 ALL 1s ALL 0s 0.05 2.0 03162-020 1.0 ALL 0s 0.30 0.10 MIN INL -4 VDD = 5V 0.35 MAX DNL 1 LSB 0 Figure 22. IOUT1 Leakage Current vs. Temperature Figure 19. Linearity vs. VBIAS Voltage Applied to IOUT2 -5 0.5 -20 03162-022 -1 IOUT1 VDD 5V 1.0 0 -60 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 Figure 23. Supply Current vs. Temperature Figure 20. Linearity vs. VBIAS Voltage Applied to IOUT2 Rev. H | Page 10 of 24 120 140 03162-023 0 03162-019 LSB 1 Data Sheet AD5426/AD5432/AD5443 3.5 3 TA = 25C AD5443 3.0 LOADING 010101010101 VREF = 0.15V, AD8038 CC 1pF VREF = 2V, AD8038 CC 1pF 0 VREF = 3.51V, AD8038 CC 1.8pF 2.0 1.5 GAIN (dB) VCC = 5V 1 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M -9 10k 0.060 ALL ON DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ALL OFF 100 1k 10k 100k FREQUENCY (Hz) TA = 25C VDD = 5V VREF = 3.5V CCOMP = 1.8pF AD8038 AMPLIFIER 10M 100M OUTPUT VOLTAGE (V) 0.040 1M 0.020 VDD 3V, 0V REF NRG = 1.877nVs 0x7FF TO 0x800 0.010 0 VDD 5V, 0V REF NRG = 0.119nVs, 0x800 TO 0x7FF -0.020 0 OUTPUT VOLTAGE (V) -0.4 TA = 25C VDD = 5V VREF = 3.5V CCOMP = 1.8pF AD8038 AMPLIFIER 100 200 250 300 TA = 25C VREF = 3.5V AD8038 AMPLIFIER CCOMP = 1.8pF AD5443 -1.72 VDD 3V, 3.5V REF NRG = 1.433nVs 0x7FF TO 0x800 -1.73 VDD 3V, 3.5V REF NRG = 0.647nVs 0x800 TO 0x7FF -1.74 -1.75 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M 03162-026 10 150 TIME (ns) VDD 5V, 3.5V REF NRG = 1.184nVs 0x7FF TO 0x800 -1.71 -0.2 100 Figure 28. Midscale Transition VREF = 0 V 0 GAIN (dB) 50 -1.70 1 100M VDD 3V, 0V REF NRG = 0.088nVs 0x800 TO 0x7FF 0.030 -0.010 0.2 -0.8 10M TA = 25C VREF = 0V AD8038 AMPLIFIER CCOMP = 1.8pF AD5443 VDD 5V, 0V REF NRG = 2.049nVs 0x7FF TO 0x800 0.050 Figure 25. Reference Multiplying Bandwidth vs. Frequency and Code -0.6 1M FREQUENCY (Hz) Figure 27. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor 03162-025 6 LOADING 0 ZS TO FS -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 -96 -102 1 10 100k 03162-027 100 03162-028 10 03162-024 1 TA = 25C VDD = 5V AD8038 AMPLIFIER Figure 24. Supply Current vs. Update Rate GAIN (dB) VREF = 0.15V, AD8038 CC 1.47pF -6 VCC = 3V 0.5 0 VREF = 2V, AD8038 CC 1.47pF -3 Figure 26. Reference Multiplying Bandwidth--All 1s Loaded -1.76 VDD 5V, 3.5V REF, NRG = 0.364nVs, 0x800 TO 0x7FF 0 50 100 150 TIME (ns) 200 250 Figure 29. Midscale Transition VREF = 3.5 V Rev. H | Page 11 of 24 300 03162-029 IDD (mA) 2.5 AD5426/AD5432/AD5443 Data Sheet 20 100 TA = 25C VDD = 3V 0 AMPLIFIER = AD8038 MCLK = 200kHz 80 MCLK = 500kHz MCLK = 1MHz -40 -60 SFDR (dB) FULL SCALE -80 60 40 ZERO SCALE 20 TA = 25C VREF = 3.5V AD8038 AMP AD5443 -100 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 10M 0 03162-030 -120 0 10 40 50 Figure 33. Wideband SFDR vs. fOUT Frequency (AD5443) 80 TA = 25C VDD = 3V VREF = 3.5V p-p -65 30 fOUT (kHz) Figure 30. Power Supply Rejection vs. Frequency -60 20 03162-034 PSRR (dB) -20 MCLK = 500kHz MCLK = 1MHz 60 MCLK = 200kHz SFDR (dB) THD + N (dB) -70 -75 40 -80 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 03162-031 -90 TA = 25C VREF = 3.5V AD8038 AMP AD5426 0 0 10 30 40 50 fOUT (kHz) Figure 34. Wideband SFDR vs. fOUT Frequency (AD5426) Figure 31. THD and Noise vs. Frequency 1.8 20 03162-035 20 -85 0 TA = 25C TA = 25C VREF = 3.5V AD8038 AMPLIFIER AD5443 -10 1.6 -20 VIH -30 1.0 VIL 0.8 -40 -50 -60 0.6 -70 0.4 -80 0.2 -90 0 2.5 3.0 3.5 4.0 VOLTAGE (V) 4.5 5.0 5.5 -100 0 50 100 150 200 250 300 350 FREQUENCY (Hz) 400 450 500 Figure 35. Wideband SFDR fOUT = 50 kHz, Update = 1 MHz Figure 32. Threshold Voltages vs. Supply Voltage Rev. H | Page 12 of 24 03162-036 SFDR (dB) 1.2 03162-033 THRESHOLD VOLTAGE (V) 1.4 Data Sheet AD5426/AD5432/AD5443 -20 -20 -30 -40 -40 SFDR (dB) -30 -50 -60 -50 -60 -70 -70 -80 -80 -90 -100 10 50 100 150 200 250 300 350 FREQUENCY (Hz) 400 450 500 03162-037 -90 -100 0 Figure 36. Wideband SFDR fOUT = 20 kHz, Update = 1 MHz 0 -20 0 -10 -20 -30 -40 -40 -50 -50 dB -30 -60 -70 -70 -80 -80 -90 -90 30 35 40 45 50 55 FREQUENCY (Hz) 60 65 70 75 Figure 37. Narrowband (50%) SFDR fOUT = 50 kHz, Update = 1 MHz 03162-038 -60 -100 25 12 14 16 18 20 22 FREQUENCY (Hz) 24 26 28 30 Figure 38. Narrowband (50%) SFDR fOUT = 20 kHz, Update = 1 MHz TA = 25C VREF = 3.5V AD8038 AMPLIFIER AD5443 -10 SFDR (dB) TA = 25C VREF = 3.5V AD8038 AMPLIFIER AD5443 -10 03162-039 -10 SFDR (dB) 0 TA = 25C VREF = 3.5V AD8038 AMPLIFIER AD5443 TA = 25C VREF = 3.5V AD8038 AMPLIFIER AD5443 -100 10 15 20 25 FREQUENCY (Hz) 30 35 03162-040 0 Figure 39. Narrowband (50%) IMD fOUT = 20 kHz, 25 kHz, Update = 1 MHz Rev. H | Page 13 of 24 AD5426/AD5432/AD5443 Data Sheet TERMINOLOGY Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for 0 and full scale and is normally expressed in LSBs or as a percentage of full-scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of -1 LSB maximum over the operating temperature range ensures monotonicity. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is VREF - 1 LSB. Gain error of the DACs is adjustable to 0 with external resistance. Output Leakage Current Output leakage current is current that flows in the DAC ladder switches when these are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current flows in the IOUT2 line when the DAC is loaded with all 1s. Output Capacitance Capacitance from IOUT1 or IOUT2 to AGND. Output Current Settling Time This is the amount of time it takes for the output to settle to a specified level for a full-scale input change. For these devices, it is specified with a 100 resistor to ground. The settling time specification includes the digital delay from SYNC rising edge to the full-scale output charge. Digital-to-Analog Glitch Impulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-s or nV-s depending upon whether the glitch is measured as a current or voltage signal. Digital Feedthrough When the device is not selected, high frequency logic activity on the device digital inputs may be capacitively coupled to show up as noise on the IOUT pins and subsequently into the following circuitry. This noise is digital feedthrough. Multiplying Feedthrough Error This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal, when all 0s are loaded to the DAC. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonics are included, such as second to fifth. THD = 20 log (V 2 2 + V3 2 + V4 2 + V5 2 ) V1 Digital Intermodulation Distortion Second-order intermodulation distortion (IMD) measurements are the relative magnitude of the fa and fb tones generated digitally by the DAC and the second-order products at 2fa - fb and 2fb - fa. Spurious-Free Dynamic Range (SFDR) SFDR is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. It is the measure of the difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling rate, or fS/2). Narrow band SFDR is a measure of SFDR over an arbitrary window size, in this case 50% of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave. Rev. H | Page 14 of 24 Data Sheet AD5426/AD5432/AD5443 THEORY OF OPERATION The AD5426, AD5432, and AD5443 are 8-, 10-, and 12-bit current output DACs consisting of a standard inverting R-2R ladder configuration. A simplified diagram for the 8-bit AD5426 is shown in Figure 40. The matching feedback resistor, RFB, has a value of R. The value of R is typically 10 k (minimum 8 k and maximum 12 k). If IOUT1 and IOUT2 are kept at the same potential, a constant current flows in each ladder leg, regardless of digital input code. Therefore, the input resistance presented at VREF is always constant and nominally of value R. The DAC output (IOUT) is code-dependent, producing various resistances and capacitances. External amplifier choice should take into account the variation in impedance generated by the DAC on the amplifiers inverting input node. R R R These DACs are designed to operate with either negative or positive reference voltages. The VDD power pin is used by only the internal digital logic to drive the DAC switches' on and off states. These DACs are also designed to accommodate ac reference input signals in the range of -10 V to +10 V. With a fixed 10 V reference, the circuit shown in Figure 41 gives a unipolar 0 V to -10 V output voltage swing. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. Table 5 shows the relationship between digital code and expected output voltage for unipolar operation (AD5426, 8-bit device). Table 5. Unipolar Code Table 2R 2R 2R 2R S1 S2 S3 S8 2R DAC DATA LATCHES AND DRIVERS R RFBA IOUT1 IOUT2 Digital Input 1111 1111 1000 0000 0000 0001 0000 0000 03162-041 VREF Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. Analog Output (V) -VREF (255/256) -VREF (128/256) = -VREF/2 -VREF (1/256) -VREF (0/256) = 0 Figure 40. Simplified Ladder VDD VDD VREF VREF C1 RFB IOUT1 A1 A1 IOUT2 SYNC SCLK SDIN GND MICROCONTROLLER VOUT = 0 TO -VREF AGND NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. CIRCUIT OPERATION Unipolar Mode Using a single op amp, these devices can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 41. When an output amplifier is connected in unipolar mode, the output voltage is given by VOUT = - VREF x R1 AD5426/ AD5432/ AD5443 R2 D 2n where D is the fractional representation of the digital word loaded to the DAC, and n is the number of bits. D = 0 to 255 (8-bit AD5426) = 0 to 1023 (10-bit AD5432) = 0 to 4095 (12-bit AD5443) Rev. H | Page 15 of 24 Figure 41. Unipolar Operation 03162-042 Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of the DAC, making the device extremely versatile and allowing it to be configured in several different operating modes. For example, it can be configured to provide a unipolar output, 4-quadrant multiplication in bipolar or single-supply modes of operation. Note that a matching switch is used in series with the internal RFB feedback resistor. If users attempt to measure RFB, power must be applied to VDD to achieve continuity. AD5426/AD5432/AD5443 Data Sheet Bipolar Operation Table 6. Bipolar Code Table In some applications, it may be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. This can easily be accomplished by using another external amplifier and some external resistors, as shown in Figure 42. In this circuit, the second amplifier, A2, provides a gain of 2. Biasing the external amplifier with an offset from the reference voltage results in full 4-quadrant multiplying operation. The transfer function of this circuit shows that both negative and positive output voltages are created as the input data, D, which is incremented from code zero (VOUT = -VREF) to midscale (VOUT = 0 V) to full scale (VOUT = +VREF). Digital Input 1111 1111 1000 0000 0000 0001 0000 0000 Analog Output (V) +VREF (127/128) 0 -VREF (127/128) -VREF (128/128) Stability In the I-to-V configuration, the IOUT of the DAC and the inverting node of the op amp must be connected as close as possible and proper PCB layout techniques must be employed. Since every code change corresponds to a step function, gain peaking may occur if the op amp has limited gain bandwidth product (GBP) and there is excessive parasitic capacitance at the inverting node. This parasitic capacitance introduces a pole into the open-loop response that can cause ringing or instability in closed-loop applications. D VOUT = VREF x n - 1 - VREF 2 where D is the fractional representation of the digital word loaded to the DAC and n is the resolution of the DAC. An optional compensation capacitor, C1, can be added in parallel with RFB for stability, as shown in Figure 41 and Figure 42. Too small a value of C1 can produce ringing at the output, while too large a value can adversely affect the settling time. C1 should be found empirically, but 1 pF to 2 pF is generally adequate for compensation. D = 0 to 255 (8-bit AD5426) = 0 to 1023 (10-bit AD5432) = 0 to 4095 (12-bit AD5443) When VIN is an ac signal, the circuit performs 4-quadrant multiplication. Table 6 shows the relationship between digital code and the expected output voltage for bipolar operation (AD5426, 8-bit device). R3 20k VDD 10V R1 VREF AD5426/ AD5432/ AD5443 RFB IOUT1 IOUT2 C1 A1 A1 A2 VOUT = -VREF TO +VREF SYNC SCLK SDIN GND MICROCONTROLLER R4 10k AGND NOTES 1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC. 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER. Figure 42. Bipolar Operation Rev. H | Page 16 of 24 03162-043 VDD VREF R5 20k R2 Data Sheet AD5426/AD5432/AD5443 VDD SINGLE-SUPPLY APPLICATIONS Current Mode Operation These DACs are specified and tested to guarantee operation in single-supply applications. In the current mode circuit of Figure 43, IOUT2 and hence IOUT1 is biased positive by an amount applied to VBIAS. RFB VIN R1 R2 VDD A1 IOUT1 VOUT VREF GND VDD VIN IOUT1 VREF IOUT2 A1 A1 VOUT Figure 44. Single-Supply Voltage Switching Mode Operation GND It is important to note that VIN is limited to low voltages because the switches in the DAC ladder no longer have the same source drain drive voltage. As a result, their on resistance differs, which degrades the linearity of the DAC. A2 NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Also, VIN must not go negative by more than 0.3 V or an internal diode turns on, exceeding the maximum ratings of the device. In this type of application, the full range of multiplying capability of the DAC is lost. 03162-044 VBIAS 03162-045 RFB Figure 43. Single-Supply Current Mode Operation ADDING GAIN In this configuration, the output voltage is given by VOUT = {D x (RFB/RDAC) x (VBIAS - VIN)} + VBIAS As D varies from 0 to 255 (AD5426), 1023 (AD5432) or 4095 (AD5443), the output voltage varies from VOUT = VBIAS to VOUT = 2 VBIAS - VIN VBIAS should be a low impedance source capable of sinking and sourcing all possible variations in current at the IOUT2 terminal without any problems. It is important to note that VIN is limited to low voltages because the switches in the DAC ladder no longer have the same source drain drive voltage. As a result, their on resistance differs, which degrades the linearity of the DAC. See Figure 15 to Figure 20. Voltage Switching Mode of Operation Figure 44 shows these DACs operating in the voltage switching mode. The reference voltage, VIN, is applied to the IOUT1 pin, IOUT2 is connected to AGND, and the output voltage is available at the VREF terminal. In this configuration, a positive reference voltage results in a positive output voltage, making single-supply operation possible. The output from the DAC is voltage at a constant impedance (the DAC ladder resistance), thus an op amp is necessary to buffer the output voltage. The reference input no longer sees a constant input impedance, but one that varies with code. Therefore, the voltage input should be driven from a low impedance source. In applications where the output voltage is required to be greater than VIN, gain can be added with an additional external amplifier or it can be achieved in a single stage. It is important to consider the effect of temperature coefficients of the thin film resistors of the DAC. Simply placing a resistor in series with the RFB resistor causes mismatches in the temperature coefficients, resulting in larger gain temperature coefficient errors. Instead, the circuit shown in Figure 45 is a recommended method of increasing the gain of the circuit. R1, R2, and R3 should all have similar temperature coefficients, but they need not match the temperature coefficients of the DAC. This approach is recommended in circuits where gains of greater than 1 are required. Note that RFB is much greater than R2||R3 and that a gain error percentage of 100 x (R2||R3)/RFB must be taken into consideration. VDD VDD VIN R1 RFB IOUT1 VREF IOUT2 GND C1 A1 VOUT R3 R2 GAIN = R2 + R3 R2 R1 = R2R3 R2 + R3 NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 45. Increasing Gain of Current Output DAC Rev. H | Page 17 of 24 03162-047 VDD NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. C1 AD5426/AD5432/AD5443 Data Sheet DACS USED AS A DIVIDER OR PROGRAMMABLE GAIN ELEMENT Current-steering DACs are very flexible and lend themselves to many different applications. If this type of DAC is connected as the feedback element of an op amp and RFB is used as the input resistor as shown in Figure 46, then the output voltage is inversely proportional to the digital input fraction, D. For D = 1 - 2-n the output voltage is VOUT = -VIN/D = -VIN/(1 - 2-N) As D is reduced, the output voltage increases. For small values of D, it is important to ensure that the amplifier does not saturate and also that the required accuracy is met. For example, an 8-bit DAC driven with the binary code 0x10 (00010000), that is, 16 decimal, in the circuit of Figure 46 should cause the output voltage to be 16 x VIN. However, if the DAC has a linearity specification of 0.5 LSB, then D can in fact have the weight anywhere in the range 15.5/256 to 16.5/256 so that the possible output voltage will be in the range 15.5 VIN to 16.5 VIN--an error of +3% even though the DAC itself has a maximum error of 0.2%. DAC leakage current is also a potential error source in divider circuits. The leakage current must be counterbalanced by an opposite current supplied from the op amp through the DAC. Since only a fraction D of the current into the VREF terminal is routed to the IOUT1 terminal, the output voltage has to change as follows: Output Error Voltage due to DAC Leakage = (Leakage x R)/D where R is the DAC resistance at the VREF terminal. For a DAC leakage current of 10 nA, R = 10 k, and a gain (that is, 1/D) of 16, the error voltage is 1.6 mV. VDD VIN RFB IOUT2 VREF Table 7 suggests some references available from Analog Devices that are suitable for use with this range of current output DACs. AMPLIFIER SELECTION The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. The input offset voltage of an op amp is multiplied by the variable gain (due to the code-dependent output resistance of the DAC) of the circuit. A change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifier's input offset voltage. This output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, could cause the DAC to be nonmonotonic. In general, the input offset voltage should be a fraction (approximately <1/4) of an LSB to ensure monotonic behavior when stepping through codes. Common-mode rejection of the op amp is important in voltage switching circuits since it produces a code-dependent error at the voltage output of the circuit. Most op amps have adequate common-mode rejection at an 8-, 10-, or 12-bit resolution. GND 03162-048 VOUT ADDITIONAL PINS OMITTED FOR CLARITY. When selecting a reference for use with the AD5426 series of current output DACs, pay attention to the references output voltage temperature coefficient specification. This parameter not only affects the full-scale error, but can also affect the linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy specifications. For example, an 8-bit system required to hold its overall specification to within 1 LSB over the temperature range 0C to 50C dictates that the maximum system drift with temperature should be less than 78 ppm/C. A 12-bit system with the same temperature range to overall specification within 2 LSBs requires a maximum drift of 10 ppm/C. By choosing a precision reference with low output temperature coefficient this error source can be minimized. The input bias current of an op amp also generates an offset at the voltage output as a result of the bias current flowing in the feedback resistor, RFB. Most op amps have input bias currents low enough to prevent any significant errors in 12-bit applications. VDD IOUT1 REFERENCE SELECTION Figure 46. Current Steering DAC as a Divider or Programmable Gain Element Provided the DAC switches are driven from true wideband low impedance sources (VIN and AGND), they settle quickly. Consequently, the slew rate and settling time of a voltage switching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, it is important to minimize capacitance at the VREF of the DAC. This is done by using low input capacitance buffer amplifiers and careful board design. Most single-supply circuits include ground as part of the analog signal range, which in turn requires an amplifier that can handle rail-to-rail signals. There is a large range of single-supply amplifiers available from Analog Devices. Rev. H | Page 18 of 24 Data Sheet AD5426/AD5432/AD5443 Table 7. Suitable ADI Precision References Part No. ADR01 ADR01 ADR02 ADR02 ADR03 ADR03 ADR06 ADR06 ADR431 ADR435 ADR391 ADR395 Output Voltage (V) 10 10 5 5 2.5 2.5 3 3 2.5 5 2.5 5 Initial Tolerance (%) 0.05 0.05 0.06 0.06 0.10 0.10 0.10 0.10 0.04 0.04 0.16 0.10 Temp Drift (ppm/C) 3 9 3 9 3 9 3 9 3 3 9 9 ISS (mA) 1 1 1 1 1 1 1 1 0.8 0.8 0.12 0.12 Output Noise V p-p 20 20 10 10 6 6 10 10 3.5 8 5 8 Package SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 TSOT-23, SC70 SOIC-8 SOIC-8 TSOT-23 TSOT-23 IB (Max) (nA) 0.1 2 0.05 0.001 0.1 0.1 Hz to 10 Hz Noise (V p-p) 0.5 0.4 1 2.3 0.5 Supply Current (A) 600 500 975 50 850 Package SOIC-8 MSOP, SOIC-8 MSOP, SOIC-8 TSOT TSOT, SOIC-8 Slew Rate (V/s) 180 100 425 1,300 VOS (Max) (V) 1,500 1,000 3,000 10,000 IB (Max) (nA) 6,000 10,500 750 7,000 Table 8. Suitable ADI Precision Op Amps Part No. OP97 OP1177 AD8551 AD8603 AD8628 Supply Voltage (V) 2 to 20 2.5 to 15 2.7 to 5 1.8 to 6 2.7 to 6 VOS (Max) (V) 25 60 5 50 5 Table 9. Suitable ADI High Speed Op Amps Part No. AD8065 AD8021 AD8038 AD9631 Supply Voltage (V) 5 to 24 2.5 to 12 3 to 12 2 to 6 BW @ ACL (MHz) 145 490 350 320 Rev. H | Page 19 of 24 Package SOIC-8, SOT-23, MSOP SOIC-8, MSOP SOIC-8, SC70-5 SOIC-8 AD5426/AD5432/AD5443 Data Sheet Low Power Serial Interface DAC Control Bits C3 to C0 Control Bits C3 to C0 allow control of various functions of the DAC, as seen in Table 10. Default settings of the DAC on power-on are as follows: Data is clocked into the shift register on falling clock edges and daisy-chain mode is enabled. Device powers on with zero-scale load to the DAC register and IOUT lines. The DAC control bits allow the user to adjust certain features on power-on, for example, daisy-chaining may be disabled if not in use, active clock edge may be changed to rising edge, and DAC output may be cleared to either zero scale or midscale. The user may also initiate a readback of the DAC register contents for verification purposes. Table 10. DAC Control Bits C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DB0 (LSB) C1 C0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function Implemented No operation (power-on default) Load and update Initiate readback Reserved Reserved Reserved Reserved Reserved Reserved Daisy-chain disable Clock data to shift register on rising edge Clear DAC output to zero scale Clear DAC output to midscale Reserved Reserved Reserved X X X X DATA BITS CONTROL BITS Figure 47. AD5426 8-Bit Input Shift Register Contents DB15 (MSB) C2 DB0 (LSB) C1 C0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CONTROL BITS X X DATA BITS 03162-050 C3 Figure 48. AD5432 10-Bit Input Shift Register Contents DB15 (MSB) C3 C2 DB0 (LSB) C1 C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CONTROL BITS To minimize the power consumption of the device, the interface powers up fully only when the device is being written to, that is, on the falling edge of SYNC. The SCLK and DIN input buffers are powered down on the rising edge of SYNC. The SYNC of the AD5426/AD5432/AD5443 needs to be synchronous with the microprocessor control. Unfinished data frames are latched into the part and will affect the output. C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 DATA BITS 03162-051 The AD5426/AD5432/AD5443 have an easy to use 3-wire interface that is compatible with SPI/QSPI/MICROWIRE and DSP interface standards. Data is written to the device in 16 bit words. This 16-bit word consists of 4 control bits and either 8 , 10 , or 12 data bits as shown in Figure 47, Figure 48, and Figure 49. The AD5443 uses all 12 bits of DAC data. The AD5432 uses 10 bits and ignores the 2 LSBs, while the AD5426 uses 8 bits and ignores the last 4 bits. C3 03162-049 DB15 (MSB) SERIAL INTERFACE Figure 49. AD5443 12-Bit Input Shift Register Contents SYNC Function SYNC is an edge-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the device only while SYNC is low. To start the serial data transfer, SYNC should be taken low observing the minimum SYNC falling to SCLK falling edge setup time, t4. Daisy-Chain Mode Daisy-chain is the default power-on mode. Note that the SDO line operates with a VDD of 3.0 V to 5.5 V. To disable the daisy chain function, write 1001 to the control word. In daisy-chain mode, the internal gating on SCLK is disabled. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK (this is the default, use the control word to change the active edge) and is valid for the next device on the falling edge (default). By connecting this line to the DIN input on the next device in the chain, a multidevice interface is constructed. Sixteen clock pulses are required for each device in the system. Therefore, the total number of clock cycles must equal 16 N where N is the total number of devices in the chain. See the timing diagram in Figure 4. When the serial transfer to all devices is complete, SYNC should be taken high. This prevents any further data being clocked into the input shift register. A burst clock containing the exact number of clock cycles may be used and SYNC taken high some time later. After the rising edge of SYNC, data is automatically transferred from each device's input shift register to the addressed DAC. When control bits = 0000, the device is in no operation mode. This may be useful in daisy-chain applications where the user does not want to change the settings of a particular DAC in the chain. Simply write 0000 to the control bits for that DAC and the following data bits will be ignored. To re-enable the daisychain mode, if disabled, a power recycle is required. Rev. H | Page 20 of 24 Data Sheet AD5426/AD5432/AD5443 Standalone Mode After power-on, write 1001 to the control word to disable daisychain mode. The first falling edge of SYNC resets a counter that counts the number of serial clocks, ensuring the correct number of bits are shifted in and out of the serial shift registers. A rising edge on SYNC during a write causes the write cycle to be aborted. After the falling edge of the 16th SCLK pulse, data is automatically transferred from the input shift register to the DAC. For another serial transfer to take place, the counter must be reset by the falling edge of SYNC. Rev. H | Page 21 of 24 AD5426/AD5432/AD5443 Data Sheet PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5426/AD5432/AD5443 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the DAC is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close to the device as possible. The DAC should have ample supply bypassing of 10 F in parallel with 0.1 F on the supply located as close to the package as possible, ideally right up against the device. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Low ESR, 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. It is good practice to employ compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between VREF and RFB should also be matched to minimize gain error. To maximize on high frequency performance, the I-to-V amplifier should be located as close to the device as possible. Rev. H | Page 22 of 24 Data Sheet AD5426/AD5432/AD5443 OVERVIEW OF THE AD5426/AD5432/AD5443 AND RELATED DACs Table 11. Part No. AD5424 AD5426 AD5428 AD5429 AD5450 AD5432 AD5433 AD5439 AD5440 AD5451 AD5443 AD5444 AD5415 AD5405 AD5445 AD5447 AD5449 AD5452 AD5446 AD5453 AD5553 AD5556 AD5555 AD5557 AD5543 AD5546 AD5545 AD5547 Resolution 8 8 8 8 8 10 10 10 10 10 12 12 12 12 12 12 12 12 14 14 14 14 14 14 16 16 16 16 No. DACs 1 1 2 2 1 1 1 2 2 1 1 1 2 2 2 2 2 1 1 1 1 1 2 2 1 1 2 2 INL (LSB) 0.25 0.25 0.25 0.25 0.25 0.5 0.5 0.5 0.5 0.25 1 0.5 1 1 1 1 1 0.5 1 2 1 1 1 1 2 2 2 2 Interface Parallel Serial Parallel Serial Serial Serial Parallel Serial Parallel Serial Serial Serial Serial Parallel Parallel Parallel Serial Serial Serial Serial Serial Parallel Serial Parallel Serial Parallel Serial Parallel Package RU-16, CP-20 RM-10 RU-20 RU-10 RJ-8 RM-10 RU-20, CP-20 RU-16 RU-24 RJ-8 RM-10 RM-8 RU-24 CP-40 RU-20, CP-20 RU-24 RU-16 RJ-8, RM-8 RM-8 UJ-8, RM-8 RM-8 RU-28 RM-8 RU-38 RM-8 RU-28 RU-16 RU-38 Rev. H | Page 23 of 24 Features 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 50 MHz serial interface 10 MHz BW, 50 MHz serial 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 17 ns CS pulse width 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 10 MHz BW, 50 MHz serial 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width 4 MHz BW, 50 MHz serial clock 4 MHz BW, 20 ns WR pulse width AD5426/AD5432/AD5443 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 15 MAX 1.10 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.15 6 0 0.70 0.55 0.40 0.23 0.13 COMPLIANT TO JEDEC STANDARDS MO-187-BA 091709-A 0.95 0.85 0.75 Figure 50. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5426YRM AD5426YRM-REEL7 AD5426YRMZ AD5426YRMZ-REEL AD5426YRMZ-REEL7 AD5432YRMZ AD5432YRMZ-REEL AD5432YRMZ-REEL7 AD5443YRM AD5443YRM-REEL AD5443YRM-REEL7 AD5443YRMZ AD5443YRMZ-REEL AD5443YRMZ-REEL7 EV-AD5443/46/53SDZ 1 Resolution (Bit) 8 8 8 8 8 10 10 10 12 12 12 12 12 12 INL (LSB) 0.25 0.25 0.25 0.25 0.25 0.5 0.5 0.5 1 1 1 1 1 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked. (c)2004-2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03162-0-9/15(H) Rev. H | Page 24 of 24 Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 Branding D1Q D1Q D6W D6W D6W D1R# D1R# D1R# D1S D1S D1S D1S# D1S# D1S#