UC3848DWG4 - Texas Instruments High-Performance Analog

UC1848

UC2848

UC3848

SLUS225A - April 1996 - REVISED MARCH 2004

FEATURES

•Practical Primary Side Control of

Isolated Power Supplies with DC

Control of Secondary Side Current

•Accurate Programmable Maximum

Duty Cycle Clamp

•Maximum Volt-Second Product Clamp

to Prevent Core Saturation

•Practical Operation Up to 1MHz

•High Current (2A Pk) Totem Pole

Output Driver

•Wide Bandwidth (8MHz) Current Error

Amplifier

•Under Voltage Lockout Monitors VCC,

VIN and VREF

•Output Active Low During UVLO

•Low Startup Current (500µA)

•Precision 5V Reference (1%)

The UC3848 family of PWM control ICs makes primary

side average current mode control practical for isolated

switching converters. Average current mode control in-

sures that both cycle by cycle peak switch current and

maximum average inductor current are well defined and

will not run away in a short circuit situation. The UC3848

can be used to control a wide variety of converter topolo-

gies.

In addition to the basic functions required for pulse width

modulation, the UC3848 implements a patented tech-

nique of sensing secondary current in an isolated buck

derived converter from the primary side. A current wave-

form synthesizer monitors switch current and simulates

the inductor current down slope so that the complete cur-

rent waveform can be constructed on the primary side

without actual secondary side measurement. This infor-

mation on the primary side allows for full DC control of

output current.

The UC3848 circuitry includes a precision reference, a

wide bandwidth error amplifier for average current con-

trol, an oscillator to generate the system clock, latching

PWM comparator and logic circuits, and a high current

output driver. The current error amplifier easily interfaces

with an optoisolator from a secondary side voltage sens-

ing circuit.

A full featured undervoltage lockout (UVLO) circuit is con-

tained in the UC3848. UVLO monitors the supply voltage

to the controller (VCC), the reference voltage (VREF),

and the input line voltage (VIN). All three must be good

before soft start commences. If either VCC or VIN is low,

the supply current required by the chip is only 500µA and

the output is actively held low.

Two on board protection features set controlled limits to

prevent transformer core saturation. Input voltage is mon-

itored and pulse width is constrained to limit the maxi-

mum volt-second product applied to the transformer. A

unique patented technique limits maximum duty cycle

within 3% of a user programmed value.

These two features allow for more optimal use of trans-

formers and switches, resulting in reduced system size

and cost.

Patents embodied in the UC3848 belong to Lambda

Electronics Incorporated and are licensed for use in ap-

plications employing these devices.

DESCRIPTION

BLOCK DIAGRAM

Average Current Mode PWM Controller

UDG-93003-1

application

INFO

available

UC1848

UC2848

UC3848

Supply Voltage (Pin 15). . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V

Output Current, Source or Sink (Pin 14)

DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A

Pulse (0.5 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2A

Power Ground to Ground (Pin 1 to Pin 13) . . . . . . . . . . . ±0.2V

Analog Input Voltages

(Pins 3, 4, 7, 8, 12, 16). . . . . . . . . . . . . . . . . . . . . –0.3 to 7V

Analog Input Currents, Source or Sink

(Pins 3, 4, 7, 8, 11, 12, 16) . . . . . . . . . . . . . . . . . . . . . . 1mA

Analog Output Currents, Source or Sink (Pins 5 & 10) . . . 5mA

Power Dissipation at TA = 60°C. . . . . . . . . . . . . . . . . . . . . . 1W

Storage Temperature Range...............−65°C to +150°C

Lead Temperature (Soldering 10 seconds) . . . . . . . . . . +300°C

ABSOLUTE MAXIMUM RATINGS

PACKAGE PIN FUNCTION

FUNCTION PIN

N/C 1

GND 2

VREF 3

NI 4

INV 5

N/C 6

CAO 7

CT 8

VS 9

DMAX 10

N/C 11

CDC 12

CI 13

IOFF 14

ION 15

N/C 16

PGND 17

OUT 18

VCC 19

UV 20

PLCC-20 & LCC-20

(Top View)

Q & L Packages

CONNECTION DIAGRAMS

DIL-16, SOIC-16 (Top View)

J, N, or DW Packages

Package QJA QJC

DIL-16J 80-120 28(2)

DIL-16N 90(1) 45

SOIC-16DW 50-100(1) 27

PLCC-20 43-75(1) 34

LCC-20 70-80 20(2)(3)

THERMAL RATINGS TABLE

UC1848

UC2848

UC3848

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, all specifications are over the junction temperature range

of −55°C to +125°C for the UC1848, −40°C to +85°C for the UC2848, and 0°C to +70°C for the UC3848. Test conditions are: VCC

= 12V, CT = 400pF, CI = 100pF, IOFF = 100µA, CDC = 100nF, Cvs = 100pF, and Ivs = 400µA, TA=TJ.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Real Time Current Waveform Synthesizer

Ion Amplifier

Offset Voltage 0.95 1 1.05 V

Slew Rate (Note 1) 20 25 V/µs

lib -2 -20 µA

IOFF Current Mirror

Input Voltage 0.95 1 1.05 V

Current Gain 0.9 1 1.1 A/A

Current Error Amplifier

AVOL 60 100 dB

Vio 12V ≤VCC 20V, 0V VCM 5V 10 mV

lib -0.5 -3 µA

Voh IO=−200µA 3 3.3 V

Vol IO= 200µA 0.3 0.6 V

Source Current VO= 1V 1.4 1.6 2.0 mA

GBW Product f = 200kHz 5 8 MHz

Slew Rate (Note 1) 810 V/µs

Oscillator

Frequency TA= 25°C 240 250 260 kHz

235 265 kHz

Ramp Amplitude 1.5 1.65 1.8 V

Duty Cycle Clamp

Max Duty Cycle V(DMAX) = 0.75 •VREF 73.5 76.5 79.5 %

Volt Second Clamp

Max On Time 900 1100 ns

VCC Comparator

Turn-on Threshold 13 14 V

Turn-off Threshold 910 V

Hysteresis 2.5 3 3.5 V

UC1848

UC2848

UC3848

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, all specifications are over the junction temperature range

of −55°C to +125°C for the UC1848, −40°C to +85°C for the UC2848, and 0°C to +70°C for the UC3848. Test conditions are: VCC

= 12V, CT = 400pF, CI = 100pF, IOFF = 100µA, CDC = 100nF, Cvs = 100pF, and Ivs = 400µA, TA=TJ.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

UV Comparator

Turn-on Threshold 4.1 4.35 4.6 V

RHYSTERESIS Vuv = 4.2V 77 90 103 kΩ

Reference

VREF TA= 25°C 4.95 5 5.05 V

0<IO<10mA, 12 <VCC <20 4.93 5.07 V

Line Regulation 12 < VCC < 20V 4 15 mV

Load Regulation 0 < IO< 10mA 3 15 mV

Short Circuit Current VREF = 0V 30 50 70 mA

Output Stage

Rise & Fall Time (Note 1) Cl = 1nF 20 45 ns

Output Low Saturation IO= 20mA 0.25 0.4 V

IO= 200mA 1.2 2.2 V

Output High Saturation IO= -200mA 2.0 3.0 V

UVLO Output Low Saturation IO= 20mA 0.8 1.2 V

ICC

ISTART VCC = 12V 0.2 0.4 mA

ICC (pre-start) VCC = 15V, V(UV) = 0 0.5 1 mA

ICC (run) 22 26 mA

Under Voltage Lockout

The Under Voltage Lockout block diagram is shown in

Fig 1. The VCC comparator monitors chip supply voltage.

Hysteretic thresholds are set at 13V and 10V to facilitate

off-line applications. If the VCC comparator is low, ICC is

low (<500µA) and the output is low.

The UV comparator monitors input line voltage (VIN). A

pair of resistors divides the input line to UV. Hysteretic in-

put line thresholds are programmed by Rv1 and Rv2. The

thresholds are

VIN(on) = 4.35V •(1 + Rv1/Rv2′) and

VIN(off) = 4.35V •(1 + Rv1/Rv2) where

Rv2′= Rv2||90k.

The resulting hysteresis is

VIN(hys) = 4.35V •Rv1 / 90k.

When the UV comparator is low, ICC is low (500µA) and

the output is low.

When both the UV and VCC comparators are high, the

internal bias circuitry for the rest of the chip is activated.

The CDC pin (see discussion on Maximum Duty Cycle

Control and Soft Start) and the Output are held low until

VREF exceeds the 4.5V threshold of the VREF compara-

tor. When VREF is good, control of the output driver is

transferred to the PWM circuitry and CDC is allowed to

charge.

If any of the three UVLO comparators go low, the UVLO

latch is set, the output is held low, and CDC is dis-

charged. This state will be maintained until all three com-

parators are high and the CDC pin is fully discharged.

APPLICATION INFORMATION

UC1848

UC2848

UC3848

APPLICATION INFORMATION (cont.)

UDG-93004

100

1000

10000

10 100 1000 10000

C (pF)

FREQUENCY (kHz)

Oscillator Frequency as a Function of CT

Frequency Decrease as a Function of RT

RT = Open

UDG-93006

UDG-93005

UC1848

UC2848

UC3848

Oscillator

A capacitor from the CT pin to GND programs oscillator

frequency, as shown in Fig. 2. Frequency is determined

by:

F = 1 / (10k CT).

The sawtooth wave shape is generated by a charging

current of 200 A and a discharge current of 1800 A. The

discharge time of the sawtooth is guaranteed dead time

for the output driver. If the maximum duty cycle control is

defeated by connecting DMAX to VREF, the maximum

duty cycle is limited by the oscillator to 90%. If an adjust-

ment is required, an additional trim resistor RT from CT

to Ground can be used to adjust the oscillator frequency.

RT should not be less than 40k . This will allow up to a

22% decrease in frequency.

Inductor Current Waveform Synthesizer

Average current mode control is a very useful technique

to control the value of any current within a switching con-

verter. Input current, output inductor current, switch cur-

rent, diode current or almost any other current can be

controlled. In order to implement average current mode

control, the value of the current must be explicitly known

at all times. To control output inductor current (IL) in a

buck derived isolated converter, switch current provides

inductor current information, but only during the on time

of the switch. During the off time, switch current drops

abruptly to zero, but the inductor current actually dimin-

ishes with a slope dIL/dt = –VO/L. This down slope must

be synthesized in some manner on the primary side to

provide the entire inductor current waveform for the con-

trol circuit.

The patented current waveform synthesizer (Fig. 4) con-

sists of a unidirectional voltage follower which forces the

voltage on capacitor CI to follow the on time switch cur-

rent waveform. A programmable discharge current syn-

thesizes the off time portion of the waveform. ION is the

input to the follower. The discharge current is pro-

grammed at IOFF.

The follower has a one volt offset, so that zero current

corresponds to one volt at CI. The best utilization of the

UC3848 is to translate maximum average inductor cur-

rent to a 4V signal level. Given N and Ns (the turns ratio

of the power and current sense transformers), proper

scaling of IL to V(CI) requires a sense resistor Rs as cal-

culated from:

Rs = 4V Ns N / IL(max).

Restated, the maximum average inductor current will be

limited to:

IL(max) = 4V Ns N/Rs.

IOFF and CI need to be chosen so that the ratio of

dV(CI)/dt to dIL/dt is the same during switch off time as

on time. Recommended nominal off current is 100 A.

This requires

CI = (100 A NNs L) / (Rs VO(nom))

where L is the output inductor value and VO(nom) is the

converter regulated output voltage.

There are several methods to program IOFF. If accurate

average current control is required during short circuit op-

eration, IOFF must track output voltage. The method

shown in Fig. 4 derives a voltage proportional to VIN D

(Duty Cycle). (In a buck converter, output voltage is pro-

portional to VIN D.) A resistively loaded diode connec-

tion to the bootstrap winding yields a square wave whose

amplitude is proportional to VIN and is duty cycle modu-

lated by the control circuit. Averaging this waveform with

a filter generates a primary side replica of secondary reg-

ulated VO. A single pole filter is shown, but in practice a

two or three pole filter provides better transient response.

Filtered voltage is converted by ROFF to a current to the

IOFF pin to control CI down slope.

APPLICATION INFORMATION (cont.)

UDG-93008-1

UC1848

UC2848

UC3848

If the system is not sensitive to short circuit requirements,

Figure 5 shows the simplest method of downslope gener-

ation: a single resistor (ROFF = 40k) from IOFF to VREF.

The discharge current is then 100µA. The disadvantage

to this approach is that the synthesizer continues to gen-

erate a down slope when the switch is off even during

short circuit conditions. Actual inductor down slope is

closer to zero during a short circuit. The penalty is that

the average current is understated by an amount approxi-

mately equal to the nominal inductor ripple current. Out-

put short circuit is therefore higher than the designed

maximum output current.

A third method of generating IOFF is to add a second

winding to the output inductor core (Fig. 6). When the

power switch is off and inductor current flows in the free

wheeling diode, the voltage across the inductor is equal

to the output voltage plus the diode drop. This voltage is

then transformed by the second winding to the primary

side of the converter. The advantages to this approach

are its inherent accuracy and bandwidth. Winding the

second coil on the output inductor core while maintaining

the required isolation makes this a more costly solution.

In the example, ROFF = VO/ 100µA. The 4 •ROFF re-

sistor is added to compensate the one volt input level of

the IOFF pin. Without this compensation, a minor current

foldback behavior will be observed.

APPLICATION INFORMATION (cont.)

UDG-93010 UDG-93011

UDG-93009

UC1848

UC2848

UC3848

UDG-93012-1 UDG-93013-1

Maximum Volt-Second Circuit

A maximum volt-second product can be programmed by

a resistor (Rvs) from VS to VIN and a capacitor (Cvs)

from VS to ground (Figure 7). VS is discharged while the

switch is off. When the output turns on, VS is allowed to

charge. Since the threshold of the VS comparator is

much less than VIN, the charging profile at Vs will be es-

sentially linear. If VS crosses the 4.0V threshold before

the PWM turns the output off, the VS comparator will turn

the output off for the remainder of the cycle. The maxi-

mum volt-second product is

VIN •TON(max) = 4.0V •Rvs •Cvs.

Maximum Duty Cycle And Soft Start

A patented technique is used to accurately program max-

imum duty cycle. Programming is accomplished by a di-

vider from VREF to DMAX (Fig. 7). The value

programmed is:

D(max) = Rd1 / (Rd1 + Rd2).

For proper operation, the integrating capacitor, CDC,

should be larger than CDC(min) >T(osc) / 80k, where

T(osc) is the oscillator period. CDC also sets the soft start

time constant, so values of CDC larger than minimum may

be desired. The soft start time constant is approximately:

T(ss) = 20k •CDC.

Ground Planes

The output driver on the UC3848 is capable of 2A peak

currents. Careful layout is essential for correct operation

of the chip. A ground plane must be employed (Fig. 8). A

unique section of the ground plane must be designated

for high di/dt currents associated with the output stage.

This point is the power ground to which to PGND pin is

connected. Power ground can be separated from the rest

of the ground plane and connected at a single point, al-

though this is not strictly necessary if the high di/dt paths

are well understood and accounted for. VCC should be

bypassed directly to power ground with a good high fre-

quency capacitor. The sources of the power MOSFET

should connect to power ground as should the return

connection for input power to the system and the bulk in-

put capacitor. The output should be clamped with a high

current Schottky diode to both VCC and PGND. Nothing

else should be connected to power ground.

VREF should be bypassed directly to the signal portion

of the ground plane with a good high frequency capacitor.

Low esr/esl ceramic 1 F capacitors are recommended

for both VCC and VREF. The capacitors from CT, CDC,

and CI should likewise be connected to the signal ground

plane.

APPLICATION INFORMATION (cont.)

UC1848

UC2848

UC3848

UDG-93014

UDG-93015

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

UC1848J OBSOLETE CDIP J 16 TBD Call TI Call TI

UC2848DW ACTIVE SOIC DW 16 40 Green (RoHS &