GE Data Sheet
QBDW033A0B Barracuda Series; DC-DC Converter Power Modules
36-75Vdc Input; 12.0Vdc, 33.0A, 400W Output
May 9, 2013 ©2012 General Electric Company. All rights reserved. Page 16
Digital Feature Descriptions
PMBus Interface Capability
The QBDW033A0B series is equipped with a digital PMBus
interface to allow the module to be configured, and
communicate with system controllers. Detailed timing and
electrical characteristics of the PMBus can be found in the
PMB Power Management Protocol Specification, Part 1,
revision 1.2, available at http://pmbus.org. The QBDW033A0B
supports both the 100kHz and 400kHz bus timing
requirements. The QBDW033A0B shall stretch the clock, as
long as it does not exceed the maximum clock LO period of
35ms. The QBDW033A0B will check the Packet Error
Checking scheme (PEC) byte, if provided by the PMBus
master, and include a PEC byte in all responses to the master.
However, the QBDW033A0B does not require a PEC byte from
the PMBus master.
The QBDW033A0B supports a subset of the commands in the
PMBus 1.2 specification. Most all of the controller parameters
can be programmed using the PMBus and stored as defaults
for later use. All commands that require data input or output
use the linear format. The exponent of the data words is fixed
at a reasonable value for the command and altering the
exponent is not supported. Direct format data input or
output is not supported by the QBDW033A0B. The supported
commands are described in greater detail below.
The QBDW033A0B contains non-volatile memory that is used
to store configuration settings and scale factors. The settings
programmed into the device are not automatically saved into
this non-volatile memory though. The STORE_DEFAULT_ALL
command must be used to commit the current settings to
non-volatile memory as device defaults. The settings that are
capable of being stored in non-volatile memory are noted in
their detailed descriptions.
SMBALERT Interface Capability
The QBDW033A0B also supports the SMBALERT response
protocol. The SMBALERT response protocol is a mechanism
through which the QBDW033A0B can alert the PMBus master
that it has an active status or alarm condition via pulling the
SMBALERT pin to an active low. The master processes this
condition, and simultaneously addresses all slaves on the
PMBus through the Alert Response Address. Only the slave(s)
that caused the alert (and that support the protocol)
acknowledges this request. The master performs a modified
receive byte operation to get the slave’s address. At this
point, the master can use the PMBus status commands to
query the slave that caused the alert. Note: The
QBDW033A0B can only respond to a single address at any
given time. Therefore, the factory default state for the
QBDW033A0B module is to retain it’s resistor programmed
address, when it is in an ALERT active condition, and not
respond to the ARA. This allows master systems, which do not
support ARA, to continue to communicate with the slave
QBDW033A0B using the programmed address, and using the
various READ_STATUS commands to determine the cause for
the SMBALERT. The CLEAR_FAULTS command will retire the
active SMBALERT. However, when the QBDW033A0B module
is used in systems that do support ARA, Bit 4 of the
MFR_CPIN_ARA_CONFIG command can be used to
reconfigure the module to utilize ARA. In this case, the
QBDW033A0B will no longer respond to its programmed
address, when in an ALERT active state. The master is
expected to perform the modified received byte operation,
and retire the ALERT active signal. At this time, the
QBDW033A0B will return to it’s resistor programmed address,
allowing normal master-slave communications to proceed.
The QBDW033A0B does not contain capability to arbitrate
data bus contention caused by multiple modules responding
to the modified received byte operation. Therefore, when the
ARA is used in a multiple module PMBus application, it is
necessary to have the QBDW033A0B module at the lowest
programmed address in order for the host to properly
determine all modules’ address that are associated with an
active SMBAlert. Please contact your GE sales representative
for further assistance, and for more information on the
SMBus alert response protocol, see the System Management
Bus (SMBus) specification.
PMBus Addressing
The power module can be addressed through the PMBus
using a device address. The module has 64 possible
addresses (0 to 63 in decimal) which can be set using
resistors connected from the ADDR0 and ADDR1 pins to GND.
Note that some of these addresses (0 through 12, 40, 44, 45,
and 55 in decimal) are reserved according to the SMBus
specifications and may not be useable. The address is set in
the form of two octal (0 to 7) digits, with each pin setting one
digit. The ADDR1 pin sets the high order digit and ADDR0 sets
the low order digit. The resistor values suggested for each
digit are shown in Table 4 (1% tolerance resistors are
recommended).
Table 4
Digit
Resistor Value (KΩ)
0 10
1 15.4
2 23.7
3 36.5
4 54.9
5 84.5
6 130
7 200
DDR0
SIG_GND
R
ADDR0
R
ADDR1
DDR1
Figure 27. Circuit showing connection of resistors used to
set the PMBus address of the module.
The user must know which I2C addresses are reserved in a
system for special functions and set the address of the
module to avoid interfering with other system operations.
Both 100kHz and 400kHz bus speeds are supported by the