W986432EH / W9864G2EH 512K x 4 BANKS x 32BIT SDRAM Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 3 2. FEATURES ................................................................................................................................. 3 3. AVAILABLE OPTIONS................................................................................................................ 3 4. PIN ASSIGNMENT ..................................................................................................................... 4 5. PIN DESCRIPTION..................................................................................................................... 5 6. BLOCK DIAGRAM ...................................................................................................................... 6 7. FUNCTIONAL DESCRIPTION.................................................................................................... 7 7.1 Power Up and Initialization ............................................................................................. 7 7.2 Programming Mode Register.......................................................................................... 7 7.3 Bank Activate Command ................................................................................................ 7 7.4 Read and Write Access Modes ...................................................................................... 7 7.5 Burst Read Command .................................................................................................... 8 7.6 Burst Command .............................................................................................................. 8 7.7 Read Interrupted by a Read ........................................................................................... 8 7.8 Read Interrupted by a Write............................................................................................ 8 7.9 Write Interrupted by a Write............................................................................................ 8 7.10 Write Interrupted by a Read............................................................................................ 8 7.11 Burst Stop Command ..................................................................................................... 9 7.12 Addressing Sequence of Sequential Mode .................................................................... 9 7.13 Addressing Sequence of Interleave Mode...................................................................... 9 7.14 Auto-precharge Command ........................................................................................... 10 7.15 Precharge Command.................................................................................................... 10 7.16 Self Refresh Command ................................................................................................ 10 7.17 Power Down Mode ....................................................................................................... 11 7.18 No Operation Command............................................................................................... 11 7.19 Deselect Command ...................................................................................................... 11 7.20 Clock Suspend Mode.................................................................................................... 11 8. TABLE OF OPERATING MODES ............................................................................................ 12 9. SIMPLIFIED STATE DIAGRAM................................................................................................ 13 10. DC CHARACTERISTICS .......................................................................................................... 14 10.1 Absolute Maximum Rating............................................................................................ 14 11. RECOMMENDED DC OPERATING CONDITIONS................................................................. 14 12. CAPACITANCE......................................................................................................................... 15 12.1 DC CHARACTERISTICS.............................................................................................. 15 -1- Publication Release Date: August 17,2005 Revision A09 W986432EH / W9864G2EH 13. AC CHARACTERISTICS .......................................................................................................... 16 14. TIMING WAVEFORMS ............................................................................................................. 19 15. 14.1 Command Input Timing ................................................................................................ 19 14.2 Read Timing.................................................................................................................. 20 14.3 Control Timing of Input Data......................................................................................... 21 14.4 Control Timing of Output Data ...................................................................................... 22 14.5 Mode Register Set Cycle .............................................................................................. 23 OPERATING TIMING EXAMPLE ............................................................................................. 24 15.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 24 15.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge) ............ 25 15.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 26 15.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge) ............ 27 15.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 28 15.6 Interleaved Bank Write (Burst Length = 8, Autoprecharge).......................................... 29 15.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)............................................... 30 15.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ..................................... 31 15.9 Autoprecharge Read (Burst Length = 4, CAS Latency = 3) ......................................... 32 15.10 Autoprecharge Write (Burst Length = 4)....................................................................... 33 15.11 Autorefresh Cycle ......................................................................................................... 34 15.12 Self-refresh Cycle ......................................................................................................... 35 15.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3) .............................. 36 15.14 Power-down Mode ........................................................................................................ 37 15.15 Auto-precharge Timing (Write Cycle) ........................................................................... 38 15.16 Auto-precharge Timing (Read Cycle) ........................................................................... 39 15.17 Timing Chart of Read to Write Cycle ............................................................................ 40 15.18 Timing Chart of Write to Read Cycle ............................................................................ 41 15.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) ........................................... 42 15.20 Timing Chart of Burst Stop Cycle (Precharge Command) ........................................... 43 15.21 CKE/DQM Input Timing (Write Cycle) .......................................................................... 44 15.22 CKE/DQM Input Timing (Read Cycle) .......................................................................... 45 15.23 Self Refresh/Power Down Mode Exit Timing................................................................ 46 16. PACKAGE DIMENSIONS ......................................................................................................... 47 16.1 17. 86L TSOP (II)-400 mil................................................................................................... 47 REVISION HISTORY ................................................................................................................ 48 -2- W986432EH / W9864G2EH 1. GENERAL DESCRIPTION W986432EH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words x 4 banks x 32 bits. Using pipelined architecture and 0.13 m process technology, W986432EH delivers a data bandwidth of up to 800M bytes per second (-5). For different application, W986432EH is sorted into the following speed grades: -5, -6, -7. The -5 parts can run up to 200 MHz/CL3. The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W986432EH is ideal for main memory in high performance applications. 2. FEATURES x x x x 3.3V0.3V Power Supply. x x x x x x All inputs are sampled at the positive going edge of the system clock . Interface : LVTTL. Four banks operation. MRS cycle with address key programs. - CAS latency (2 & 3). - Burst length (1, 2, 4, 8 & Full page). - Burst type (Sequential & Interleave). Burst read single-bit write operation. DQM for masking. Auto & self refresh. 64ms refresh period (4K cycle). W9864G2EH is using Lead free materials , RoHS compliant 3. AVAILABLE OPTIONS PART NUMBER SPEED SELF REFRESH CURRENT (MAX.) TEMPERATURE RANGE W986432EH-5 200MHz/CL3 3mA 0C - 70 C W986432EH-6 166MHz/CL3 3mA 0C - 70 C W986432EH-7 143MHz/CL3 3mA 0C - 70 C -3- Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH 4. PIN ASSIGNMENT VCC 1 86 Vss DQ0 2 85 DQ15 VCCQ 3 84 VSSQ DQ1 4 83 DQ14 DQ2 5 82 DQ13 VSSQ 6 81 VCCQ DQ3 7 80 DQ12 DQ4 8 79 DQ11 VCCQ 9 78 VSSQ DQ5 10 77 DQ10 DQ6 11 76 DQ9 VSSQ 12 75 VCCQ DQ7 13 74 DQ8 NC 14 73 NC VCC 15 72 VSS DQM0 16 71 DQM1 WE 17 70 NC CAS 18 69 NC RAS 19 68 CLK CS 20 67 CKE NC 21 66 A9 BS0 22 65 A8 BS1 23 64 A7 A10/AP 24 63 A6 A0 25 62 A5 A1 26 61 A4 A2 27 60 A3 DQM2 28 59 DQM3 VCC 29 58 VSS NC 30 57 NC DQ16 31 56 DQ31 VSSQ 32 55 VCCQ DQ17 33 54 DQ30 DQ18 34 53 DQ29 35 52 VSSQ DQ19 36 51 DQ28 DQ20 37 50 DQ27 VSSQ 38 49 VCCQ DQ21 39 48 DQ26 DQ22 40 47 DQ25 VCCQ 41 46 VSSQ DQ23 42 45 DQ24 VCC 43 44 VSS VCCQ -4- W986432EH / W9864G2EH 5. PIN DESCRIPTION PIN NUMBER PIN NAME FUNCTION DESCRIPTION 24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66 A0-A10 Address Multiplexed pins for row and column address. Row address: A0-A10. Column address: A0-A7. A10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by BS0, BS1. 22, 23 BS0, BS1 Bank Select Select bank to activate during row address latch time, or bank to read/write during address latch time. DQ0- DQ31 Data Input/ Output Multiplexed pins for data output and input. CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. 19 RAS Row Address Strobe 18 CAS 17 WE Write Enable Referred to RAS DQM0- DQM3 Input/Output Mask The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. CLK Clock Inputs System clock used to sample inputs on the rising edge of clock. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. 2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76, 77, 79, 80, 82, 83, 85 20 16, 28, 59, 71 68 Command input. When sampled at the rising edge of the clock RAS , CAS and WE define the operation to be executed. Column Address Referred to RAS Strobe 67 CKE Clock Enable 1, 15, 29, 43 VCC Power Power for input buffers and logic circuit inside DRAM. 44, 58, 72, 86 VSS Ground Ground for input buffers and logic circuit inside DRAM. 3, 9, 35, 41, 49, 55, 75, 81 VCCQ Power for I/O Buffer 6, 12, 32, 38, 46, 52, 78, 84 VSSQ Ground for I/O Separated ground from VSS, to improve DQ Buffer noise immunity. 14, 21, 30, 57, 69, 70, 73 NC No Connection -5- Separated power from VCC, to improve DQ noise immunity. No connection.(The NC pin 14 and pin 70 and pin 73 must connect to ground or floating.) Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH 6. BLOCK DIAGRAM CLK CLOCK BUFFER CKE CONTROL CS GENERATOR DECODER COLUMN DECODER ROW DECODER WE A10 MODE REGISTER A0 CELL ARRAY BANK #1 SENSE AMPLIFIER SENSE AMPLIFIER ADDRESS BUFFER DATA CONTROL CIRCUIT REFRESH COUNTER DQ BUFFER DQ0 DQ31 COLUMN DQM0~3 COUNTER COLUMN DECODER ROW DECODER A9 BS0 BS1 CELL ARRAY BANK #0 COLUMN DECODER ROW DECODER CAS SIGNAL COMMAND CELL ARRAY BANK #2 COLUMN DECODER ROW DECODER RAS SENSE AMPLIFIER NOTE: The cell array configuration is 2048 * 256 * 32 -6- CELL ARRAY BANK #3 SENSE AMPLIFIER W986432EH / W9864G2EH 7. FUNCTIONAL DESCRIPTION 7.1 Power Up and Initialization The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. During power up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed VCC +0.3V on any of the input pins or VCC supplies. After power up, an initial pause of 200 S is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation. 7.2 Programming Mode Register After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table. 7.3 Bank Activate Command The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as TRAS (max.). 7.4 Read and Write Access Modes After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The address inputs determine the starting column address. Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle. -7- Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH 7.5 Burst Read Command The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode. 7.6 Burst Command The Burst Write command is initiated by applying logic low level to CS , CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored. 7.7 Read Interrupted by a Read A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command the is satisfied. 7.8 Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed. 7.9 Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. 7.10 Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored. -8- W986432EH / W9864G2EH 7.11 Burst Stop Command A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored. 7.12 Addressing Sequence of Sequential Mode A column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2. Table 2 Address Sequence of Sequential Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 BL = 2 (disturb address is A0) No address carry from A0 to A1 BL = 4 (disturb addresses are A0 and A1) No address carry from A1 to A2 BL = 8 (disturb addresses are A0, A1 and A2) No address carry from A2 to A3 7.13 Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3. Table 3 Address Sequence of Interleave Mode DATA ACCESS ADDRESS BUST LENGTH Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2 Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 4 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 5 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 6 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 -9- BL = 4 BL = 8 Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH 7.14 Auto-precharge Command If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS latency. A Read or Write Command with auto-precharge cannot be interrupted before the entire burst operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of AutoPrecharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred to as write tDPL. The bank undergoing auto-precharge cannot be reactivated until tDPL and tRP are satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tDPL + tRP). When using the Autoprecharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS (min). 7.15 Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1 are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). 7.16 Self Refresh Command The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the tAC cycle time plus the Self Refresh exit time. If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode. - 10 - W986432EH / W9864G2EH 7.17 Power Down Mode The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to tCES (min.) + tCK (min.). 7.18 No Operation Command The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS , CAS , and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 7.19 Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS , CAS , and WE signals become don't cares. 7.20 Clock Suspend Mode During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. - 11 - Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH 8. TABLE OF OPERATING MODES Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. Table 1 Truth Table (note (1), (2)) COMMAND DEVICE STATE CKEN-1 CKEN DQM BS0, 1 A10 A0A9 CS RAS CAS WE Bank Active Idle H x x v v V L L H H Bank Precharge Any H x x v L x L L H L Precharge All Any H x x x H x L L H L Write Active (3) H x x v L v L H L L Write with Autoprecharge Active (3) H x x v H v L H L L Read Active (3) H x x v L v L H L H Read with Autoprecharge Active (3) H x x v H v L H L H Mode Register Set Idle H x x v v v L L L L No-Operation Any H x x x x x L H H H Active (4) H x x x x x L H H L Device Deselect Any H x x x x x H x x x Auto-Refresh Idle H H x x x x L L L H Self-Refresh Entry Idle H L x x x x L L L H idle L H x x x x H x x x (S.R) L H x x x x L H H x Active H L x x x x x x x x Idle H L x x x x H x x X Active (5) H L x x x x L H H H Active L H x x x x x x x X L H x x x x H x x X L H x x x x L H H H Burst Stop Self Refresh Exit Clock suspend Mode Entry Power Down Mode Entry Clock Suspend Mode Exit Any Power Down Mode Exit (power down) Data write/Output Enable Active H x L x x x x x x x Data Write/Output Disable Active H x H x x x x x x x Notes: (1) v = valid, x = Don't care, L = Low Level, H = High Level (2) CKEn signal is input leve l when commands are provided. (3) These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. - 12 - W986432EH / W9864G2EH 9. SIMPLIFIED STATE DIAGRAM Self Refresh SE LF LF SE Mode Register Set MRS it ex REF IDLE CBR Refresh CK E CK E ACT Power Down CKE CKE e Wr ite w Aut o p ith rec har g rit e W WRITEA SUSPEND Read WRITE CKE T BS CKE d ea R WRITE SUSPEND with ad Re rg e cha p re Write Active Power Down CKE o Aut BS T ROW ACTIVE Read READ Write CKE i na term READA CKE CKE READA SUSPEND t ina ) ion PR E(p re te r m cha r ge rge cha PRE CKE re E(p PR WRITEA tion ) CKE READ SUSPEND POWER ON Precharge Precharge Automatic sequence Manual input MRS = Mode Register Set REF = Refresh ACT = Active PRE = Precharge WRITEA = Write with Auto precharge READA = Read with Auto precharge - 13 - Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH 10. DC CHARACTERISTICS 10.1 Absolute Maximum Rating PARAMETER SYM. RATING UNIT NOTES Input, Column Output Voltage VIN, VOUT -0.3~VCC+0.3V V 1 Power Supply Voltage VCC, VCCQ -0.3~4.6V V 1 Operating Temperature TOPR 0 - 70 C 1 Storage Temperature TSTG -55 - 150 C 1 Soldering Temperature (10s) TSOLDER 260 C 1 Power Dissipation PD 1 W 1 Short Circuit Output Current IOUT 50 mA 1 Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 11. RECOMMENDED DC OPERATING CONDITIONS (TA = 0 to 70C) PARAMETER SYM. MIN. TYP. MAX. UNIT VCC 3.0 3.3 3.6 V VCCQ 3.0 3.3 3.6 V Input High Voltage VIH 2 - VCC +0.3 V 1 Input Low Voltage VIL -0.3 - +0.8 V 2 Output logic high voltage VOH 2.4V - - V IOH= -2mA Output logic low voltage VOL - - 0.4 V IOL= 2mA Input leakage current ILI -10 - 10 uA 3 Power Supply Voltage Power Supply Voltage (for I/O Buffer) Note: NOTES 1. VIH (max.) = VCC/VCCQ+1.2V for pulse width < 5 nS 2. VIL (min.) = VSS/VSSQ-1.2V for pulse width < 5 nS 3. Any input 0V<VIN<VCCQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. - 14 - W986432EH / W9864G2EH 12. CAPACITANCE (VCC =3.3V0.3V, TA = 25 C, f = 1 MHz) PARAMETER Input Capacitance (A0 to A10, BS0, BS1, CS , RAS , CAS , WE , DQM, CKE) Input Capacitance (CLK) Input/Output capacitance (DQ0-DQ31) SYM. MIN. MAX. UNIT Ci 2.5 4 pf CCLK Co 2.5 4 4 6.5 pf pf Note: These parameters are periodically sampled and not 100% tested 12.1 DC CHARACTERISTICS (VCC = 3.3V0.3V, TA = 0~70C for -5/-6/-7) PARAMETER 1 bank operation Operating Current tCK = min., tRC = min. Active precharge command cycling without burst operation Standby Current CKE = VIH tCK = min., CS = VIH VIH/L = VIH (min.)/VIL (max.) Bank: inactive state CKE = VIL (Power Down mode) CKE = VIH Standby Current CLK = VIL, CS = VIH VIH/L=VIH (min.)/VIL (max.) BANK: inactive state CKE = VIL (Power Down mode) CKE = VIH No Operating Current tCK = min., CS = VIH (min.) BANK: active state (4 CKE = VIL (Power banks) Down mode) Burst Operating Current (tCK = min.) Read/Write command cycling Auto Refresh Current (tCK = min.) Auto refresh command cycling Self Refresh Current Standard (-5/-6/-7) CKE = 0.2V Self refresh mode -5 -6 -7 MAX. MAX. MAX. ICC1 110 90 80 3 ICC2 45 35 30 3 ICC2P 3 3 3 3 ICC2S 8 8 8 ICC2PS 3 3 3 ICC3 70 60 55 ICC3P 15 15 15 ICC4 190 165 145 3, 4 ICC5 125 120 110 3 ICC6 3 3 3 SYM. - 15 - UNIT NOTES mA Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH 13. AC CHARACTERISTICS (VCC = 3.3V0.3V, VSS = 0V, Ta = 0 to 70 C for -5/-6/-7) (Notes: 5, 6.) PARAMETER -5 SYM. -6 MIN. MAX. MIN. Ref/Active to Ref/Active Command Period tRC 54 60 -7 UNIT NOTE MAX. MIN. MAX. 65 Active to precharge Command Period tRAS 40 100000 42 Active to Read/Write Command Delay Time tRCD 14 18 20 Read/Write(a) to Read/Write(b) Command tCCD Period 1 1 1 Precharge to Active(b) Command Period tRP 14 18 20 tRRD 10 12 14 tWR 2 2 2 tCK 7 1000 7.5 1000 8 1000 5 1000 6 1000 7 1000 Active(a) to Active(b) Command Period Write Recovery Time CL* = 2 CL* = 3 CLK Cycle Time CL* = 2 CL* = 3 100000 45 100000 nS tCK nS tCK CLK High Level tCH 2 2 2 7 CLK Low Level tCL 2 2 2 7 Access Time from CLK CL* = 2 tAC CL* = 3 5.5 5.5 6 4.5 5 5.5 Output Data Hold Time tOH 1.5 Output Data High Impedance Time tHZ 1.5 Output Data Low Impedance Time tLZ 0 Power Down Mode Entry Time tSB 0 5 0 6 0 7 tT 0.5 1 0.5 1 0.5 1 Data-in-Set-up Time tDS 1.5. 1.5 1.5 7 Data-in Hold Time tDH 1 1 1 7 Address Set-up Time tAS 1.5 1.5 1.5 7 Transition Time of CLK (Rise and Fall) Address Hold Time 2 5 2 2 6 0 2 7 0 nS tAH 1 1 1 7 CKE Set-up Time tCKS 1.5 1.5 1.5 7 CKE Hold Time tCKH 1 1 1 7 Command Set-up Time tCMS 1.5 1.5 1.5 7 Command Hold Time tCMH 1 1 1 7 Refresh Time tREF Mode Register Set Cycle Time tRSC 64 10 - 16 - 64 12 64 14 mS nS W986432EH / W9864G2EH Notes: 1.Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices. 2. All voltages are referenced to VSS 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC. 4. These parameters depend on the output loading conditions. Specified values are obtained with output open. 5. Power up Sequence (1) Power up must be performed in the following sequence. (2) Power must be applied to VCC and VCCQ (simultaneously) while all input signals are held in the "NOP" state. The CLK signals must be started at the same time. (3) After power-up a pause of at least 200 seconds is required. It is required that DQM and CKE signals then be held `high` (VCC levels) to ensure that the DQ output is impedance. (4) All banks must be precharged. (5) The Mode Register Set command must be asserted to initialize the Mode Register. (6) A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of the device 6. AC Testing Conditions PARAMETER CONDITIONS Output Reference Level 1.4V Output Load See diagram below Input Signal Levels (VIH/VIL) 2.4V/0.4V Transition Time (Rise and Fall) of Input Signal 1 nS Input Reference Level 1.4V 1.4 V 50 ohms output Z = 50 ohms 50pF AC TEST LOAD - 17 - Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH 1. Transition times are measured between VIH and VIL. 2. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. 3. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows the number of clock cycles = specified value of timing/ clock period (count fractions as whole number) (1) tCH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min.). tCL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max.).A.C Latency Characteristics CKE to clock disable (CKE Latency) 1 DQM to output to HI-Z (Read DQM Latency) 2 DQM to output to HI-Z (Write DQM Latency) 0 Write command to input data (Write Data Latency) 0 CS tCK 0 to Command input ( CS Latency) Precharge to DQ Hi-Z Lead time Precharge to Last Valid data out Bust Stop Command to DQ Hi-Z Lead time Bust Stop Command to Last Valid Data out Read with Auto-precharge Command to Active/Ref Command Write with Auto-precharge Command to Active/Ref Command CL = 2 2 CL = 3 3 CL = 2 1 CL = 3 2 CL = 2 2 CL = 3 3 CL = 2 1 CL = 3 2 CL = 2 BL + tRP CL = 3 BL + tRP CL = 2 (BL+1) + tRP CL = 3 (BL+1) + tRP 7. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. ( The tT maximum can't be more than 10nS for low frequency application. ) - 18 - tCK + nS W986432EH / W9864G2EH 14. TIMING WAVEFORMS 14.1 Command Input Timing tCL tCK CLK tCH VIH VIL tT tCMS tCMH tCMS tCMH tCMS tCMH tCMS tCMH tAS tAH tCMH tT tCMS CS RAS CAS WE A0-A10 BS0, 1 tCKS tCKH tCKS tCKH tCKS tCKH CKE - 19 - Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH Timing Waveforms, continued 14.2 Read Timing Read CAS Latency CLK CS RAS CAS WE A0-A10 BS0, 1 tAC tAC tLZ tHZ tOH tOH Valid Data-Out Valid Data-Out DQ Read Command Burst Length - 20 - W986432EH / W9864G2EH Timing Waveforms, continued 14.3 Control Timing of Input Data (Word Mask) CLK tCMH tCMS tCMH tCMS DQM0 tCMH tCMS tCMH tDH tDS tDH tCMS DQM1 tDS tDH tDS Valid Data-in DQ0 -DQ7 tDS tDH Valid Data-in tDS Valid Data-in DQ8-DQ15 tDS tDH tDS tDH tDS tDH tDS tDH Valid Data-in tDH tDS tDH tDS Valid Data-in tDH tDH Valid Data-in tDS Valid Data-in tDS tDH Valid Data-in Valid Data-in Valid Data-in Valid Data-in DQ24-DQ31 tDS Valid Data-in Valid Data-in DQ16 -DQ23 tDH tDS tDH tDS Valid Data-in tDS Valid Data-in tDH tDH Valid Data-in tDS Valid Data-in tDH Valid Data-in *DQM2,3="L" (Clock Mask) CLK tCKH tCKS tDH tDS tCKH tCKS CKE tDS Valid Data-in DQ0 -DQ7 tDS tDS Valid Data-in DQ8 -DQ15 tDS tDH tDS tDH Valid Data-in tDS tDS tDH tDS tDS tDH tDH tDS tDH tDS tDH tDS tDH Valid Data-in - 21 - tDH Valid Data-in tDS Valid Data-in Valid Data-in tDH Valid Data-in Valid Data-in Valid Data-in tDS tDH Valid Data-in Valid Data-in Valid Data-in DQ16 -DQ23 DQ24 -DQ31 tDH tDH Valid Data-in tDH Valid Data-in tDS tDH Valid Data-in Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH Timing Waveforms, continued 14.4 Control Timing of Output Data (Output Enable) CLK tCMH tCMS tCMH tCMS tCMH tCMS DQM0 tCMS tCMH DQM1 tAC tAC tOH tOH tHZ tOH Valid Data-Out DQ0 -DQ7 tAC tAC tOH tOH Valid Data-Out DQ8 -DQ15 tAC tAC tOH tOH tHZ Valid Data-Out DQ16 -DQ23 tAC tAC tOH tOH tHZ tOH Valid Data-Out tAC tOH Valid Data-Out tAC tAC Valid Data-Out tOH Valid Data-Out DQ24 -DQ31 OPEN tLZ Valid Data-Out tAC tLZ Valid Data-Out tOH Valid Data-Out tHZ tOH Valid Data-Out tAC tOH OPEN Valid Data-Out tAC tOH tAC tLZ tAC tOH Valid Data-Out Valid Data-Out *DQM2,3="L" (Clock Mask) CLK tCKH tCKS tCKH tCKS CKE tAC tOH tOH Valid Data-Out DQ0 -DQ7 tAC tOH tOH tAC tAC tOH tOH tOH tOH tOH Valid Data-Out tAC Valid Data-Out - 22 - tAC Valid Data-Out tOH Valid Data-Out tAC Valid Data-Out tAC tAC Valid Data-Out DQ16 -DQ23 tAC Valid Data-Out tOH tAC Valid Data-Out tAC Valid Data-Out tOH tOH Valid Data-Out tOH DQ8 -DQ15 DQ24 -DQ31 tAC tAC tOH tAC tOH tAC Valid Data-Out W986432EH / W9864G2EH Timing Waveforms, continued 14.5 Mode Register Set Cycle tRSC CLK tCMS tCMH tCMS tCMH tCMS tCMH tCMS tCMH CS RAS CAS WE tAS A0-A10 BS0,1 tAH Register set data A0 A1 Burst Length A2 A3 Addressing Mode A4 A5 CAS Latency A2 0 0 0 0 1 1 1 1 A6 A0 A7 "0" (Test Mode) A8 "0" Reserved WriteA0 Mode A0 A9 A10 "0" A11 A0 "0" BS0 "0" BS1 A0 "0" A0 Reserved A0 A0 A1 A0 0 A0 0 A0 1 A0 1 A0 0 A0 0 A0 1 A0 1 A0 0 1 0 1 0 1 0 1 A0 A3 A0 0 A0 1 A6 0 0 0 0 1 A0 A5 A0 0 A0 0 A0 1 A0 1 A0 0 A0 A9 A0 0 A0 1 - 23 - next command BurstA0 Length Sequential A0 Interleave A0 1 A0 1 A0 A0 2 2 A0 4 A0 4 A0 8 A0 8 A0 Reserved A0 Reserved FullA0 Page A0 Mode Addressing Sequential A0 Interleave A0 A4 0 1 0 1 0 CAS A0 Latency Reserved A0 Reserved A0 2 A0 3 Reserved Single Write Mode Burst read and A0 Burst write Burst read and A0 single write Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH 15. OPERATING TIMING EXAMPLE 15.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 1 0 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC RAS tRAS tRC tRP tRAS tRAS tRP tRP tRAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9 RAa tRCD tRCD RBb CAw tRCD RAc CBx RBb RBd RAc CAy RAe RBd CBz RAe DQM CKE aw0 tRRD Bank #0 Active Bank #1 tAC tAC tAC DQ aw1 aw2 aw3 bx0 Precharge Active bx2 bx3 Active Read Idle Bank #3 - 24 - cy1 cy2 cy3 tRRD Precharge Read Precharge Bank #2 tAC cy0 tRRD tRRD Read bx1 Active Read Active W986432EH / W9864G2EH Operating Timing Example, continued 15.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 11 10 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRAS tRP tRAS tRP tRAS CAS WE BS0 BS1 tRCD tRCD tRCD A10 RAa RBb A0-A9 RAa CAw RBb tRCD CBx RAe RBd RAc CAy RAc CBz RBd RAe DQM CKE tAC DQ tRRD Active Bank #0 Bank #1 Bank #2 tAC tAC aw0 aw1 aw2 aw3 bx0 bx1 tAC cy0 cy1 Read AP* cy2 cy3 dz0 tRRD Read Active AP* Active bx3 tRRD tRRD Read bx2 AP* Active Active Read Idle Bank #3 * AP is the internal precharge start timing - 25 - Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH Operating Timing Example, continued 15.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK CS tRC RAS tRAS tRP tRAS tRP tRAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9 RAa tRCD tRCD RAc RBb CAx RBb CBy RAc CAz DQM CKE tAC DQ tAC ax0 ax1 tRRD Bank #0 Active Bank #2 ax3 ax4 ax5 ax6 tAC by0 by1 by4 by5 by6 by7 tRRD Read Precharge Bank #1 ax2 Precharge Active Read Idle Bank #3 - 26 - Active Read Precharge CZ0 22 23 W986432EH / W9864G2EH Operating Timing Example, continued 15.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge) (CLK = 100 MHz) 0 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRC CS RAS tRAS tRP tRAS CAS WE BS0 BS1 tRCD A10 A0-A9 RBb RAa RAa tRCD tRCD CAx RAc RBb RAc CBy CAz DQM CKE tCAC tCAC DQ ax0 ax1 ax2 tRRD Bank #0 Active Bank #2 Bank #3 Idle ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 CZ0 tRRD AP* Read Active Bank #1 ax3 tCAC Active Read Read AP* * AP is the internal precharge start timing - 27 - Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH Operating Timing Example, continued 15.5 Interleaved Bank Write (Burst Length = 8) (CLK = 100 MHz) 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS CAS tRCD tRCD tRCD WE BS0 BS1 A10 RAa A0-A9 RAa RBb CAx RAc RBb CBy RAc CAz DQM CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 tRRD Bank #0 Active Bank #2 Bank #3 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD Precharge Write Active Bank #1 by1 Write Idle - 28 - Active Write Precharge W986432EH / W9864G2EH Operating Timing Example, continued 15.6 Interleaved Bank Write (Burst Length = 8, Autoprecharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRP tRAS tRAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9 RAa tRCD tRCD RBb CAx RAb CBy RBb CAz RAc DQM CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 tRRD Bank #0 Active by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD AP* Write Active Bank #1 by2 Active Write AP* Write Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 29 - Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH Operating Timing Example, continued 15.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK tCCD tCCD tCCD CS tRAS tRAS RAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9 RAa tRCD RBb RBb CAI CBx CAy CAm CBz DQM CKE tAC DQ tAC tAC a0 a1 a2 a3 bx0 bx1 Ay0 tAC Ay1 Ay2 tAC am0 am1 am2 bz0 bz1 tRRD Bank #0 Active Active Bank #1 Bank #2 Bank #3 Read Read Read Read Precharge Read Idle * AP is the internal precharge start timing - 30 - AP* bz2 bz3 22 23 W986432EH / W9864G2EH Operating Timing Example, continued 15.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRAS tRP RAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa CAx CAy DQM CKE tAC DQ tWR ax0 Q Q Bank #0 Active ax1 ax3 ax2 Q Q ax5 ax4 Q Q Read ay1 ay0 D D Write ay2 D ay4 ay3 D D Precharge Bank #1 Bank #2 Bank #3 Idle - 31 - Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH Operating Timing Example, continued 15.9 Autoprecharge Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) CLK 0 1 2 3 4 6 5 7 8 9 11 10 12 13 14 15 16 17 18 19 20 21 22 CS tRC RAS tRAS tRP tRAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9 RAa tRCD RAb CAw RAb CAx DQM CKE tAC DQ Bank #0 tAC aw0 Active Read aw1 AP* aw2 aw3 bx0 Active Read Bank #1 Bank #2 Bank #3 Idle * AP is the internal precharge start timing - 32 - bx1 AP* bx2 bx3 23 W986432EH / W9864G2EH Operating Timing Example, continued 15.10 Autoprecharge Write (Burst Length = 4) (CLK = 100 MHz) CLK 0 1 2 3 5 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRC tRC RAS tRP tRAS tRAS tRP CAS WE BS0 BS1 tRCD tRCD A10 RAa A0-A9 RAa RAc RAb CAw RAb CAx RAc DQM CKE DQ Bank #0 aw0 Active Write aw1 aw2 bx0 aw3 AP* Active Write bx1 bx2 bx3 AP* Active Bank #1 Bank #2 Bank #3 Idle * AP is the internal precharge start - 33 - Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH Operating Timing Example, continued 15.11 Autorefresh Cycle (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK tRP tRC tRC CS RAS CAS WE BS0,1 A10 A0-A9 DQM CKE DQ All Banks Prechage Auto Refresh Auto Refresh (Arbitrary Cycle) - 34 - 21 22 23 W986432EH / W9864G2EH Operating Timing Example, continued 15.12 Self-refresh Cycle (CLK = 100 MHz) 0 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRP RAS CAS WE BS0,1 A10 A0-A9 DQM tCKS tCKS tSB CKE tCKS DQ tRC Self Refresh Cycle All Banks Precharge No Operation Cycle Self Refresh Entry Arbitrary Cycle - 35 - Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH Operating Timing Example, continued 15.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK CS RAS CAS tRCD WE BS0 BS1 A10 RBa A0-A9 RBa CBv CBw CBx CBy CBz DQM CKE tAC DQ av0 Q Bank #0 Bank #1 Bank #2 Bank #3 tAC Active Read av1 Q av3 av2 Q Q aw0 D ax0 D ay0 Single Write Idle - 36 - az1 az0 D Q Read Q az2 Q az3 Q 22 23 W986432EH / W9864G2EH Operating Timing Example, continued 15.14 Power-down Mode (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS WE BS A10 RAa A0-A9 RAa RAa CAa RAa CAx DQM tSB tSB CKE tCKS tCKS ax0 Active tCKS tCKS DQ NOP ax1 ax2 ax3 Precharge Read NOPActive Precharge Standby Power Down mode Active Standby Power Down mode Note: The PowerDown Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode. When CKE goes high, command input must be No operation at next CLK rising edge. - 37 - Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH Operating Timing Example, continued 15.15 Auto-precharge Timing (Write Cycle) 0 1 2 3 4 5 6 7 8 9 10 11 12 CLK (1) CAS Latency = 2 (a) burst length = 1 Command Write AP tWR DQ Act tRP D0 (b) burst length = 2 Command Write AP Act tWR DQ D0 tRP D1 (c) burst length = 4 Command AP Write DQ D0 D1 D2 Act tRP tWR D3 (d) burst length = 8 Command Write AP tWR DQ D0 D1 D2 D3 D4 D5 D6 Act tRP D7 (2) CAS Latency = 3 (a) burst length = 1 Command Write AP Act tWR DQ (b) burst length = 2 Command tRP D0 Write AP Act tWR DQ D0 tRP D1 (c) burst length = 4 Command Write AP Act tWR DQ D0 D1 D2 tRP D3 (d) burst length = 8 Command Write AP tWR DQ D0 D1 D2 D3 D4 D5 D6 D7 Note ) Write represents the Write with Auto precharge command. AP represents the start of internal precharing. Act represents the Bank Active command. When the /auto precharge command is asserted,the period from Bank Activate command to the start of intermal precgarging must be at least tRAS (min). - 38 - Act tRP W986432EH / W9864G2EH Operating Timing Example, continued 15.16 Auto-precharge Timing (Read Cycle) (1) CAS Latency=2 ( a ) burst length = 1 Command 0 1 Read AP 2 3 4 5 6 7 8 9 10 11 Act tRP Q0 DQ ( b ) burst length = 2 Command Read AP Q0 DQ Act tRP Q1 ( c ) burst length = 4 Command Read AP Act tRP Q0 DQ Q1 Q2 Q3 ( d ) burst length = 8 Command Read AP Q0 DQ Q1 Q2 Q3 Q4 Q5 Q6 Act tRP Q7 (2) CAS Latency=3 ( a ) burst length = 1 Command Read AP Q0 DQ ( b ) burst length = 2 Command Read AP Command Act tRP Q0 DQ ( c ) burst length = 4 Act tRP Read Q1 AP Act tRP Q0 DQ ( d ) burst length = 8 Command Q1 Q2 Q3 Read AP Q0 DQ Q1 Q2 Q3 Q4 Q5 Act tRP Q6 Q7 Note: Read AP Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to (min). the start of internal precgarging must be at least RAS t - 39 - Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH Operating Timing Example, continued 15.17 Timing Chart of Read to Write Cycle In the case of Burst Length = 4 0 1 2 Read Write 3 4 5 D1 D2 D3 D0 D1 D2 D1 D2 D3 D1 D2 6 (1) CAS Latency=2 ( a ) Command DQM D0 DQ ( b ) Command Read Write DQM DQ (2) CAS Latency=3 ( a ) Command Read D3 Write DQM D0 DQ ( b ) Command Read Write DQM DQ D0 D3 Note: The Output data must be masked by DQM to avoid I/O conflict. - 40 - 7 8 9 10 11 W986432EH / W9864G2EH Operating Timing Example, continued 15.18 Timing Chart of Write to Read Cycle In the case of Burst Length = 4 0 (1) CAS Latency = 2 ( a ) Command 1 2 Write Read 3 4 5 6 7 8 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 9 10 11 DQM DQ ( b ) Command D0 Read Write DQM DQ D0 D1 Write Read (2) CAS Latency = 3 ( a ) Command DQM DQ ( b ) Command D0 Write Read DQM DQ D0 D1 - 41 - Q3 Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH Operating Timing Example, continued 15.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) 0 1 2 3 4 5 6 7 8 (1) Read cycle ( a ) CAS latency =2 Command Read BST Q0 DQ Q1 Q2 Q3 Q4 ( b )CAS latency = 3 Command Read BST Q0 DQ Q1 Q2 Q3 Q4 (2) Write cycle Command DQ Write Q0 BST Q1 Q2 Note: Q3 BST Q4 represents the Burst stop command - 42 - 9 10 11 W986432EH / W9864G2EH 15.20 Timing Chart of Burst Stop Cycle (Precharge Command) 0 1 2 3 4 5 6 7 8 9 10 11 (1) Read cycle (a) CAS latency =2 Command Read PRCG DQ (b) CAS latency =3 Command Q0 Q1 Q2 Read Q3 Q4 PRCG DQ Q0 Q1 Q2 Q3 Q4 (2) Write cycle (a) CAS latency =2 Command PRCG Write tWR DQM DQ (b) CAS latency =3 Command Q0 Q1 Q2 Q3 Q4 PRCG Write tWR DQM DQ Q0 Q1 Q2 Q3 Q4 - 43 - Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH Operating Timing Example, continued 15.21 CKE/DQM Input Timing (Write Cycle) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ D5 DQM MASK D6 CKE MASK (1) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ DQM MASK D5 D6 5 6 7 D4 D5 D6 CKE MASK (2) CLK cycle No. 1 2 3 D1 D2 D3 4 External CLK Internal CKE DQM DQ CKE MASK (3) - 44 - W986432EH / W9864G2EH Operating Timing Example, continued 15.22 CKE/DQM Input Timing (Read Cycle) CLK cycle No. 1 2 3 4 Q1 Q2 Q3 Q4 5 6 7 External CLK Internal CKE DQM DQ Q6 Open Open (1) CLK cycle No. 1 2 3 Q1 Q2 Q3 4 5 6 7 External CLK Internal CKE DQM DQ Q6 Q4 Open (2) CLK cycle No. 1 2 Q1 Q2 3 4 5 6 7 Q4 Q5 Q6 External CLK Internal CKE DQM DQ Q3 (3) - 45 - Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH Operating Timing Example, continued 15.23 Self Refresh/Power Down Mode Exit Timing Asynchronous Control Input Buffer turn on tim e (Power down m ode exit tim e) is specified by t CKS (m in.) + t CK (m in.) A ) t CK < t CKS (m in.) + t CK (m in.) tCK CLK CKE tCKS(m in)+tCK(m in) NOP Com m and Command Input Buffer Enable B) t CK >= t CKS (m in.) + t CK (m in.) t CK CLK tCKS(m in)+tCK(m in) CKE Com mand Com m and Input Buffer Enable Note: All Input Buffer (Include CLK Buffer) are turned off in the Power Down m ode and Self Refresh m ode NOP Command Represents the No-Operation com m and Represents one com m and - 46 - W986432EH / W9864G2EH 16. PACKAGE DIMENSIONS 16.1 86L TSOP (II)-400 mil 86 44 HE E 1 43 e b C D q L A2 ZD A L1 A1 Y SEATING PLANE Controlling Dimension: Millimeters DIMENSION (MM) DIMENSION (INCH) SYM. MIN. NOM. A A1 A2 b 0.05 MAX. MIN. NOM. MAX. 0.047 0.006 1.20 0.15 0.002 0.27 0.21 0.007 0.005 0.871 0.875 0.905 0.039 1.00 0.011 c 0.17 0.12 D 22.12 22.22 22.62 E 10.06 10.16 10.26 0.396 0.400 0.404 HE 11.56 11.76 11.96 0.455 0.463 0.471 0.50 e L L1 0.40 0.50 0.020 0.60 0.016 0.80 0.020 0.024 0.032 0.004 0.10 Y ZD 0.008 0.024 0.61 - 47 - Publication Release Date: August 17 ,2005 Revision A09 W986432EH / W9864G2EH 17. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A01 8/22/2003 A02 11/10/2003 13 Icc3p A03 11/20/2003 13 Icc2p, Icc2PS,Icc6 spec A04 12/04/2003 28,32 A05 2/4/2004 12 Correct dc characteristics A06 4/22/2004 1,12-14 Remove 6I and 7L spec. Adjust -7 support voltage A07 2/25/2005 5 add NC pin description A08 6/23/2005 48 add important notice A09 8/17/2005 3,16 Formal version Correct timing chart Revise the -7 operation voltage Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 48 -