IDT72615L25JG - Integrated Device Technology

CMOS SyncBiFIFOTM

256 x 18 x 2

512 x 18 x 2

IDT72605

IDT72615

APRIL 2003

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

FUNCTIONAL BLOCK DIAGRAM

FEATURES:

••

•Two independent FIFO memories for fully bidirectional data

transfers

••

•256 x 18 x 2 organization (IDT72605)

••

•512 x 18 x 2 organization (IDT72615)

••

•Synchronous interface for fast (20ns) read and write cycle times

••

•Each data port has an independent clock and read/write control

••

•Output enable is provided on each port as a three-state control

of the data bus

••

•Built-in bypass path for direct data transfer between two ports

••

•Two fixed flags, Empty and Full, for both the A-to-B and the B-

to-A FIFO

••

•Programmable flag offset can be set to any depth in the FIFO

••

•The synchronous BiFIFO is packaged in a 64-pin TQFP (Thin

Quad Flatpack) and 68-pin PLCC

••

•Industrial temperature range (–40°°

°°

°C to +85°°

°°

°C)

DESCRIPTION:

The IDT72605 and IDT72615 are very high-speed, low-power bidirec-

tional First-In, First-Out (FIFO) memories, with synchronous interface for fast

read and write cycle times. The SyncBiFIFO™ is a data buffer that can store

or retrieve information from two sources simultaneously. Two Dual-Port FIFO

memory arrays are contained in the SyncBiFIFO; one data buffer for each

direction.

The SyncBiFIFO has registers on all inputs and outputs. Data is only

transferred into the I/O registers on clock edges, hence the interfaces are

synchronous. Each Port has its own independent clock. Data transfers to the

I/O registers are gated by the enable signals. The transfer direction for each

port is controlled independently by a read/write signal. Individual output enable

signals control whether the SyncBiFIFO is driving the data lines of a port or

whether those data lines are in a high-impedance state.

Bypass control allows data to be directly transferred from input to output

The SyncBiFIFO has eight flags. The flag pins are Full, Empty, Almost-Full,

and Almost-Empty for both FIFO memories. The offset depths of the Almost-Full

and Almost-Empty flags can be programmed to any location.

The SyncBiFIFO is fabricated using IDT’s high-speed, submicron CMOS

technology.

CLK

FLAG

LOGIC

MEMORY

ARRAY

512 x 18

256 x 18

INPUT REGISTER

MUX

OUTPUT REGISTER

HIGH

CONTROL

OUTPUT REGISTER INPUT REGISTER

CLK

MUX

MEMORY

ARRAY

512 x 18

256 x 18

HIGH

CONTROL

FLAG

LOGIC

RESET

LOGIC

POWER

SUPPLY

R/W

PAE

PAF

R/W

PAE

PAF

GND

BYP

µP

INTERFACE

-D

B17

-D

A17

2704 drw 01

INDUSTRIAL TEMPERATURE RANGE

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2

PIN CONFIGURATIONS

TQFP (PN64-1, order code: PF)

TOP VIEW

6162636465666768

23456789

35 43424140393837363433323130292827

DA16

CA17

CLKA

R/WA

ENA

CSA

VCC

EFAB

FFAB

PAEAB

PAFAB

OEA

DB17

DB16

DA2

DA1

DA0

EFBA

FFBA

PAEBA

PAFBA

GND

BYPB

OEB

ENB

R/WB

CLKB

DB0

DB1

DB2

DB15

GND

DB14

DB13

DB12

DB11

DB10

VCC

GND

DB9

DB8

DB7

DB6

DB5

GND

DB4

DB3

DA15

GND

DA14

DA13

DA12

DA11

DA10

VCC

GND

DA9

DA8

DA7

DA6

DA5

GND

DA4

DA3

2704 drw 02

GND

A10

A11

A12

A13

A14

A15

GND

B10

B11

B12

B13

B14

GND

B15

B16

A16

A17

CLK

R/W

PAE

PAF

B17

PAE

PAF

GND

BYB

R/W

CLK

2704 drw 03

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

PIN 1

PLCC (J68-1, order code: J)

TOP VIEW

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2 INDUSTRIAL TEMPERATURE RANGE

PIN DESCRIPTION

Symbol Name I/O Description

DA0-DA17 Data A I/O Data inputs & outputs for the 18-bit Port A bus.

CSAChip Select A I Port A is accessed when CSA is LOW. Port A is inactive if CSA is HIGH.

R/WARead/Write A I

This pin controls the read or write direction of Port A. If R/W

is LOW, Data A input data is written into Port A. If R/W

is HIGH,

Data A output data is read from Port A. In bypass mode, when R/W

is LOW, message is written into A

→

B output register. If

R/W

is HIGH, message is read from B

→

A output register.

CLKAClock A I CLKA is typically a free running clock. Data is read or written into Port A on the rising edge of CLKA.

ENAEnable A I

When EN

is LOW, data can be read or written to Port A. When EN

is HIGH, no data transfers occur.

OEA

Output Enable A

I When R/WA is HIGH, Port A is an output bus and OEA controls the high-impedance state of DA0-DA17. If OEA is HIGH, Port A is

in a high-impedance state. If OEA is LOW while CSA is LOW and R/WA is HIGH, Port A is in an active (low-impedance) state.

A0, A1, A2Addresses I When CSA is asserted, A0, A1, A2 and R/WA are used to select one of six internal resources.

DB0-DB17 Data B I/O Data inputs & outputs for the 18-bit Port B bus.

R/WBRead/Write B I

This pin controls the read or write direction of Port B. If R/W

is LOW, Data B input data is written into Port B. If R/W

is HIGH,

Data B output data is read from Port B. In bypass mode, when R/W

is LOW, message is written into B

→

A output register. If

R/W

is HIGH, message is read from A

→

B output register.

CLKBClock B I

Clock B is typically a free running clock. Data is read or written into Port B on the rising edge of CLK

ENBEnable B I

When EN

is LOW, data can be read or written to Port B. When EN

is HIGH, no data transfers occur.

OEB

Output Enable B

I When R/WB is HIGH, Port B is an output bus and OEB controls the high-impedance state of DB0-DB17. If OEB is HIGH, Port B is

in a high-impedance state. If OEB is LOW while R/WB is HIGH, Port B is in an active (low-impedance) state.

EFAB A→B Empty O When EFAB is LOW, the A→B FIFO is empty and further data reads from Port B are inhibited. When EFAB is HIGH, the FIFO is

Flag not empty. EFAB is synchronized to CLKB. In the bypass mode, EFAB HIGH indicates that data DA0-DA17 is available for passing

through. After the data DB0-DB17 has been read, EFAB goes LOW.

PAEAB A→B O When PAEAB is LOW, the A→B FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset

Programmable programmed into PAEAB Register. When PAEAB is HIGH, the A→B FIFO contains more than offset in PAEAB Register. The

Almost-Empty default offset value for PAEAB Register is 8. PAEAB is synchronized to CLKB.

Flag

PAFAB A→B O When PAFAB is LOW, the A→B FIFO is almost-full. An almost-full FIFO contains greater than the FIFO depth minus the offset

Programmable programmed into PAFAB Register. When PAFAB is HIGH, the A→B FIFO contains less than or equal to the depth minus the

Almost-Full offset in PAFAB Register. The default offset value for PAFAB Register is 8. PAFAB is synchronized to CLKA.

Flag

FFAB A→B Full Flag O

When FF

is LOW, the A

→

B FIFO is full and further data writes into Port A are inhibited. When FF

is HIGH, the FIFO is not

full. FF

is synchronized to CLK

. In bypass mode, FF

tells Port A that a message is waiting in Port B’s output register. If

is LOW, a bypass message is in the register. If FF

is HIGH, Port B has read the message and another message can be

written into Port A.

EFBA B→A Empty O When EFBA is LOW, the B→A FIFO is empty and further data reads from Port A are inhibited. When EFBA is HIGH, the FIFO

Flag is not empty. EFBA is synchronized to CLKA. In the bypass mode, EFBA HIGH indicates that data DB0-DB17 is available for

passing through. After the data DA0-DA17 has been read, EFBA goes LOW on the following cycle.

PAEBA B→A O When PAEBA is LOW, the B→A FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset

Programmable programmed into PAEBA Register. When PAEBA is HIGH, the B→A FIFO contains more than offset in PAEBA Register. The

Almost-Empty default offset value for PAEBA Register is 8. PAEBA is synchronized to CLKA.

Flag

PAFBA B→A O When PAFBA is LOW, the B→A FIFO is almost-full. An almost-full FIFO contains greater than the FIFO depth minus the offset

Programmable programmed into PAFBA Register. When PAFBA is HIGH, the B→A FIFO contains less than or equal to the depth minus the

Almost-Full offset in PAFBA Register. The default offset value for PAFBA Register is 8. PAFBA is synchronized to CLKB.

Flag

FFBA B→A Full Flag O

When FF

is LOW, the B

→

A FIFO is full and further data writes into Port B are inhibited. When FF

is HIGH, the FIFO is

not full. FF

is synchronized to CLK

. In bypass mode, FF

tells Port B that a message is waiting in Port A’s output register. If

is LOW, a bypass message is in the register. If FF

is HIGH, Port A has read the message and another message can be

written into Port B.

BYPBPort B Bypass O

This flag informs Port B that the synchronous BiFIFO is in bypass mode. When BYP

is LOW, Port A has placed the FIFO into

Flag bypass mode. If BYP

is HIGH, the synchronous BiFIFO passes data into memory. BYP

is synchronized to CLK

RS Reset I A LOW on this pin will perform a reset of all synchronous BiFIFO functions.

VCC Power There are three +5V power pins for the PLCC and two for the TQFP.

GND Ground There are seven ground pins for the PLCC and four for the TQFP.

INDUSTRIAL TEMPERATURE RANGE

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2

ABSOLUTE MAXIMUM RATINGS(1)

DC ELECTRICAL CHARACTERISTICS

RECOMMENDED DC OPERATING

CONDITIONS

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

VCC Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V

VIH Input High Voltage 2.0 — — V

VIL(1) Input Low Voltage — — 0.8 V

TAOperating Temperature -40 — 85 °C

NOTE:

1. 1.5V undershoots are allowed for 10ns once per cycle.

Symbol Rating Industrial Unit

VTERM Terminal Voltage with –0.5 to +7.0 V

Respect to Ground

TSTG Storage Temperature –55 to +125 °C

IOUT DC Output Current –50 to +50 mA

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

(Industrial: VCC = 5V ± 10%, T A = -40°C to +85°C) IDT72615L

IDT72605L

Industrial

tCLK = 20, 25, 35, 50ns

Symbol Parameter Min. Typ. Max. Unit

ILI(1) Input Leakage Current (Any Input) –1 — 1 µA

ILO(2) Output Leakage Current –10 — 10 µA

VOH Output Logic "1" Voltage IOUT = –2mA 2. 4 — — V

VOL Output Logic "0" Voltage IOUT = 8mA — — 0. 4 V

ICC(3) Active Power Supply Current — — 230 mA

NOTES:

1. Measurements with 0.4V ≤ VIN ≤ VCC.

2. OEA, OEB ≥ VIH; 0.4 ≤ VOUT ≤ VCC.

3. Tested with outputs open (IOUT = 0). Testing frequency f=20MHz.

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol Parameter Conditions Max. Unit

CIN(2) Input Capacitance VIN = 0V 10 pF

COUT(1,2) Output Capacitance VOUT = 0V 10 pF

NOTES:

1. With output deselected.

2. Characterized values, not currently tested.

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2 INDUSTRIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS

(Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C)

+5V

1.1KΩ

680Ω30pF*

D.U.T.

2704 drw 04

Industrial

IDT72615L20 IDT72615L25 IDT72615L35 IDT72615L50

IDT72605L20 IDT72605L25 IDT72605L35 IDT72605L50

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit Timing Figures

fCLK Clock frequency — 50 — 4 0 — 2 8 — 20 MHz —

tCLK Clock cycle time 20 — 25 — 35 — 50 — ns 4,5,6,7

tCLKH Clock HIGH time 8 — 10 — 14 — 20 — ns 4,5,6,7,12,13,14,15

tCLKL Clock LOW time 8 — 1 0 — 14 — 20 — n s 4,5,6,7,12,13,14,15

tRS Reset pulse width 20 — 25 — 35 — 50 — ns 3

tRSS Reset setup time 12 — 15 — 21 — 30 — ns 3

tRSR Reset recovery time 1 2 — 15 — 2 1 — 3 0 — ns 3

tRSF Reset to flags in initial state — 27 — 28 — 3 5 — 5 0 ns 3

tAData access time 3 10 3 1 5 3 21 3 25 ns 5,7,8,9,10,11

tCS Control signal setup time(1) 6 — 6 — 8 — 10 — ns 4,5,6,7,8,9,10,11,

12, 13,14,15

tCH Control signal hold time(1) 1 — 1 — 1 — 1 — ns 4,5,6,7,10,11,12,

13, 14,15

tDS Data setup time 6 — 6 — 8 — 10 — ns 4,6,8,9,10,11

tDH Data hold time 1 — 1 — 1 — 1 — ns 4,6

tOE Output Enable LOW to output data valid(2) 3 10 3 13 3 20 3 28 ns 5,7,8,9,10,11

tOLZ Output Enable LOW to data bus at Low-Z(2) 0 — 0 — 0 — 0 — ns 5,7,8,9,10,11

tOHZ Output Enable HIGH to data bus at High-Z(2) 3 10 3 13 3 20 3 28 ns 5,7,10,11

tFF Clock to Full Flag time — 1 0 — 1 5 — 2 1 — 3 0 n s 4,6,10,11

tEF Clock to Empty Flag time — 1 0 — 1 5 — 21 — 3 0 n s 5,7,8,9,10,11

tPAE Clock to Programmable — 12 — 15 — 21 — 30 ns 12,14

Almost-Empty Flag time

tPAF Clock to Programmable — 12 — 15 — 21 — 30 ns 13,15

Almost-Full Flag time

tSKEW1 Skew between CLKA & CLKB10 — 12 — 17 — 20 — ns 4,5,6,7,8,9,10,11

for Empty/Full Flags(2)

tSKEW2 Skew between CLKA & CLKB17 — 19 — 25 — 34 — ns 4, 7,12,13,14,15

for Programmable Flags(2)

NOTES:

1. Control signals refer to CSA, R/WA, ENA, A2, A1, A0, R/WB, ENB.

2. Minimum values are guaranteed by design.

AC TEST CONDITIONS

In Pulse Levels GND to 3.0V

Input Rise/Fall Times 3ns

Input Timing Reference Levels 1.5V

Output Reference Levels 1.5V

Output Load See Figure 2

or equivalent circuit

Figure 2. Output Load

* Includes jig and scope capacitances.

INDUSTRIAL TEMPERATURE RANGE

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2

CLK

DATA

ADDR, I/0 CONTROL

LOGIC

RAM A

IDT

SYNCBIFIFO

DATA B

CONTROL B

SYSTEM

CLOCK A

CONTROL

LOGIC

CLK

MICROPROCESSOR

AMICROPROCESSOR

DATA

ADDR, I/0

RAM B

SYSTEM

CLOCK B

IDT

SYNCBIFIFO

DATA B

CLKB

CONTROL B

DATA A

CLKA

CONTROL A

DATA A

CONTROL A

2704 drw 05

CLKBCLKA

FUNCTIONAL DESCRIPTION

IDTs SyncBiFIFO is versatile for both multiprocessor and peripheral

applications. Data can be stored or retrieved from two sources simultaneously.

The SyncBiFIFO has registers on all inputs and outputs. Data is only

transferred into the I/O registers on clock edges, hence the interfaces are

synchronous. Two Dual-Port FIFO memory arrays are contained in the

SyncBiFIFO; one data buffer for each direction. Each port has its own

independent clock. Data transfers to the I/O registers are gated by the enable

signals. The transfer direction for each port is controlled independently by a

read/write signal. Individual output enable signals control whether the SyncBiFIFO

is driving the data lines of a port or whether those data lines are in a high-

impedance state. The processor connected to Port A of the BiFIFO can send

or receive messages directly to the Port B device using the 18-bit bypass path.

The SyncBiFIFO can be used in multiples of 18-bits. In a 36- to 36-bit

configuration, two SyncBiFIFOs operate in parallel. Both devices are pro-

grammed simultaneously, 18 data bits to each device. This configuration can

be extended to wider bus widths (54- to 54-bits, 72- to 72-bits, etc.) by adding

more SyncBiFIFOs to the configuration. Figure 1 shows multiple SyncBiFIFOs

configured for multiprocessor communication.

The microprocessor or microcontroller connected to Port A controls all

operations of the SyncBiFIFO. Thus, all Port A interface pins are inputs driven

by the controlling processor. Port B interfaces with a second processor. The

Port B control pins are inputs driven by the second processor.

RESET

Reset is accomplished whenever the Reset (RS) input is taken to a LOW state

with CSA, ENA and ENB HIGH. During reset, both internal read and write

pointers are set to the first location. A reset is required after power up before a

write operation can take place. The A→B and B→A FIFO Empty Flags (EFAB,

EFBA) and Programmable Almost-Empty flags (PAEAB, PAEBA) will be set to

LOW after tRSF. The A→B and B→A FIFO Full Flags (FFAB, FFBA) and

Programmable Almost- Full flags (PAFAB, PAFBA) will be set to HIGH after tRSF.

After the reset, the offsets of the Almost-Empty flags and Almost- Full flags for the

A→B and B→A FIFO offset default to 8.

PORT A INTERFACE

The SyncBiFIFO is straightforward to use in micro-processor-based

systems because each port has a standard microprocessor control set. Port A

interfaces with microprocessor through the three address pins (A2-A0) and a

Chip Select CSA pins. When CSA is asserted, A2,A1,A0 and R/WA are used

to select one of six internal resources (Table 1).

With A2=0 and A1=0, A0 determines whether data can be read out of output

FIFO through the bypass path (A0=1).

With A2=1, four programmable flags (two A→B FIFO programmable flags

and two B→A FIFO programmable flags) can be selected: the A→B FIFO

Almost-Empty flag Offset (A1=0, A0=0), A→B FIFO Almost-Full flag Offset

(A1=0, A0=1), B→A FIFO Almost-Empty flag Offset (A1=1, A0=0), B→A FIFO

Almost-Full flag Offset (A1=1, A0=1).

Port A is disabled when CSA is deasserted and data A is in high-impedance

state.

BYPASS PATH

The bypass paths provide direct communication between Port A and Port

B. There are two full 18-bit bypass paths, one in each direction. During a bypass

operation, data is passed directly between the input and output registers, and

the FIFO memory is undisturbed.

Port A initiates and terminates all bypass operations. The bypass flag, BYPB,

is asserted to inform Port B that a bypass operation is beginning. The bypass

flag state is controlled by the Port A controls, although the BYPB signal is

synchronized to CLKB. So, BYPB is asserted on the next rising edge of CLKB

when A2A1A0=001and CSA is LOW. When Port A returns to normal FIFO mode

(A2A1A0=000 or CSA is HIGH), BYPB is deasserted on the next CLKB rising

edge.

Once the SyncBiFIFO is in bypass mode, all data transfers are controlled

by the standard Port A (R/WA, CLKA, ENA, OEA) and Port B (R/WB, CLKB,

ENB, OEB) interface pins. Each bypass path can be considered as a one word

deep FIFO. Data is held in each input register until it is read. Since the controls

Figure 1. 36- to 36-bit Processor Interface Configuration

NOTES:

1. Upper SyncBiFIFO only is used in 18- to 18-bit configuration.

2. Control A consists of R/WA, ENA, OEA, CSA, A2, A1, A0. Control B consists of R/WB, ENB, OEB.

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2 INDUSTRIAL TEMPERATURE RANGE

Data A

CSAR/WAENAOEAI/O Port A Operation

0 0 0 0 I Data A is written on CLKA ≠. This write cycle immediately following low-impedance cycle is prohibited. Note

that even though OEA = 0, a LOW logic level on R/WA, once qualified by a rising edge on CLKA, will put Data A into

a high-impedance state.

0 0 0 1 I Data A is written on CLKA ≠

0 0 1 X I Data A is ignored

0 1 0 0 O Data is read(1) from RAM array to output register on CLKA ≠, Data A is low-impedance

0 1 0 1 O Data is read(1) from RAM array to output register on CLKA ≠, Data A is high-impedance

0 1 1 0 O Output register does not change(2), Data A is low-impedance

0 1 1 1 O Output register does not change(2), Data A is high-impedance

1 0 X X I Data A is ignored(3)

1 1 X X O Data A is high-impedance(3)

NOTES:

1. When A2A1A0 = 000, the next B→A FIFO value is read out of the output register and the read pointer advances. If A2A1A0 = 001, the bypass path is selected and bypass

data from the Port B input register is read from the Port A output register. If A2A1A00 = 1XX, a flag offset register is selected and its offset is read out through Port A output

2. Regardless of the condition of A2A1A0, the data in the Port A output register does not change and the B→A read pointer does not advance.

3. If CSA# is HIGH, then BYPB is HIGH. No bypass occur under this condition.

TABLE 1  PORT A OPERATION CONTROL SIGNALS

CSAA2A1A0Read Write

0000 B→A FIFO A→B FIFO

0 0 0 1 18-bit Bypass Path

0100 A→B FIFO Almost-Empty

Flag Offset

0101 A→B FIFO Almost-Full

Flag Offset

0110 B→A FIFO Almost-Empty

Flag Offset

0111 B→A FIFO Almost-Full

Flag Offset

1 X X X Port A Disabled

TABLE 2  ACCESSING PORT A RE-

SOURCES USING CSA, A2, A1, AND A0

of each port operate independently, Port A can be reading bypass data at the

same time Port B is reading bypass data.

When R/WA and ENA is LOW, data on pins DA0-DA17 is written into Port

A input register. Following the rising edge of CLKA for this write, the A→B Full

Flag (FFAB) goes LOW. Subsequent writes into Port A are blocked by internal

logic until FFAB goes HIGH again. On the next CLKB rising edge, the A→B

Empty Flag (EFAB) goes HIGH indicating to Port B that data is available. Once

R/WB is HIGH and ENB is LOW, data is read into the Port B output register. OEB

still controls whether Port B is in a high-impedance state. When OEB is LOW,

the output register data appears at DB0-DB17. EFAB goes LOW following the

CLKB rising edge for this read. FFAB goes HIGH on the next CLKA rising edge,

letting Port A know that another word can be written through the bypass path.

Bypass data transfers from Port B to Port A work in a similar manner with

EFBA and FFBA indicating the Port A output register state.

When the Port A address changes from bypass mode (A2A1A0=001) to

FIFO mode (A2A1A0=000) on the rising edge of CLKA, the data held in the Port

B output register may be overwritten. Unless Port A monitors the BYPB pin and

waits for Port B to clock out the last bypass word, data from the A→B FIFO will

overwrite data in the Port B output register. BYPB will go HIGH on the rising

edge of CLKB signifying that Port B has finished its last bypass operation. Port

B must read any bypass data in the output register on this last CLKB clock or

it is lost and the SyncBiFIFO returns to FIFO operations. It is especially important

to monitor BYPB when CLKB is much slower than CLKA to avoid this condition.

BYPB will also go HIGH after CSA is brought HIGH; in this manner the Port B

bypass data may also be lost.

Since the Port A processor controls CSA and the bypass mode, this scenario

can be handled for B→A bypass data. The Port A processor must be set up

to read the last bypass word before leaving bypass mode.

PORT A CONTROL SIGNALS

The Port A control signals pins dictate the various operations shown in Table

2. Port A is accessed when CSA is LOW, and is inactive if CSA is HIGH. R/

WA and ENA lines determine when Data A can be written or read. If R/WA and

ENA are LOW, data is written into input register on the LOW-to-HIGH transition

of CLKA. If R/WA is HIGH and OEA is LOW, data comes out of bus and is read

from output register into three-state buffer. Refer to pin descriptions for more

information.

PROGRAMMABLE FLAGS

The IDT SyncBiFIFO has eight flags: four flags for A→B FIFO (EFAB,

PAEAB, PAFAB, FFAB), and four flags for B→A FIFO (EFBA, PAEBA, PAFBA,

FFBA). The Empty and Full flags are fixed, while the Almost-Empty and Almost-

Full offsets can be set to any depth through the Flag Offset Registers (see Table

3). The flags are asserted at the depths shown in the Flag Truth Table (Table

4). After reset, the programmable flag offsets are set to 8. This means the Almost-

Empty flags are asserted at Empty +8 words deep, and the Almost-Full flags are

asserted at Full -8 words deep.

The PAEAB is synchronized to CLKB, while PAEAB is synchronized to CLKA;

and PAEBA is synchronized to CLKA, while PAEBA is synchronized to CLKB.

If the minimum time (tSKEW2) between a rising CLKB and a rising CLKA is met,

the flag will change state on the current clock; otherwise, the flag may not change

state until the next clock rising edge. For the specific flag timings, refer to Figures

12-15.

PORT B CONTROL SIGNALS

The Port B control signal pins dictate the various operations shown in Table

5. Port B is independent of CSA. R/WB and ENB lines determine when Data

INDUSTRIAL TEMPERATURE RANGE

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2

can be written or read in Port B. If R/WB and ENB are LOW, data is written into

input register, and on LOW-to-HIGH transition of CLKB data is written into input

out of bus and is read from output register into three-state buffer. In bypass mode,

if R/WB is LOW, bypass messages are transferred into B→A output register.

If R/WA is HIGH, bypass messages are transferred into A→B output register.

Refer to pin descriptions for more information.

TABLE 3  FLAG OFFSET REGISTER FORMAT

NOTE:

1. Bit 8 must be set to 0 for the IDT72605 (256 x 18) Synchronous BiFIFO.

17161514131211109876543210

PAEAB Register XXXXXXXXX A→B FIFO Almost-Empty Flag Offset

17161514131211109876543210

PAFAB Register XXXXXXXXX A→B FIFO Almost-Full Flag Offset

17161514131211109876543210

PAEBA Register XXXXXXXXX B→A FIFO Almost-Empty Flag Offset

17161514131211109876543210

PAFBA Register XXXXXXXXX B→A FIFO Almost-Full Flag Offset

TABLE 4  INTERNAL FLAG TRUTH TABLE

Number of Words

in FIFO

From To EF PAE PAF FF

0 0 LOW LOW HIGH HIGH

1 n HIGH LOW HIGH HIGH

n+1 D-(m+1) HIGH HIGH HIGH HIGH

D-m D-1 HIGH HIGH LOW HIGH

D D HIGH HIGH LOW LOW

NOTE:

1. n = Programmable Empty Offset (PAEAB Register or PAEBA Register)

m = Programmable Full Offset (PAFAB Register or PAFBA Register)

D = FIFO Depth (IDT72605 = 256 words, IDT72615= 512 words)

TABLE 5  PORT B OPERATION CONTROL SIGNALS

Data B

R/WBENBOEBI /O Port B Operation

000I

Data B is written on CLKB

↑

. This write cycle immediately following output low-impedance cycle is prohibited. Note

that even though OEB = 0, a LOW logic level on R/WB, once qualified by a rising edge on CLK B, will put Data B into a high-

impedance state.

0 0 1 I Data B is written on CLKB ↑.

0 1 X I Data B is ignored

1 0 0 O Data is read(1) from RAM array to output register on CLKB ≠ Data B is low-impedance

1 0 1 O Data is read(1) from RAM array to output register on CLKB ≠, Data B is high- impedance

1 1 0 O Output register does not change(2), Data B is low-impedance

1 1 1 O Output register does not change(2), Data B is high-impedance

NOTES:

1. When A2A1A0 = 000 or 1XX, the next A→B FIFO value is read out of the output register and the read pointer advances. If A2A1A0 = 001, the bypass path is selected and

bypass data is read from the Port B output register.

2. Regardless of the condition of A2A1A0, the data in the Port B output register does not change and the A→B read pointer does not advance.

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2 INDUSTRIAL TEMPERATURE RANGE

tRSF

tRS

tRSF

tRSR

EFAB,

PAEAB,

EFBA,

PAEBA

CSA,

ENA

ENB

tRSS

2704 drw 06

EFAB,

PAEAB,

EFBA,

PAEBA

CLK

, A

tDS

A0-

A17

CLK

READ NO READ OPERATION

DATA IN VALID

NO OPERATION

tFF

tSKEW1

tDH

tCH

tCS

tCLKL

tCLK

tCLKH

2704 drw 07

Figure 4. Port A (A

→→

→

B) Write Timing

Figure 3. Reset Timing

INDUSTRIAL TEMPERATURE RANGE

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2

NO OPERATION

CLK

, A

A0-

A17

CLK

CLKH

CLKL

OLZ

OHZ

SKEW1

NO WRITE WRITE

VALID DATA

2704 drw 08

DATA IN VALID

SKEW1

READ NO READ OPERATION

CLK

B0-

B17

CLK

NO OPERATION

CLKL

CLKH

CLK

2704 drw 09

Figure 6. Port B (B

→→

→

A) Write Timing

Figure 5. Port A (B

→→

→

A) Read Timing

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2 INDUSTRIAL TEMPERATURE RANGE

VALID DATA

tSKEW1

NO WRITE OPERATION

CLKB

ENB

EFBA

DB0-DB17

CLKA

NO OPERATION

tEF

tCS tCH

tCLKL

tCLKH

tCLK

OEB

WRITE

tOE

tOLZ

tOHZ

2704 drw 10

(First Valid Write)

(1)

SKEW1

CLK

B0-

B17

CLK

OLZ

A0-

A17

, EN

, A

FRL

2704 drw 11

Figure 7. Port B (A

→→

→

B) Read Timing

NOTE:

1. When tSKEW1 ≥ minimum specification, tFRL(Max.) = tCLK + tSKEW1

tSKEW1 < minimum specification, tFRL(Max.) = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timing applies only at the Empty Boundary (EF = LOW).

Figure 8. A

→→

→

B First Data Word Latency after Reset for Simultaneous Read and Write

INDUSTRIAL TEMPERATURE RANGE

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2

(First valid write)

(1)

SKEW1

CLK

A0-

A17

CLK

OLZ

B0-

B17

, EN

, A

FRL

2704 drw 12

NOTE:

1. When tSKEW1 ≥ minimum specification, tFRL(Max.) = tCLK + tSKEW1

tSKEW1 < minimum specification, tFRL(Max.) = 2tCLK + tSKEW1

The Latency Timing apply only at the Empty Boundary (EF = LOW).

Figure 9. B

→→

→

A First Data Word Latency after Reset for Simultaneous Read and Write

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2 INDUSTRIAL TEMPERATURE RANGE

DATA INPUT

BYPASS FLAG

tSKEW1

CLKB

ENB

FFAB

DA0-DA17

CLKA

tCS

OEB

tOE

tOLZ

DB0-DB17

ENA

A0, A1, A2

tDS

2704 drw 13

CSA

EFAB

BYPB

A2, A1, A0 = 001

tFF

tCH

tCS

tFF tFF

tEF tEF tEF

tOHZ

DATA OUTPUT

FIFO FLAG

BYPASS FLAGFIFO FLAG

FIFO FLAG

tSKEW1 tSKEW1

tCH

NOTES:

1. When CSA is brought HIGH, A→B Bypass mode will switch to FIFO mode on the following CLKA LOW-to-HIGH transition.

2. After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags. The bypass path becomes available for the next bypass

operation.

3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be forced back to FIFO

mode.

Figure 10. A

→→

→

B Bypass Timing

INDUSTRIAL TEMPERATURE RANGE

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2

DATA INPUT

BYPASS FLAG

DATA OUTPUT

BYPASS FLAG

CLK

B0-

B17

CLK

OLZ

A0-

A17

, A

2704 drw 14

BYP

, A

= 001

OHZ

FIFO FLAG

SKEW1

FIFO FLAGFIFO FLAG

SKEW1

NOTES:

1. When CSA is brought HIGH, A

→→

→

B Bypass mode will switch to FIFO mode on the following CLKA going LOW-to-HIGH.

2. After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags.

3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be forced back to FIFO

mode.

Figure 11. B

→→

→

A Bypass Timing

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2 INDUSTRIAL TEMPERATURE RANGE

(1)

WRITE

READ

n words in FIFO

n+1 words in FIFO

CLKL

2704 drw 15

CLK

(R/W

= 0)

PAE

CLK

(R/W

= 1)

CLKH

SKEW2

PAE

(2)

WRITE

READ

(2)

Full - (m+1) words in FIFO Full - m words in FIFO

CLKL

2704 drw 16

CLK

(R/W

= 0)

PAF

CLK

(R/W

= 1)

CLKH

PAF

NOTES:

1. tSKEW2 the minimum time between a rising CLKA edge and a rising CLKB edge for PAEAB to change during that clock cycle. If the time between the rising edge of CLKA and

the rising edge of CLKB is less than tSKEW, then PAEAB may not go HIGH until the next CLKB rising edge.

2. If a read is performed on this rising edge of the read clock, there will be Empty + (n + 1) words in the FIFO when PAE goes LOW.

Figure 12. A

→→

→

B Programmable Almost-Empty Flag Timing

NOTES:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFAB to change during that clock cycle. If the time between the rising edge of CLKB

and the rising edge of CLKA is less than tSKEW2, then PAFAB may not go HIGH until the next CLKA rising edge.

2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.

Figure 13. A

→→

→

B Programmable Almost-Full Flag Timing

INDUSTRIAL TEMPERATURE RANGE

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2

Full - m words in FIFO

WRITE

(2)

Full - (m+1) words in FIFO

tCLKL

2704 drw 18

CLKB

ENB

(R/WA = 0)

PAFBA

CLKA

ENA

(R/WA = 1)

tCLKH

tCS tCH

tPAF

tCS tCH

tSKEW2(1) tPAF

READ

NOTES:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFBA to change during that clock cycle. If the time between the rising edge of CLKB

and the rising edge of CLKA is less than tSKEW2, then PAFBA may not go HIGH until the next CLKA rising edge.

2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.

Figure 15. B

→→

→

A Programmable Almost-Full Flag Timing

(1)

WRITE

READ

n words in FIFO n+1 words in FIFO

CLKL

2704 drw 17

CLK

(R/W

= 0)

PAE

CLK

(R/W

= 1)

CLKH

PAE

SKEW2

PAE

(2)

Figure 14. B

→→

→

A Programmable Almost-Empty Flag Timing

NOTES:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAEBA to change during that clock cycle. If the time between the rising edge of CLKB

and the rising edge of CLKA is less than tSKEW2, then PAEBA may not go HIGH until the next CLKA rising edge.

2. If a read is performed on this rising edge of the read clock, there will be Empty + (n - 1) words in the FIFO when PAE goes LOW.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753

San Jose, CA 95138 fax: 408-284-2775 em ail: FIFOhel p@idt.com

www.idt.com

ORDERING INFORMATION

DATASHEET DOCUMENT HISTORY

11/02/2000 pgs. 1, 2, 3, 4, 16

04/08/2003 pg. 17.

IDT XXXXX XXX X X

Device Type Power Speed Package Process/

Temperature

Range

Blank

72605

72615

Industrial (-40°C to +85°C)

Plastic Leaded Chip Carrier (PLCC, J68-1)

Thin Quad Flat Pack (TQFP, PN64-1)

Low Power

256 x 18  Parallel SyncBiFIFO

512 x 18  Parallel SyncBiFIFO

2704 drw19

Clock Cycle Time (tCLK)

in Nanoseconds