Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
1
SP6330, SP6332
and SP6334
Quad µPower Supervisory Circuits
with Manual Reset & Watchdog
SP6330-SP6332- SP6334 Quad Power Supervisory Circuit Family is a family of
microprocessor reset supervisory circuits with multiple reset voltages. The family provides
low voltage monitoring ability for up-to four supplies with two precision factory-set thresholds
and two user defined custom thresholds. These circuits perform a single function: if any of
the input supply voltages drops below its associated threshold, reset outputs are asserted.
The SP6330, SP6332, and SP6334 are packaged in an 8-pin TSOT package. All devices are
fully specified over -40oC to +85oC temperature range.
FEATURES
■ Low operating voltage of 1.6V
■ Low operating current of 20µA typical
■ Monitors up to four supplies simultaneously
■ Adjustable inputs monitor down to 0.5V
■ Reset asserted down to 0.9V
■ 2% accuracy over temperature range
■ Open Drain (OD) or CMOS RSTB output or
CMOS RST output
■ 4 Reset Timeout Periods:
50ms, 100ms, 200ms and 400ms
■ Watch Dog Input Functionality -- WDI
■ Manual Reset Input (Active Low) -- MRIB
■ 8 Pin TSOT package
DESCRIPTION
Available in Lead Free Packaging
SEE PAGE 2 FOR OTHER
AVAILABLE PINOUTS
1
2
3
45
6
7
8
8 Pin TSOT
V2
SP6330
V1
MRIB
V3
WDI
GND
V4
RSTB
Open Drain RESET
TYPICAL APPLICATION CIRCUIT
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporatio n
2
Terminal Voltage (with respect to GND)
V1, V2..................................................... -0.3 to +6V
Open-Drain RSTB.......................................-0.3 to +6V
CMOS RST, RSTB, ..................... -0.3 to (V1+0.3V)
Input Current/Output
Current..................................,,........................20mA
V3, V4, MRIB, WDI........................-0.3 to (V1+0.3V)
ABSOLUTE MAXIMUM RATINGS
Feature and Pinout Diagram
Operating Temperature
Range...............................................-40°Cto +85 °C
Storage Temperature
Range...............................................-65°C to 150°C
Thermal Resistance OJA.............................134°C/W
PART
NUMBER V1 V2 V3 V4 Reset MRIB WDI
SP6330 √ √ √ √ OD Active Low √ √
SP6332 √ √ √ √ CMOS Active Low √ √
SP6334 √ √ √ √ CMOS Active High √ √
1
2
3
45
6
7
8
8 Pin TSOT
V2
SP6330
V1
MRIB
V3
WDI
GND
V4
RSTB
Open Drain RESET
1
2
3
45
6
7
8
8 Pin TSOT
V2
SP6332
V1
MRIB
V3
WDI
GND
V4
RSTB
CMOS RESET
1
2
3
45
6
7
8
8 Pin TSOT
V2
SP6334
V1
MRIB
V3
WDI
GND
V4
RST
CMOS RESET
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability
and cause permanent damage to the device.
Representative Samples Available
PINOUT DIAGRAMS
Sipex
Product
Product
Description Package V1
(Volts)
V2
(Volts)
V3
(Volts)
V4
(Volts)
Reset
(ms)
Ordering #
SP6330 Quad Supervisor
Open Drain low 8 Pin TSOT 2.925 1.575 0.5 0.5 200 SP6330EK1-L-W-G-C
SP6330 Quad Supervisor
O
p
en Drain low 8 Pin TSOT 3.075 2.313 0.5 0.5 200 SP6330EK1-L-X-J-C
SP6330 Quad Supervisor
Open Drain low 8 Pin TSOT 4.625 2.313 0.5 0.5 200 SP6330EK1-L-Z-J-C
SP6332 Quad Supervisor
CMOS low 8 Pin TSOT 2.625 1.575 0.5 0.5 200 SP6330EK1-L-V-G-C
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
3
ELECTRICAL CHARACTERISTICS
PARAMETER MIN TYP MAX
UNITS
CONDITIONS
Operating Voltage
Ran
g
e 0.9 5.5 V T
A
= -40ºC to +85ºC
20 30 uA V1 < 5.5V, V2 < 3.60V, all I/O
pins open
15 25 V1 < 3.6V, V2 < 2.75V, all I/O
pins open
4.532 4.625 4.718 Z
(
valid for V1 fallin
g)
4.287 4.375 4.463 Y
(
valid for V1 fallin
g)
3.013 3.075 3.137 X
(
valid for V1 fallin
g)
2.866 2.925 2.984 W
(
valid for V1 fallin
g)
V1 Reset 2.572 2.625 2.678 V
(
valid for V1 fallin
g)
Threshold 2.273 2.320 2.367 U
(
valid for V1 fallin
g)
2.146 2.190 2.234 T
(
valid for V1 fallin
g)
1.636 1.670 1.704 S
(
valid for V1 fallin
g)
1.548 1.580 1.612 R
(
valid for V1 fallin
g)
2.266 2.313 2.360 J
(
valid for V2 fallin
g)
2.144 2.188 2.232 I
(
valid for V2 fallin
g)
1.631 1.665 1.698 H
(
valid for V2 fallin
g)
1.543 1.575 1.607 G
(
valid for V2 fallin
g)
V2 Reset 1.360 1.388 1.416 F
(
valid for V2 fallin
g)
Threshold 1.286 1.313 1.340 E
(
valid for V2 fallin
g)
1.087 1.110 1.133 D
(
valid for V2 fallin
g)
1.029 1.050 1.071 C
(
valid for V2 fallin
g)
0.816 0.833 0.850 B
(
valid for V2 fallin
g)
0.772 0.788 0.804 A
(
valid for V2 fallin
g)
Threshold 1
Tempco 0.06 mV/ºC
Threshold 2
Tempco 0.04 mV/ºC
Threshold 1
H
y
steresis 0.65 % reference to Vth1 typical
Threshold 2
H
y
steresis 0.5 % reference to Vth2 typical
V1 to RST/RSTB
Dela
y
50 us V1 = Vth1 to (Vth1-0.1V), Vth1
= 3.075
V2 to RST/RSTB
Dela
y
50 us V2 = Vth2 to (Vth2-0.1V), Vth2
= 1.575
Reset Timeout
Period
(
T1
)
37 50 63 ms TOPT-1
Reset Timeout
Period
(
T2
)
74 100 126 ms TOPT-2
Reset Timeout
Period
(
T3
)
148 200 252 ms TOPT-3
Reset Timeout
Period (T4) 296 400 504 ms TOPT-4
V1 =1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC
Supply Current
V
V
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
4
ELECTRICAL CHARACTERISTICS
PARAMETER MIN TYP MAX
UNITS
CONDITIONS
V3 Input Threshold 490 500 510 mV
V3 Input Current -50 50 nA T
A
= +25ºC
V3 Threshold
Hysteresis 1.5 mV
V4 Input Threshold 490 500 510 mV
V4 In
p
ut Current -50 50 nA T
A
= +25ºC
V4 Threshold
H
y
steresis 1.5 mV
MRIB Input
Threshold 0.2*V1 V Vil
MRIB Input
Threshold 0.8*V1 V Vih
MRIB Minimum
In
p
ut Pulse Width 1 us
MRIB Glitch
Re
j
ection 150 ns
MRIB to RST/RSTB
Dela
y
100 ns
MRIB Pull-Up
Resistance 30 55 85 kΩ
Watchdog Timeout
Period 1.3 1.6 1.9 sec
WDI Pulse Width 0.1 us
WDI Input
Threshold 0.2*V1 V Vil
WDI Input
Threshold 0.8*V1 V Vih
WDI Input Current -500 500 nA WDI = 0.0V or V1
RSTB
(CMOS or OD) 0.2*V1 V V1 = Vth1 - 0.1V, Isink = 1mA,
output asserted
RSTB (CMOS) 0.8*V1 V V1 = Vth1 + 0.1V, Isource =
1mA, out
p
ut not asserted
RST (CMOS) 0.8*V1 V V1 = Vth1 - 0.1V, Isource =
1mA, out
p
ut asserted
RST (CMOS) 0.2*V1 V
V1 = Vth1 + 0.1V, V2 > Vth2,
V3 > 0.5, V4 > 0.5, Isource =
1mA, out
p
ut not asserted
RSTB Output OD
Leakage Current 2 nA T
A
= +25ºC
V3 RESET COMPARATOR INPUT
V4 RESET COMPARATOR INPUT
MRIB - MANUAL RESET INPUT
V1 =1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC
RESET OUTPUTS RST / RSTB
WDI - WATCHDOG INPUT
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
5
PIN DESCRIPTION
Pin # Name Description
1 V1 First supply voltage input. Also powers internal circuitry. Trip threshold
voltage internally set.
2 V2 Second supply voltage input. Trip threshold voltage internally set.
3 MRIB
Manual Reset Input pin. Active low. It has an internal pull-up resistor.
Reset asserted when MRIB is pulled low and is kept asserted for
200ms after MRIB is released or pulled high. Leave open if not used.
4 V3 Input for the third supply voltage. Trip threshold is 0.5V.
5 V4 Input for the fourth supply voltage. Trip threshold is 0.5V.
6 GND Common ground reference pin.
7 WDI
Watch-Dog Input pin. When no transition is detected at the WDI pin for
the duration of WDI timeout period, reset is asserted. Leave open if
not used. RST/RSTB output is used to signal watchdog timeout
overflow. RST/RSTB output pulses high/low (depending on the active
reset polarity) for the reset timeout period after each watchdog timeout
overflow. The watchdog timer clears whenever the reset is asserted
or manual reset is asserted or a transition is observed at WDI pin.
Watchdog timer functionality can be disabled in parts by leaving this
input floating.
8 RST/RSTB
Reset output. Open-Drain or CMOS, active high or low. Reset is
asserted when any of the four supply inputs is below its trip threshold.
It stays asserted for 200 ms (typical / default) after the last supply input
traverses its trip threshold. Reset is guaranteed to be in the correct
state for V1>0.9V. RST/RSTB asserts when V1 or V2 or V3 or V4 drop
below their corresponding reset thresholds, or MRIB is pulled
“LOW” or the watchdog timer triggers a reset (devices without
WDOB). RST/RSTB remains asserted for the reset timeout period
after V1 and V2 and V3 and V4 exceed their corresponding reset
thresholds or MRIB goes “LOW” to “HIGH”. Open-drain outputs
require an external pull-up resistor. CMOS outputs are referenced to
V1.
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
6
The SP6330, SP6332, and SP6334 include
a low-voltage precision bandgap reference,
four precision comparators, an oscillator, a
digital counter chain, a logic control block,
trimmed resistor divider chains and
additional supporting circuitry. The family is
designed to supervise up to 4 independent
supply voltages. V1 and V2 supply inputs
have their resistor dividers on the chip.
Their trip thresholds are factory trimmed.
V3 and V4 inputs allow user to customize
Block Diagram
THEORY OF OPERATION
two additional supply thresholds to be
monitored by means of external resistor
dividers. The devices also feature manual
reset and watchdog functionalities.
As these devices do not have watchdog
outputs, the watchdog timer is serviced
internally during the watchdog timeout
period when WDI is left unconnected. The
watchdog functionality can be disabled by
leaving the WDI input floating.
OSC
WDI
LOGIC
CONTROL
LOGIC
V1 V2 V3 V4 WDI
RSTB (RST)
GND
1.25V
0.5V
MRIB
Bandgap
Ref
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
7
Figure 1: Functionality of a SP63XX family member with manual reset and watchdog
capabilities but without WDOB output.
• V1 > Vth1, V2 > Vth2 , V3 > Vth3 and V4 > Vth4 (all supplies over their corresponding
thresholds)---> RSTB is de-asserted after reset timeout period (Trp).
• MRIB goes to “LOW” to force “Reset” ----> RSTB is asserted immediately.
• WDI does not make any transition during watchdog timeout period (Twd) ---->RSTB is
asserted for a duration of reset timeout period (Trp).
• One of the supplies drops below its corresponding threshold (in this case V3)---->RSTB
is asserted immediately.
THEORY OF OPERATION
V1
V2
V3
V4
Vth1
Vth2
Vth3=0.5V
Vth4=0.5V
MRIB
WDI
RSTB
Trp Trp Twd
Trp
T<Twd T<Twd T<Twd T<Twd
T<Twd
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
8
V1
RSTB
ResetB Timeout Delay
APPLICATION INFORMATION
V1
RSTB
WDI = GND, V1=V2=V3=V4=5V,
MRIB = open.
Watchdog Timeout Period = 1.52S
Watchdog Timeout Period
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporatio n
9
0
100
200
300
400
500
85 80 70 60 50 40 30 20 10 0 -10 -20 -30 -40
D e g C
R
e
s
e
t T
i
m
e
o
u
t (
m
S
e
c
)
Reset Timeout vs. Temperature
ResetTimeout Delay Vs. Temperature
R S T B v s . V 1 (V 2 = G N D )
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
V1 (Vdc)
RS T B (V o lt s DC)
Reset Good
APPLICATION INFORMATION
(400ms Reset)
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
10
V 1 a n d V 2 G litc h r e je c tio n
0
50
100
150
200
250
0 20 40 60 80 100 120
Overdrive (mV)
RS TB asser ted
above line
D u
r
a
t i
o
n ( u
Se c )
V 3 a n d V 4 g litc h re je c tio n
0
20
40
60
80
100
120
0 20 40 60 80 100 120
O v e rd riv e (mV)
RS TB asser ted
above line
D
u r
a
t i o n ( u Se
c
)
V1 and V2 Glitch Rejection
V3 and V4 Glitch Rejection
APPLICATION INFORMATION
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
11
PACKAGE: 8 PIN TSOT
FRONT VIEW
L
ø1
Gauge Plane
L2
c
R
R1
ø1
ø
Seating
Plane
SIDE VIEW
A
A1
A2
Seating
Plane
D
E
E/2
e1
3
2
1
b
e
E1
E1/2
5
4
Pin1 Designator
to be within this
INDEX AREA
(D/2 x E1/2) TOP VIEW
(L1)
D/2
8 7 6
MIN NOM MAX MIN NOM MAX
A - - 1.10 - - 0.043
A1 0.00 - 0.10 0.000 - 0.004
A2 0.70 0.90 1.00 0.028 0.036 0.039
c 0.08 - 0.20 0.003 - 0.008
D
E
E1
L 0.30 0.45 0.60 0.012 0.018 0.024
L1
L2
Ø 0˚ 4º 8º 0º 4º 8º
Ø1 4˚ 10º 12º 4º 10º 12º
R 0.10 - - 0.004 - -
R1 0.10 - 0.25 0.004 - 0.010
b 0.22 - 0.38 0.009 - 0.015
e
e1 1.95 BSC
0.60 REF 0.024 REF
1.60 BSC 0.063 BSC
0.077 BSC
0.65 BSC 0.026 BSC
0.25 BSC 0.010 BSC
SIPEX Pkg Signoff Date/Rev: JL Oct3-05 / Rev A
SYMBOL
8 Pin TSOT JEDEC MO-193 Variation BA
2.90 BSC 0.114 BSC
2.80 BSC 0.110 BSC
Dimensions in Millimeters:
Controlling Dimension
Dimensions in Inches
Conversion Factor:
1 Inch = 25.40 mm
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
12
Part Naming Nomenclature
SP63NN - Th1 - Th2 - TOPT
T1 -- 50 ms
T2 -- 100 ms
T3 -- 200 ms
T4 -- 400 ms
A -- 0.788 V
B -- 0.833 V
C -- 1.050 V
D -- 1.110 V
E -- 1.313 V
F -- 1.388 V
G -- 1.575 V
H -- 1.665 V
I -- 2.188 V
J -- 2.313 V
Z -- 4.625 V
Y -- 4.375 V
X -- 3.075 V
W -- 2.925 V
V -- 2.625 V
U -- 2.320 V
T -- 2.190 V
S -- 1.670 V
R -- 1.580 V
30 -- Quad Sp, MR, WDI, OD RSTB
31 -- Quad Sp, OD RSTB
32 -- Quad Sp, MR, WDI, CMOS RSTB
33 -- Quad Sp, CMOS RSTB
34 -- Quad Sp, MR, WDI, CMOS RST
35 -- Quad Sp, CMOS RST
36 -- Triple Sp, WDI, PF, OD RSTB
37 -- Triple Sp, WDI, PF, CMOS RSTB
38 -- Triple Sp, WDI, PF, CMOS RST
39 -- Triple Sp, MR, WDI, OD RSTB - WDOB
40 -- Dual Sp, WDI, OD RSTB - WDOB
41 -- Triple Sp, WDI, PF, CMOS RSTB - WDOB
42 -- Dual Sp, WDI, CMOS RSTB - WDOB
{
{
{
A
B
C
D
E
FG
H
IJK
LM
A
B
C
D
Example:
AZJD means:
SP6330 in TSOT-8 lead package
V1 Threshold is 4.625V
V2 Threshold is 2.313V
Reset Timeout is 400ms
AZJD
Pin 1
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
13
Model Temperature Range
Package Types
SP6330EK1-L-X-X-X...........................................-40°C to +85°C.................................Lead Free 8-Pin TSOT
SP6330EK1-L-X-X-X/TR......................................-40°C to +85°C.................................Lead Free 8-Pi n TSOT
SP6332EK1-L-X-X-X............................................-40°C to +85°C.................................Lead Free 8-Pin TSOT
SP6332EK1-L-X-X-X/TR......................................-40°C to +85°C.................................Lead Free 8-Pi n TSOT
SP6334EK1-L-X-X-X............................................-40°C to +85°C.................................Lead Free 8-Pin TSOT
SP6334EK1-L-X-X-X/TR......................................-40°C to +85°C.................................Lead Free 8-Pi n TSOT
Available in lead free packaging only. /TR = Tape and Reel
Pack quantity 2,500 forTSOT-8
Contact Factory for availability of particular voltage threshold and reset timeout options. Note that the
Ordering Information denoting those options corresponds to the Part Naming Nomenclature shown on the
previous page.
Ordering example: SP6330EK1-L-W-G-C/TR == W -- 2.925V for Voltage Threshold 1; G -- 1.575V for
Voltage Threshold 2; and C -- 200ms reset timeout.
ORDERING INFORMATION
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Datasheet Appendix & Web Link Information © 2007 Sipex Corporation
For further assistance:
Email: Sipexsupport@sipex.com
WWW Support page: http://www.sipex.com/content.aspx?p=support
Sipex Application Notes: http://www.sipex.com/applicationNotes.aspx
Product Change Notices: http://www.sipex.com/content.aspx?p=pcn
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA95035
tel: (408) 934-7500
faX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of
any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
The following sections contain information which is more
changeable in nature and is therefore generated as appendices.
1) Package Outline Drawings
2) Ordering Information
If Available:
3) Frequently Asked Questions
4) Evaluation Board Manuals
5) Reliability Reports
6) Product Characterization Reports
7) Application Notes for this product
8) Design Solutions for this product
Solved by
TM
Solved by
TM
Appendix and Web Link Information
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SP6334 product details
You are here : Home : Products : Supervisors
: SP6334
Features
Low operating voltage of 1.6V
Low operating current of 20uA typical
Monitors up to four supplies simultaneously
Adjustable inputs monitor down to 0.5V
Reset asserted down to 0.9V
2% accuracy over temperature range
CMOS RST High output
4 Reset Timeout Periods: 50ms, 100ms, 200ms and
400 ms
Watch Dog Input Functionality -- WDI
Manual Reset Input (Active Low) -- MRIB
8 Pin TSOT package
Contact factory for availability of particular threshold and
reset timeout options. For sampling, please request
SP6330EK1-xxx [ SP6330EK1-L-W-G-C , or SP6330EK1-L-X-
J-C , or SP6330EK1-L-Z-J-C ] for evaluation. The SP6330
device is the superset of the all functions represented within
the family.
Quad microPower Supervisory Circuits with Manual
Reset and Watchdog
Quick Links
Download
Datasheet
Check Price and
Availability
Design-
In Support
Email: Tech Support
Supervisors Product
Selector
Applications Notes
Evaluation Boards
Quality Information
Part Nomenclature
SP6334 FAQ
Ordering Part Number
Part Number Package
Code
RoHS MIN.
Temp. (°
C)
MAX.
Temp.(°
C)
Status Buy
SP6334EK1-L
SUPERVISORS QUAD
SP6334: CONTACT
FACTORY FOR VOLTAGE
OPTIONS
New!
TSOT8 ▪ -40 85 CF_
Part Status Legend
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-
times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.
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Jun 27-06 SP6330 Family: Selecting a Multi-Voltage Supervisor © 2006 Sipex Corporation
Page 1 of 6
Introduction
The primary function of a microprocessor (µP) supervisor circuit is to ensure that
the input supply voltage of a microprocessor is at proper levels during power up,
power down and brownout conditions. If the input supply voltage to a
microprocessor is below its required operating range, it could cause code-
execution errors, memory corruption and latch up. The supervisor will constantly
monitor the input supply to the microprocessor, and in the event this supply
voltage falls below a certain threshold, the RESET output will be asserted. Many
of today’s power products require several different voltage rails for powering
various components. The microprocessor itself can have a separate core voltage
and logic voltage. Other components such as DSPs, ASICs and microcontrollers
can have their own unique voltage requirements. To service this demand of
monitoring multi-voltage systems, Sipex has developed the SP6330 family. The
SP6330 family is a series of multi-voltage supervisors that offer monitoring of up
to 4 separate supplies and are equipped with specialized features. A complete
listing of products and features are listed in Figure 4 at the end of this note.
SP6332 typical applications circuit for monitoring 4 supplies with Master
Reset, Watchdog input and CMOS Reset output
RSTB
V1
V2
V3
V4
I/O
R2
R3
R4
R5
0.1uF
0.1uF
0.1uF 0.1uF
MR
SP6332
V1
1
V2
2
MRIB
3
V3
4
GND 6
WDI 7
RSTB 8
V4 5
Supplies
uP
C4C3
C2
C1
monitored
to be
Solved by
TM
APPLICATION NOTE ANP14
Understanding and Selecting a Multi-Voltage
Supervisor
F
eaturing the SP6330
F
amily
Jun 27-06 SP6330 Family: Selecting a Multi-Voltage Supervisor © 2006 Sipex Corporation
Page 2 of 6
Inputs to the SP6330 Family
The SP6330 family has the ability to monitor up to 4 different voltages. Two of
these inputs (V1 and V2) have precision factory-set thresholds while the
remaining two inputs (V3 and V4) are adjustable. V3 and V4 inputs allow the user
to customize two additional supply thresholds by means of an external divider.
The threshold for V3 and V4 inputs is 0.5Volts. The V1 input supplies power to
the device and will have the highest threshold for a given application; its
minimum operating voltage for is 1.8V. The factory set threshold range for V1
and V2 inputs are shown in Figure 1.
V1
Typical
Threshold
V2
Typical
Threshold
4.625 2.313
4.375 2.188
3.075 1.665
2.925 1.575
2.625 1.388
2.320 1.313
2.190 1.110
1.670 1.050
1.580 0.833
0.788
Figure 1
Reset Output – RST or RSTB
The reset output can be either active low or active high depending on each
device. The reset output can also be either open-drain or push-pull outputs. The
open drain output requires an external pull-up resistor to V1 for normal operation.
The output high voltage (V
OH
) of the reset output will be approximately equal to
the V1 input voltage.
Reset Timeout Period
The reset timeout period is a built-in time delay for the reset output. This timeout
period is activated at power up or when all monitored voltages have risen above
their respective thresholds. Reset timeout period for the SP6330 family is offered
in four different time intervals: 50ms, 100ms, 200ms and 400ms. The actual
selection of timeout period depends on the applications requirements of the
system voltage settle time. The reset timeout period is used to ensure that all
voltage rails and system clocks have stabilized prior to executing code to prevent
errors or data corruption.
Jun 27-06 SP6330 Family: Selecting a Multi-Voltage Supervisor © 2006 Sipex Corporation
Page 3 of 6
Manual Reset Input (Active Low) – MRIB
The manual reset input allows the user to manually trigger a reset when
monitored voltages are within tolerance. This is useful for resetting the
microprocessor when it locks up due to software issues. A push-button type
switch can be used to allow the user to trigger a reset externally. However, since
a push button switch will bounce several times, a debounce element is needed.
The manual reset input signal may also be a logic signal from an I/O line,
watchdog timer or a power fail output.
Watchdog Input – WDI
The watchdog checks for proper software execution. If the software locks up or
enters into an unwanted, loop the watchdog timer can either assert a reset output
or a watchdog output. Some members of the SP6330 family offer a watchdog
output while others do not. The watchdog has an internal timer that has a typical
watchdog timeout period of 1.6 seconds. If the watchdog input (WDI) does not
detect a transition within 1.6 seconds, a reset or watchdog output (WDO) will be
generated. The watchdog input is usually connected to an I/O line for monitoring
software activity. The watchdog circuit is useful for generating a reset or Non-
Maskable Interrupt (NMI) signal during software lock up conditions without
human intervention. Floating the WDI will disable the watchdog feature.
Watchdog Output (Active Low) – WDOB
The Watchdog output is active low and can be either an open drain or push-pull
output. If WDI remains at “HIGH” or “LOW” logic level for longer than the
watchdog timeout period, the internal watchdog timer overflows and the WDOB
will be asserted. Additionally, if the reset output is asserted due to an under-
voltage condition, at any voltage input the WDOB would also be asserted.
Floating WDI will not disable the watchdog timer in devices with dedicated
WDOB output.
Power Fail Input (PFI)
The power fail input is used to monitor the unregulated DC voltage or other
upstream voltage and to alert the system that a brownout or power failure is
imminent. When the PFI input is tripped, it can inform the system to start a
power-down routine in order to save important data before a reset output is
asserted. The power fail input has a threshold of 0.5V. By using a voltage divider
the user can monitor any upstream voltage. Connect PFI to V1 or GND if not used.
Jun 27-06 SP6330 Family: Selecting a Multi-Voltage Supervisor © 2006 Sipex Corporation
Page 4 of 6
Power Fail Output (Active Low) - PFOB
The PFOB pin is an open drain, active low output. When the input voltage at PFI
is <0.5V, PFOB will be asserted.
R4
R5
R6
RI
RSTB
V1
V3
V2
uP
I/O
R2
R3
0.1uF
0.1uF
0.1uF
Unregulated DC
monitored
to be
Supplies
C1
C3
C2
SP6336
V1
1
V2
2
PFI
3
V3
4PFOB 5
GND 6
WDI 7
RSTB 8
NMI
SP6336 Typical Applications circuit for monitoring 3 supplies with Power
Fail Input / Output function and open drain RESET output
Glitch Immunity at Voltage Inputs
The V1, V2, V3 and V4 inputs have a built-in glitch immunity feature that
prevents nuisance resets during normal operation. Noise and normal voltage
transients can cause these unwanted resets without some type of glitch
immunity. Figure 2 shows the combination of voltage overdrive and duration that
will not cause a reset for V1 and V2 inputs. Figure 3 shows the same data as
applied to the V3 and V4 inputs. Adding a small bypass capacitor to voltage
inputs can improve glitch rejection for very harsh environments.
Jun 27-06 SP6330 Family: Selecting a Multi-Voltage Supervisor © 2006 Sipex Corporation
Page 5 of 6
Figure 2
Figure 3
V3 and V4 glitch rejection
0
20
40
60
80
100
120
0 20 40 60 80 100 120
Overdrive (mV)
Duration (uS)
RSTB asserted
above line
V1 and V2 Glitch rejection
0
50
100
150
200
250
0 20 40 60 80 100 120
Overdrive (mV)
Duration (uS)
RSTB asserted
above line
Jun 27-06 SP6330 Family: Selecting a Multi-Voltage Supervisor © 2006 Sipex Corporation
Page 6 of 6
SP633X Features
• Quad, triple or dual supply monitoring
• Very low operating voltage down to 1.6V
• Low 20µA typical operating current
• Adjustable inputs monitor down to 0.5V
• Open drain or CMOS reset outputs
• 4 reset timeout periods: 50ms, 100ms, 200ms and 400ms
• Glitch immunity inputs
• Tiny 6 pin or 8 pin TSOT package
P/N V1
V2
V3
V4
Reset Reset
MRIB
WDI
WDOB
WDOB
PFI
PFOB
Package
Output
Active
OD CMOS
SP6330 X X X X OD LOW X X 8-TSOT
SP6332 X X X X CMOS
LOW X X 8-TSOT
SP6334 X X X X CMOS
HIGH
X X 8-TSOT
SP6331 X X X X OD LOW 6-TSOT
SP6333 X X X X CMOS
LOW 6-TSOT
SP6335 X X X X CMOS
HIGH
6-TSOT
SP6336 X X X OD LOW X X X 8-TSOT
SP6337 X X X CMOS
LOW X X X 8-TSOT
SP6338 X X X CMOS
HIGH
X X X 8-TSOT
SP6339 X X X OD LOW X X X 8-TSOT
SP6341 X X X CMOS
LOW X X X 8-TSOT
SP6340 X X OD LOW X X 6-TSOT
SP6342 X X CMOS
LOW X X 6-TSOT
Figure 4: Product Selection Guide
Date: 5/3/06 SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
1
FAQ SP6330 - SP6342
Dual/Triple/Quad µPower Supervisory Circuit
Family
SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family is a family of
microprocessor reset supervisory circuits with multiple reset voltages. The SP6330 family
provides low voltage monitoring ability for up-to four supplies with two precision factory-set
thresholds and two user defined custom thresholds. These circuits perform a single function:
if any of the input supply voltages drops below its associated threshold, reset outputs are
asserted. Some of the products in the family offer manual reset,power fail and watchdog
functionalities. The SP63XX family includes a low-voltage precision bandgap reference, four
precision comparators, an oscillator, a digital counter chain, a logic control block, trimmed
resistor divider chains and additional supporting circuitry. V1 and V2 supply inputs have their
resistor dividers on the chip. Their trip thresholds are factory trimmed. V3 and V4 inputs allow
user to customize two additional supply thresholds to be monitored by means of external
resistor dividers. Some members of the family are furnished with manual reset, power fail
indication, watchdog functionalities.SP6330 thru SP6342 are housed in a 6-pin or 8-pin
SOT23 package. All devices are fully specified over -40oC to +85oC temperature range.
FEATURES
■ Low operating voltage of 1.8V
■ Low operating current of 20µA typical
■ Monitors up to four supplies simultaneously
■ Adjustable inputs monitor down to 0.5V
■ Reset asserted down to 0.9V
■ 2% accuracy over temperature range
■ Power Fail function
■ Open Drain (OD) or CMOS RSTB output or
CMOS RST output
■ 200ms Reset Timeout Period
■ Watch Dog Timer Function
■ Independent Open Drain Watchdog Output
■ Manual Reset Input
■ SOT23-6/8 packages
DESCRIPTION
Available in Lead Free Packaging
1
2
3
45
6
7
8
8 Pin SOT-23
V2
SP6330
V1
MRIB
V3
WDI
GND
V4
RSTB
Open Drain RESET
SEE PAGE 3 FOR OTHER
AVAILABLE PINOUTS
Date: 5/3/06 SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
2
PART
NUMBER V1 V2 V3 V4 Reset
Manual
Reset
Input BAR
WatchDog
Input
WatchDog
Output BAR
Power
Fail
Input
Power Fail
Output
BAR
# of
Pins
Data-
sheet
Group
SP6330 √ √ √ - OD Active Low √ √ - - - 8 1
SP6331 √√√√ OD Active Low - - - - - 6 5
SP6332 √ √ √ - CMOS Active Low √ √ - - - 8 1
SP6333 √√√√CMOS Active Low - - - - - 6 5
SP6334 √ √ √ - CMOS Active High √ √ - - - 8 1
SP6335 √√√√CMOS Active High - - - - - 6 5
SP6336 √ √ √ - OD Active Low - √ - √ √ 8 2
SP6337 √ √ √ - CMOS Active Low - √ - √ √ 8 2
SP6338 √ √ √ - CMOS Active High - √ - √ √ 8 2
SP6339 √ √ √ - OD Active Low √ √ OD Active Low - - 8 3
SP6340 √ √ - - OD Active Low - √ OD Active Low - - 6 4
SP6341 √ √ √ - CMOS Active Low √ √ CMOS Active Low - - 8 3
SP6342 √ √ - - CMOS Active Low - √ CMOS Active Low - - 6 4
FEATURE MAPPING DIAGRAM
Date: 5/3/06 SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
3
PINOUT MASTER DIAGRAM
V1
V2
V1
V2
RSTB
WDI
GND
V4
V1
V2
MRIB
V4
WDI
RST
GND
Open Drain RSTB CMOS RSTB CMOS RST
V1
V2
V3 V4
RSTB
GND
Open Drain RSTB
V1
V2
V3 V4
RSTB
GND
CMOS RSTB
V1
V2
V3 V4
RST
GND
CMOS RST
V1
V2
V3
PFI
WDI
RSTB
GND
V1
V2
V3
PFI
WDI
RSTB
GND
V1
V2
V3
PFI
WDI
RST
GND
Open Drain RSTB CMOS RSTB
CMOS RST
PFOB
PFOBPFOBV3
V1
V2
V3
WDI GND
RSTB
MRIB
WDOB
1
2
3
45
6
7
81
2
3
45
6
7
81
2
3
45
6
7
81
2
3
45
6
7
81
2
3
45
6
7
8
1
2
3
45
6
7
81
2
34
5
61
2
34
5
61
2
34
5
61
2
3
45
6
7
8
SV02-SIP1
MOPT-B
(SOT23-6)
1
2
34
5
6
V1
V2
V3
WDI GND
RSTB
MRIB
WDOB
1
2
3
45
6
7
8
V1
V2
WDI WDOB
RSTB
GND
1
2
34
5
6
Open Drain RSTB
Open Drain RSTB CMOS RSTB
V1
V2
WDI WDOB
RSTB
GND
1
2
34
5
6
CMOS RSTB
V3
MRIB
V4
GND
WDI
RSTB
V3
MRIB
SP6342
(SOT23-6)
SP6341
(SOT23-8)
SP6339
(SOT23-8)
SP6338
(SOT23-8)
SP6337
(SOT23-8)
SP6336
(SOT23-8)
SP6335
(SOT23-6)
SP6334
(SOT23-8)
SP6333
(SOT23-6)
SP6332
(SOT23-8)
SP6331
(SOT23-6)
SP6330
(SOT23-8)
SP6340
(SOT23-6)
Date: 5/3/06 SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
1
FAQ SP6330 - SP6342
Dual/Triple/Quad µPower Supervisory Circuit
Family
SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family is a family of
microprocessor reset supervisory circuits with multiple reset voltages. The SP6330 family
provides low voltage monitoring ability for up-to four supplies with two precision factory-set
thresholds and two user defined custom thresholds. These circuits perform a single function:
if any of the input supply voltages drops below its associated threshold, reset outputs are
asserted. Some of the products in the family offer manual reset,power fail and watchdog
functionalities. The SP63XX family includes a low-voltage precision bandgap reference, four
precision comparators, an oscillator, a digital counter chain, a logic control block, trimmed
resistor divider chains and additional supporting circuitry. V1 and V2 supply inputs have their
resistor dividers on the chip. Their trip thresholds are factory trimmed. V3 and V4 inputs allow
user to customize two additional supply thresholds to be monitored by means of external
resistor dividers. Some members of the family are furnished with manual reset, power fail
indication, watchdog functionalities.SP6330 thru SP6342 are housed in a 6-pin or 8-pin
SOT23 package. All devices are fully specified over -40oC to +85oC temperature range.
FEATURES
■ Low operating voltage of 1.8V
■ Low operating current of 20µA typical
■ Monitors up to four supplies simultaneously
■ Adjustable inputs monitor down to 0.5V
■ Reset asserted down to 0.9V
■ 2% accuracy over temperature range
■ Power Fail function
■ Open Drain (OD) or CMOS RSTB output or
CMOS RST output
■ 200ms Reset Timeout Period
■ Watch Dog Timer Function
■ Independent Open Drain Watchdog Output
■ Manual Reset Input
■ SOT23-6/8 packages
DESCRIPTION
Available in Lead Free Packaging
1
2
3
45
6
7
8
8 Pin SOT-23
V2
SP6330
V1
MRIB
V3
WDI
GND
V4
RSTB
Open Drain RESET
SEE PAGE 3 FOR OTHER
AVAILABLE PINOUTS
Date: 5/3/06 SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
2
PART
NUMBER V1 V2 V3 V4 Reset
Manual
Reset
Input BAR
WatchDog
Input
WatchDog
Output BAR
Power
Fail
Input
Power Fail
Output
BAR
# of
Pins
Data-
sheet
Group
SP6330 √ √ √ - OD Active Low √ √ - - - 8 1
SP6331 √√√√ OD Active Low - - - - - 6 5
SP6332 √ √ √ - CMOS Active Low √ √ - - - 8 1
SP6333 √√√√CMOS Active Low - - - - - 6 5
SP6334 √ √ √ - CMOS Active High √ √ - - - 8 1
SP6335 √√√√CMOS Active High - - - - - 6 5
SP6336 √ √ √ - OD Active Low - √ - √ √ 8 2
SP6337 √ √ √ - CMOS Active Low - √ - √ √ 8 2
SP6338 √ √ √ - CMOS Active High - √ - √ √ 8 2
SP6339 √ √ √ - OD Active Low √ √ OD Active Low - - 8 3
SP6340 √ √ - - OD Active Low - √ OD Active Low - - 6 4
SP6341 √ √ √ - CMOS Active Low √ √ CMOS Active Low - - 8 3
SP6342 √ √ - - CMOS Active Low - √ CMOS Active Low - - 6 4
FEATURE MAPPING DIAGRAM
Date: 5/3/06 SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation
3
PINOUT MASTER DIAGRAM
V1
V2
V1
V2
RSTB
WDI
GND
V4
V1
V2
MRIB
V4
WDI
RST
GND
Open Drain RSTB CMOS RSTB CMOS RST
V1
V2
V3 V4
RSTB
GND
Open Drain RSTB
V1
V2
V3 V4
RSTB
GND
CMOS RSTB
V1
V2
V3 V4
RST
GND
CMOS RST
V1
V2
V3
PFI
WDI
RSTB
GND
V1
V2
V3
PFI
WDI
RSTB
GND
V1
V2
V3
PFI
WDI
RST
GND
Open Drain RSTB CMOS RSTB
CMOS RST
PFOB
PFOBPFOBV3
V1
V2
V3
WDI GND
RSTB
MRIB
WDOB
1
2
3
45
6
7
81
2
3
45
6
7
81
2
3
45
6
7
81
2
3
45
6
7
81
2
3
45
6
7
8
1
2
3
45
6
7
81
2
34
5
61
2
34
5
61
2
34
5
61
2
3
45
6
7
8
SV02-SIP1
MOPT-B
(SOT23-6)
1
2
34
5
6
V1
V2
V3
WDI GND
RSTB
MRIB
WDOB
1
2
3
45
6
7
8
V1
V2
WDI WDOB
RSTB
GND
1
2
34
5
6
Open Drain RSTB
Open Drain RSTB CMOS RSTB
V1
V2
WDI WDOB
RSTB
GND
1
2
34
5
6
CMOS RSTB
V3
MRIB
V4
GND
WDI
RSTB
V3
MRIB
SP6342
(SOT23-6)
SP6341
(SOT23-8)
SP6339
(SOT23-8)
SP6338
(SOT23-8)
SP6337
(SOT23-8)
SP6336
(SOT23-8)
SP6335
(SOT23-6)
SP6334
(SOT23-8)
SP6333
(SOT23-6)
SP6332
(SOT23-8)
SP6331
(SOT23-6)
SP6330
(SOT23-8)
SP6340
(SOT23-6)
Reliability Report: SP6330 April 7, 2006
Page 1 of 5
Reliability and Qualification Report
SP6330
Prepared by: G. West Reviewed by: Fred Claussen
Manager, Quality Assurance VP Quality & Reliability
Date: April 7, 2006 Date: April 7, 2006
Reliability Report: SP6330 April 7, 2006
Page 2 of 5
Table Of Contents
Title Page…………………………………………………………..………I
Table of Contents………………………………………………….………II
Device Description …………………………………………..………..…..II
Block Diagram……………………………………………………………..II
Manufacturing Information……………………….……………………….III
Package Information………………………………….……………………III
Reliability Test Summary.………………..……………….…………….…IV
Life Test Data……………………………………………………………...IV
FIT Data Calculations……………………………………………….……..V
MTBF Data Calculations……………………………………...…………...V
Device Description:
SP6330-SP6332- SP6334 Quad Power Supervisory Circuit Family is a family of
microprocessor reset supervisory circuits with multiple reset voltages. The family provides
low voltage monitoring ability for up-to four supplies with two precision factory-set thresholds
and two user defined custom thresholds. These circuits perform a single function: if any of
the input supply voltages drops below its associated threshold, reset outputs are asserted.
The SP6330, SP6332, and SP6334 are packaged in an 8-pin TSOT package. All devices are
fully specified over -40oC to +85oC temperature range.
SP6330 Pin Out
Manufacturing Information:
Products: SP6330
Description: Quad Power Supervisory Circuit
Mask Set(s): MS1512AZ
Process: CMOS
Process Name: PBC4
Wafer Manufacturer: Polar Semiconductor, Inc.
Assembly Location: Carsem – Malaysia
Qualification Lot #’s: 3522A001A.11, 3638A001.8, 3638A001.6
Reliability Report: SP6330 April 7, 2006
Page 3 of 5
Package Information:
Package Type: 8 pin TSOT
Die Size: 45 x 67 mil
Reliability Qualification Test Summary:
Stress Level
Device Burn-In Temp Sample Size No. Fail
168Hrs SP6330 125 °C 240 0
500Hrs SP6330 125 °C 240 0
1000Hrs SP6330 125 °C 240 0
Life Test
Life testing is conducted to determine if there are any fundamental reliability related
failure mechanism(s) present in the device.
These failure mechanisms can be divided roughly into four groups:
1. Process or die related failures, such as oxide-related defec ts, metalization-related
defects and diffusion-related defects.
2. Assembly-related defects such as chip mount wire bond or package-related
failures.
3. Design related defects.
4. Miscellaneous, undetermined or application-induced failures.
Life Test Results
As part of the Sipex design qualification program, the Engineering group had subjected
80 parts from each of 3 lots of SP6330 for a 1000 hour reliability life test at 125° C.
168 hour Life test
240 parts of SP6330 parts were subjected to the life test profile and completed
168hr the test without any part failures.
500 hour Life test
Reliability Report: SP6330 April 7, 2006
Page 4 of 5
The 240 parts of SP6330 we reintroduced to the second phase of the test, where
the parts again showed successfully completing the 500-hour life test without any
failures.
1000 hour Life test
The 240 parts of the SP6330 were reintroduced to the final phase of the test,
where the parts again successfully completed 1000-hour life test without any shift
on the process parameters.
FIT Rate Calculations
The FIT (failures in time) rate is the predicted number of failures per billion device-
hours. This predicted value is based upon the:
1. Life Test conditions (time and temperature, device quantity and number of failures)
are summarized under HTOL test table.
2. Activation Energy (Ea) of the potential failure modes.
The weighted Activation Energy, E
a, of observed failure mechanisms of Sipex products
has been determined to be 0.8 eV.
Based on the above criteria, the FIT rates at 25°, 55° and 70°C operation at both 60% and
90% confidence levels for the SP6330 product lines have been calculated and are listed
below.
FIT Failure Rates SP6330 Product
Confidence Level +25°C +55°C +70°C
60% 1.6 26.6 90.8
90% 4.1 68.4 233.1
1 FIT = 1 Failure per Billion Device-Hours
MTBF Calculation for SP6330 Product
Confidence Level +25°C +55°C +70°C
60% 6.30E+08 3.75E+07 1.10E+07
90% 2.46E+08 1.46E+07 4.29E+06
Reliability Report: SP6330 April 7, 2006
Page 5 of 5
ESD Testing
HBM ESD Testing - 5 units from each of three lots were subjected to 4000 V Human
Body Model (HBM) ESD stress. Each pin was subjected to three positive and three
negative pulses with respect to ground. All units passed testing after ESD stress.
Latch-up Testing - 5 units from each of three lots were subjected to latch-up testing at +/-
100mA. All units passed.
