SP6330, SP6332 and SP6334 Quad Power Supervisory Circuits with Manual Reset & Watchdog FEATURES Low operating voltage of 1.6V Low operating current of 20A typical Monitors up to four supplies simultaneously Adjustable inputs monitor down to 0.5V Reset asserted down to 0.9V 2% accuracy over temperature range Open Drain (OD) or CMOS RSTB output or CMOS RST output 4 Reset Timeout Periods: 50ms, 100ms, 200ms and 400ms Watch Dog Input Functionality -- WDI Manual Reset Input (Active Low) -- MRIB 8 Pin TSOT package V1 1 V2 2 MRIB 3 8 RSTB SP6330 8 Pin TSOT 7 WDI 6 GND V3 4 5 V4 Open Drain RESET SEE PAGE 2 FOR OTHER AVAILABLE PINOUTS Available in Lead Free Packaging DESCRIPTION SP6330-SP6332- SP6334 Quad Power Supervisory Circuit Family is a family of microprocessor reset supervisory circuits with multiple reset voltages. The family provides low voltage monitoring ability for up-to four supplies with two precision factory-set thresholds and two user defined custom thresholds. These circuits perform a single function: if any of the input supply voltages drops below its associated threshold, reset outputs are asserted. The SP6330, SP6332, and SP6334 are packaged in an 8-pin TSOT package. All devices are fully specified over -40oC to +85oC temperature range. TYPICAL APPLICATION CIRCUIT Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family 1 (c) Copyright 2006 Sipex Corporation PINOUT DIAGRAMS V1 1 V2 2 MRIB 3 SP6330 8 Pin TSOT V3 4 8 RSTB V1 1 7 WDI V2 2 6 GND MRIB 3 5 V3 4 V4 8 RSTB V1 1 7 WDI V2 2 6 GND MRIB 3 5 SP6334 8 Pin TSOT V3 4 V4 8 RST 7 WDI 6 GND 5 V4 CMOS RESET CMOS RESET Open Drain RESET PART NUMBER SP6332 8 Pin TSOT V1 V2 V3 V4 Reset MRIB WDI SP6330 OD Active Low SP6332 CMOS Active Low SP6334 CMOS Active High Feature and Pinout Diagram Representative Samples Available Sipex Product SP6330 SP6330 SP6330 SP6332 Product Description Quad Supervisor Open Drain low Quad Supervisor Open Drain low Quad Supervisor Open Drain low Quad Supervisor CMOS low V1 V2 V3 V4 Reset (Volts) (Volts) (Volts) (Volts) (ms) 8 Pin TSOT 2.925 1.575 0.5 0.5 200 SP6330EK1-L-W-G-C 8 Pin TSOT 3.075 2.313 0.5 0.5 200 SP6330EK1-L-X-J-C 8 Pin TSOT 4.625 2.313 0.5 0.5 200 SP6330EK1-L-Z-J-C 8 Pin TSOT 2.625 1.575 0.5 0.5 200 SP6330EK1-L-V-G-C Package Ordering # ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. Terminal Voltage (with respect to GND) V1, V2..................................................... -0.3 to +6V Open-Drain RSTB.......................................-0.3 to +6V CMOS RST, RSTB, ..................... -0.3 to (V1+0.3V) Input Current/Output Current..................................,,........................20mA Operating Temperature Range...............................................-40Cto +85 C Storage Temperature Range...............................................-65C to 150C Thermal Resistance OJA.............................134C/W V3, V4, MRIB, WDI........................-0.3 to (V1+0.3V) Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family 2 (c) Copyright 2006 Sipex Corporation ELECTRICAL CHARACTERISTICS PARAMETER MIN TYP MAX UNITS CONDITIONS V1 =1.6V to 5.5V; TA = -40C to +85C; unless otherwise noted. Typical values are at TA =+25C Operating Voltage Range 0.9 5.5 V 20 30 uA 15 25 4.625 4.375 3.075 2.925 2.625 2.320 2.190 1.670 1.580 2.313 2.188 1.665 1.575 1.388 1.313 1.110 1.050 0.833 0.788 4.718 4.463 3.137 2.984 2.678 2.367 2.234 1.704 1.612 2.360 2.232 1.698 1.607 1.416 1.340 1.133 1.071 0.850 0.804 Supply Current V1 Reset Threshold V2 Reset Threshold Threshold 1 Tempco Threshold 2 Tempco Threshold 1 Hysteresis Threshold 2 Hysteresis V1 to RST/RSTB Delay V2 to RST/RSTB Delay Reset Timeout Period (T1) Reset Timeout Period (T2) Reset Timeout Period (T3) Reset Timeout Period (T4) Nov20-06 Rev M 4.532 4.287 3.013 2.866 2.572 2.273 2.146 1.636 1.548 2.266 2.144 1.631 1.543 1.360 1.286 1.087 1.029 0.816 0.772 V V TA = -40C to +85C V1 < 5.5V, V2 < 3.60V, all I/O pins open V1 < 3.6V, V2 < 2.75V, all I/O pins open Z (valid for V1 falling) Y (valid for V1 falling) X (valid for V1 falling) W (valid for V1 falling) V (valid for V1 falling) U (valid for V1 falling) T (valid for V1 falling) S (valid for V1 falling) R (valid for V1 falling) J (valid for V2 falling) I (valid for V2 falling) H (valid for V2 falling) G (valid for V2 falling) F (valid for V2 falling) E (valid for V2 falling) D (valid for V2 falling) C (valid for V2 falling) B (valid for V2 falling) A (valid for V2 falling) 0.06 mV/C 0.04 mV/C 0.65 % reference to Vth1 typical 0.5 % reference to Vth2 typical 50 us 50 us V1 = Vth1 to (Vth1-0.1V), Vth1 = 3.075 V2 = Vth2 to (Vth2-0.1V), Vth2 = 1.575 37 50 63 ms TOPT-1 74 100 126 ms TOPT-2 148 200 252 ms TOPT-3 296 400 504 ms TOPT-4 SP6330/32/34 Quad Power Supervisory Circuit Family 3 (c) Copyright 2006 Sipex Corporation ELECTRICAL CHARACTERISTICS PARAMETER MIN TYP MAX CONDITIONS UNITS V1 =1.6V to 5.5V; TA = -40C to +85C; unless otherwise noted. Typical values are at TA =+25C V3 RESET COMPARATOR INPUT V3 Input Threshold 490 V3 Input Current -50 V3 Threshold Hysteresis V4 RESET COMPARATOR INPUT V4 Input Threshold 490 -50 V4 Input Current V4 Threshold Hysteresis MRIB - MANUAL RESET INPUT MRIB Input Threshold MRIB Input 0.8*V1 Threshold MRIB Minimum 1 Input Pulse Width MRIB Glitch Rejection MRIB to RST/RSTB Delay MRIB Pull-Up 30 Resistance WDI - WATCHDOG INPUT Watchdog Timeout 1.3 Period WDI Pulse Width 0.1 WDI Input Threshold WDI Input 0.8*V1 Threshold WDI Input Current -500 RESET OUTPUTS RST / RSTB RSTB (CMOS or OD) 500 510 50 1.5 500 mV nA mV 510 50 1.5 mV nA 0.2*V1 V Vil V Vih us 150 ns 100 ns 55 85 k 1.6 1.9 sec us 0.2*V1 V Vil V Vih 500 nA WDI = 0.0V or V1 0.2*V1 V 0.8*V1 V RST (CMOS) 0.8*V1 V RST (CMOS) Nov20-06 Rev M TA = +25C mV RSTB (CMOS) RSTB Output OD Leakage Current TA = +25C 0.2*V1 2 V nA SP6330/32/34 Quad Power Supervisory Circuit Family 4 V1 = Vth1 - 0.1V, Isink = 1mA, output asserted V1 = Vth1 + 0.1V, Isource = 1mA, output not asserted V1 = Vth1 - 0.1V, Isource = 1mA, output asserted V1 = Vth1 + 0.1V, V2 > Vth2, V3 > 0.5, V4 > 0.5, Isource = 1mA, output not asserted TA = +25C (c) Copyright 2006 Sipex Corporation PIN DESCRIPTION Pin # Name 1 V1 First supply voltage input. Also powers internal circuitry. Trip threshold voltage internally set. 2 V2 Second supply voltage input. Trip threshold voltage internally set. 3 MRIB 4 V3 Input for the third supply voltage. Trip threshold is 0.5V. 5 V4 Input for the fourth supply voltage. Trip threshold is 0.5V. 6 GND Common ground reference pin. WDI Watch-Dog Input pin. When no transition is detected at the WDI pin for the duration of WDI timeout period, reset is asserted. Leave open if not used. RST/RSTB output is used to signal watchdog timeout overflow. RST/RSTB output pulses high/low (depending on the active reset polarity) for the reset timeout period after each watchdog timeout overflow. The watchdog timer clears whenever the reset is asserted or manual reset is asserted or a transition is observed at WDI pin. Watchdog timer functionality can be disabled in parts by leaving this input floating. RST/RSTB Reset output. Open-Drain or CMOS, active high or low. Reset is asserted when any of the four supply inputs is below its trip threshold. It stays asserted for 200 ms (typical / default) after the last supply input traverses its trip threshold. Reset is guaranteed to be in the correct state for V1>0.9V. RST/RSTB asserts when V1 or V2 or V3 or V4 drop below their corresponding reset thresholds, or MRIB is pulled "LOW" or the watchdog timer triggers a reset (devices without WDOB). RST/RSTB remains asserted for the reset timeout period after V1 and V2 and V3 and V4 exceed their corresponding reset thresholds or MRIB goes "LOW" to "HIGH". Open-drain outputs require an external pull-up resistor. CMOS outputs are referenced to V1. 7 8 Nov20-06 Rev M Description Manual Reset Input pin. Active low. It has an internal pull-up resistor. Reset asserted when MRIB is pulled low and is kept asserted for 200ms after MRIB is released or pulled high. Leave open if not used. SP6330/32/34 Quad Power Supervisory Circuit Family 5 (c) Copyright 2006 Sipex Corporation THEORY OF OPERATION V1 V2 V3 V4 WDI WDI LOGIC OSC Bandgap Ref CONTROL LOGIC 1.25V RSTB (RST) 0.5V MRIB GND Block Diagram The SP6330, SP6332, and SP6334 include a low-voltage precision bandgap reference, four precision comparators, an oscillator, a digital counter chain, a logic control block, trimmed resistor divider chains and additional supporting circuitry. The family is designed to supervise up to 4 independent supply voltages. V1 and V2 supply inputs have their resistor dividers on the chip. Their trip thresholds are factory trimmed. V3 and V4 inputs allow user to customize Nov20-06 Rev M two additional supply thresholds to be monitored by means of external resistor dividers. The devices also feature manual reset and watchdog functionalities. As these devices do not have watchdog outputs, the watchdog timer is serviced internally during the watchdog timeout period when WDI is left unconnected. The watchdog functionality can be disabled by leaving the WDI input floating. SP6330/32/34 Quad Power Supervisory Circuit Family 6 (c) Copyright 2006 Sipex Corporation THEORY OF OPERATION Vth1 V1 Vth2 V2 Vth3=0.5V V3 Vth4=0.5V V4 MRIB T<Twd T<Twd T<Twd T<Twd T<Twd WDI Trp Trp Trp Twd RSTB Figure 1: Functionality of a SP63XX family member with manual reset and watchdog capabilities but without WDOB output. * V1 > Vth1, V2 > Vth2 , V3 > Vth3 and V4 > Vth4 (all supplies over their corresponding thresholds)---> RSTB is de-asserted after reset timeout period (Trp). * MRIB goes to "LOW" to force "Reset" ----> RSTB is asserted immediately. * WDI does not make any transition during watchdog timeout period (Twd) ---->RSTB is asserted for a duration of reset timeout period (Trp). * One of the supplies drops below its corresponding threshold (in this case V3)---->RSTB is asserted immediately. Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family 7 (c) Copyright 2006 Sipex Corporation APPLICATION INFORMATION V1 RSTB ResetB Timeout Delay WDI = GND, V1=V2=V3=V4=5V, MRIB = open. Watchdog Timeout Period = 1.52S V1 RSTB Watchdog Timeout Period Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family 8 (c) Copyright 2006 Sipex Corporation APPLICATION INFORMATION Re se t Ti m eo ut (m S ec ) Reset Timeout vs. Temperature (400ms Reset) 500 400 300 200 100 0 85 80 70 60 50 40 30 20 10 0 -10 -20 -30 -40 Deg C ResetTimeout Delay Vs. Temperature R S T B v s . V 1 (V 2 = G N D ) RSTB (Volts DC) 5 4.5 4 3 3. 2.5 5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 V1 (Vdc) Reset Good Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family 9 (c) Copyright 2006 Sipex Corporation APPLICATION INFORMATION V 1 a n d V 2 G litc h r e je c tio n 250 Duration (uSec) 200 150 RS TB asser ted above line 100 50 0 0 20 40 60 80 100 120 Overdrive (mV) V1 and V2 Glitch Rejection V 3 a n d V 4 g litc h re je c tio n Duration (uSec) 120 100 80 RS TB asser ted above line 60 40 20 0 0 20 40 60 80 100 120 O v e rd riv e (mV) V3 and V4 Glitch Rejection Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family 10 (c) Copyright 2006 Sipex Corporation PACKAGE: 8 PIN TSOT D D/2 e1 7 8 5 6 E/2 SIDE VIEW E1/2 E E1 A2 A Pin1 Designator to be within this INDEX AREA (D/2 x E1/2) Seating Plane A1 4 3 2 1 (L1) e b TOP VIEW o1 FRONT VIEW R1 R Gauge Plane L2 o L 8 Pin TSOT SYMBOL A A1 A2 c D E E1 L L1 L2 O O1 R R1 JEDEC MO-193 Dimensions in Millimeters: Controlling Dimension MIN 0.00 0.70 0.08 0.30 0 4 0.10 0.10 0.22 b e e1 SIPEX Pkg Signoff Nov20-06 Rev M o1 Seating Plane NOM 0.90 2.90 BSC 2.80 BSC 1.60 BSC 0.45 0.60 REF 0.25 BSC 4 10 0.65 BSC 1.95 BSC Date/Rev: MAX 1.10 0.10 1.00 0.20 0.60 8 12 0.25 0.38 SP6330/32/34 Quad Power Supervisory Circuit Family 11 c Variation BA Dimensions in Inches Conversion Factor: 1 Inch = 25.40 mm MIN NOM MAX 0.043 0.000 0.004 0.028 0.036 0.039 0.003 0.008 0.114 BSC 0.110 BSC 0.063 BSC 0.012 0.018 0.024 0.024 REF 0.010 BSC 0 4 8 4 10 12 0.004 0.004 0.010 0.009 0.015 0.026 BSC 0.077 BSC JL Oct3-05 / Rev A (c) Copyright 2006 Sipex Corporation Part Naming Nomenclature SP63NN - Th1 - Th2 - TOPT { Example: AZJD means: SP6330 in TSOT-8 lead package V1 Threshold is 4.625V V2 Threshold is 2.313V Reset Timeout is 400ms AZJD Pin 1 T1 -- 50 ms A T2 -- 100 ms B T3 -- 200 ms C T4 -- 400 ms D { { A 30 -- Quad Sp, MR, WDI, OD RSTB B 31 -- Quad Sp, OD RSTB C 32 -- Quad Sp, MR, WDI, CMOS RSTB D 33 -- Quad Sp, CMOS RSTB E 34 -- Quad Sp, MR, WDI, CMOS RST F 35 -- Quad Sp, CMOS RST G 36 -- Triple Sp, WDI, PF, OD RSTB H 37 -- Triple Sp, WDI, PF, CMOS RSTB I 38 -- Triple Sp, WDI, PF, CMOS RST J 39 -- Triple Sp, MR, WDI, OD RSTB - WDOB K 40 -- Dual Sp, WDI, OD RSTB - WDOB L 41 -- Triple Sp, WDI, PF, CMOS RSTB - WDOB M 42 -- Dual Sp, WDI, CMOS RSTB - WDOB Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family 12 A -- 0.788 V B -- 0.833 V C -- 1.050 V D -- 1.110 V E -- 1.313 V F -- 1.388 V G -- 1.575 V H -- 1.665 V I -- 2.188 V J -- 2.313 V Z -- 4.625 V Y -- 4.375 V X -- 3.075 V W -- 2.925 V V -- 2.625 V U -- 2.320 V T -- 2.190 V S -- 1.670 V R -- 1.580 V (c) Copyright 2006 Sipex Corporation ORDERING INFORMATION Model Package Types Temperature Range SP6330EK1-L-X-X-X...........................................-40C to +85C.................................Lead Free 8-Pin TSOT SP6330EK1-L-X-X-X/TR......................................-40C to +85C.................................Lead Free 8-Pin TSOT SP6332EK1-L-X-X-X............................................-40C to +85C.................................Lead Free 8-Pin TSOT SP6332EK1-L-X-X-X/TR......................................-40C to +85C.................................Lead Free 8-Pin TSOT SP6334EK1-L-X-X-X............................................-40C to +85C.................................Lead Free 8-Pin TSOT SP6334EK1-L-X-X-X/TR......................................-40C to +85C.................................Lead Free 8-Pin TSOT Available in lead free packaging only. /TR = Tape and Reel Pack quantity 2,500 forTSOT-8 Contact Factory for availability of particular voltage threshold and reset timeout options. Note that the Ordering Information denoting those options corresponds to the Part Naming Nomenclature shown on the previous page. Ordering example: SP6330EK1-L-W-G-C/TR == W -- 2.925V for Voltage Threshold 1; G -- 1.575V for Voltage Threshold 2; and C -- 200ms reset timeout. Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family 13 (c) Copyright 2006 Sipex Corporation Solved by TM Appendix and Web Link Information For further assistance: Email: WWW Support page: Sipex Application Notes: Product Change Notices: Sipexsupport@sipex.com http://www.sipex.com/content.aspx?p=support http://www.sipex.com/applicationNotes.aspx http://www.sipex.com/content.aspx?p=pcn Sipex Corporation Solved by TM Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA95035 tel: (408) 934-7500 faX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. The following sections contain information which is more changeable in nature and is therefore generated as appendices. 1) Package Outline Drawings 2) Ordering Information If Available: 3) Frequently Asked Questions 4) Evaluation Board Manuals 5) Reliability Reports 6) Product Characterization Reports 7) Application Notes for this product 8) Design Solutions for this product Datasheet Appendix & Web Link Information (c) 2007 Sipex Corporation Sipex Corporation - Sipex Product Details Page 1 of 1 Advanced Search Part Number Search PartnerNet Keyword Search Home Products Support Product Lines Power Management Boost Regulators Buck Regulators Charge Pumps LED Drivers Linear Regulators Power BloxTM PWM Controllers References Supervisors USB Vbus Switches Interface Multiprotocol RS232 RS422 RS485 USB Optical Storage Advanced Power Control Photo Detector IC Contact Us About Us SP6334 product details News Investors Careers You are here : Home : Products : Supervisors : SP6334 Quad microPower Supervisory Circuits with Manual Reset and Watchdog Quick Links Download Datasheet Features Low operating voltage of 1.6V Low operating current of 20uA typical Monitors up to four supplies simultaneously Adjustable inputs monitor down to 0.5V Reset asserted down to 0.9V 2% accuracy over temperature range CMOS RST High output 4 Reset Timeout Periods: 50ms, 100ms, 200ms and 400 ms Watch Dog Input Functionality -- WDI Manual Reset Input (Active Low) -- MRIB 8 Pin TSOT package Check Price and Availability Design-In Support Email: Tech Support Supervisors Product Selector Applications Notes Evaluation Boards Quality Information Part Nomenclature SP6334 FAQ Contact factory for availability of particular threshold and reset timeout options. For sampling, please request SP6330EK1-xxx [ SP6330EK1-L-W-G-C , or SP6330EK1-L-XJ-C , or SP6330EK1-L-Z-J-C ] for evaluation. The SP6330 device is the superset of the all functions represented within the family. Ordering Part Number Part Number Package Code RoHS MIN. MAX. Temp. ( Temp.( C) C) Status Buy SP6334EK1-L SUPERVISORS QUAD SP6334: CONTACT FACTORY FOR VOLTAGE OPTIONSNew! TSOT8 -40 85 CF_ Part Status Legend Active - the part is released for sale, standard product. EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock. CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply. PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only. OBS (Obsolete) - the part is no longer being manufactured and may not be ordered. NRND (Not Recommended for New Designs) - the part is not recommended for new designs. Home | Site Map | Term of Use | Privacy Policy | Contact Us All rights reserved, Sipex 2007 http://www.sipex.com/productDetails.aspx?part=SP6334&keyword=6334 7/23/2007 Solved by APPLICATION NOTE ANP14 TM Understanding and Selecting a Multi-Voltage Supervisor Featuring the SP6330 Family Introduction The primary function of a microprocessor (P) supervisor circuit is to ensure that the input supply voltage of a microprocessor is at proper levels during power up, power down and brownout conditions. If the input supply voltage to a microprocessor is below its required operating range, it could cause codeexecution errors, memory corruption and latch up. The supervisor will constantly monitor the input supply to the microprocessor, and in the event this supply voltage falls below a certain threshold, the RESET output will be asserted. Many of today's power products require several different voltage rails for powering various components. The microprocessor itself can have a separate core voltage and logic voltage. Other components such as DSPs, ASICs and microcontrollers can have their own unique voltage requirements. To service this demand of monitoring multi-voltage systems, Sipex has developed the SP6330 family. The SP6330 family is a series of multi-voltage supervisors that offer monitoring of up to 4 separate supplies and are equipped with specialized features. A complete listing of products and features are listed in Figure 4 at the end of this note. MR Supplies to be monitored C1 0.1uF V1 1 2 V2 C2 0.1uF V3 3 4 V4 R2 V1 RSTB V2 WDI MRIB V3 GND V4 8 RSTB 7 I/O 6 5 R4 C3 R3 uP SP6332 0.1uF C4 R5 0.1uF SP6332 typical applications circuit for monitoring 4 supplies with Master Reset, Watchdog input and CMOS Reset output Jun 27-06 SP6330 Family: Selecting a Multi-Voltage Supervisor Page 1 of 6 (c) 2006 Sipex Corporation Inputs to the SP6330 Family The SP6330 family has the ability to monitor up to 4 different voltages. Two of these inputs (V1 and V2) have precision factory-set thresholds while the remaining two inputs (V3 and V4) are adjustable. V3 and V4 inputs allow the user to customize two additional supply thresholds by means of an external divider. The threshold for V3 and V4 inputs is 0.5Volts. The V1 input supplies power to the device and will have the highest threshold for a given application; its minimum operating voltage for is 1.8V. The factory set threshold range for V1 and V2 inputs are shown in Figure 1. V1 Typical Threshold 4.625 4.375 3.075 2.925 2.625 2.320 2.190 1.670 1.580 V2 Typical Threshold 2.313 2.188 1.665 1.575 1.388 1.313 1.110 1.050 0.833 0.788 Figure 1 Reset Output - RST or RSTB The reset output can be either active low or active high depending on each device. The reset output can also be either open-drain or push-pull outputs. The open drain output requires an external pull-up resistor to V1 for normal operation. The output high voltage (VOH) of the reset output will be approximately equal to the V1 input voltage. Reset Timeout Period The reset timeout period is a built-in time delay for the reset output. This timeout period is activated at power up or when all monitored voltages have risen above their respective thresholds. Reset timeout period for the SP6330 family is offered in four different time intervals: 50ms, 100ms, 200ms and 400ms. The actual selection of timeout period depends on the applications requirements of the system voltage settle time. The reset timeout period is used to ensure that all voltage rails and system clocks have stabilized prior to executing code to prevent errors or data corruption. Jun 27-06 SP6330 Family: Selecting a Multi-Voltage Supervisor Page 2 of 6 (c) 2006 Sipex Corporation Manual Reset Input (Active Low) - MRIB The manual reset input allows the user to manually trigger a reset when monitored voltages are within tolerance. This is useful for resetting the microprocessor when it locks up due to software issues. A push-button type switch can be used to allow the user to trigger a reset externally. However, since a push button switch will bounce several times, a debounce element is needed. The manual reset input signal may also be a logic signal from an I/O line, watchdog timer or a power fail output. Watchdog Input - WDI The watchdog checks for proper software execution. If the software locks up or enters into an unwanted, loop the watchdog timer can either assert a reset output or a watchdog output. Some members of the SP6330 family offer a watchdog output while others do not. The watchdog has an internal timer that has a typical watchdog timeout period of 1.6 seconds. If the watchdog input (WDI) does not detect a transition within 1.6 seconds, a reset or watchdog output (WDO) will be generated. The watchdog input is usually connected to an I/O line for monitoring software activity. The watchdog circuit is useful for generating a reset or NonMaskable Interrupt (NMI) signal during software lock up conditions without human intervention. Floating the WDI will disable the watchdog feature. Watchdog Output (Active Low) - WDOB The Watchdog output is active low and can be either an open drain or push-pull output. If WDI remains at "HIGH" or "LOW" logic level for longer than the watchdog timeout period, the internal watchdog timer overflows and the WDOB will be asserted. Additionally, if the reset output is asserted due to an undervoltage condition, at any voltage input the WDOB would also be asserted. Floating WDI will not disable the watchdog timer in devices with dedicated WDOB output. Power Fail Input (PFI) The power fail input is used to monitor the unregulated DC voltage or other upstream voltage and to alert the system that a brownout or power failure is imminent. When the PFI input is tripped, it can inform the system to start a power-down routine in order to save important data before a reset output is asserted. The power fail input has a threshold of 0.5V. By using a voltage divider the user can monitor any upstream voltage. Connect PFI to V1 or GND if not used. Jun 27-06 SP6330 Family: Selecting a Multi-Voltage Supervisor Page 3 of 6 (c) 2006 Sipex Corporation Power Fail Output (Active Low) - PFOB The PFOB pin is an open drain, active low output. When the input voltage at PFI is <0.5V, PFOB will be asserted. RI Supplies to be monitored uP C1 0.1uF V1 1 2 V2 C2 0.1uF V3 3 4 V1 RSTB V2 WDI PFI GND V3 PFOB 8 RSTB 7 I/O 6 NMI 5 R6 SP6336 Unregulated DC R2 R3 R4 C3 0.1uF R5 SP6336 Typical Applications circuit for monitoring 3 supplies with Power Fail Input / Output function and open drain RESET output Glitch Immunity at Voltage Inputs The V1, V2, V3 and V4 inputs have a built-in glitch immunity feature that prevents nuisance resets during normal operation. Noise and normal voltage transients can cause these unwanted resets without some type of glitch immunity. Figure 2 shows the combination of voltage overdrive and duration that will not cause a reset for V1 and V2 inputs. Figure 3 shows the same data as applied to the V3 and V4 inputs. Adding a small bypass capacitor to voltage inputs can improve glitch rejection for very harsh environments. Jun 27-06 SP6330 Family: Selecting a Multi-Voltage Supervisor Page 4 of 6 (c) 2006 Sipex Corporation V1 and V2 Glitch rejection 250 Duration (uS) 200 150 RSTB asserted above line 100 50 0 0 20 40 60 80 100 120 Overdrive (mV) Figure 2 V3 and V4 glitch rejection Duration (uS) 120 100 80 RSTB asserted above line 60 40 20 0 0 20 40 60 80 100 120 Overdrive (mV) Figure 3 Jun 27-06 SP6330 Family: Selecting a Multi-Voltage Supervisor Page 5 of 6 (c) 2006 Sipex Corporation SP633X Features * * * * * * * * Quad, triple or dual supply monitoring Very low operating voltage down to 1.6V Low 20A typical operating current Adjustable inputs monitor down to 0.5V Open drain or CMOS reset outputs 4 reset timeout periods: 50ms, 100ms, 200ms and 400ms Glitch immunity inputs Tiny 6 pin or 8 pin TSOT package P/N SP6330 SP6332 SP6334 SP6331 SP6333 SP6335 SP6336 SP6337 SP6338 SP6339 SP6341 SP6340 SP6342 V1 V2 V3 V4 Reset Output X X X X OD X X X X CMOS X X X X CMOS X X X X OD X X X X CMOS X X X X CMOS X X X OD X X X CMOS X X X CMOS X X X OD X X X CMOS X X OD X X CMOS Reset Active LOW LOW HIGH LOW LOW HIGH LOW LOW HIGH LOW LOW LOW LOW MRIB WDI WDOB WDOB PFI PFOB Package OD CMOS X X 8-TSOT X X 8-TSOT X X 8-TSOT 6-TSOT 6-TSOT 6-TSOT X X X 8-TSOT X X X 8-TSOT X X X 8-TSOT X X X 8-TSOT X X X 8-TSOT X X 6-TSOT X X 6-TSOT Figure 4: Product Selection Guide Jun 27-06 SP6330 Family: Selecting a Multi-Voltage Supervisor Page 6 of 6 (c) 2006 Sipex Corporation FAQ SP6330 - SP6342 Dual/Triple/Quad Power Supervisory Circuit Family FEATURES Low operating voltage of 1.8V Low operating current of 20A typical Monitors up to four supplies simultaneously Adjustable inputs monitor down to 0.5V Reset asserted down to 0.9V 2% accuracy over temperature range Power Fail function Open Drain (OD) or CMOS RSTB output or CMOS RST output 200ms Reset Timeout Period Watch Dog Timer Function Independent Open Drain Watchdog Output Manual Reset Input SOT23-6/8 packages V1 1 V2 2 MRIB 3 SP6330 8 Pin SOT-23 8 RSTB 7 WDI 6 GND V3 4 5 V4 Open Drain RESET SEE PAGE 3 FOR OTHER AVAILABLE PINOUTS Available in Lead Free Packaging DESCRIPTION SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family is a family of microprocessor reset supervisory circuits with multiple reset voltages. The SP6330 family provides low voltage monitoring ability for up-to four supplies with two precision factory-set thresholds and two user defined custom thresholds. These circuits perform a single function: if any of the input supply voltages drops below its associated threshold, reset outputs are asserted. Some of the products in the family offer manual reset,power fail and watchdog functionalities. The SP63XX family includes a low-voltage precision bandgap reference, four precision comparators, an oscillator, a digital counter chain, a logic control block, trimmed resistor divider chains and additional supporting circuitry. V1 and V2 supply inputs have their resistor dividers on the chip. Their trip thresholds are factory trimmed. V3 and V4 inputs allow user to customize two additional supply thresholds to be monitored by means of external resistor dividers. Some members of the family are furnished with manual reset, power fail indication, watchdog functionalities.SP6330 thru SP6342 are housed in a 6-pin or 8-pin SOT23 package. All devices are fully specified over -40oC to +85oC temperature range. Date: 5/3/06 SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family 1 (c) Copyright 2006 Sipex Corporation Date: 5/3/06 SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family 2 (c) Copyright 2006 Sipex Corporation SP6331 SP6332 SP6333 SP6334 SP6335 SP6336 SP6337 SP6338 SP6339 SP6340 SP6341 SP6342 - - - - - - - - - - - - V1 V2 V3 V4 SP6330 PART NUMBER CMOS Active Low CMOS Active Low OD Active Low OD Active Low CMOS Active High CMOS Active Low OD Active Low CMOS Active High CMOS Active High CMOS Active Low CMOS Active Low OD Active Low OD Active Low Reset - - - - - - - - - - - Manual WatchDog Reset Input Input BAR CMOS Active Low CMOS Active Low OD Active Low OD Active Low - - - - - - - - - WatchDog Output BAR - - - - - - - - - - Power Fail Input - - - - - - - - - - 8 8 8 8 8 8 8 8 6 6 6 6 6 4 3 4 3 2 2 2 5 1 5 1 5 1 Power Fail Data# of Output sheet Pins BAR Group FEATURE MAPPING DIAGRAM Date: 5/3/06 2 3 4 V2 MRIB V3 (SOT23-8) SP6330 5 6 7 8 SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family 3 2 3 4 1 2 2 3 3 V2 PFI V3 V1 V2 WDI SV02-SIP1 SP6340 MOPT-B (SOT23-6) CMOS RST (SOT23-8) SP6338 4 4 5 5 6 5 6 7 8 Open Drain RSTB 1 V1 Open Drain RSTB 1 V1 2 V2 4 3 1 WDI (SOT23-6) SP6331 CMOS RSTB (SOT23-8) SP6332 4 5 6 5 6 7 8 CMOS RSTB (SOT23-8) SP6341 5 6 7 8 Open Drain RSTB 3 2 1 4 3 2 1 V1 V3 V2 V1 V3 MRIB V2 V1 WDOB V3 GND RSTB PFOB GND WDI RST V4 GND WDI RSTB V2 V1 V2 V1 V3 V2 V1 V3 WDOB WDI GND MRIB RSTB V4 GND RSTB V4 GND MRIB WDI RSTB 3 2 1 3 2 1 4 3 2 1 CMOS RSTB (SOT23-6) SP6342 CMOS RSTB (SOT23-6) SP6333 CMOS RST (SOT23-8) SP6334 4 5 6 4 5 6 5 6 7 8 WDOB GND RSTB V4 GND RSTB V4 GND WDI RST V3 V2 V1 V3 PFI V2 V1 (SOT23-8) SP6336 5 6 7 8 3 2 1 CMOS RST (SOT23-6) SP6335 4 5 6 Open Drain RSTB 4 3 2 1 V4 GND RST PFOB GND WDI RSTB V3 WDI V2 V1 V3 PFI V2 V1 4 3 2 1 (SOT23-8) SP6339 CMOS RSTB (SOT23-8) SP6337 5 6 7 8 5 6 7 8 Open Drain RSTB 4 3 2 1 WDOB GND MRIB RSTB PFOB GND WDI RSTB PINOUT MASTER DIAGRAM (c) Copyright 2006 Sipex Corporation FAQ SP6330 - SP6342 Dual/Triple/Quad Power Supervisory Circuit Family FEATURES Low operating voltage of 1.8V Low operating current of 20A typical Monitors up to four supplies simultaneously Adjustable inputs monitor down to 0.5V Reset asserted down to 0.9V 2% accuracy over temperature range Power Fail function Open Drain (OD) or CMOS RSTB output or CMOS RST output 200ms Reset Timeout Period Watch Dog Timer Function Independent Open Drain Watchdog Output Manual Reset Input SOT23-6/8 packages V1 1 V2 2 MRIB 3 SP6330 8 Pin SOT-23 8 RSTB 7 WDI 6 GND V3 4 5 V4 Open Drain RESET SEE PAGE 3 FOR OTHER AVAILABLE PINOUTS Available in Lead Free Packaging DESCRIPTION SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family is a family of microprocessor reset supervisory circuits with multiple reset voltages. The SP6330 family provides low voltage monitoring ability for up-to four supplies with two precision factory-set thresholds and two user defined custom thresholds. These circuits perform a single function: if any of the input supply voltages drops below its associated threshold, reset outputs are asserted. Some of the products in the family offer manual reset,power fail and watchdog functionalities. The SP63XX family includes a low-voltage precision bandgap reference, four precision comparators, an oscillator, a digital counter chain, a logic control block, trimmed resistor divider chains and additional supporting circuitry. V1 and V2 supply inputs have their resistor dividers on the chip. Their trip thresholds are factory trimmed. V3 and V4 inputs allow user to customize two additional supply thresholds to be monitored by means of external resistor dividers. Some members of the family are furnished with manual reset, power fail indication, watchdog functionalities.SP6330 thru SP6342 are housed in a 6-pin or 8-pin SOT23 package. All devices are fully specified over -40oC to +85oC temperature range. Date: 5/3/06 SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family 1 (c) Copyright 2006 Sipex Corporation Date: 5/3/06 SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family 2 (c) Copyright 2006 Sipex Corporation SP6331 SP6332 SP6333 SP6334 SP6335 SP6336 SP6337 SP6338 SP6339 SP6340 SP6341 SP6342 - - - - - - - - - - - - V1 V2 V3 V4 SP6330 PART NUMBER CMOS Active Low CMOS Active Low OD Active Low OD Active Low CMOS Active High CMOS Active Low OD Active Low CMOS Active High CMOS Active High CMOS Active Low CMOS Active Low OD Active Low OD Active Low Reset - - - - - - - - - - - Manual WatchDog Reset Input Input BAR CMOS Active Low CMOS Active Low OD Active Low OD Active Low - - - - - - - - - WatchDog Output BAR - - - - - - - - - - Power Fail Input - - - - - - - - - - 8 8 8 8 8 8 8 8 6 6 6 6 6 4 3 4 3 2 2 2 5 1 5 1 5 1 Power Fail Data# of Output sheet Pins BAR Group FEATURE MAPPING DIAGRAM Date: 5/3/06 2 3 4 V2 MRIB V3 (SOT23-8) SP6330 5 6 7 8 SP6330-SP6342 Dual/Triple/Quad Power Supervisory Circuit Family 3 2 3 4 1 2 2 3 3 V2 PFI V3 V1 V2 WDI SV02-SIP1 SP6340 MOPT-B (SOT23-6) CMOS RST (SOT23-8) SP6338 4 4 5 5 6 5 6 7 8 Open Drain RSTB 1 V1 Open Drain RSTB 1 V1 2 V2 4 3 1 WDI (SOT23-6) SP6331 CMOS RSTB (SOT23-8) SP6332 4 5 6 5 6 7 8 CMOS RSTB (SOT23-8) SP6341 5 6 7 8 Open Drain RSTB 3 2 1 4 3 2 1 V1 V3 V2 V1 V3 MRIB V2 V1 WDOB V3 GND RSTB PFOB GND WDI RST V4 GND WDI RSTB V2 V1 V2 V1 V3 V2 V1 V3 WDOB WDI GND MRIB RSTB V4 GND RSTB V4 GND MRIB WDI RSTB 3 2 1 3 2 1 4 3 2 1 CMOS RSTB (SOT23-6) SP6342 CMOS RSTB (SOT23-6) SP6333 CMOS RST (SOT23-8) SP6334 4 5 6 4 5 6 5 6 7 8 WDOB GND RSTB V4 GND RSTB V4 GND WDI RST V3 V2 V1 V3 PFI V2 V1 (SOT23-8) SP6336 5 6 7 8 3 2 1 CMOS RST (SOT23-6) SP6335 4 5 6 Open Drain RSTB 4 3 2 1 V4 GND RST PFOB GND WDI RSTB V3 WDI V2 V1 V3 PFI V2 V1 4 3 2 1 (SOT23-8) SP6339 CMOS RSTB (SOT23-8) SP6337 5 6 7 8 5 6 7 8 Open Drain RSTB 4 3 2 1 WDOB GND MRIB RSTB PFOB GND WDI RSTB PINOUT MASTER DIAGRAM (c) Copyright 2006 Sipex Corporation Reliability and Qualification Report SP6330 Prepared by: G. West Manager, Quality Assurance Date: April 7, 2006 Reviewed by: Fred Claussen VP Quality & Reliability Date: April 7, 2006 Reliability Report: SP6330 April 7, 2006 Page 1 of 5 Table Of Contents Title Page.............................................................................I Table of Contents...................................................................II Device Description ..................................................................II Block Diagram.......................................................................II Manufacturing Information........................................................III Package Information................................................................III Reliability Test Summary...........................................................IV Life Test Data........................................................................IV FIT Data Calculations...............................................................V MTBF Data Calculations............................................................V Device Description: SP6330-SP6332- SP6334 Quad Power Supervisory Circuit Family is a family of microprocessor reset supervisory circuits with multiple reset voltages. The family provides low voltage monitoring ability for up-to four supplies with two precision factory-set thresholds and two user defined custom thresholds. These circuits perform a single function: if any of the input supply voltages drops below its associated threshold, reset outputs are asserted. The SP6330, SP6332, and SP6334 are packaged in an 8-pin TSOT package. All devices are fully specified over -40o C to +85o C temperature range. SP6330 Pin Out Manufacturing Information: Products: Description: Mask Set(s): Process: Process Name: Wafer Manufacturer: Assembly Location: Qualification Lot #'s: SP6330 Quad Power Supervisory Cir cuit MS1512AZ CMOS PBC4 Polar Semiconductor, Inc. Carsem - Malaysia 3522A001A.11, 3638A001.8, 3638A001.6 Reliability Report: SP6330 April 7, 2006 Page 2 of 5 Package Information: Package Type: Die Size: 8 pin TSOT 45 x 67 mil Reliability Qualification Test Summary: Stress Level Device Burn-In Temp Sample Size 168Hrs 500Hrs 1000Hrs SP6330 SP6330 SP6330 125 C 125 C 125 C 240 240 240 No. Fail 0 0 0 Life Test Life testing is conducted to determine if there are any fundamental reliability related failure mechanism(s) present in the device. These failure mechanisms can be divided roughly into four groups: Process or die related failures, such as oxide-related defects, metalization-related defects and diffusion-related defects. 2. Assembly-related defects such as chip mount wire bond or package-related failures. 3. Design related defects. 4. Miscellaneous, undetermined or application- induced failures. 1. Life Test Results As part of the Sipex design qualification program, the Engineering group had subjected 80 parts from each of 3 lots of SP6330 for a 1000 hour reliability life test at 125 C. 168 hour Life test 240 parts of SP6330 parts were subjected to the life test profile and completed 168hr the test without any part failures. 500 hour Life test Reliability Report: SP6330 April 7, 2006 Page 3 of 5 The 240 parts of SP6330 we reintroduced to the second phase of the test, where the parts again showed successfully completing the 500-hour life test without any failures. 1000 hour Life test The 240 parts of the SP6330 were reintroduced to the final phase of the test, where the parts again successfully completed 1000-hour life test without any shift on the process parameters. FIT Rate Calculations The FIT (failures in time) rate is the predicted number of failures per billion devicehours. This predicted value is based upon the: Life Test conditions (time and temperature, device quantity and number of failures) are summarized under HTOL test table. 2. Activation Energy (Ea) of the potential failure modes. 1. The weighted Activation Energy, Ea, of observed failure mechanisms of Sipex products has been determined to be 0.8 eV. Based on the above criteria, the FIT rates at 25, 55 and 70C operation at both 60% and 90% confidence levels for the SP6330 product lines have been calculated and are listed below. FIT Failure Rates SP6330 Product Confidence Level 60% 90% +25C 1.6 4.1 +55C 26.6 68.4 +70C 90.8 233.1 +55C 3.75E+07 1.46E+07 +70C 1.10E+07 4.29E+06 1 FIT = 1 Failure per Billion Device-Hours MTBF Calculation for SP6330 Product Confidence Level 60% 90% +25C 6.30E+08 2.46E+08 Reliability Report: SP6330 April 7, 2006 Page 4 of 5 ESD Testing HBM ESD Testing - 5 units from each of three lots were subjected to 4000 V Human Body Model (HBM) ESD stress. Each pin was subjected to three positive and three negative pulses with respect to ground. All units passed testing after ESD stress. Latch-up Testing - 5 units from each of three lots were subjected to latch-up testing at +/100mA. All units passed. Reliability Report: SP6330 April 7, 2006 Page 5 of 5