NAND01GW3B2CN6E - MICRON TECHNOLOGY

January 2010 Rev 5 1/67

NAND01GR3B2C NAND01GW3B2C

NAND01GR4B2C NAND01GW4B2C

1-Gbit, 2112-byte/1056-word page,

1.8 V/3 V, single level cell NAND flash memory

Features

■NAND interface

– x8 or x16 bus width

– Multiplexed address/ data

– Pinout compatibility for all densities

■Supply voltage: 1.8 V/3 V

■Page size

– x8 device: (2048 + 64 spare) bytes

– x16 device: (1024 + 32 spare) words

■Block size

– x8 device: (128K + 4K spare) bytes

– x16 device: (64K + 2K spare) words

■Page read/program

– Random access: 25 µs (max)

– Sequential access: 25 ns (min)

– Page program t ime: 200 µs (typ)

■Copy back program mode

■Cache read mode

■Fast block erase: 2 ms (typ)

■Status register

■Electronic signature

■Chip enable ‘don’t care’

■Security features

–OTP area

– Serial number (unique ID)

– Non-volatile protection option

■Data protection

– Hardwar e block locking

– Hardware program/erase locked during

power transitions

■ONFI 1.0 support

– Cache read

– Read signature

– Read

■Data integrity

– 100,000 program/erase cycles per block

(with ECC)

– 10 years data retention

■RoHS compliant packages

■Development tools

– Error correction code models

– Bad bl oc ks manage ment and wear le v e ling

algorithms

– Hardw are simulation mod els

FBGA

TSOP48 12 x 20 mm

VFBGA63 9 x 11 x 1 .05 mm

VFBGA153 8x9x0.9mm

Table 1. Device summary

Reference Root part numbers

NAND01G-B2C NAND01GR3B2C, NAND01GW3B2C

NAND01GR4B2C, NAND01GW4B2C(1)

1. x16 organization only available for MCP products.

www.numonyx.com

Contents NAND01G-B2C

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Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1 Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 Inputs/outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.6 Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.7 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.8 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.9 Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.10 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.11 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.4 Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.5 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.6 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1.1 Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1.2 Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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6.2 Cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3 Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.3.1 Sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.3.2 Random data input in a page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4 Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.5 Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.7 Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.7.1 Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.7.2 P/E/R controller and cache ready/busy bit (SR6) . . . . . . . . . . . . . . . . . 31

6.7.3 P/E/R controller bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.7.4 Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.7.5 SR4, SR3, SR2, and SR1 are reserved . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.8 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.9 Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.10 Read parameter page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.2 NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.6 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.6.1 Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.6.2 IBIS simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 45

10 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

11 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

11.1 Ready/Busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 59

11.2 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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12 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

13 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

NAND01G-B2C List of tables

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List of tables

Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Product description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 6. Address insertion, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Address insertion, x16 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Address definitions, x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 9. Address definitions, x16 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 10. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 12. Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 13. Electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 14. Electronic signature byte/word 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 15. Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 16. Parameter page data structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 17. NAND flash failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 18. Program, erase times and program erase endurance cycles. . . . . . . . . . . . . . . . . . . . . . . 45

Table 19. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 20. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 21. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 22. DC characteristics, 1.8 V devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 23. DC characteristics, 3 V devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 24. AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 25. AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 26. TSOP48 - 48 lead plastic thin sm all ou tlin e, 12 x 20 mm, packag e m ech a nic al da ta . . . . . 62

Table 27. VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15, 0.80 mm pitch, package mechanical data . . . . . 63

Table 28. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 29. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

List of figures NAND01G-B2C

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List of figures

Figure 1. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3. TSOP48 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. VFBGA63 connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. VFBGA153 connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. Memory array organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7. Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 8. Read operations (intercepted by E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9. Random data output during sequential data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 10. Cache read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 11. Page program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 12. Random data input during sequential data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 13. Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 14. Page copy back program with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 15. Block erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 16. Read ONFI signature waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 17. Read parameter page waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 18. Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 19. Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 20. Equivalent testing circuit for AC characteristics measurement. . . . . . . . . . . . . . . . . . . . . . 48

Figure 21. Command Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 22. Address Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3

Figure 23. Data Input Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3

Figure 24. Sequential data output after read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 25. Serial access cycle after read, for frequency higher than 33 MHz . . . . . . . . . . . . . . . . . . . 54

Figure 26. Read status register AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 27. Read electronic signature AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 28. Page read operation AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 29. Page program AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 30. Block erase AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 31. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 32. Program/erase enable waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 33. Program/erase disable waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 34. Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0

Figure 35. Ready/Busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 36. Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 60

Figure 37. Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 38. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 62

Figure 39. VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15, 0.80 mm pitch, package outline . . . . . . . . . . . . . 63

Figure 40. VFBGA153 8 x 9 x 0.9 mm - 132+21 3R14, 0.50 mm pitch, package outline

and mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

NAND01G-B2C Description

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1 Description

The NAND01G-B2C is a 1-Gbit device belonging to the NAND SLC large page family. The

device operates with a 1.8 V or 3 V voltage supply. The size of a page is either 2112 bytes

(2048 + 64 spare) or 105 6 w ords ( 1024 + 32 sp are) de pendin g on whether the device has a

x8 or x16 bus width.

The address lines are multiplexed with the data input/output signals on a multiplexed x8 or

x16 input/output bus. This interface reduces the pin count and makes it po ssible to migrate

to other densities without changing the footprint.

Each block can be programmed and erased up to 100,000 cycles (with ECC on). To extend

the lifetime of NAND flash de vices, the implementation of an error correction code (ECC) is

mandatory.

The devices feature a write protect pin that allows performing hardware protection against

program and erase operations.

The devices feature an open-drain ready/busy output that can be used to identify if the

program/erase/read (P/E/R) controller is curren tly active. The use of an open-drain output

allows the ready/busy pins from several memories to be connected to a single pull-up

resistor.

A Copy Back Program command is available to optimize the man agement of defective

bl oc ks. When a page progr am oper at ion fails, the data can be prog r amme d in another page

without having to resend the data to be programmed.

The cache read feature is also implemented according to ONFI 1.0 specification.

All devices have the chip enable don’t care feature, which allows the bus to be shared

among several memories active at the same time, as chip enable transitions during the

latency time do not stop the read oper ation. Program and erase operations can never be

interr up te d by chip enable transitions.

The devices are available in the following packages:

●TSOP48 (12 x 20 mm)

●VFBGA63 (9 x 11 x 1.05 mm, 0.8 mm pitch)

●VFBGA153 (8 x 9 x 0.9 mm, 0.5 mm pitch)

and come with three security features:

●OTP (one time programmable) area, which is a restricted access area wher e sensitive

data/code can be stored permanently.

●Serial number (unique identifier), which allows the devices to be uniquely identified.

●Non-volatile protection to lock sensible data permanently. For more details of this

option contact your nearest Numonyx sales office.

These security features are subj ect to an NDA (non-disclosure agreement) and are,

therefore, not described in the datasheet. For more details about them, refer to the nearest

Numonyx sales office.

For information on how to order these options refer to Table 28: Ordering information

scheme. Devices are shipped from the factory with block 0 always valid and the memory

content bits, in valid blocks, erased to ’1’.

See Table 2: Product description, for all the devices available in the family.

Description NAND01G-B2C

8/67

Figure 1. Logic block diagram

Table 2. Product description

Reference Part number Density Bus

width Page

size Block

size Memory

array Operating

voltage

Timings

Package

Random

access

time

(max)

Sequential

access

time

(min)

Page

Program

time

(typ)

Block

erase

(typ)

NAND01G-

B2C

NAND01GR3B2C

1 Gbit

x8 2048

+64

bytes

128K

+4K

bytes 64

pages x

1024

blocks

1.7 to

1.95 V 25 µs 45 ns

200 µs 2 ms

VFBGA63

VFBGA153

NAND01GW3B2C 2.7 to

3.6 V 25 µs 25 ns TSOP48

NAND01GR4B2C x16 1024

+32

words

64K+

words

1.7 to

1.95 V 25 µs 45 ns (1)

NAND01GW4B2C 2.7 to

3.6 V 25 µs 25 ns (1)

1. x16 organization only available for MCP.

Address

Command

interface

logic

P/E controller,

high voltage

generator

Buffers

AI14291

Y decoder

Page buffer

1024-Mbit + 32Mbit

NAND flash

memory array

X decoder

I/O

Command register

Data register

NAND01G-B2C Description

9/67

Figure 2. Logic diagram

1. x16 organization only available for MCP.

AI13101b

I/O8-I/O15, x16

VDD

NAND01G-B2C

VSS

RI/O0-I/O7, x8/x16

Table 3. Signal names

Signal Function Direction

I/O8-15 Data input/outputs for x16 devices I/O

I/O0-7 Data input/outputs, address inputs, or command inputs

for x8 and x16 devices I/O

AL Address Latch En able Input

CL Command Latch Enable Input

EChip Enable Input

RRead Enable Input

RB Ready/Busy (open-drain output) Output

WWrite Enable Input

WP Write Protect Input

VDD Supply voltage Supply

VSS Ground Supply

NC Not connected internally –

DU Do not use –

Description NAND01G-B2C

10/67

Figure 3. TSOP48 connections

1. Only available for 3 V devices.

I/O3

I/O2

I/O6

I/O4

I/O7

AI13102b

NAND01G-B2C

24 25

I/O1

VSS

VDD

I/O5

I/O0

VDD

VSS

NAND01G-B2C Description

11/67

Figure 4. VFBGA63 connections (top view through package)

1. Only available for 3 V devices.

AI13103

I/O7

I/O4I/O3

NC VDD

I/O5VDD

VSS

I/O6

BDU

87654321

NCNC

NC NC

I/O0

NC NC

NCNC NC NCNC

NCNC

VSS

NCNC

NC NC

I/O2

I/O1

109

VSS

DU DU

Description NAND01G-B2C

12/67

Figure 5. VFBGA153 connections (top view through package)

1234567891011121314

ADU DU NC VSS VDD NC NC NC NC VSS NC NC DU DU A

BDU VSS ⎯RCL WP ⎯WNC NC NC NC NC NC NC DU B

C VSS NC NC AL ⎯ERB NC NC NC NC NC NC NC NC C

DNC NC NC DU NC NC NC D

E NC NC A2 VDD NC NC NC NC NC NC NC NC E

F NC A12 A0 NC NC NC NC NC F

G NC A9 NC VSS NC NC NC NC G

H NC A11 A7 DQ8 DQ15 VSS NC NC H

JA4 VSS A5 DQ9 DQ14 NC NC NCJ

K A6 A10 A3 DQ10 DQ11 VDD VSS DQ12 DQ13 NC NC NC K

L A13 A8 A1 NC NC NC L

MVSSNCNCDQ5DQ2DQ0NCNCNCNCNCNCNCNCM

NDU VDDNCDQ6DQ3NCNCNCNCNCNCNCNCDU N

PDU DU VSS DQ7 DQ4 DQ1 NC NC NC VSS NC NC DU DU P

1234567891011121314

DUNCActiveLegend:

NAND01G-B2C Memory array organization

13/67

2 Memory array organization

The memory array is made up of two NAND structures where 32 cells are connected in

series.

The memory array is organized in bloc ks where each b lock contains 64 pages. The array is

split into tw o area s , t he main area an d the spa re ar ea. The main a rea of the array is used to

store data wher eas the spare ar ea is typically used to stor e error correctio n codes , softw are

flags or bad block identification.

In x8 de vices the pages a re split into a 2048 -byte main area and a spar e area of 64 b ytes . In

the x16 devices the pages are split into a 1024-w ord main area and a 32-word spare area.

Refer to Figure 6: Memory array organization.

2.1 Bad blocks

The NAND flash 2112-byte/1056-word page devices may contain bad blocks, that is blocks

that contain one or more invalid bits whose reliability is not guaranteed. Additional bad

blocks may develop during the lifetime of the device.

The bad block Information is written prior to shipping (refer to Section 8.1: Bad block

management for more details).

Table 4: Vali d blocks shows the minimum number of valid blocks in the device. The values

shown includ e both the ba d b locks that are present when the device is shipped and the bad

blocks that could develop later on.

These blocks need to be managed using bad blocks management, block replacement or

error correction codes (refer to Section 8: Software algorithms).

Table 4. Valid blocks

Density of device Min Max

1 Gbit 1004 1024

Memory array organization NAND01G-B2C

14/67

Figure 6. Memory array organization

AI09854

Block = 64 pages

Page = 2112 bytes (2048 + 64)

2,048 bytes

2048 bytes

Spare area

bytes

Block

8 bits

bytes 8 bits

Page

Page buffer, 2112 bytes

Block = 64 pages

Page = 1056 words (1024 + 32)

1,024 words

1024 words

Spare area

Main area

words

16 bits

words 16 bits

Page buffer, 1056 words

Block

Page

x8 DEVICES x16 DEVICES

Main area

NAND01G-B2C Signal descriptions

15/67

3 Signal descriptions

See Figure 2: Logic diagram, and Table 3: Signal nam es, for a brief overview of th e signals

connected to this device.

3.1 Inputs/outputs (I/O0-I/O7)

Input/outpu ts 0 to 7 are used to input the selected address, output the da ta during a read

operation or input a command or data during a write operation. The inputs are latched on

the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or

the outputs are disabled.

3.2 Inputs/outputs (I/O8-I/O15)

Input/outputs 8 to 15 are only available in x16 devices. They are used to outp ut the data

during a read operation or input data during a write operation. Command and address

inputs only require I/O0 to I/O7.

The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when

the device is deselected or the outputs are disabled.

3.3 Address Latc h Enable (AL)

The Address Latch Enable activates the latching of the address inputs in the command

interface. When AL is High, the inputs are latched on the rising edge of Write Enable.

3.4 Command Latch Enab le (CL)

The Command Latch Enable activates the latching of the command inputs in the command

interface. When CL is High, the inputs are latched on the rising edge of Write Enable .

3.5 Chip Enable (E)

The Chip Enable input activates the memory control logic, input buffers, decoders and

sense amplifiers. When Chip Enab le is Lo w, VIL, the device is selected. If Chip Enable goes

High, VIH, while the device is busy, the de vice remains selected and does not go into

standby mode.

3.6 Read Enable (R)

The Read Enable pin, R, controls the sequential dat a outpu t during read oper atio ns . Data is

valid tRLQV after the falling edge of R. The falling edge of R also increments the internal

column address counter by one.

Signal descriptions NAND01G-B2C

16/67

3.7 Write Enable (W)

The Write Enable input, W, controls writing to the command interface, input address and

data latches. Both addresses and data are latched on the rising edge of Write Enable.

During power-up and power-down a recovery time of 10 µs (min) is required before the

command interface is ready to accept a co mmand. It is r ecommended to keep Write Enable

High during the recovery time.

3.8 Write Protect (WP)

The Write Protect pin is an inpu t that giv es a hardware protecti on against unwanted program

or erase operations. When Write Protect is Low, VIL, the device does not accept any

program or erase operations.

It is recommended to k e ep the Write Prot ect pin L ow, VIL, during pow er- up and po w er- down.

3.9 Ready/Busy (RB)

The Ready/Busy output , RB, is an op en-drain out put that can b e used to identi fy if the P/E/R

controller is currently active. When Ready/Busy is Low, VOL, a read, program or erase

operation is in progress. When the operation comple tes Ready/Busy goes High, VOH.

The use of an open-drain output allows the Ready/Busy pins from several memories to be

connected to a single pull-up resistor. A Low will then indicate that one, or more, of the

memories is busy.

Refer to the Section 11.1: Ready/Busy signal electrical characteristics for details on how to

calculate the value of the pull-up resis tor.

During power-up and power-down a minimum recovery time of 10 µs is required before the

command interface is ready to accept a command. During this period the RB signal is Low,

VOL.

3.10 VDD supply voltage

VDD provides the power supply to the internal core of the memory device. It is the main

power supply for all operations (read, program and erase).

An internal voltage detector disables all functions wh enever VDD is below VLKO (see

Table 22 and Table 23) to protect the de vice from any involuntary program/ erase during

power-transitions.

Each device in a system should ha ve VDD decoupled with a 0.1 µF capacitor. The PCB trac k

widths should be sufficient to carry the required program and erase currents.

3.11 VSS ground

Ground, VSS, is the reference for the power supply. It must be connected to the system

ground.

NAND01G-B 2C Bus operation s

17/67

4 Bus operations

There are six standard bus operatio ns that control the memory. Each of these is described

in this section, see Table 5: Bus operations, for a summary.

Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are

ignored by the memory and do not affect bus operations.

4.1 Command input

Command input b us oper atio ns are used to give commands to the memory. Commands are

accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable

is Low and Read Enable is High. They are latche d on the rising edge of the Write Enable

signal. For commands that star t a modify operation (write/erase) the Write Protect pin must

be High.

Only I/O0 to I/O7 are used to input commands.

See Figure 21 and Table 24 for details of the timings requirements.

4.2 Address input

Address input bus operations are used to input th e memory addresses. Four bus cycle s are

required to input the addresses for 1-Gbit devices (refer to Table 6 and Table 7, Address

insertion).

The addresses a re accepted when Chip Enable is Low, Address Latch Enab le is High,

Command Latch Enable is Low and Read Enable is High. They are latched on the rising

edge of the Write Enable signal. For commands that star t a modify operation (write/erase)

the Write Protect pin must be High. Only I/O0 to I/O7 ar e used to input addresses.

See Figure 22 and Table 24 for details of the timings requirements.

4.3 Data input

Data input bus operations are used to input the data to be pro gram med.

Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command

Latch Enable is Low, Read Enable, and Write Protect is High. The data is latched on the

rising edge of the Write Enable signal. Th e data is input sequent ially using the Write Enab le

signal.

See Figure 23 and Table 24 and Table 25 for details of the timing s re qu ire m en ts.

4.4 Data output

Data output bus operations are used to read: the data in the memory array, the status

Bus operations NAND01G-B2C

18/67

Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,

and Command Latch Enable is Low. The data is output sequentially using the Read Enable

signal.

See Figure 24 and Table 25 for details of the timings requirements.

4.5 Write Protect

Write Protect bus operations are used to protect the memory against program or erase

operations . When the Write Protect signal is Low the de vice will not accept program or erase

operations and so the contents of the memory array cannot be altered. The Write Protect

signal is not latched by Write Enable to ensure protection even during power-up.

4.6 Standby

When Chip Enable is High the memory enters standby mode, the device is deselected,

outputs are disabled and power consumption is reduced.

Table 5. Bus operations

Bus opera t io n E AL CL R WWP I/O0 - I/O7 I/O8 - I/O15(1)

1. Only for x16 devices.

Command input VIL VIL VIH VIH Rising X(2)

2. WP must be VIH when issuing a program or erase command.

Command X

Address input VIL VIH VIL VIH Rising X Address X

Data input VIL VIL VIL VIH Rising VIH Data input Data input

Data output VIL VIL VIL Falling VIH X Data output Data output

Write Protect X X X X X VIL XX

Standby VIH XXX X

VIL/VD

DXX

Table 6. Address insertion, x8 devices

Bus cycle(1)

1. Any additional address input cycles will be ignored.

I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

1st A7 A6 A5 A4 A3 A2 A1 A0

2nd VIL VIL VIL VIL A11 A10 A9 A8

3rd A19 A18 A17 A16 A15 A14 A13 A12

4th A27 A26 A25 A24 A23 A22 A21 A20

NAND01G-B 2C Bus operation s

19/67

Table 7. Address insertion, x16 devices

Bus

cycle(1)

1. Any additional address input cycles will be ignored.

I/O8-

I/O15 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

1st X A7A6A5A4A3A2A1A0

2nd X VIL VIL VIL VIL VIL A10 A9 A8

3rd XA18 A17 A16 A15 A14 A13 A12 A11

4th XA26 A25 A24 A23 A22 A21 A20 A19

Table 8. Address definitions, x8 devices

Address Definition

A0 - A11 Column address

A12 - A17 Page address

A18 - A27 Block address

Table 9. Address definitions, x16 devices

Address Definition

A0 - A10 Column address

A11 - A16 Page address

A17 - A26 Block address

Command set NAND01G-B2C

20/67

5 Command set

All bus write operations to the device are interpreted by the command interface. The

commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when

the Command Latch Enable signal is High. Device operations are selected by writing

specific commands to the command register. The two-step command sequences for

program and erase oper ations are imposed to maximize data security.

The commands are summarized in Table 10: Commands.

Table 10. Commands

Command

Bus write operations(1)

1. The bus cycles are only shown for issuing the codes. The cycles required to input the

addresses or input/output data are not shown.

Commands

accepted

during

busy

1st cycle 2nd cycle 3rd cycle 4th cycle

Read 00h 30h – –

Random Data Output 05h E0h – –

Cache Read 00h 31h – –

Exit Cache Read 3Fh – – –

Page Program

(sequential input default) 80h 10h – –

Random Data Input 85h – – –

Copy Back Program 00h 35h 85h 10h

Block Erase 60h D0h – –

Reset FFh – – – Yes

Read Electronic Signature 90h – – –

Read Status Register 70h – – – Yes

Read ONFI Parameter Page ECh – – –

NAND01G-B2C Device operations

21/67

6 Device operations

The following section gives the details of the device operations.

6.1 Read memory array

At power-up the device defaults to read mode. To enter read mode from another mode the

Read command must be issu ed, see Table 10: Commands.

Once a Read command is issued tw o types of operations are available: random read and

page read.

6.1.1 Random read

Each time the Read command is issued the first read is random read.

6.1.2 Page read

After the first random read access, the page data (2112 bytes or 1056 words) is transferred

to the page buffer in a time of tWHBH (refer to Table 25 for value). Once the transfer is

complete the Ready/Busy signal goes High. The data can then be read out sequentially

(from selected column address to last column address) by pulsing the Read Enable signal.

Alternatively, the user may check the tran sfer completion by issuing the Read Status

on outputting the read status register until the 00h command is issued.

The de vice can output random dat a in a page, instead of the co nsecutive sequentia l data, by

issuing a Random Data Output command.

The Random Data Output command can be used t o skip some data during a sequential

data output.

The sequential ope r at ion ca n be resum ed by changing the column addre ss of th e next data

to be output, to the address which follows the Random Data Output command.

The Random Data Outp ut command can be issued as many times as required within a

page.

The Random Data Output command is not accepted during cache read operations.

Device operations NAND01G-B2C

22/67

Figure 7. Read operations

I/O

00h

Data

NData

N+1 Data

N+2 Data

Last

NI3185

Busy

Command

code Address N input Data Output

from address N to last byte in page

Add.N

cycle 1 Add.N

cycle 4

Add.N

cycle 3

Add.N

cycle 2

tBLBH1

30h

Command

code

NAND01G-B2C Device operations

23/67

Figure 8. Read operations (intercepted by E)

I/O

00h

Data

NData

N+1 Data

N+2

ai14292

Busy

Column

Address

Col.

Add 1 Row

Add 1

tBLBH1

30h

Col.

Add 2 Row

Add 2

Row

Address

tEHCLX

tWHBL

tALLRL1

tWHBH tRLRL

tEHQZ

tEHQX

tBHRL

Device operations NAND01G-B2C

24/67

Figure 9. Random data output during sequential data out put

ai08658b

4 Add cycles

Main area Spare

area

Col Add 1,2

Row Add 1,2 2Add cycles

Main area Spare

area

Col Add 1,2

I/O

tWHBL

tALLRL2

00h

Data out

NData out

N+1 05h

tWHBH tRLRL

tCLLRL

tRLQV

Busy

Command

code

Col

Add 1

tBLBH1

30h

tBHRL

Col

Add 2 Row

Add 1 Row

Add 2 Col

Add 1 Col

Add 2

E0h

Data out

MData out

M+1

tWHRL

tRHWL

NAND01G-B2C Device operations

25/67

6.2 Cache read

The cache read oper at ion is used to improve the read throu ghp ut by reading data usin g th e

cache register . Since the device has only one cache register , serial data output on one page

may be executed while data from another page is read into the cache register.

A Page Read command must be issued prior to the Seq uential or Random Ca che Read

command in a cache read sequence. The Cache Read command can be issued only after

the read function is complete (SR6 = ‘1’).

A cache read operation consists of three steps (see Table 10: Commands):

1. One bus cycle is required to setup the Cache Read comman d (the same as the

standard Read command)

2. Four (refer to Table 6 and Table 7) bus cycles are then required to inp u t the start

address. If the host does not enter an address, the next sequential page is read.

3. One bus cycle is required to issue the Cache Read Confirm command to start the

P/E/R controller.

The start address must be at the beginning of a page (column address = 00h, see Table 8

and Table 9). This allows the data to be output uninterrupted after the latency time (tBLBH1),

see Figure 10.

The Ready/Busy signal can be used to monitor the start of the opera tion. During the latency

period the Ready/Busy signal goes L o w, after this the Ready/Busy signal go es High, even if

the device is internally downloading page n+1.

Once the cache read ope ration has started, the status register can be read using the Read

Status Register command.

During the operatio n, SR5 can be read, to fin d out whether the inte rnal reading is ongoing

(SR5 = ‘0’), or has completed (SR5 = ‘1’), while SR6 indicates whether the cache register is

ready to download new data.

To exit the cache read operation an Exit Cache Read command must be issued (see

Table 10).

After the device has internally read page n, the user is allowed to download data of that

page by toggling R, but the device will not trigger internally the reading of a ne xt page.

Device operations NAND01G-B2C

26/67

Figure 10. Cache read oper ation

6.3 Page program

The page prog ram o peration is t he standard op eration to p rogram data to the memo ry arra y.

Within a given block, the pages must be programmed sequentially. Random page address

programming is not recommended.

The memory array is programmed by page, however partial page programming is allowed

where any number of bytes (1 to 2112) or words (1 to 1056) can be programmed.

The maximum number of consecutive partial page program operations allowed in the same

page is f our . After e xceeding this a Bloc k Erase command m ust be issued befor e any further

program operations can take place in that page.

6.3.1 Sequential input

To input data sequentially the addresses must be sequen tial and remain in one block.

For sequential input each page program operation consists of five steps (see Figure 11):

1. one bus cycle is requir ed to setup the Page Program (sequential input) comma nd (see

Table 10)

2. four bus cycles are then required t o input the program address (refer to Table 6 and

Table 7)

3. the data is then loaded into the data registers

4. one bus cycle is required to issue the Page Program Confirm command to start the

P/E/R controller. The P/E/R will only start if the data has been loaded in step 3

5. the P/E/R controller then programs the data into the array.

I/O

R/B

ai14293

30h 00h D0

tBLBHx

tBLBH1

C1 C2 R1 R2 31h

Random

tBLBHx

... Dn 31h D0

Sequential

NAND01G-B2C Device operations

27/67

6.3.2 Random data input in a page

During a sequential input operation, the next sequential address to be programmed can be

replaced by a random address, by issuing a Random Data Input comm and. The following

two steps are required to issue the command:

1. one bus cycle is required to setup the Random Data Input command (see Table 10)

2. two bus cycles are then required to inpu t the ne w column address (refer to Table 6).

Random Data Input can be repeated as often as required in any given page.

Once the prog ram operation has started the status register can be read using the Read

Status Register command. During program operations the status register will only flag errors

for bits set to '1' that have not been successfully programmed to '0'.

During the program operation, only the Read Status Register and Reset commands will be

accepted, all other commands will be ignored.

Once the prog r am oper a tion has co mplete d the P/E/ R contro ller bit SR6 is set t o ‘1’ and t he

Ready/Busy signal goes High.

The device remains in read status register mode until another valid command is written to

the command interface.

Figure 11. Page program operation

I/O

Address Inputs SR0

ai08659

Data Input 10h 70h

80h

Page Program

Setup Code Confirm

Code Read Status Register

Busy

tBLBH2

(Program Busy time)

Device operations NAND01G-B2C

28/67

Figure 12. Random data input during sequential data input

I/O Address

Inputs

ai08664b

Data Intput

80h

Cmd

Code

Address

Inputs Data Input

85h

4 Add cycles

Main area Spare

area

Col Add 1,2Row Add 1,2

Cmd

Code

2 Add cycles

Main area Spare

area

Col Add 1,2

Busy

tBLBH2

(Program Busy time)

SR0

10h 70h

Confirm

Code Read Status Register

NAND01G-B2C Device operations

29/67

6.4 Copy back program

The copy back program oper ation is used to copy the data stored in one page and

reprogram it in another pa g e.

The cop y bac k prog ram o peration d oes not require external memory and so the operation is

faster and more efficient because the reading and loading cycles are not required. The

operat ion is particularly useful when a portion of a bloc k is upda ted and the re st of the b l oc k

needs to be copied to the newly assigne d block.

If the copy back program operation fails, an error is signalled by the pass/fail status.

Howe ver, if cop y back operations are accumulated ov er time, a bit error due to charge loss is

not checked by an external error detection/correction scheme. For this reason it is

recommended to use a 2-bit error correction in a copy back operation.

The copy back program operation requires four steps:

1. The first step reads the source page. The operation copies all 1056 words/ 2112 bytes

from the page into the data buffer. It requires:

– one bus write cycle to setup the command

– 4 bus write cycles to input the source page address (see Table 6 and Table 7)

– one bus write cycle to issue the confirm command code

2. When the device returns to the ready state (Ready/Busy High), the user may read the

contents of the source page by toggling R. In this case, random data output is also

allow ed. To proceed with the copy bac k of the page into the target location, the user will

issue 85h followed by 4 bus cycles to input the target page address (see Table 6 and

Table 7).

3. Then the confirm command is issued to start the P/E/R controller.

For an example of the copy back program operation, refer to Figure 13, while Figure 14

shows an example of Copy Back Program with Random Data Input.

A data input cycle to modi fy a portion or a multiple distant portion of the source page, is

shown in Figure 14.

Figure 13. Copy back program

I/O

Source

Add Inputs

ai09858b

85h

Copy Back

Code

Read

Code Read Status Register

Target

Add Inputs

tBLBH1

(Read Busy time)

Busy

tBLBH2

(Program Busy time)

00h 10h 70h SR0

Busy

35h

Device operations NAND01G-B2C

30/67

Figure 14. Page copy back program with random data input

6.5 Block erase

Erase operations are done one block at a time. An erase operation sets all of the bits in the

addressed block to ‘1’. All previous data in the block is lost.

An erase operation consists of three steps (refer to Figure 15):

1. One bus cycle is required to setup the Block Erase command. Only addresses A18-

A27 (x8) or A17-A26 ( x16) are used, the other address inputs are ignored

2. Two bus cycles are then required to load the address of the b lock to be erased. Ref er to

Table 8 and Table 9 for the block addresses of each d evice

3. One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R

controller.

The opera tion is initiated on the rising edge of write Enable, W, after the Confirm command

is issued. The P/E/R controller handles block erase and implements the verify process.

During the block erase operation, only the Read Status Register and Reset commands will

be accepted, all other commands will be ignored.

Once the prog r am oper a tion has co mplete d the P/E/ R contro ller bit SR6 is set t o ‘1’ and t he

Ready/Busy signal goes High. If the operation completed successfully, the write status bit

SR0 is ‘0’, otherwise it is set to ‘1’.

Figure 15. Block erase operation

I/O

Source

Add Inputs

ai11001

85h

Read

Code

Target

Add Inputs

tBLBH1

(Read Busy time)

00h

Busy

35h 85h Data

2 Cycle

Add Inputs

Data

Copy Back

Code

10h 70h

Unlimited number of repetitions

Busy

tBLBH2

(Program Busy time)

SR0

I/O

Block Address

Inputs SR0

ai07593

D0h 70h

60h

Block Erase

Setup Code Confirm

Code Read Status Register

Busy

tBLBH3

(Erase Busy time)

NAND01G-B2C Device operations

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6.6 Reset

The Reset command is used to reset the command interface and status register. If the

Reset command is issued during any operation, the operation will be aborted. If it was a

program or erase operation that was aborted, the contents of the memory locations being

modified will no longer be valid as the data will be partially programmed or erased.

If the device has already been reset then the new Reset command will not be accepted.

The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value

of tBLBH4 depends on the oper ation that the de vice w as p erf o rming when the command was

issued, refer to Table 25: AC characteristics f or operations for the values.

6.7 Read status register

The device contains a status register which provides information on the current or previous

program or erase operation. The various bits in the status register convey information and

errors on the operation.

The status register is read by issuing th e Read Status Register command. The status

Enable or Read Enab le, whichever occurs last. When several memories are connected in a

system, the use of Chip Enable and Read Enable signals allows the system to poll each

de vice separately, e ven when the Ready/Busy pins are common-wired. It is not necessary to

toggle the Chip Enable or Read Enable signals to update the contents o f the status register.

After the Read Status Register command has been issued, the device remains in read

status register mode until another command is issued. Therefore if a Read Status Register

command is issued during a random read cycle a new Read command must be issued to

continue with a page read operation.

The Status Register bits are summarized in Table 11: Status regi ster bits ,. Refer to Table 11

in conjunction with the following text descriptions.

6.7.1 Write protection bit (SR7)

The write protection bit can be used to identify if the device is protected or not. If the write

protection bit is set to ‘1’ the device is not protected and program or erase o perations are

allowed. If the write protection bit is set to ‘0’ the device is protected and program or erase

operations are not allowed.

6.7.2 P/E/R controller and cache read y/busy bit (SR6)

Status register bit SR6 has two different functions depending on the current operation.

During cache read operations SR6 indicates whether the next selected page can be read

from the page register (SR6 is set to '1') or no t (SR6 is set to '0').

During all other oper ations SR6 acts as a P/E/ R controller bit, which indicates whether the

P/E/R controller is active or inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R

controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive

(device is ready).

Device operations NAND01G-B2C

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6.7.3 P/E/R controller bit (SR5)

The program/er ase/read controller bit indicates whether the P/E/R controller is active or

inactive . When the P/E/R controller bit is set to ‘0’, the P/E/R controller is active (device is

busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is ready).

6.7.4 Error bit (SR0)

T he er ror bit is used to identify if an y err ors h ave been detected by th e P/E/R co ntro ller. The

error bit is set to ’ 1’ when a progr am or er ase operat ion has f ailed to write the corre ct data to

the memory. If the error bit is set to ‘0’ the operation has completed successfully.

6.7.5 SR4, SR3, SR2, and SR1 are reserved

Table 11. Status register bits

Bit Name Logic level Definition

SR7 Write protection '1' Not protected

'0' Protected

SR6

Program/ erase/ read

controller '1' P/E/R C inac tive, device ready

'0' P/E/R C active, device busy

Cache ready/busy '1' Cache register ready (cache operati on only)

'0' Cache register busy (cache operation only)

SR5 Program/ erase/ read

controller '1' P/E/R C inac tive, device ready

'0' P/E/R C active, device busy

SR4, SR3,

SR2, SR1 Reserved Don’t care

SR0 Generi c error ‘1’ Error – operation fa iled

‘0’ No error – operation successful

NAND01G-B2C Device operations

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6.8 Read electronic signature

The devic e contains a manufacturer code and device code. To read these codes three steps

are required :

1. One bus write cycle to issue the Read Electronic Signature command (90h)

2. One bus write cycle to input the address (00h)

3. Four bus read cycles to sequentially output the data (as shown in Table 12: Electronic

signature).

Table 12. Electronic signature

Part number

byte/word 1 byte/word 2 byte/word 3

(see Table 13)byte/word 4

(see Table 14)

Manufacturer

code Device code

NAND01GR3B2C

20h

A1h

00h

15h

NAND01GW3B2C F1h 1Dh

NAND01GR4B2C B1h 55h

NAND01GW4B2C C1h 5Dh

Table 13. Electronic signature byte 3

I/O Definition Value Description

I/O1-I/O0 Internal chip number

0 0

0 1

1 0

1 1

Reserved

I/O3-I/O2 Cell type

0 0

0 1

1 0

1 1

Single level cell

2x multilevel cell

Reserved

I/O5-I/O4 Number of simultaneously

programmed pages

0 0

0 1

1 0

1 1

I/O6 Interleaved programmi n g

between multiple devices 0

1Not supported

Supported

I/O7 Cache program 0

1Not supported

Supported

Device operations NAND01G-B2C

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6.9 Read ONFI signature

To recognize NAND flash devices that are compatible with ONFI 1.0 command set, the

Read Electronic Signature command can be issued, followed by an address of 20h. The

next four-byte output is the ONFI signature, which is the ASCII encoding of the ‘ONFI’ word.

Reading be yond four bytes produces indeterminate values . The device remains in this state

until a new command is issued.

Figure 16 describes the read O NFI signature waveforms and Table 15 defines the output

bytes.

Table 14. Electronic signature byte/word 4

I/O Definition Value Description

I/O1-I/O0 Page size

(without spare area)

0 0

0 1

1 0

1 1

1Kbyte

2Kbytes

Reserved

I/O2 Spare area size

(byte / 512-byte) 0

1 8

I/O3 Minimum sequential

access time 0

150 ns

30 ns

I/O5-I/O4 Bloc k size

(without spare area)

0 0

0 1

1 0

1 1

64 Kbytes

128 Kbytes

256 Kbytes

Reserved

I/O6 Organization 0

1x8

x16

I/O7 Not used Reserved

Table 15. Read ONFI signature

Byte Value ASCII character

1st byte 4Fh O

2nd byte 4Eh N

3rd byte 46h F

4th byte 49h I

5th byte Undefined Undefined

NAND01G-B2C Device operations

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Figure 16. Read ONFI signature waveforms

6.10 Read parameter page

The Read Parameter Page command retrieves th e da ta structure th at des cribes the N AND

flash organization, features, timings and other behavioral parameters. This data structure

enables the host processor to automatically recognize the NAND flash configuration of a

device . The whole data structure is repe ated at least five times.

See Figure 17 for a description of the read parameter page waveforms.

The Random Data Read command can be issued during execution of the read parameter

page to read specific portions of the parameter page.

The Read Status comman d ma y be used to chec k the stat us of read parame ter page during

execution. After completio n of the Read Status command, 00h is issued by the host on the

command line to contin ue with t he data ou tput flo w for the Read Parameter Page command.

Read status enhanced is not be used during execution of the Read Parameter Page

command.

Table 16 defines the parameter page data structure. For parameters that span multiple

bytes, the least significant byte of the parameter correspon d s to the first byte.

Values are reported in the parameter page in bytes when referring to items related to the

size of data access (as in an x8 data access device). For example, the chip returns how

many data bytes are in a page. For a device that supports x16 data access, the host is

required to convert byte values to word values for its use. Unused fields are set to 0h.

For more detaile d information about parameter page data bits, refer to ONFI Specification

1.0 section 5.4. 1.

90h 20h

I/O

tRLQV

Read Electronic

Signature

command

1st cycle

address

ai13178b

(Read ES access time)

tALLRL1

49h46h

4Fh 4Eh XXh

Device operations NAND01G-B2C

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Figure 17. Read parameter page waveforms

ECh 00h

I/O0-7

ai14409

P11

P01

P10... ...

P00

tBLBH1

R/B

NAND01G-B2C Device operations

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Table 16. P arameter page data structure

Byte O/M(1) Description

Revision information and features block

0-3 M

Parameter page signature

– Byte 0: 4Fh, ‘O’

– Byte 1: 4Eh, ‘N’

– Byte 2: 46h, ‘F’

– Byte 3: 49h, ‘I’

4-5 M

Revision number

Bit 2 to bit 15 Reserved (0)

Bit 1 1 = supports ONFI version 1.0

Bit 0 Reserved (0)

6-7 M

Features supported

Bit 5 to bit 15 Reserved (0)

Bit 4 1 = supports od d to even page copy

back

Bit 3 1 = supports interleaved operations

Bit 2 1 = supports no n-sequential page

programming

Bit 1 1 = supports multiple LUN operations

Bit 0 1 = supports 16-bit data bus width

8-9 M

Optional commands suppor ted

Bit 6 to bit 15 Reserved (0)

Bit 5 1 = supports read uniq ue ID

Bit 4 1 = supports copy back

Bit 3 1 = supports read status enhanced

Bit 2 1 = supports ge t features and set

features

Bit 1 1 = supports read cache commands

Bit 0 1 = supports pa ge cache program

command

10-31 Reserved (0)

Manufacturer

information block

32-43 M Device manufacturer (12 ASCII characters)

44-63 M Device model (20 ASCII characters)

64 M JEDEC man ufacturer ID

65-66 O Date code

67-79 Reserved (0)

Device operations NAND01G-B2C

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Memory organization block

80-83 M Number of data bytes per page

84-85 M Number of spare bytes per page

86-89 M Number of data bytes per partial page

90-91 M Number of spare bytes per partial page

92-95 M Number of pages per block

96-99 M Number of blocks per logical unit (LUN)

100 M Number of logical units (LUNs)

101 M

Number of address cycles

Bit 4 to bit 7 Column address cycles

Bit 0 to bit 3 Row address cycles

102 M Number of bits per cell

103-104 M Bad blocks maximum per LUN

105-106 M Block endurance

107 M Guaranteed valid blocks at beginning of

target

108-109 M Block endurance for guaranteed valid

blocks

110 M Number of programs per page

111 M

Partial programming attributes

Bit 5 to bit 7 Reserved

41 = partial page layout is partial page

data followed by partial page spare

Bit 1 to bit 3 Reserved

01 = partial page programming has

constraints

112 M Number of bits ECC correctability

113 M

Number of interleaved address bits

Bit 4 to bit 7 Reserved (0)

Bit 0 to bit 3 Number of interleave d address bits

114 O

Interleaved operation attributes

Bit 4 to bit 7 Reserved (0)

Bit 3 Address restrictions for program cache

Bit 2 1 = program cache supported

Bit 1 1 = no block address restrictions

Bit 0 Overlapped / concurrent interleaving

support

115-127 Reserved (0)

Table 16. Parameter page data structure (continued)

Byte O/M(1) Description

NAND01G-B2C Device operations

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128 M I/O pin capacitance

Electrical parameter block

129-130 M

Timing mode support

Bit 6 to bit 15 Reserved (0)

Bit 5 1 = supports timing mode 5

Bit 4 1 = supports timing mode 4

Bit 3 1 = supports timing mode 3

Bit 2 1 = supports timing mode 2

Bit 1 1 = supports timing mode 1

Bit 0 1 = supports timing mode 0, shall be 1

131-132 O

Program cache timing mode support

Bit 6 to bit 15 Reserved (0)

Bit 5 1 = supports timing mode 5

Bit 4 1 = supports timing mode 4

Bit 3 1 = supports timing mode 3

Bit 2 1 = supports timing mode 2

Bit 1 1 = supports timing mode 1

Bit 0 1 = supports timing mode 0

133-134 M tPROG maximum page program time (µs)

135-136 M tBERS maximum block erase time (µs)

137-138 M tR maximum page read time (µs)

139-140 M tCCS minimum change column setup

time (ns)

141-163 M Reserved (0)

Vendor

block

164-165 M Vendor specific revision number

166-253 M Vendor specific

254-255 M Integrity CRC

Red. param.

pages

256-511 M Value of bytes 0-255

512-767 M Value of bytes 0-255

768+ O Additional redundant parameter pages

1. O = optional, M = mandatory.

Table 16. Parameter page data structure (continued)

Byte O/M(1) Description

Data protection NAND01G-B2C

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7 Data protection

The device has hardware features to protect against program and erase operations.

It f eatures a Write Protect, WP, pin, which can be used to protect t he device against progr am

and erase operations. It is recommended to k eep WP at VIL during power-up and power-

down.

In addition, to protect the memory from any involuntary program/erase operations during

power-transitions, the device has an internal voltage detect or which disables all functions

whenever VDD is below VLKO (see Table 22 and Table 23).

NAND01G-B2C Software algorit h ms

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8 Software algorithms

This section gives information on the software a lgorithms that Numonyx reco mmends to

implement to mana ge the bad b locks and extend the lifetime of the NAND device.

NAND flash memories are prog rammed and erased by Fowler-Nordheim tunneling using a

high voltage. Exposing the device to a high voltage for extended periods can cause the

oxide layer to be damaged. For this reason, the number of progr am and erase cycles is

limited (see Table 18 for v alue) and it is mandatory to implement error correction code

algorithms to extend the number of program and erase cycles and increase data retention.

To help integrate a NAND memory into an application, Numonyx can provide a full range of

software solutions: file system, sector manager, driv ers and code management.

Contact the near est Numonyx sales office or visit www.numonyx.com for more details.

8.1 Bad block management

Devices with bad blocks have the same quality le vel and the same A C an d DC

characteristics as devices where all the blocks are valid. A bad block does not affect the

performance of valid blocks because it is isolated from the bit line and common source line

by a select transistor.

The devices are supplied with all the locations inside valid blocks erased (FFh). The bad

block information is written prior to shipping. Any block, where the 1st and 6th bytes (x8

device)/1st word (x16 device), in the spare area of the 1st page, does not contain FFh, is a

bad block.

The bad block Information must be read before any erase is attempted as the bad bl ock

inf o rmation ma y be e r ased. For the system to be ab le t o recogniz e the b ad b l oc ks ba sed on

the original inf ormation it is recommended to create a bad b loc k tab le f ollowing the f lowchart

shown in Figure 18.

8.2 NAND flash memory failure modes

Over the lifetime of the device additional bad blocks may develop.

To implement a highly reliable system, all the possible failure modes must be considered:

●Pro gram/erase failure: in this case the b lock has to be replaced b y cop ying the data to

a valid block. These additional bad blocks can be identified as attempts to program or

erase them will give errors in the status register

As the f ailure of a page progr am operat ion does not aff ect the data in other page s in the

same bl ock, t he bloc k can be repl aced by re-pr ogrammin g the current data and cop ying

the rest of the replaced block to an available valid block. The Copy Back Prog ram

command can be use d to co py the data to a valid blo ck. See Section 6.4: Copy back

program for more details

●Read failure: in this case, ECC correcti on m u st be imp l ement ed . To efficiently use the

memory space, it is recommended to recover single-bit error in read by ECC, without

replacing the whole block.

Refer to Table 17 for the procedure to follow if an error occurs during an operation.

Software algorithms NAND01G-B2C

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Figure 18. Bad block management flowc hart

Figure 19. Garbage collection

Table 17. NAND flash failure modes

Operation Procedure

Erase Bloc k replacement

Program Block replacement or ECC

Read ECC

AI07588C

START

END

YES

Block Address =

Block 0

Data

= FFh?

Last

block?

Increment

Block Address

Update

Bad Block table

Valid

page

Invalid

page Free

page

(erased)

Old area

AI07599B

New area (after GC)

NAND01G-B2C Software algorit h ms

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8.3 Garbage collection

When a data page needs to be modified, it is faster to write to the first available page, and

the previous page is marked as invalid. After several updates it is necessary to remove

invalid pages to free some memory space.

To free this memory space and allow further program oper ations it is recommended to

implement a garbage collection algorithm. In a garbage collection software the valid pages

are copied into a free area and the block containing the invalid pages is erased (see

Figure 19).

8.4 Wear-leveling algorithm

For write-intensive applications, it is recommended to implement a wear-l eveling algorithm

to monitor and sprea d the number of write cycles per block.

In memories that do not use a wear-leveling algorithm not all blocks get used at the same

rate. Blocks with long-lived data do not endure as many write cycles as the blocks with

frequently-changed data.

The wear-leveling algorithm ensures that equal use is made of all the available write cycles

for each block. There are two wear-leveling levels:

●First level wear-leveling, new data is programmed to the fr ee blocks that have had the

fewest write cycles

●Second level wear-leveling, long-lived data is copied to another bloc k so that the

original block can be used for more frequently-changed data.

The second level wear-leveling is triggered when the difference between the maximum and

the minimum number of write cycles per block reaches a specific threshold.

8.5 Error correction code

Users must implement an error correction code (ECC) to identify and correct errors in data

stored in NAND flash memories. The ECC implemented must be able to correct 1 bit every

512 bytes. Sensible data stored in spare area must be covered by ECC as well.

8.6 Hardware simulation models

8.6.1 Behavioral simulation models

Denali Software Corporation models are platform independent functional models designed

to assist customers in performing entire system simulat ions (typical VHDL/Verilog). These

models describe the logi c behavior and timings of NAND flash devices, and so allow

software to be developed before hardwar e.

8.6.2 IBIS simulation models

IBIS (I/O buffer information specification) models describe the behavior of the I/O buffers

and electrical characteristics of flash devices.

Software algorithms NAND01G-B2C

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These models provide information such as AC characteristics, rise/fall times and package

mechanical data, all of which are measured or simula ted at v oltage and te mperatur e ranges

wider than those allowed by target specifications.

IBIS models are used to simulate PCB connections and can be used to resolve compatibility

issues when upgrading devices. They can be imported into SPICETOOLS.

NAND01G-B2C Program and erase times and endurance cycles

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9 Program and erase times and endurance cycles

The progr am and eras e times and th e number of prog r am/er ase cycles per b lock are shown

in Table 18.

Table 18. Program , erase times and program erase endurance cycles

Parameters NAND flash Unit

Min Typ Max

Page program time 200 700 µs

Block erase time 23ms

Program/erase cycles per block (with ECC) 100,000 cycles

Data retention 10 years

Maximum ratings NAND01G-B2C

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10 Maximum ratings

Stressing the device above the ratings listed in Table 19: Absolute maximum ratings, may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exp osur e to abso lute maximum rating conditions for

extended periods may affect device reliability.

Table 19. Absolute maximum ratings

Symbol Parameter Value Unit

Min Max

TBIAS Temperature under bias – 50 125 °C

TSTG Storage temperature – 65 150 °C

VIO(1)

1. Minimum voltage may undershoot to –2 V for less than 20 ns during transitions on input and I/O pins.

Maximum voltage may overshoot to VDD + 2 V for less than 20 ns during transitions on I/O pins.

Input or output voltage 1.8 V devices – 0.6 2.7 V

3 V devices – 0.6 4.6 V

VDD Supply voltage 1.8 V devices – 0.6 2.7 V

3 V devices – 0.6 4.6 V

NAND01G-B2C DC and AC parameters

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11 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The paramete rs in the DC and AC characteristics tables that

follow, are derived from tests performed under the measurement conditions summarized in

Table 20: Operating and AC measurement conditions. Designer s sho u ld che ck that the

operating conditions in their circuit match the measurement cond itions when relying on the

quoted parameters.

Table 20. Operating and AC measurement conditions

Parameter NAND flash Units

Min Max

Supply voltage (VDD)1.8 V devices 1.7 1.95 V

3 V devices 2.7 3.6 V

Ambient temperature (TA)Grade 1 0 70 °C

Grade 6 –40 85 °C

Load capacitance (CL)

(1 TTL GATE and CL)1.8 V devices 30 pF

3 V devices (2.7 - 3.6 V) 50 pF

Input pulses voltages 1.8 V devices 0 VDD V

3 V devices 0 VDD V

Input and output timing ref. voltages VDD/2 V

Output circuit resistor Rref 8.35 kΩ

Input rise and fall times 5 ns

Table 21. Capacitance(1)

1. TA = 25 °C, f = 1 MHz. CIN and CI/O are not 100% tested.

Symbol Parameter Test condition Typ Max Unit

CIN Input capacitance VIN = 0 V 10 pF

CI/O Input/output capacitance(2)

2. Input/output capacitances double in stacked devices.

VIL = 0 V 10 pF

DC and AC parameters NAND01G-B2C

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Figure 20. Equivalent testing circuit for AC characteristics measurement

Ai11085

NAND flash

2Rref

VDD

2Rref

GND

NAND01G-B2C DC and AC parameters

49/67

Table 22. DC characteristics, 1.8 V dev ices

Symbol Parameter Test conditions Min Typ Max Unit

IDD1

Operating current

Sequential

read tRLRL minimum

E = VIL, IOUT = 0 mA –1020mA

IDD2 Program – – 10 20 mA

IDD3 Erase – – 10 20 mA

IDD5 Standby current (CMOS)(1) E = VDD – 0.2,

WP = 0/VDD –10 50 µA

ILI Input leakage current(1) VIN = 0 to VDDmax – – ±10 µA

ILO Output leakage current(1) VOUT = 0 to VDDmax – – ±10 µA

VIH Input high voltage –0.8xVDD – VDD +0.3 V

VIL Input low voltage –-0.3 –0.2xVDD V

VOH Output high voltage level IOH = –100 µA VDD -0.1 – – V

VOL Output low voltage level IOL = 100 µA – – 0.1 V

IOL (RB)Output low current (RB) VOL = 0.1 V 3 4 mA

VLKO VDD supply voltage (erase and

program lockout) – – 1.1 V

1. Leakage current and standby current double in stacked devices.

Table 23. DC characteristics, 3 V devices

Symbol Parameter Test conditions Min Typ Max Unit

IDD1

Operating current

Sequential

Read tRLRL minimum

E=V

IL, IOUT =0mA –1530mA

IDD2 Program ––1530mA

IDD3 Erase ––1530mA

IDD4 Standb y curr ent (TTL) (1) E=V

IH, WP =0/V

DD 1mA

IDD5 Standby current (CMOS)(1) E = VDD – 0.2,

WP = 0/VDD –10 50 µA

ILI Input leakage current(1) VIN = 0 to VDDmax – – ±10 µA

ILO Output leakage current(1) VOUT = 0 to VDDmax – – ±10 µA

VIH Input high voltage –0.8xVDD – VDD +0.3 V

VIL Input low v oltage –-0.3 –0.2xVDD V

VOH Output high voltage le vel IOH =–400µA 2.4 – – V

VOL Output low voltage level IOL =2.1mA – – 0.4 V

IOL (RB)Output low current (RB) VOL =0.4V 810 mA

VLKO VDD supply voltage (erase and

program lockout) – – 1.8 V

1. Leakage current and standby current double in stacked devices.

DC and AC parameters NAND01G-B2C

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Table 24. AC characteristics for command, address, data input

Symbol Alt.

symbol Parameter 1.8 V

devices 3 V

devices Unit

tALLWH tALS Address Latch Low to Write Enable High AL setup time Min 25 12 ns

tALHWH Address Latch High to Write Enable High

tCLHWH tCLS

Command Latch High to Write Enable

High CL setup time Min 25 12 ns

tCLLWH Command Latch Low to Write Enable

High

tDVWH tDS Data Valid to Write Enable High Data setup time Min 20 12 ns

tELWH tCS Chip Enable Low to Write Enable High E setup time Min 35 20 ns

tWHALH tALH Write Enable High to Address Latch High AL hold time Min 10 5ns

tWHALL Write Enable High to Address Latch Low AL hold time Min

tWHCLH tCLH

Write Enable High to Command Latch

High CL hold time Min 10 5ns

tWHCLL Write Enable High to Command Latch

Low

tWHDX tDH Write Enable High to Data Transition Data hold time Min 10 5ns

tWHEH tCH Write Enable High to Chip Enable High E hold time Min 10 5ns

tWHWL tWH Write Enable High to Write Enable Low W High hold time Min 15 10 ns

tWLWH tWP Write Enable Low to Write Enable High W pulse width Min 25 12 ns

tWLWL tWC Write Enable Low to Write Enable Low Write cycle time Min 45 25 ns

NAND01G-B2C DC and AC parameters

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Table 25. AC charac teristics for operati o ns(1)

Symbol Alt.

symbol Parameter 1.8 V

devices 3 V

devices Unit

tALLRL1 tAR Address Latch Low to

Read Enable Low Read electronic si gnature Min 10 10 ns

tALLRL2 Read cycle Min 10 10 ns

tBHRL tRR Ready/Busy High to Read Enable Low Min 20 20 ns

tBLBHx Busy time during cache read Typ 3 3 µs

Max 25 25 µs

tBLBH1

Ready/Busy Low to

Ready/Busy High

Read busy time Max 25 25 µs

tBLBH2 tPROG Program busy time Max 700 700 µs

tBLBH3 tBERS Erase busy time Max 3 3 ms

tBLBH4 tRST

Reset busy time, during ready Max 5 5 µs

Reset busy time, during read Max 5 5 µs

Reset busy time, during program Max 10 10 µs

Reset busy time, during erase Max 500 500 µs

tCLLRL tCLR Command Latch Low to Read Enable Low Min 10 10 ns

tDZRL tIR Data Hi-Z to Read Enable Low Min 0 0 ns

tEHQZ tCHZ Chip Enable High to Output Hi-Z Max 30 30 ns

tRHQZ tRHZ Read Enable High to Output Hi-z Max 100 100 ns

tWHWH tADL(2) Last addre s s latched to data loadi ng time during program

operations Min 100 70 ns

tVHWH

tVLWH tWW(3) Write protection time Min 100 100 ns

tELQV tCEA Chip Enable Low to Output Valid Max 45 25 ns

tRHRL tREH Read Enable High to

Read Enable Low Read Enable High hold time Min 15 10 ns

tEHQX tOH Chip Enable High or Read Enable High to Output Hold Min 15 15 ns

tRHQX(4)

tRLQX(4) tRLOH Read Enable Low to Output Hold 5ns

tRLRH tRP Read Ena ble Low to

Read Enable High Read Enable pulse width Min 25 12 ns

tRLRL tRC Read Ena ble Low to

Read Enable Low Read cycle time Min 45 25 ns

tRLQV tREA Read Ena ble Low to

Output Valid Read Enable access time Max 30 20 ns

Read ES access time(5)

tWHBH tRWrite Enable High to

Ready/Busy High Read busy time Max 25 25 µs

tWHBL tWB Write Enable High to Ready/Busy Low Max 100 100 ns

tWHRL tWHR Write Enable High to Read Enable Low Min 60 60 ns

tEHALX tCSD Chip Enable High to Address Latch or Command Latch

don’t care Min 10 10 ns

tEHCLX

tRHWL tRHW Read Enable High to Write Enable Low Min 100 100 ns

DC and AC parameters NAND01G-B2C

52/67

Figure 21. Command Latch AC waveforms

1. The time to ready depends on the value of the pull-up resistor tied to the ready/busy pin. See Figure 34, Figure 35 and

Figure 36.

2. tWHWH is the time from W rising edge during the final address cycle to W rising edge during the first data cycle.

3. During a program/erase enable operation, tWW is the delay from WP high to W High.

During a program/erase disable Operation, tWW is the delay from WP Low to W High.

4. tRLQX is valid when frequency is higher than 33 MHz, tRHQX is valid for frequency lower than 33 MHz.

5. ES = electronic signature.

ai13105

I/O

tCLHWH

tELWH

tWHCLL

tWHEH

tWLWH

tALLWH tWHALH

Command

tDVWH tWHDX

(CL Setup time) (CL Hold time)

(Data Setup time) (Data Hold time)

(ALSetup time) (AL Hold time)

H(E Setup time) (E Hold time)

NAND01G-B2C DC and AC parameters

53/67

Figure 22. Address Latch AC waveforms

Figure 23. Data Input Latch AC waveforms

1. Data in last is 2112 in x8 devices and 1056 in x16 devices.

ai13106b

I/O

tWLWH

tELWH tWLWL

tCLLWH

tWHWL

tALHWH

tDVWH

tWLWL tWLWL

tWLWHtWLWH tWLWH

tWHWL tWHWL

tWHDX

tWHALL

tDVWH

tWHDX

tDVWH

tWHDX

tDVWH

tWHDX

tWHALL

Adrress

cycle 1

tWHALL

(AL Setup time)

(AL Hold time)

Adrress

cycle 4

Adrress

cycle 3

Adrress

cycle 2

(CL Setup time)

(Data Setup time)

(Data Hold time)

(E Setup time)

tWLWL

tWHWL

tWHALL

tWHCLH

I/O

tALLWH

tWLWL

tWLWH

tWHEH

tWLWH

Data In 0 Data In 1 Data In

Last

tDVWH

tWHDX

tDVWH

tWHDX

tDVWH

tWHDX

ai13107

(Data Setup time)

(Data Hold time)

(ALSetup time)

(CL Hold time)

(E Hold time)

DC and AC parameters NAND01G-B2C

54/67

Figure 24. Sequential data output after read AC waveforms

1. CL = Low, AL = Low, W = High.

Figure 25. Serial access cycle after read, f o r frequency higher than 33 MHz

ai08031b

I/O

tRLRL

tRLQV

tRHRL

tRLQV

Data Out Data Out Data Out

tRHQZ

tBHRL

tRLQV

tRLQX

tEHQZ

(Read Cycle time)

(R Accesstime)

(R High Holdtime)

tEHQX

tRHQX

ai14294

I/O Data Out

NData Out

N+1 Data Out

N+2

tEHCLX

tRLRL

tBHRL

tEHQZ

tEHQX

NAND01G-B2C DC and AC parameters

55/67

Figure 26. Read status register AC waveforms

Figure 27. Read electronic signature AC waveforms

1. Refer to Table 12 for the values of the manufacturer and device codes, and to Table 13 and Table 14 for the information

contained in byte 3 and 4.

tELWH

tDVWH

Status Register

Output

70h

I/O

tCLHWH

tWHDX

tWLWH

tWHCLL

tCLLRL

tDZRL

tRLQV

tEHQZ

tRHQZ

tWHRL

tELQV

tWHEH

ai13108b

(Data Setup time) (Data Hold time)

tEHQX

tRHQX

90h 00h

Man.

code Device

code

I/O

tRLQV

Read Electronic

Signature

Command

1st Cycle

Address

ai08667

(Read ES Access time)

tALLRL1

00h

Byte4

Byte3Byte1 Byte2

see Note.1

DC and AC parameters NAND01G-B2C

56/67

Figure 28. Page read operation AC waveforms

I/O

tWLWL

tWHBL

tALLRL2

00h

Data

NData

N+1 Data

N+2 Data

Last

tWHBH tRLRL

tEHQZ

tRHQZ

ai13109c

Busy

Command

code Address N input Data Output

from address N to last byte or word in page

Add.N

cycle 1 Add.N

cycle 4

Add.N

cycle 3

Add.N

cycle 2

(Read Cycle time)

tRLRH

tBLBH1

30h

NAND01G-B2C DC and AC parameters

57/67

Figure 29. Page program AC waveforms

I/O

SR0

ai13110c

Last 10h

70h

80h

Page Program

setup code Confirm

code Read Status Register

tWLWL tWLWL tWLWL

tWHBL

tBLBH2

Page

Program

Address Input Data Input

Add.N

cycle 1 Add.N

cycle 4

Add.N

cycle 3

Add.N

cycle 2

(Write Cycle time)

(Program Busy time)

tWHWH

DC and AC parameters NAND01G-B2C

58/67

Figure 30. Block erase AC waveforms

Figure 31. Reset AC waveforms

D0h60h SR0

70h

ai14295

tWHBL

tWLWL

tBLBH3

Block Erase

Setup command Block Erase

I/O

Confirm

code Read Status Register

Block

address

input

(Erase Busy time)

(Write Cycle time)

Add.

cycle 1 Add.

cycle 2

I/O

tBLBH4

FFh

ai08043

(Reset Busy time)

NAND01G-B2C DC and AC parameters

59/67

Figure 32. Program/erase enable waveforms

Figure 33. Pr ogram/erase disable waveforms

11.1 Ready/Busy signal electrical characteristics

Figure 35, Figure 34 and Figure 36 show the electric al cha racteristics for the Ready/Busy

signal. The v alue required for the resistor RP can be calculated using the f ollowing equation:

So,

where IL is the sum of the input currents of all the de vices tied to the Ready/Busy signal. RP

max is determined by the maximum value of tr.

tVHWH

ai12477

I/O 80h 10h

tVLWH

ai12478

I/O 80h 10h

High

RPmin VDDmax VOLmax

–()

IOL IL

-------------------------------------------------------------=

RPmin 1.8V()

1.85V

3mA IL

---------------------------=

RPmin 3V() 3.2V

8mA IL

---------------------------=

DC and AC parameters NAND01G-B2C

60/67

Figure 34. Ready/Busy AC waveform

Figure 35. Ready/Busy load circuit

Figure 36. Resistor value versus wave form timings for Ready/Busy signal

1. T = 25°C.

NI3087B

busy

VOH

ready VDD

VOL

tftr

AI07563C

VDD

VSS

DEVICE

Open Drain Output

ibusy

NAND01G-B2C DC and AC parameters

61/67

11.2 Data protection

The Numonyx NAND de vice is designed to guarantee data prote ction during power

transitions.

A VDD detection cir cuit disables all NAND operations, if VDD is below the VLKO threshold.

In the VDD range from VLKO to the lower limit of nominal range, the WP pin should be kept

low (VIL) to gu arantee hardware protection during power transitions as shown in the below

figure.

Figure 37. Data protection

Ai11086

VLKO

VDD

Nominal Range

Locked

Package mechanical NAND01G-B2C

62/67

12 Package mechanical

To meet environmental requirements, Numonyx offers these devices in RoHS compliant

packages, which have a lead-free second-level interconnect. The category of second-level

interconnect is marked on the package and on the inner box label, in compliance with

JEDEC Standard JESD97. The maximum ratings re lated to soldering conditions are also

marked on the inner box label.

RoHS compliant specifications are available at www.numonyx.com.

Figure 38. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline

1. Drawing is not to scale.

TSOP-G

DIE

LA1 α

Table 26. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.20 0.047

A1 0.10 0.05 0.15 0.004 0.002 0.006

A2 1.00 0.95 1.05 0.039 0.037 0.041

B 0.22 0.17 0.27 0.009 0.007 0.011

C 0.10 0.21 0.004 0.008

CP 0.08 0.003

D1 12.00 11.90 12.10 0.472 0.468 0.476

E 20.00 19.80 20.20 0.787 0.779 0.795

E1 18.40 18.30 18.50 0.724 0.720 0.728

e0.50– –0.020–

L 0.60 0.50 0.70 0.024 0.020 0.028

L1 0.80 0.031

α3° 0° 5° 3° 0° 5°

NAND01G-B2C Package mechanical

63/67

Figure 39. VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15, 0.80 mm pitch, package outline

1. Drawing is not to scale

SD FD

BGA-Z75

ddd

FD1

E2 E1

FE1

BALL "A1"

Table 27. VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15, 0.80 mm pitch, package mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.05 0.041

A1 0.25 0.010

A2 0.65 0.026

b 0.45 0.40 0.50 0.018 0.016 0.020

D 9.00 8.90 9.10 0.354 0.350 0.358

D1 4.00 0.157

D2 7.20 0.283

ddd 0.10 0.004

E 11.00 10.90 11.10 0.433 0.429 0.437

E1 5.60 0.220

E2 8.80 0.346

e 0.80 – – 0.031 – –

FD 2.50 0.098

FD1 0.90 0.035

FE 2.70 0.106

FE1 1.10 0.043

SD 0.40 – – 0.016 – –

SE 0.40 – – 0.016 – –

Package mechanical NAND01G-B2C

64/67

Figure 40. VFBGA153 8 x 9 x 0.9 mm - 132+21 3R14, 0.50 mm pitch, package outline

and mechanical data

MIN NOM MAX

A0.90

A1 0.15

A2 0.58

Øb 0.25 0.30 0.35

D7.90 8.00 8.10

D1 6.50

E8.90 9.00 9.10

E1 6.50

eD 0.50

eE 0.50

FD 0.75

FE 1.25

SD 0.25

SE 0.25

mD 14

mE 14

n153

aaa 0.15

bbb 0.10

ddd 0.08

eee 0.15

fff 0.05

Control unit: mm

NAND01G-B2C Ordering information

65/67

13 Ordering information

Note: Not all combinations are necessarily available. For a list of available devices or for further

information on any aspect of these products, please contact your nearest Numonyx sales

office.

Table 28. Ordering information scheme

Example: NAND01GW3B2C ZA 6 E

Device type

NAND flash memory

Density

01G = 1 Gbit

Operatin g voltage

R = VDD = 1.7 to 1.95 V

W = VDD = 2.7 to 3.6 V

Bus width

3 = x8

4 = x16(1)

1. x16 organization only available for MCP products.

Family identifier

B = 2112-byte/ 1056-word page

Device options

2 = chip enable don't care enabled

Pro duct version

B = second version

C = third version

Package

N = TSOP48 12 x 20 mm

ZA = VFBGA63 9 x 11 x 1.05 mm, 0.8 mm pitch

ZF = VFBGA153 8 x 9 x 0.9 mm. 0.5 mm pitch

Temperature range

5 = –25 to 85 °C

6 = –40 to 85 °C

Option

E = RoHS compliant package, standard packing

F = RoHS compliant package, tape & reel packing

Revision history NAND01G-B2C

66/67

14 Revision history

Table 29. Document revision history

Date Version Changes

24-Jun-2008 1 Initial release.

16-Jan-2009 2 Modified Section 8.5: Error correction code, Figure 34: Ready/Busy AC

waveform, and Figure 36: Resistor value versus waveform timings for

Ready/Busy signal. Re moved Figure 19: Error detection.

23-Feb-2009 3

Modified Figure 7: Read operations, Table 12: Electronic signature and

Table 16: Parameter page data structure. Add ed security features on

the cover page and in Section 1: Description.

Removed references to ECOPACK packages throughout the document.

08-Jun-2009 4

Document status promoted from preliminary data to full datasheet.

Modified dimension A2 of the VFBGA63 package in Table 27:

VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15, 0.80 mm pitch, package

mechanical data.

29-Jan-2010 5 Added references to the VFBGA153 8 x 9 x 0.9 mm package

throughout the document. Removed temperature range 1 and added

temperature range 5 in Table 28: Ordering information scheme.

NAND01G-B2C

67/67

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WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF

NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

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Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the

presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,

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these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obt ain the latest specifications and before placing your product order.

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