TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 D Maximum Throughput . . . 140/200 KSPS D Built-In Conversion Clock D INL/DNL: 1 LSB Max, SINAD: 72 dB, D D D D SFDR: 85 dB, fi = 20 kHz SPI/DSP-Compatible Serial Interface Single Supply: 2.7 Vdc to 5.5 Vdc Rail-to-Rail Analog Input With 500 kHz BW Three Options Available: - TLV2541: Single Channel Input TOP VIEW TLV2541 CS VREF GND AIN D D - TLV2542: Dual Channels With Autosweep - TLV2545: Single Channel With Pseudo-Differential Input Low Power With Autopower Down - Operating Current: 1 mA at 2.7 V, 1.5 mA at 5 V Autopower Down: 2 A at 2.7 V, 5 A at 5 V Small 8-Pin MSOP and SOIC Packages TOP VIEW TLV2542 1 8 2 7 3 6 4 5 SDO FS VDD SCLK CS VREF GND AIN0 TOP VIEW TLV2545 1 8 2 7 3 6 4 5 SDO SCLK VDD AIN1 CS VREF GND AIN(+) 1 8 2 7 3 6 4 5 SDO SCLK VDD AIN(-) description The TLV2541, TLV2542, and TLV2545 are a family of high performance, 12-bit, low power, miniature, CMOS analog-to-digital converters (ADC). The TLV254x family operates from a single 2.7-V to 5.5-V supply. Devices are available with single, dual, or single pseudo-differential inputs. Each device has a chip select (CS), serial clock (SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial port of most popular host microprocessors (SPI interface). When interfaced with a TMS320t DSP, a frame sync signal (FS) can be used to indicate the start of a serial data frame on CS for all devices or FS for the TLV2541. TLV2541, TLV2542, and TLV2545 are designed to operate with very low power consumption. The power saving feature is further enhanced with an autopower-down mode. This product family features a high-speed serial link to modern host processors with SCLK up to 20 MHz. The maximum SCLK frequency is dependent upon the mode of operation (see Table 1). The TLV254x family uses the built-in oscillator as the conversion clock, providing a 3.5-s conversion time. AVAILABLE OPTIONS PACKAGED DEVICES TA 8-MSOP (DGK) 8-SOIC (D) TLV2541CDGK (AGZ) 0C 70C 0 C to 70 C TLV2542CDGK (AHB) TLV2545CDGK (AHD) -40C 40 C to 85C 85 C TLV2541IDGK (AHA) TLV2541ID TLV2542IDGK (AHC) TLV2542ID TLV2545IDGK (AHE) TLV2545ID Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320 is a trademark of Texas Instruments. Copyright (c) 2000 - 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 1 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 functional block diagram TLV2541 TLV2542 VDD VDD VREF VREF AIN0 S/H AIN OSC SCLK CS FS LOW POWER 12-BIT SAR ADC Mux AIN1 SDO Conversion Clock OSC CONTROL LOGIC SCLK CS GND Conversion Clock CONTROL LOGIC GND TLV2545 VDD VREF AIN (+) OSC SCLK CS LOW POWER 12-BIT SAR ADC S/H AIN (-) Conversion Clock CONTROL LOGIC GND 2 LOW POWER SAR ADC S/H * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * SDO SDO TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 Terminal Functions TLV2541 TERMINAL NAME NO. I/O DESCRIPTION AIN 4 I Analog input channel CS 1 I Chip select. A high-to-low transition on the CS input removes SDO from 3-state within a maximum setup time. CS can be used as the FS pin when a dedicated DSP serial port is used. FS 7 I DSP frame sync input. Indication of the start of a serial data frame. Tie this terminal to VDD if not used. GND 3 I Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. SCLK 5 I Output serial clock. This terminal receives the serial SCLK from the host processor. SDO 8 O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state until CS falling edge or FS rising edge, whichever occurs first. The output format is MSB first. When FS is not used (FS = 1 at the falling edge of CS): The MSB is presented to the SDO pin after CS falling edge and output data is valid on the first falling edge of SCLK. When CS and FS are both used (FS = 0 at the falling edge of CS): The MSB is presented to the SDO pin after the falling edge of CS. When CS is tied/held low, the MSB is presented on SDO after the rising FS. Output data is valid on the first falling edge of SCLK. (This is typically used with an active FS from a DSP using a dedicated serial port.) VDD 6 I Positive supply voltage VREF 2 I External reference input TLV2542/45 TERMINAL I/O DESCRIPTION NAME NO. AIN0 /AIN(+) 4 I Analog input channel 0 for TLV2542--Positive input for TLV2545. AIN1/AIN (-) 5 I Analog input channel 1 for TLV2542--Inverted input for TLV2545. CS 1 I Chip select. A high-to-low transition on CS removes SDO from 3-state within a maximum delay time. This pin can be connected to the frame sync of a DSP using a dedicated serial port. GND 3 I Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. SCLK 7 I Output serial clock. This terminal receives the serial SCLK from the host processor. SDO 8 O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS is high and presents output data after the CS falling edge until the LSB is presented. The output format is MSB first. SDO returns to the Hi-Z state after the 16th SCLK. Output data is valid on the falling SCLK edge. VDD 6 I Positive supply voltage VREF 2 I External reference input detailed description The TLV2541, TLV2542, and TLV2545 are successive approximation (SAR) ADCs utilizing a charge redistribution DAC. Figure 1 shows a simplified version of the ADC. The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is balanced, the conversion is complete and the ADC output code is generated. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 3 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 detailed description (continued) Charge Redistribution DAC _ AIN Control Logic + ADC Code GND/AIN(-) Figure 1. Simplified SAR Circuit serial interface OUTPUT DATA FORMAT MSB LSB D15-D4 D3-D0 Conversion result (OD11-OD0) Don't care The output data format is binary (unipolar straight binary). binary Zero-scale code = 000h, Vcode = GND Full-scale code = FFFh, Vcode = VREF - 1 LSB pseudo-differential inputs The TLV2545 operates in pseudo-differential mode. The inverted input is available on pin 5. It can have a maximum input ripple of 0.2 V. This is normally used for ground noise rejection. control and timing start of the cycle Each cycle may be started by either CS, FS, or a combination of both. The internal state machine requires one SCLK high-to-low transition to determine the state of these control signals so internal blocks can be powered up in an active cycle. Special care to SPI mode is necessary. Make sure there is at least one SCLK whenever CS (pin 1) is high to ensure proper operation. TLV2541 D Control via CS ( FS = 1 at the falling edge of CS)--The falling edge of CS is the start of the cycle. The MSB should be read on the first falling SCLK edge after CS is low. Output data changes on the rising edge of SCLK. This is typically used for a microcontroller with an SPI interface, although it can also be used for a DSP. The microcontroller SPI interface should be programmed for CPOL = 0 (serial clock referenced to ground) and CPHA = 1 (data is valid on the falling edge of the serial clock). At least one falling edge transition on SCLK is needed whenever CS is brought high. D Control via FS (CS is tied/held low)--The MSB is presented after the rising edge of FS. The falling edge of FS is the start of the cycle. The MSB should be read on the first falling edge of SCLK after FS is low. This is the typical configuration when the ADC is the only device on the DSP serial port. 4 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 control and timing (continued) D Control via both CS and FS--The MSB is presented after the falling edge of CS. The falling edge of FS is the start of the sampling cycle. The MSB should be read on the first falling SCLK edge after FS is low. Output data changes on the rising edge of SCLK. This configuration is typically used for multiple devices connected to a TMS320 DSP. TLV2542/5 All control is provided using CS (pin 1) on the TLV2542 and TLV2545. The cycle is started on the falling edge transition provided by either a CS signal from an SPI microcontroller or FS signal from a TMS320 DSP. Timing is similar to the TLV2541, with control via CS only. TLV2542 channel MUX reset cycle The TLV2542 uses CS to reset the analog input multiplexer. A short active CS cycle (4 to 7 SCLKs) resets the MUX to AIN0. When the CS cycle time is greater than 7 SCLKs in duration, as in the case for a complete conversion cycle (CS is low for 16 SCLKs plus maximum conversion time), the MUX toggles to the next channel (see Figure 4 for timing). One dummy conversion cycle is recommended after power up before attempting to reset the MUX. sampling The converter sample time is 12 SCLKs in duration, beginning on the fifth SCLK received after the converter has received a high-to-low CS transition (or a high-to-low FS transition for the TLV2541). conversion The TLV2541, TLV2542, and TLV2545 complete conversions in the following manner. The conversion is started after the 16th SCLK falling edge and takes 3.5 s to complete. Enough time (for conversion) should be allowed before a rising CS or FS edge so that no conversion is terminated prematurely. TLV2542 input channel selection is toggled on each rising CS edge. The MUX channel can be reset to AIN0 via CS as described in the earlier section and in Figure 4. The input is sampled for 12 SCLKs, converted, and the result is presented on SDO during the next cycle. Care should also be taken to allow enough time between samples to avoid prematurely terminating the cycle, which occurs on a rising CS transition if the conversion is not complete. The SDO data presented during a cycle is the result of the conversion of the sample taken during the previous cycle. timing diagrams/conversion cycles 1 2 3 4 5 6 7 12 13 14 15 16 1 SCLK CS FS IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII t(sample) SDO OD11 OD10 OD9 OD8 OD7 OD6 OD5 tc t(powerdown) OD0 Figure 2. TLV2541 Timing: Control via CS (FS = 1) * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 5 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 timing diagrams/conversion cycles (continued) 1 2 3 4 5 6 12 13 14 15 16 1 SCLK CS FS IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII t(sample) SDO OD11 OD10 OD9 OD8 OD7 OD6 t(powerdown) tc OD0 Figure 3. TLV2541 Timing: Control via CS and FS or FS Only 1 2 3 4 5 1 4 12 16 1 4 12 16 SCLK >8 SCLKs, MUX Toggles to AIN1 <8 SCLKs, MUX Resets to AIN0 CS t(powerdown) t(sample) IIIIII IIIIIII IIIIII IIIIIII SDO t(sample) tc AIN0 Result OD11 III III tc OD0 Figure 4. TLV2542 Reset Timing 1 2 3 4 5 6 7 12 13 14 15 16 1 SCLK CS IIIIII IIIIII t(sample) SDO OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD0 tc t(powerdown) OD11 OD10 OD9 Figure 5. TLV2542 and TLV2545 Timing using CS as the FS input When interfacing the TLV2541 with the TMS320 DSP, the FSR signal from the DSP may be connected to the CS input if this is the only device on the serial port. This saves one output terminal from the DSP. (Output data changes on the falling edge of SCLK. This is the default configuration for the TLV2542 and TLV2545.) 6 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 using CS as the FS input (continued) SCLK and conversion speed The input frequency of SCLK can range from 100 kHz to 20 MHz maximum. The ADC conversion uses a separate internal oscillator with a minimum frequency of 4 MHz. The conversion cycle takes 14 internal oscillator clocks to complete. This leads to a 3.5-s conversion time. For a 20-MHz SCLK, the minimum total cycle time is given by: 16x(1/20M)+14x(1/4M)+one SCLK = 4.35 s. An additional SCLK is added to account for the required CS and/or FS high time. These times specify the minimum cycle time for an active CS or FS signal. If violated, the conversion terminates, invalidating the next data output cycle. Table 1 gives the maximum SCLK frequency for a given supply voltage and operational mode. control via pin 1 (CS, SPI interface) All devices are compatible with this mode operation. A falling CS initiates the cycle (for TLV2541, the FS input is tied to VDD). CS remains low for the entire cycle time (sample+convert+one SCLK) and can then be released. NOTE: IMPORTANT: A single SCLK is required whenever CS is high. control via pin 1 (CS, DSP interface) All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the CS input of the ADC. A falling edge on the CS input initiates the cycle. (For the TLV2541, the FS input can be tied to VDD, although better performance can be achieved when using the FS input for control. Refer to the next section.) The CS input should remain low for the entire cycle time (sample+convert+one SCLK) and can then be released. NOTE: IMPORTANT: A single SCLK is required whenever CS is high. This should be of little consequence, since SCLK is normally always present when interfacing with a DSP. control via pin 1 and pin 7 (CS and FS or FS only, DSP interface) Only the TLV2541 is compatible with this mode of operation. The CS input to the ADC can be controlled via a general-purpose I/O pin from the DSP. The FS signal from the DSP is connected directly to the FS input of the ADC. A falling edge on CS, if used, releases the MSB on the SDO output. When CS is not used, the rising FS edge releases the MSB. The falling edge on the FS input while SCLK is high initiates the cycle. The CS and FS inputs should remain low for the entire cycle time (sample+convert+one SCLK) and can then be released. reference voltage An external reference is applied via VREF. The voltage level applied to this pin establishes the upper limit of the analog inputs to produce a full-scale reading. The value of VREF and the analog input should not exceed the positive supply or be less than GND, consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher than VREF and at zero when the input signal is equal to or lower than GND. power down and power up Autopower down is built into these devices in order to reduce power consumption. The actual power savings depends on the inactive time between cycles and the power supply (loading) decoupling/storage capacitors. Power-down takes effect immediately after the conversion is complete. This is fast enough to provide some power savings between cycles with longer than 1 SCLK inactive time. The device power goes down to 5 A within 0.5 s. To achieve the lowest power-down current (deep powerdown) of 1 A requires 2-ms inactive time between cycles. The power-down state is initiated at the end of conversion. These devices wake up immediately at the next falling edge of CS or the rising edge of FS. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 7 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 ICC VDD = 5 V With 1-F/0.1-F Capacitor Between Supply and Ground VDD = 2.7 V 0.5 S 2 mS 1.5 mA 0.95 mA 5 A 2 A 1 A 1 A t(Powerdown) - Powerdown time - S Table 1. Modes of Operation and Data Throughput MAX SCLK (MHz) (50/50 duty cycle) CONTROL PIN(s)/DEVICE APPROXIMATE CONVERSION THROUGHPUT (ksps) VDD = 2.7 V VDD = 4.5 V VDD = 2.7 V VDD = 4.5 V For SPI interface 10 15 175 200 For DSP interface (Use CS as FS) 5 8 140 175 15 20 200 200 CS control only (TLV2541 only) CS and FS control (TLV2541 only) DSP interface See Figure 29(a). See Figure 29(b). See Figure 29(c). absolute maximum ratings over operating free-air temperature (unless otherwise noted) 8 Supply voltage range, GND to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD+ 0.3 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 150C Operating free-air temperature range, TA: C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 recommended operating conditions Supply voltage, VDD MIN NOM MAX 2.7 3.3 5.5 UNIT V Positive external reference voltage input, VREFP (see Note 1) 2 VDD V Analog input voltage (see Note 1) 0 VDD V High level control input voltage, VIH 2.1 V Low-level control input voltage, VIL 0.6 Setup time, CS falling edge before first SCLK falling edge, VDD = REF = 4.5 V tsu(CSL-SCLKL) VDD = REF = 2.7 V Hold time, CS falling edge after SCLK falling edge, th(SCLKL-CSL) 40 ns 70 5 Delay time, delay from CS falling edge to FS rising edge, td(CSL-FSH) (TLV2541 only) 0.5 Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKL) (TLV2541 only) 0.35 V ns 7 SCLKs SCLKs Hold time, FS high after SCLK falling edge, th(SCLKL-FSL) (TLV2541 only) 0.65 SCLKs Pulse width CS high time, tw(H_CS) 100 ns Pulse width FS high time, tw(H_FS) (TLV2541 only) 0.75 SCLKs SCLK cycle time, VDD = 3.6 V to 2.7 V, tc(SCLK) (maximum tolerance of 40/60 duty cycle) 90 10000 SCLK cycle time, VDD = 5.5 V to 4.5 V, tc(SCLK) (maximum tolerance of 40/60 duty cycle) 50 10000 Pulse width low time, tw(L_SCLK) 0.4 0.6 SCLK Pulse width high time, tw(H_SCLK) 0.4 0.6 SCLK Hold time, hold from end of conversion to CS high, th(EOC-CSH) (EOC is internal, indicates end of conversion time, tc) Active CS cycle time to reset internal MUX to AIN0, t(reset cycle) (TLV2542 only) 0.05 4 7 40 VDD = REF = 2.7 V, 25-pF load 70 Delay time, delay from FS falling edge to SDO valid, td(FSL-SDOV) VDD = REF = 4.5 V, 25-pF load (TLV2541 only) VDD = REF = 2.7 V, 25-pF load 1 1 Delay time, delay from SCLK rising edge to SDO valid, td(SCLKH-SDOV) VDD = REF = 4.5 V, 25-pF load 11 VDD = REF = 2.7 V, 25-pF load 21 Delay time, delay from 17th SCLK rising edge to SDO 3-state, 3 state, td(SCLK17H-SDOZ) VDD = REF = 4.5 V, 25-pF load 30 VDD = REF = 2.7 V, 25-pF load 60 Conversion time, tc Conversion clock = internal oscillator 2.1 Sampling time, t(sample) See Note 2 300 TLV2541/2/5C Operating free-air free air temperature temperature, TA TLV2541/2/5I 2.6 ns s VDD = REF = 4.5 V, 25-pF load Delay time, time delay from CS falling edge to SDO valid, valid td(CSL-SDOV) ns 3.5 SCLKs ns ns ns ns s ns 0 70 -40 85 C NOTES: 1. Analog input voltages greater than that applied to VREF convert as all ones (111111111111), while input voltages less than that applied to GND convert as all zeros(000000000000). 2. Minimal t(sample) is given by 0.9 x 50 pF x (RS + 0.5 k), where RS is the source output impedance. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 9 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 electrical characteristics over recommended operating free-air temperature range, VDD = VREF = 2.7 V to 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 5.5 V, IOH = -0.2 mA at 30-pF load VOH High level output voltage High-level VOL Low level output voltage Low-level IOZ Off-state output current (high-impedance-state) VO = 0 IIH High-level input current IIL ICC UNIT V VDD-0.2 VDD = 5.5 V, IOL = 0.8 mA at 30-pF load 0.4 0.1 V 1 2.5 -2.5 VI = VDD 0.005 2.5 A Low-level input current VI = 0 V -0.00 5 2.5 A Operating supply current CS at 0 V Autopower-down current t(powerdown) 0.5 s For all digital inputs, 0 VI 0.3 V or VI VDD- 0.3 V, SCLK = 0, VDD = 4.5 V to 5.5 V, Ext ref 5 VDD = 2.7 V to 3.3 V, 2 Deep autopower-down current t(powerdown) 2 ms For all digital inputs, 0 VI 0.3 V or VI VDD- 0.3 V, SCLK = 0, VDD = 4.5 V to 5.5 V, Ext ref 1 VDD = 2.7 V to 3.3 V 1 Selected channel at VDD 1 Selected channel at 0 V -1 CS = VDD VDD = 4.5 V to 5.5 V 1.3 1.5 VDD = 2.7 V to 3.3 V 0.85 0.95 Ext ref Analog inputs Input capacitance 20 Control Inputs Input on resistance 45 50 5 25 VDD = 5.5 V 500 VDD = 2.7 V 600 Autopower down 0.5 All typical values are at VDD = 5 V, TA = 25C. 10 MAX 2.4 -1 Selected analog input channel leakage current TYP VDD = 2.7 V, IOL = 20 A at 30-pF load VO = VDD ICC(AUTOPWDN) Ci VDD = 2.7 V, IOH = -20 A at 30-pF load MIN * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * A A mA A A A A pF SCLK TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 ac specifications (fi = 20 kHz) PARAMETER SINAD Signal to noise ratio +distortion Signal-to-noise THD Total harmonic distortion ENOB Effective number of bits SFDR Spurious free dynamic range TEST CONDITIONS MIN TYP 200 KSPS, VDD = VREF = 5.5 V 70 72 150 KSPS, VDD = VREF = 2.7 V 68 71 MAX UNIT dB 200 KSPS, VDD = VREF = 5.5 V -84 -80 150 KSPS, VDD = VREF = 2.7 V -84 -80 200 KSPS, VDD = VREF = 5.5 V 11.8 150 KSPS, VDD = VREF = 2.7 V 11.6 200 KSPS, VDD = VREF = 5.5 V -84 -80 150 KSPS, VDD = VREF = 2.7 V -84 -80 dB Bits dB Analog Input Full-power bandwidth, -3 dB 1 MHz Full-power bandwidth, -1 dB 500 kHz external reference specifications PARAMETER TEST CONDITIONS Reference input voltage VDD = 2.7 V to 5.5 V UNIT VDD V SCLK = 0 CS = 0, SCLK = 20 MHz CS = 1, SCLK = 0 CS = 0, SCLK = 20 MHz VDD = VREF = 5.5 V, CS = 0, SCLK = 20 MHz 100 400 VDD = VREF = 2.7 V, CS = 0, SCLK = 20 MHz 50 200 CS = 1, SCLK = 0 CS = 0, SCLK = 20 MHz CS = 1, SCLK = 0 CS = 0, SCLK = 20 MHz VDD = 2 2.7 7V VDD = VREF = 5 5.5 5V Reference input capacitance VDD = VREF = 2 2.7 7V Reference voltage MAX CS = 1, Reference input impedance VREF TYP 2 5V VDD = 5 5.5 Reference current MIN 100 20 M 25 k 100 20 M 25 5 20 A 15 45 5 20 k 50 15 45 VDD = 2.7 V to 5.5 V pF 50 VDD V dc specification, VDD = VREF = 2.7 V to 5.5 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise noted) PARAMETER INL Integral linearity error (see Note 4) DNL Differential linearity error TEST CONDITIONS See Note 3 EO Offset error (see Note 5) See Note 3 EG Gain error (see Note 5) See Note 3 Et Total unadjusted error (see Note 6) See Note 3 MIN TYP MAX UNIT 0.6 1 LSB 1 LSB 0.5 TLV2541/42 1.5 TLV2545 2.5 TLV2541/42 2 TLV2545 5 TLV2541/42 2 TLV2545 5 LSB LSB LSB NOTES: 3. Analog input voltages greater than that applied to VREF convert as all ones (111111111111). 4. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics. 5. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference between 111111111111 and the converted output for full-scale input voltage. 6. Total unadjusted error comprises linearity, zero, and full-scale errors. * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 11 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 PARAMETER MEASUREMENT INFORMATION t(sample) tc tw(H_SCLK) VIH 1 2 4 12 16 SCLK VIL tw(L_SCLK) tsu(CSL-SCLKL) t(powerdown) CS th(SCLKL-FSL) tw(H_CS) tsu(FSH-SCLKL) th(EOC-CSH) td(CSL-FSH) td(SCLKH-SDOV) FS SDO IIIII IIIII tw(H_FS) OD11 OD8 OD0 td(CSL-SDOV) IIIII IIIII td(SCLK17H-SDOZ) Figure 6. TLV2541 Critical Timing (Control via CS and FS or FS only) t(sample) tsu(CSL-SCLKL) 1 2 tc 4 12 16 SCLK t(powerdown) CS td(SCLKH-SDOV) SDO OD11 OD10 OD9 IIIIIII IIIIIII td(SCLK17H-SDOZ) OD0 td(CSL-SDOV) Figure 7. TLV2541 Critical Timing (Control via CS only, FS = 1) 12 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * th(EOC-CSH) TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 PARAMETER MEASUREMENT INFORMATION t(sample) tc 1 1 4 12 16 SCLK t(reset cycle) MUX = AIN0 CS tw(H_CS) IIII IIII SDO th(EOC-CSH) td(SCLKH-SDOV) td(CSL-SDOV) OD11 OD0 td(CSL-SDOV) IIIII IIIII OD11 td(SCLK17H-SDOZ) Figure 8. TLV2542 Reset Cycle Critical Timing t(sample) tw(H_SCLK) VIH 1 2 4 12 tc 16 SCLK VIL th(SCLKL-CSL) tw(L_SCLK) t(powerdown) tsu(CSL-SCLKL) CS tw(H_CS) SDO th(EOC-CSH) td(SCLKH-SDOV) OD11 OD8 td(CSL-SDOV) OD0 IIIII IIIII td(SCLK17H-SDOZ) Figure 9. TLV2542 and TLV2545 Conversion Cycle Critical Timing * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 13 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 0.7 0.6 VDD = REF = 5.5 V 200 KSPS INL - Integral Nonlinearity - LSB INL - Integral Nonlinearity - LSB VDD = REF = 2.7 V 150 KSPS 0.65 0.6 -40 0.5 -40 90 25 0.55 25 TA - Free-Air Temperature - C Figure 10 Figure 11 DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE 0.35 VDD = REF = 2.7 V 150 KSPS DNL - Differential Nonlinearity - LSB DNL - Differential Nonlinearity - LSB 0.6 0.5 0.4 0.3 0.2 0.1 0 -40 25 TA - Free-Air Temperature - C VDD = REF = 5.5 V 200 KSPS 0.3 0.25 -40 90 Figure 12 14 90 TA - Free-Air Temperature - C 25 TA - Free-air Temperature - C Figure 13 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 90 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 TYPICAL CHARACTERISTICS OFFSET ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs FREE-AIR TEMPERATURE 0.5 0.9 VDD = REF = 2.7 V 150 KSPS VDD = REF = 5.5 V 200 KSPS Gain Error - LSB 0.3 0.2 0.85 0.1 0 -40 0.8 -40 90 25 TA - Free-Air Temperature - C 25 TA - Free-Air Temperature - C Figure 14 90 Figure 15 SUPPLY CURRENT vs FREE-AIR TEMPERATURE 1.5 VDD = REF = 5.5 V 200 KSPS Supply Current - mA Offset Error - LSB 0.4 1.4 1.3 1.2 -40 25 TA - Free-Air Temperature - C 90 Figure 16 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 15 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 TYPICAL CHARACTERISTICS INL - Integral Nonlinearity - LSB INTEGRAL NONLINEARITY ERROR vs DIGITAL OUTPUT CODES 1 VDD = REF = 2.7 V 150 KSPS 0.5 0 -0.5 -1 4095 1 Digital Output Codes Figure 17 DNL - Differential Nonlinearity - LSB DIFFERENTIAL NONLINEARITY ERROR vs DIGITAL OUTPUT CODES 1 VDD = REF = 2.7 V 150 KSPS 0.5 0 -0.5 -1 4095 1 Digital Output Codes Figure 18 16 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 TYPICAL CHARACTERISTICS INL - Integral Nonlinearity - LSB INTEGRAL NONLINEARITY ERROR vs DIGITAL OUTPUT CODES 1 VDD = REF = 5.5 V 200 KSPS 0.5 0 -0.5 -1 4095 1 Digital Output Codes Figure 19 DNL - Differential Nonlinearity - LSB DIFFERENTIAL NONLINEARITY ERROR vs DIGITAL OUTPUT CODES 1 VDD = REF = 5.5 V 200 KSPS 0.5 0 -0.5 -1 1 4095 Digital Output Codes Figure 20 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 17 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 TYPICAL CHARACTERISTICS 2048 POINTS FAST FOURIER TRANSFORM (FFT) 0 VDD = REF = 2.7 V 150 KSPS fi = 20 kHz Magnitude - dB -20 -40 -60 -80 -100 -120 -140 0 20 40 60 80 100 f - Input Frequency - KHz Figure 21 2048 POINTS FAST FOURIER TRANSFORM (FFT) 0 VDD = REF = 5.5 V 200 KSPS fi = 20 kHz Magnitude - dB -20 -40 -60 -80 -100 -120 -140 0 20 40 60 f - Input Frequency - KHz Figure 22 18 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 80 100 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 TYPICAL CHARACTERISTICS SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 75 VDD = REF = 2.7 V 150 KSPS SINAD - Signal-To-Noise + Distortion - dB SINAD - Signal-To-Noise + Distortion - dB 75 73 71 69 67 65 0 10 20 30 40 50 60 70 VDD = REF = 5.5 V 200 KSPS 73 71 69 67 65 80 0 20 Figure 23 ENOB - Effective Number Of Bits - Bits ENOB - Effective Number Of Bits - Bits 11.8 11.6 11.4 11.2 20 30 100 12 VDD = REF = 2.7 V 150 KSPS 10 80 EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY 12 0 60 Figure 24 EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY 11 40 f - Input Frequency - KHz f - Input Frequency - KHz 40 50 60 70 11.8 11.7 11.6 11.5 11.4 11.3 11.2 11.1 11 80 f - Input Frequency - KHz VDD = REF = 5.5 V 200 KSPS 11.9 0 20 40 60 80 100 f - Input Frequency - KHz Figure 25 Figure 26 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 19 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY THD - Total Harmonic Distortion - dB -75 VDD = REF = 2.7 V 150 KSPS -76 -77 -78 -79 -80 -81 -82 -83 -84 -85 0 10 30 20 40 50 70 60 80 f - Input Frequency - KHz Figure 27 TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY THD - Total Harmonic Distortion - dB -70 VDD = REF = 5.5 V 200 KSPS -72 -74 -76 -78 -80 -82 -84 -86 -88 -90 0 20 40 60 80 f - Input Frequency - KHz Figure 28 20 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 100 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 APPLICATION INFORMATION VDD VDD 10 k TLV2541 MISO FS SDO VDD SS CS AIN SCLK GND SCLK SPI PORT VREF EXT Reference (a) VDD VDD 10 k DR CLKX CLKR TLV2541 FS SDO VDD SCLK AIN FSX CS FSR GND DSP VREF EXT Reference (b) VDD TLV2541 FS FSX FSR DR SDO CLKX SCLK VDD AIN CLKR GPIO CS GND DSP VREF EXT Reference (c) Figure 29. Typical TLV2541 Interface to a TMS320 DSP * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * 21 TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E -MARCH 2000 - REVISED APRIL 2010 APPLICATION INFORMATION VDD TMS320 EXT Reference 10 k 10 k FSX CS SDO SCLK FSR DR CLKR DSP CLKX VDD VREF TLV2542/45 AIN 0/AIN (+) GND For TLV2545 only Figure 30. Typical TLV2542/45 Interface to a TMS320 DSP 22 * POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443 * AIN 1/AIN (-) PACKAGE OPTION ADDENDUM www.ti.com 18-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV2541CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2541CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2541CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2541CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2541ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2541IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2541IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2541IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2541IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2541IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2541IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2541IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2542CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2542CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2542CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2542CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2542ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 18-Aug-2012 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV2542IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2542IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2542IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2542IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2542IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2542IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2542IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2545CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2545CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2545ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2545IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2545IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2545IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2545IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV2545IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 2 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 18-Aug-2012 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV2541CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2541IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2541IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2542CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2542IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2542IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2545IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV2541CDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV2541IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV2541IDR SOIC D 8 2500 367.0 367.0 35.0 TLV2542CDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV2542IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV2542IDR SOIC D 8 2500 367.0 367.0 35.0 TLV2545IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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