This is information on a product in full production.
March 2015 DocID024138 Rev 7 1/20
STGIPS20C60
SLLIMM™ small low-loss intelligent molded module
IPM, 3-phase inverter - 20 A, 600 V short-circuit rugged IGBT
Datasheet
-
production data
Features
•IPM 20 A, 600 V 3-phase IGBT inverter bridge
including control ICs for gate driving and free-
wheeling diodes
•Short-circuit rugged IGBTs
•3.3 V, 5 V, 15 V CMOS/TTL inputs
comparators with hysteresis and pull down /
pull up resistors
•Undervoltage lockout
•Internal bootstrap diode
•Interlocking function
•Smart shutdown function
•Comparator for fault protection against over
temperature and overcurrent
•DBC leading to low thermal resistance
•Isolation rating of 2500 V
rms
/min
•UL recognized: UL1557 file E81734
Applications
•3-phase inverters for motor drives
•Air conditioners
Description
This intelligent power module provides a
compact, high performance AC motor driv e in a
simple, rugged design. Combining ST proprietary
control ICs with the most advanced short-circuit-
rugged IGBT system technology, this device is
ideal for 3-phase inverters in applications such as
motor drives and air conditioners. SLLIMM™ is a
trademark of STMicroelectronics.
SDIP-25L
Table 1. Device summary
Order code Marking Package Packing
STGIPS20C60 GIPS20C60 SDIP-25L Tube
www.st.com
Contents STGIPS20C60
2/20 DocID024138 Rev 7
Contents
1 Internal block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . 3
2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Wa v eforms definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4 Smart shutd own function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 SDIP-25L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DocID024138 Rev 7 3/20
STGIPS20C60 Internal block diagram and pin configuration
20
1 Internal block diagram an d pin configuration
Figure 1. Internal block diagram
AM05002v1
W
NW
P
VBOOT U
VBOOT W
OUT V
VBOOT V
OUT U
OUT W
LIN
SD/OD
VCC
GND
DT
OUT
HVG
Vboot
HIN
LVG
CP+
LIN
SD/OD
VCC
GND
DT
OUT
HVG
Vboot
HIN
LVG
CP+
Pin 16
Pin 1
P
P
Pin 17
Pin 25
GND
LIN-U
HIN-V
LIN-V
HIN-W
HIN-U
LIN-W
CIN
VCC
NU
NV
U
V
LIN
SD/OD
VCC
GND
DT
OUT
HVG
Vboot
HIN
LVG
CP+
SD/OD
Internal block diagram and pin configuration STGIPS20C60
4/20 DocID024138 Rev 7
Figure 2. Pin layout (bottom view)
Table 2. Pin description
Pin n° Symbol Description
1OUT
U
High-side reference output for U phase
2V
bootU
Bootstrap voltage for U phase
3LIN
U
Low-side logic input for U phase
4HIN
U
High-side logic input for U phase
5V
CC
Low voltage power supply
6OUT
V
High-side reference output for V phase
7V
boot V
Bootstrap voltage for V phase
8 GND Ground
9LIN
V
Low-side logic input for V phase
10 HIN
V
High-si de log ic input for V phase
11 OUT
W
High-side reference output for W phase
12 V
boot W
Bootstrap voltage for W phase
13 LIN
W
Low-side logic input for W phase
14 HIN
W
High-side logic input for W phase
15 SD / OD Shutdown logic input (active low) / open-drain (comparator output)
16 CIN Compara tor inp ut
17 N
W
Negative DC input for W phase
18 W W phase output
19 P Positi ve DC input
20 N
V
Negative DC input for V phase
21 V V phase output
22 P Positi ve DC input
23 N
U
Negative DC input for U phase
24 U U phase output
25 P Positi ve DC input
0$5.,1*$5($
DocID024138 Rev 7 5/20
STGIPS20C60 Electric al ratings
20
2 Electrical ratings
2.1 Absolute maximum ratings
Table 3. Inverter part
Symbol Parameter Value Unit
V
PN
Supply voltage applied between P - N
U
, N
V
, N
W
450 V
V
PN(surge)
Supply voltage (surge) applied between P - N
U
,
N
V
, N
W
500 V
V
CES
Each IGBT collector emitter voltage (V
IN(1)
= 0)
1. Applied between HIN
i
, LIN
i and
GND for i = U, V, W
600 V
± I
C
Each IGBT continuous collector current
at T
C
= 25°C 20 A
± I
CP (2)
2. Pulse width limited by max junction temperature
Each IGBT pulsed collector current 40 A
P
TOT
Each IGBT total dissipation at T
C
= 25°C 46 W
t
scw
Short circuit withstand time, V
CE
= 0.5 V
(BR)CES
T
J
= 125 °C, V
CC
= V
boot
= 15 V, V
IN (1)
= 0 - 5 V 5µs
Table 4. Control part
Symbol Parameter Value Unit
V
OUT
Out put voltag e applied bet ween
OUT
U,
OUT
V,
OUT
W
- GND V
boot
- 21 to V
boot
+ 0.3 V
V
CC
Low voltage power supply - 0.3 to +21 V
V
CIN
Comparator input voltage - 0.3 to V
CC
+0.3 V
V
boot
Bootstrap voltage applied between
V
boot i
- OUT
i
for i = U, V, W - 0.3 to 620 V
V
IN
Logic in put vol tage a pplied b etween HIN, L IN and
GND - 0.3 to 15 V
V
SD/OD
Open drain voltage - 0.3 to 15 V
dV
OUT
/dt Allowed outp ut sle w rate 50 V/ns
Table 5. Total system
Symbol Parameter Value Unit
V
ISO
Isolation withstand voltage applied between each
pin and heatsink plate (AC voltage, t = 60 sec.) 2500 V
T
j
Power chips operating junction temperature - 40 to 150 °C
T
C
Module case operation temperature - 40 to 125 °C
Electrical ratings STGIPS20C60
6/20 DocID024138 Rev 7
2.2 Thermal data
Table 6. Thermal data
Symbol Parameter Value Unit
R
thJC
Thermal resis t an ce jun cti on -cas e si ngl e IGBT 2.7 °C/W
Thermal resis t an ce jun cti on -cas e si ngl e diode 5 °C /W
Figure 3. Maximum I
C(RMS)
current vs. switching
frequency
(1)
Figure 4. Maximum I
C(RMS)
current vs. f
sine(1)
1. Simulated curves refer to typical IGBT parameters and maximum R
thj-c.
AM17108v1
12
14
16
18
20
22
24
26
28
IC(RMS)
(A)
4 8 12 16 fsw (kHz)
3
-phase
sinusoidal PWM
VPN = 300 V, Modulaon Index = 0.8,
PF = 0.6, Tj = 150 °C, fsine
= 60 Hz
Tc = 80 °C
Tc = 100 °C
AM17109v1
8
9
10
11
12
13
14
15
16
17
IC(RMS)
(A)
1 10 100 fsine (Hz)
3
-
phase sinusoidal PWM
V
PN = 300 V, Modulation Index = 0.8,
PF = 0.6, Tj
= 150 °C, T
c
= 100 °C
fsw = 12 kHz fsw = 16 kHz
fsw = 20 kHz
DocID024138 Rev 7 7/20
STGIPS2 0C60 Electri cal chara ct er istics
20
3 Electrical characteristics
T
J
= 25 °C unless otherwise specified.
Note: t
ON
and t
OFF
include the propagation delay time of the internal drive. t
C(ON)
and t
C(OFF)
are
the switching time of IGBT itself under the internally given gate driving condition.
Table 7. Inverter part
Symbol Parameter Test conditions Value Unit
Min. Typ. Max.
V
CE(sat)
Collector-emitter
saturati on vol t age
V
CC
= V
boot
= 15 V, V
IN(1)
= 0 ÷ 5 V,
I
C
= 20 A -1.6 2 V
V
CC
= V
boot
= 15 V, V
IN(1)
= 0 ÷ 5 V,
I
C
= 20 A, T
J
= 125 °C -1.7
I
CES
Collector-cut off current
(V
IN(1)
= 0 “logic state”) V
CE
= 550 V, V
CC
= V
Boot
= 15 V - 100 µA
V
F
Diode forward voltage V
IN(1)
= 0 “logic state”, I
C
= 20 A - 2.2 V
Inductive load switching time and energy
t
on
Turn-on time
V
PN
= 300 V,
V
CC
= V
boot
= 15 V,
V
IN(1)
= 0 ÷ 5 V,
I
C
= 20 A
(see Figure 5)
-390 -
ns
t
c(on)
Crossover t ime (on) - 170 -
t
off
Turn-off time - 970 -
t
c(off)
Crossover t ime (off) - 150 -
t
rr
Reverse recove r y time - 284 -
E
on
Turn-on switching losses - 520 - µJ
E
off
Turn-off switch ing lo sses - 460 -
1. Applied between HIN
i
, LIN
i and
GND
for i = U, V, W. (LIN inputs are active-low).
Electrical characteristics STGIPS20C60
8/20 DocID024138 Rev 7
Figure 5. Switching time test circuit
Figure 4 "Switching time definition" refers to HIN inputs (active high). For LIN inputs (active low), V
IN
polarity
must be inverted for turn-on and turn-off.
Figure 6. Switching time definition
VBOOT>VCC
RSD
L
IC
VCE
+5V
VCC
INPUT
01
BUS
/Lin
/SD
Hin
Vcc
DT LVG
HVG
OUT
BOOT
CP+
GND
AM17099v1
V
CE
I
C
I
C
V
IN
t
ON
t
C(ON)
VIN(ON) 10% IC 90% IC 10% VCE
(a) turn-on (b) turn-off
t
rr
100% IC 100% IC
V
IN
V
CE
t
OFF
t
C(OFF)
VIN(OFF) 10% VCE 10% IC
AM09223V1
DocID024138 Rev 7 9/20
STGIPS2 0C60 Electri cal chara ct er istics
20
3.1 Control part
Table 8. Low voltage power supply (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
cc_hys
V
cc
UV hysteresis 1.2 1.5 1.8 V
V
cc_thON
V
cc
UV turn ON threshold 11.5 12 12.5 V
V
cc_thOFF
V
cc
UV turn OFF threshold 10 10.5 11 V
I
qccu
Undervoltage quiescent
supply current
V
CC
= 10 V
SD/OD = 5 V; LIN = 5 V;
H
IN
= 0, C
IN
= 0 450 µA
I
qcc
Quiescent current V
CC
= 15 V
SD/OD= 5 V; LIN = 5 V
H
IN
= 0, C
IN
= 0 3.5 mA
V
ref
Internal com p a rato r (CIN)
reference voltage 0.5 0.54 0.58 V
Table 9. Bootstrapped volta ge (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
BS_hys
V
BS
UV
hysteresis 1.2 1.5 1.8 V
V
BS_thON
V
BS
UV
turn ON threshold 11.1 11.5 12.1 V
V
BS_thOFF
V
BS
UV
turn OFF threshold 9.8 10 10.6 V
I
QBSU
Undervoltage V
BS
quiescent
current
V
BS
< 9 V
SD/OD = 5 V ; LIN and
HIN = 5 V; C
IN
= 0 70 110 µA
I
QBS
V
BS
quiescent current V
BS
= 15 V
SD/OD = 5 V ; LIN and
HIN = 5 V; C
IN
= 0 200 300 µA
R
DS(on)
Bootstrap driver on resistance LIN= 5 V; HIN= 0 V 120 Ω
Table 10. Logic inputs (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
il
Low level logic threshold
voltage 0.8 1.1 V
V
ih
High level logic threshol d
voltage 1.9 2.25 V
I
HINh
HIN logic “1” input bias current HIN = 15 V 110 175 260 µA
I
HINl
HIN logic “0” input bias current HIN = 0 V 1 µA
I
LINl
LIN logic “1” input bias current LIN = 0 V 3 6 20 µA
I
LINh
LIN logic “0” input bias current LIN = 15 V 1 µA
I
SDh
SD logic “0” input bias current SD = 15 V 30 120 300 µA
I
SDl
SD logic “1” input bias current SD = 0 V 3 µA
Dt Dead time s ee Figure 7 and Table 13 1.2 µs
Electrical characteristics STGIPS20C60
10/20 DocID024138 Rev 7
Note: X: don’t care
Table 11. Sense comparator characteristics (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
ib
Input bias curr ent V
CIN(i)
= 1 V - 3 µA
V
ol
Open-dra in low-l ev el outp ut
voltage I
od
= 3 mA - 0.5 V
t
d_comp
Compar ator delay SD/OD pulled to 5 V through
100 kΩ resistor - 90 130 ns
SR Slew rate C
L
= 180 pF; R
pu
= 5 kΩ-60 V/µsec
t
sd
Shut down to high / low side
driver propagation delay VOUT
= 0, Vboot
= VCC
,
VIN
= 0 to 3.3 V 50 125 200
ns
t
isd
Comparator triggering to high /
low side driver turn-off
propagation delay
Measured applying a voltage
step from 0 V to 3.3 V to pin
CIN 50 200 250
Table 12. Truth table
Condition Logic input (V
I
) Output
SD/OD LIN HIN LVG HVG
Shutdown enable
half-brid ge tri-s tate LXXLL
Interlocking
half-brid ge tri-s tate HLHLL
0 ‘’logic state”
half-brid ge tri-s tate HHLLL
1 “logic state”
low side direct driving HLLHL
1 “logic state”
high side direct driving HHHLH
DocID024138 Rev 7 11/20
STGIPS2 0C60 Electri cal chara ct er istics
20
3.2 Waveforms definition
Figure 7. Dead time and interlocking waveforms definition
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
DTLH DTHL
DTLH DTHL
DTLH DTHL
DTLH DTHL
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
INTERLOCKING
INTERLOCKING
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
INTERLOCKING
INTERLOCKING
G
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
Smart shutdown function STGIPS20C60
12/20 DocID024138 Rev 7
4 Smart shutdown function
The STGIPS20C60 integrates a comparator for fault sensing purposes. The comparator has
an internal voltage reference V
ref
connected to the inverting input, while the non-inverting
input, available on pin (C
IN
), can be connected to an external shunt resistor in order to
implement a simple over-current protection function. When the comparator triggers, the
device is set in shutdown state and both its outputs are set to low-level leading the
halfbridge in tri-state. In the common overcurrent protection architectures the comparator
output is usually connected to the shutdown input through a RC network, in order to provide
a mono-stable circuit, which implements a protection time that follows the fault condition.
Our smart shutdown architecture allows to immediately turn-off the output gate driver in
case of overcurrent, the fault signal has a preferential path which directly switches off the
outputs. The time delay between the fault and the outputs turn-off is no more dependent on
the RC values of the external network connected to the shutdown pin. At the same time the
DMOS connected to the open-drain output (pin SD/OD) is turned on by the internal logic
which holds it on until the shutdown voltage is lower than the logic input lower threshold
(V
il
). Finally the smart shutdown function provides the possibility to increase the real disable
time without increasing the constant time of the external RC network.
DocID024138 Rev 7 13/20
STGIPS20C60 Smart shutdown function
20
Figure 8. Smart shutdown timing waveforms
Please refer to Table 11 for internal propagation delay time details.
SD/OD
FROM/TO
CONTROLLER
V
BIAS
C
SD
RSD
SMART
SD
LOGIC
RON_OD
SHUT DOWN CIRCUIT
RPD_SD
An approximation of the disable time is given by:
where:
HIN/LIN
HVG/LVG
open drain gate
(internal)
comp Vref
CP+
PROTECTION
Fast shut down:
the driver outputs are set in SD state immediately after the comparator
triggering even if the SD signal has not yet reach the lower input threshold
disable time
SD/OD
AM12947v1
Application information STGIPS20C60
14/20 DocID024138 Rev 7
5 Application information
Figure 9. Typical application circuit
AM05001v2
Cvcc
W
Nw
LIN
SD/OD
VCC
GND
DT
OUT
HVG
Vboot
HIN
LVG
CP+
VBOOT V
P
OUT U
VBOOT U
OUT V
VBOOT W
OUT W
Rg
LIN
SD/OD
VCC
GND
DT
OUT
HVG
Vboot
HIN
LVG
CP+
LIN
SD/OD
VCC
GND
DT
OUT
HVG
Vboot
HIN
LVG
CP+
Rg
Rdt
Rg
Cdt
Rg
Rg
Rg
CONTROLLER
Cvcc
Rdt Cdt
Cvcc
R
C
Rsd
VDC
M
Csd
+
3.3V/5V Line
Cbu
Cbv
Cbw
VCC
Rshunt
GND
HIN-U
LIN-U
SD/OD
HIN-W
LIN-V
HIN-V
LIN-W
CIN
VCC
Nu
Nv
T1
T2
T3
T4
T5
Rdt
T6
V
U
Cdt
D1
D2
D3
D4
D5
D6
DocID024138 Rev 7 15/20
STGIPS20C60 Application information
20
5.1 Recommendations
•Input signal HIN is active high logic. A 85 kΩ (typ.) pull down resistor is built-in for each
high side input. If an external RC filter is used, for noise immunity, pay attention to the
variation of the input signal level.
•Input signal LIN is active low logic. A 720 kΩ (typ.) pull-up resistor, connected to an
internal 5 V regulator through a diode, is built-in for each low side input.
•To prevent the input signals oscillation, the wiring of each input should be as short as
possible.
•By integrating an application specific type HVIC inside the module, direct coupling to MCU
terminals without any opto-coupler is possible.
•Each capacitor should be located as nearby the pins of IPM as possible.
•Low inductance shunt resistors should be used for phase leg current sensing.
•Electrolytic bus capacitors should be mounted as close to the module bus terminals as
possible. Additional high frequency ceramic capacitor mounted close to the module pins
will further improve performance.
•The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see
Section 4: Smart shutdown function for detailed info).
Note: For further details, refer to AN3338.
Table 13. Recommended operating conditions
Symbol Parameter Conditions Value Unit
Min. Typ. Max.
V
PN
Supply Voltage Applied between P-Nu,Nv,Nw 300 400 V
V
CC
Control supply voltage Applied between V
CC
-GND 13.5 15 18 V
V
BS
High side bias voltage Applied between V
BOOTi
-OUT
i
for
i=U,V,W 13 18 V
t
dead
Blanking time to
prevent Arm-short For each input signal 1.5 µs
f
PWM
PWM input signal -40°C < T
c
< 100°C
-40°C < T
j
< 125°C 20 kHz
T
C
Case operation
temperature 100 °C
Package information STGIPS20C60
16/20 DocID024138 Rev 7
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
Please refer to dedicated technical note TN0107 for mounting instructions.
6.1 SDIP-25L package information
Figure 10. SDIP-25L package outline
B
DocID024138 Rev 7 17/20
STGIPS20C60 Package information
20
Table 14. SDIP-25L mechanical data
Dim. mm
Min. Typ. Max.
A 43.90 44.40 44.90
A1 1.15 1.35 1.55
A2 1.40 1.60 1.80
A3 38.90 39.40 39.90
B 21.50 22.00 22.50
B1 11.25 11.85 12.45
B2 24.83 25.23 25.63
C 5.00 5.40 6.00
C1 6.50 7.00 7.50
C2 11.20 11.70 12.20
C3 2.90 3.00 3.10
e 2.15 2.35 2.55
e1 3.40 3.60 3.80
e2 4.50 4.70 4.90
e3 6.30 6.50 6.70
D 33.30
D1 5.55
E11.20
E1 1.40
F 0.85 1.00 1.15
F1 0.35 0.50 0.65
R 1.55 1.75 1.95
T 0.45 0.55 0.65
V0° 6°
Package information STGIPS20C60
18/20 DocID024138 Rev 7
6.2 Packing information
Figure 11. SDIP-25L packing specification
AM10488v1
Base quantity: 11 pcs
Bulk quantity: 132 pcs
8123127_E
DocID024138 Rev 7 19/20
STGIPS20C60 Revision history
20
7 Revision history
Table 15. Document revision history
Date Revision Changes
08-Mar-2013 1Initial release
20-Mar-2013 2 Added Figure 3 and Figu re 4 on page 6 .
17-Jun-2013 3
Updated Dt value in Table 10: Logic inpu t s (VCC = 15 V unl es s
otherwis e spe ci fie d), Figure 7: Dead time and interlocking
waveforms definition and t
dead
in Table 13: Re co mm end ed
operating conditions.
09-Jul-2013 4 Updated Dt value in Table 10: Logic inpu t s (VCC = 15 V unl es s
otherwis e spe ci fie d).
16-Jul-2013 5 Updated Table 2: Pin description, Table 8: Low voltage power
supply (VCC = 15 V unless otherwise specified) and Table 9:
Bootstrapped voltage (VCC = 15 V unless otherwise specified)
14-May-2014 6 Updated Table 3: Inverter part, Table 6: Thermal data, Table 7:
Inverter part and Section 7: Packaging mechan ic al data.
Minor text changes.
20-Mar-2015 7
Minor text and formating changes.
Updated Figure 2
Section 6: Package information:
- Renamed (was Package mechanical data)
- Updated with revised package outline and mechanical data.
- Added Section 6. 2: Packin g inform at ion (was Section 7:
Packaging mechanical data)
STGIPS20C60
20/20 DocID024138 Rev 7
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) r eserve the righ t to make changes, co rrections, enhancement s , modificat i ons, and
improveme nts t o ST product s and/o r to this do cument at any time without notice. Purchasers sho uld obta in the lat est relevan t informat ion on
ST products before placing orders. ST products are sold pursua nt to ST’s terms and conditions of sale in place at t he time of order
acknowledgement.
Purchase rs are s olely r espon si ble for t he cho ic e, s elect ion, a nd use of ST produc ts and ST ass umes no l iabil ity for app licat ion assist ance or
the design of Purchase rs’ products.
No license, express or implied, to any i ntellectual property right is granted by ST herein.
Resale of ST pr oducts with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or serv ice names are the property of their respect i ve owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this doc ument.
© 2015 STMicroelectronics – All rights reserved
