DG428/429
Siliconix
S-56532—Rev. H, 19-Jan-98 1
Single 8-Ch/Differential 4-Ch Latchable Analog Multiplexersrs
Features Benefits Applications
Low rDS(on): 55
Low Charge Injection: 1 pC
On-Board TTL Compatible
Address Latches
High Speed—tTRANS: 160 ns
Break-Before-Make
Low Power Consumption: 0.3 mW
Improved System Accuracy
Microprocessor Bus Compatible
Easily Interfaced
Reduced Crosstalk
High Throughput
Improved Reliability
Data Acquisition Systems
Automatic Test Equipment
Avionics and Military Systems
Communication Systems
Microprocessor-Controlled
Analog Systems
Medical Instrumentation
Description
The DG428/DG429 analog multiplexers have on-chip
address and control latches to simplify design in
microprocessor based applications. Break-before-make
switching action protects against momentary crosstalk of
adjacent input signals.
The DG428 selects one of eight single-ended inputs to a
common output, while the DG429 selects one of four
differential inputs to a common differential output.
An on channel conducts current equally well in both
directions. In the off state each channel blocks voltages
up to the power supply rails. An enable (EN) function
allows the user to reset the multiplexer/demultiplexer to
all switches off for stacking several devices. All control
inputs, address (Ax) and enable (EN) are TTL compatible
over the full specified operating temperature range.
The silicon-gate CMOS process enables operation over a
wide range of supply voltages. The absolute maximum
voltage rating is extended to 44 V. Additionally, single
supply operation is also allowed and an epitaxial layer
prevents latchup.
On-board TTL-compatible address latches simplify the
digital interface design and reduce board space in
bus-controlled systems such as data acquisition systems,
process controls, avionics, and ATE.
Functional Block Diagrams and Pin Configurations
DG428 DG428
WR
D
RS
S8
A0A1
EN A2
V– GND
S1V+
S2S5
S3S6
S4S7
Dual-In-Line
Decoders/Drivers
1
2
3
4
5
6
7
8
18
17
16
15
14
13
12
11
Top V iew
910
Latches
PLCC
14
15
16
17
18
8
7
6
5
4
1231920
111091312
Top V iew
EN A2
V– GND
S1V+
S2S5
S3S6
4
D
NC
8
7
A
WR
NC
RS
A
Latches
Decoders/Drivers
0
1
S
S
S
Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70063.
DG428/429
2 Siliconix
S-56532—Rev. H, 19-Jan-98
Functional Block Diagrams and Pin Configurations (Cont’d)
DG429 DG429
WR
Da
RS
Db
A0A1
EN GND
V– V+
S1a S1b
S2a S2b
S3a S3b
S4a S4b
Dual-In-Line and SOIC
Decoders/Drivers
1
2
3
4
5
6
7
8
18
17
16
15
14
13
12
11
Top V iew
910
Latches EN GND
V– VDD
S1a S1b
S2a S2b
S3a S3b
PLCC
14
15
16
17
18
8
7
6
5
4
1231920
111091312
Top V iew
4a
a
NC
b
4b
A
WR
NC
RS
A
Latches
Decoders/Drivers
0
1
S
D
D
S
Truth Table — DG428
8-Channel Single-Ended Multiplexer Truth Table — DG429
Differential 4-Channel Multiplexer
A2A1A0EN WR RS On Switch A1A0EN WR RS On Switch
 
X X X X 1 Maintains previous
switch condition X X X 1 Maintains previous
switch condition
 
X X X X X 0 None (latches cleared) X X X X 0 None (latches cleared)
   
X X X 0 0 1 None X X 0 0 1 None
0 0 0 1 0 1 1 0 0 1 0 1 1
0 0 1 1 0 1 2 0 1 1 0 1 2
0 1 0 1 0 1 3 1 0 1 0 1 3
0 1 1 1 0 1 4 1 1 1 0 1 4
100101 5
L i “0” V 08V
101101 6 Logic “0” = VAL 0.8 V
Logic
“
1
”
=V
AH 24V
110101 7
L
og
i
c
“1”
=
V
AH
2
.
4
V
X = Don’t Care
111101 8
X
=
Don t
Care
Ordering Information — DG428 Ordering Information — DG429
Temp Range Package Part Number Temp Range Package Part Number
18-Pin Plastic DIP DG428DJ 18-Pin Plastic DIP DG429DJ
–40 to 85_C
20
-
Pin PLCC
DG428DN
–40 to 85_C20-Pin PLCC DG429DN
20
-
Pi
n
PLCC
DG428DN
18-Pin Widebody SOIC DG429DW
–
55 to 125
_
C
18
-
Pin CerDIP
DG428AK –
55 to 125
_
C
18
-
Pin CerDIP
DG429AK
–
55
t
o
125_C
18
-
Pi
n
C
er
DIP
DG428AK/883 –
55
t
o
125_C
18
-
Pi
n
C
er
DIP
DG429AK/883
DG428/429
Siliconix
S-56532—Rev. H, 19-Jan-98 3
Absolute Maximum Ratings
Voltage Referenced to V–
V+ 44 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GND 25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Inputsa, VS, VD(V–) –2 V to (V+) +2 V or. . . . . . . . . . . . . . .
30 mA, whichever occurs first
Current (Any Terminal) 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) 100 mA. . . . . . . . . . . . . . . . . .
Storage Temperature (AK Suffix) –65 to 150_C. . . . . . . . . . . .
(DJ, DN Suffix) –65 to 125_C. . . . . . . . .
Power Dissipation (Package)b
18-Pin Plastic DIPc470 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18-Pin CerDIPd900 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-Pin PLCCe800 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-Pin Widebody SOIC 450 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
a. Signals on SX, DX or INX exceeding V+ or V– will be clamped by
internal diodes. Limit forward diode current to maximum current
ratings.
b. All leads soldered or welded to PC board.
c. Derate 6.3 mW/_C above 75_C.
d. Derate 12 mW/_C above 75_C.
e. Derate 10 mW/_C above 75_C.
Specificationsa
Test Conditions
Unless Otherwise Specified A Suffix
–55 to 125_CD Suffix
–40 to 85_C
Parameter Symbol V+ = 15 V, V– = –15 V, WR = 0, RS
= 2.4 V, VIN = 2.4 V, 0.8 VfTempbTypcMindMaxdMindMaxdUnit
Analog Switch
Analog Signal RangeeVANALOG Full –15 15 –15 15 V
Drain-Source
On-Resistance rDS(on) VD = "10 V, VAL = 0.8 V
IS = –1 mA, VAH = 2.4 V Room
Full 55 100
125 100
125 W
Greatest Change in
rDS(on) Between
ChannelsgDrDS(on) –10 V < VS < 10 V
IS = –1 mA Room 5 %
Source Off
Leakage Current IS(off) VS = "10 V, VD = #10 V
VEN = 0 V Room
Full "0.03 –0.5
–50 0.5
50 –0.5
–50 0.5
50
Drain Off
Lk C
ID(off)
VD = "10 V
VS=#10 V
DG428 Room
Full "0.07 –1
–100 1
100 –1
–100 1
100
Leakage Current
I
D(off)
V
S =
#10
V
VEN = 0 V DG429 Room
Full "0.05 –1
–50 1
50 –1
–50 1
50 nA
Drain On
Lk C
ID(on)
VS = VD = "10 V
VEN = 2.4 V DG428 Room
Full "0.07 –1
–100 1
100 –1
–100 1
100
Leakage Current
I
D(on)
EN
VAL = 0.8 V
VAH = 2.4 V DG429 Room
Full "0.05 –1
–50 1
50 –1
–50 1
50
Digital Control
Logic Input Current
ItVltHih
IAH
VA = 2.4 V Full 0.01 1 1
gp
Input Voltage High
I
AH VA = 15 V Full 0.01 1 1 mA
Logic Input Current
Input Voltage Low IAL VEN = 0 V, 2.4 V, VA = 0 V
RS = 0 V, WR = 0 V Full –0.01 –1 –1
mA
Logic Input Capacitance Cin f = 1 MHz Room 8 pF
Dynamic Characteristics
Transition Time tTRANS See Figure 5 Room
Full 150 250
300 250
300
Break-Before-Make
Interval tOPEN See Figure 4 Full 30 10 10
ns
Enable and Write
Turn-On Time tON(EN,WR) See Figures 6 and 7 Room
Full 90 150
225 150
225
ns
Enable and Reset
Turn-Off Time tOFF(EN,RS) See Figures 6 and 8 Room
Full 55 150
300 150
300
Charge Injection Q VGEN = 0 V, RGEN = 0 W
CL = 1 nF, See Figure 9 Room 1 pC
DG428/429
4 Siliconix
S-56532—Rev. H, 19-Jan-98
Specificationsa (Cont’d)
Test Conditions
Unless Otherwise Specified A Suffix
–55 to 125_CD Suffix
–40 to 85_C
Parameter Symbol V+ = 15 V, V– = –15 V, WR = 0, RS
= 2.4 V, VIN = 2.4 V, 0.8 VfTempbTypcMindMaxdMindMaxdUnit
Dynamic Characteristics (Cont’d)
Off Isolation OIRR VEN = 0 V, RL = 300 W, CL = 15 pF
VS = 7 VRMS, f = 100 kHz Room –75 dB
Source Off Capacitance CS(off) VS = 0 V, VEN = 0 V, f = 1 MHz Room 11
Drain Off Capacitance
CD(off)
DG428 Room 40
D
ra
i
n
Off
C
apac
it
ance
C
D(off) VD = 0 V, VEN = 0 V
f1MH
DG429 Room 20 pF
Drain On Capacitance
CD(on)
D,EN
f = 1 MHz DG428 Room 54
p
D
ra
i
n
O
n
C
apac
it
ance
C
D(on) DG429 Room 34
Minimum Input Timing Requirements
Write Pulse Width tWFull 100 100
AX, EN Data Set Up
time tSSee Figure 2 Full 100 100 ns
AX, EN Data Hold Time tHFull 10 10
Reset Pulse Width tRS VS = 5 V, See Figure 3 Full 100 100
Power Supplies
Positive Supply Current I+ Room 20 100 100
A
Negative Supply
Current I– VEN = 0 V, VA = 0, RS = 5 V Room –0.001 –5 –5 mA
Specificationsa for Single Supply
Test Conditions
Unless Otherwise Specified A Suffix
–55 to 125_CD Suffix
–40 to 85_C
Parameter Symbol V+ = 12 V, V– = 0 V, WR = 0
RS = 2.4 V, VIN = 2.4 V, 0.8 VfTempbTypcMindMaxdMindMaxdUnit
Analog Switch
Analog Signal RangeeVANALOG Full 0 12 0 12 V
Drain-Source
On-Resistance rDS(on) VD = +10 V, VAL = 0.8 V
IS = –500 mA, VAH = 2.4 V Room 80 150 150 W
rDS(on) MatchgDrDS(on) 0 V < VS < 10 V
IS = –1 mA Room 5 %
Source Off
Leakage Current IS(off) VS = 0 V, 10 V, VD = 10 V, 0 V
VEN = 0 V Room
Full 0.03 –0.5
–50 0.5
50 –0.5
–50 0.5
50
Drain Off
ID(off)
VD = 0 V, 10 V
VS=10V0V
DG428 Room
Full 0.07 –1
–100 1
100 –1
–100 1
100
Leakage Current
I
D(off)
V
S =
10
V
,
0
V
VEN = 0 V DG429 Room
Full 0.05 –1
–50 1
50 –1
–50 1
50 nA
Drain On
ID(on)
VS = VD = 0 V, 10 V
VEN = 2.4 V DG428 Room
Full 0.07 –1
–100 1
100 –1
–100 1
100
Leakage Current
I
D(on)
EN
VAL = 0.8 V
VAH = 2.4 V DG429 Room
Full 0.05 –1
–50 1
50 –1
–50 1
50
Digital Control
Logic Input Current
IAH
VA = 2.4 V Full 1 1
Input Voltage High
I
AH VA = 12 V Full 1 1 mA
Logic Input Current
Input Voltage Low IAL VEN = 0 V, 2.4 V, VA = 0 V
RS = 0 V, WR = 0 V Full –1 –1
mA
DG428/429
Siliconix
S-56532—Rev. H, 19-Jan-98 5
Specificationsa for Single Supply (Cont’d)
Test Conditions
Unless Otherwise Specified A Suffix
–55 to 125_CD Suffix
–40 to 85_C
Parameter Symbol V+ = 12 V, V– = 0 V, WR = 0
RS = 2.4 V, VIN = 2.4 V, 0.8 VfTempbTypcMindMaxdMindMaxdUnit
Dynamic Characteristics
Transition Time tTRANS S1 = 10 V/2 V, S8 = 2 V/ 10 V
See Figure 5 Room
Full 160 280
350 280
350
Break-Before-Make
Interval tOPEN See Figure 4 Room
Full 40 25
10 25
10
ns
Enable and Write
Turn-On Time tON(EN,
WR)
S1 =5 V
See Figures 6 and 7 Room
Full 110 300
400 300
400
ns
Enable and Reset
Turn-Off Time tOFF(EN,
RS)
S1 =5 V
See Figures 6 and 8 Room
Full 70 300
400 300
400
Charge Injection Q VGEN = 6 V, RGEN = 0 W
CL = 1 nF, See Figure 9 Room 4 pC
Off Isolation OIRR VEN = 0 V, RL = 300 W, CL = 15 pF
VS = 7 VRMS, f = 100 kHz Room –75 dB
Minimum Input Timing Requirements
Write Pulse Width tWFull 100 100
AX, EN
Data Set Up Time tSSee Figure 2 Full 100 100
ns
AX, EN
Data Hold Time tHFull 10 10
ns
Reset Pulse Width tRS VS = 5 V, See Figure 3 Full 100 100
Power Supplies
Positive Supply Current I+ VEN = 0 V, VA = 0, RS = 5 V Room 20 100 100 mA
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. D+ǒ*
 Ǔ
 
DG428/429
6 Siliconix
S-56532—Rev. H, 19-Jan-98
Typical Characteristics
0
20
40
60
80
100
120
140
–20 –16 –12 –8 –4 0 4 8 12 16 20
VD – Drain Voltage (V)
rDS(on) vs. VD and Supply Voltage
5 V
8 V
20 V
15 V
12 V
10 V
–15 –10 –5 0 5 10 15
0
10
20
30
40
50
60
70
80
90
100
rDS(on) – Drain-Source On-Resistance (
125_C
85_C
25_C
–40_C
–55_C
V+ = 15 V
V– = –15 V
rDS vs. VD and Temperature
rDS(on) – Drain-Source On-Resistance (
VD – Drain Voltage (V)
0 4 8 12 16 20
0
40
80
120
160
200
VD – Drain Voltage (V)
V– = 0 V
V+ = 7.5 V
10 V
12 V
15 V 20 V
rDS(on) – Drain-Source On-Resistance (
Single Supply rDS(on) vs. VD and Supply
–15 –10 –5 0 5 10 15
–30
–20
–10
0
10
20
30
40
IS(off)
V+ = 15 V
V– = –15 V
VS = –VD for ID(off)
VD = VS for ID(on)
ID, IS Leakage Currents vs. Analog Voltage
VS,VD – Source, Drain Voltage (V)
ID(on), ID(off)
– Current (pA)I , I
SD
–55 5 25 45 65 85 105 125
1 pA
10 pA
100 pA
1 nA
10 nA
IS (off)
ID(on), ID(off)
V+ = 15 V
V– = –15 V
VS, VD = 14 V
ID, IS Leakages vs. Temperature
Temperature (C_)
– Leakage CurrentI , I
SD
0
50
100
150
200
250
510 15 20
tTRANS
tON(EN)
tOFF(EN)
Supply Voltage (V)
Time (ns)
Switching Times vs. Power Supply Voltage
–35 –15
DG428/429
Siliconix
S-56532—Rev. H, 19-Jan-98 7
Typical Characteristics (Cont’d)
0
50
100
150
200
250
300
350
5 10 15 20
tTRANS
V– = 0 V
Switching Times vs. Single Supply
Time (ms)
tON
tOFF
–15 –10 –5 0 5 10 15
–60
–40
–20
0
20
40
60
Charge Injection vs. Analog Voltage
VS – Source Voltage (V)
Q – Charge (pC)
V+ = 12 V
V– = 0 V
1 k 10 k 100 k 1 M 10 M
–20
–40
–60
–80
–100
–120
–140 Off-Isolation vs. Frequency
OIRR (dB)
1 k 10 k 100 k 1 M 10 M
–8
–6
–4
–2
0
2
4
6
8
I–
I+
IGND
EN = 5 V
AX = 0 or 5 V
Supply Current vs. Switching Frequency
Supply Current (ma)
f – Frequency (Hz) f – Frequency (Hz)
0
50
100
150
200
–55 –35 45 85 125 0
0.5
1
1.5
2
2.5
3
0 ”5 ”10 ”15 ”20
tTRANS
V+ = 15 V
V– = –15 V
Switching Times vs. Temperature
Temperature (C_)
Time (nS)
Input Switching Threshold vs. Supply Voltage
V (V)
VSUPPLY – Supply Voltage (V)
tOFF
tON
–15 5 65 105
25
V+ = 15 V
V– = –15 V
in
V+ – Positive Supply (V)
DG428/429
8 Siliconix
S-56532—Rev. H, 19-Jan-98
Schematic Diagram (Typical Channel)
Figure 1.
S1
EN
D
V+
Sn
V–
Decode/
Drive
Level
Shift
V+
Latches
VREF
V+
V–
DO
Dn
CLK
RESET
QO
Qn
AX
WR
RS
GND
V–
Timing Diagrams
Figure 2. Figure 3.
3 V
0 V
3 V
0 V
50%
20% 80%
EN
3 V
0 V
0 V
50%
tWtH
WR RS
A0, A1, (A2)
VO
Switch
Output
tRS tOFF(RS)
tS
80%
Test Circuits
Figure 4. Break-Before-Make
DG428
DG429
EN
V+
GND V–
+5 V
35 pF
–15 V
+15 V
+2.4 V RS
A0, A1, (A2)D
b
, D
All S and Da
WR
300
VO
50
Logic
Input
Switch
Output
VO
VS
tOPEN
tr <20 ns
tf <20 ns
3 V
0 V 50%
80%
0 V
DG428/429
Siliconix
S-56532—Rev. H, 19-Jan-98 9
Test Circuits (Cont’d)
DG428
DG429
Figure 5. Transition Time
S1b
S1a – S4a, Da
S2b and S3b
Db
RS
A0
A1
50
WR
300
VO
#10 V
#10 V
S4b
EN
V+
GND V–
35 pF
–15 V
+15 V
+2.4 V
RS S1
S2 – S7
A0
A1
A2
50
WR
300
VO
S8
"10 V
#10 V
EN
V+
GND V– D
35 pF
–15 V
+15 V
+2.4 V
3 V
0 V
Logic
Input
Switch
Output
VS8
VO
tTRANS
tr <20 ns
tf <20 ns
S8 ONS1 ON tTRANS
0 V
VS1
50%
10%
90%
Figure 6. Enable tON/tOFF T ime
DG428
DG429
RS
EN
+2.4 V S1
S2 – S8
A0
A1
A2
50
WR
300
VO
V+
GND V– D
– 5 V
35 pF
–15 V
+15 V
S1b
S1a – S4a, Da
S2b – S4b
RS
Db
A0
A1
50
WR
300
VO
EN
+2.4 V V+
GND V–
– 5 V
35 pF
–15 V
+15 V
Logic
Input
Switch
Output
VO
tr <20 ns
tf <20 ns
3 V
0 V
0 V
tOFF(EN)
tON(EN)
50%
90%
VO
DG428/429
10 Siliconix
S-56532—Rev. H, 19-Jan-98
Test Circuits (Cont’d)
Figure 7. Write Turn-On Time tON(WR)
3 V
0 V
0 V 50%
DG428
DG429
WR
Switch
Output
VO
20%
tON(WR)
A0, A1, (A2)
Db, D
EN
WR
300 W
Remaining
Switches
S1 or S1b
VO
RS
V+
GND V–
+5 V
35 pF
–15 V
+15 V
+2.4 V
Figure 8. Reset Turn-Off Time tOFF(RS)
Figure 9. Charge Injection
3 V
0 V
0 V 50%
DG42
DG429
RS
Switch
Output
VO80%
tOFF(RS)
EN
VO
DVO
DVO is the measured voltage error due to
charge injection. The charge in coulombs is
Q = CL x DVO
OFF OFFON
RS VO
EN
Remaining
Switches
WR
S1 or S1b
Db, D
A0, A1, (A2)
300 W
V+
GND V–
+5 V
35 pF
–15 V
+15 V
+2.4 V
CL
1 nF
IN
DVO
2.4 V
RS
A0, A1, (A2)
WR V–
V+
S
3 V
Vg
Rg
–15 V
GND
+15 V
DG428/429
Siliconix
S-56532—Rev. H, 19-Jan-98 11
Detailed Description
The internal structure of the DG428/DG429 includes a
5-V logic interface with input protection circuitry
followed by a latch, level shifter, decoder and finally the
switch constructed with parallel n- and p-channel
MOSFETs (see Figure 1).
The input protection on the logic lines A0, A1, A2, EN and
control lines WR, RS shown in Figure 1 minimizes
susceptibility to ESD that may be encountered during
handling and operational transients.
The logic interface is a CMOS logic input with its supply
voltage from an internal +5 V reference voltage. The
output of the input inverter feeds the data input of a D type
latch. The level sensitive D latch continuously places the
DX input signal on the QX output when the WR input is
low, resulting in transparent latch operation. As soon as
WR returns high the latch holds the data last present on
the Dn input, subject to the “Minimum Input Timing
Requirements” table.
Following the latches the Qn signals are level shifted and
decoded to provide proper drive levels for the CMOS
switches. This level shifting ensures full on/off switch
operation for any analog signal level between the V+ and
V– supply rails.
The EN pin is used to enable the address latches during
the WR pulse. It can be hard wired to the logic supply or
to V+ if one of the channels will always be used (except
during a reset) or it can be tied to address decoding
circuitry for memory mapped operation. The RS pin is
used as a master reset. All latches are cleared regardless
of the state of any other latch or control line. The WR pin
is used to transfer the state of the address control lines to
their latches, except during a reset or when EN is low (see
Truth Tables).
Applications
Bus Interfacing
The DG428/DG429 minimize the amount of interface
hardware between a microprocessor system bus and the
analog system being controlled or measured. The internal
TTL compatible latches give these multiplexers write-only
memory, that is, they can be programmed to stay in a
particular switch state (e.g., switch 1 on) until the
microprocessor determines it is necessary to turn different
switches on or turn all switches off (see Figure 10).
The input latches become transparent when WR is held
low; therefore, these multiplexers operate by direct
command of the coded switch state on A2, A1, A0. In this
mode the DG428 is identical to the popular DG408. The
same is true of the DG429 versus the popular DG409.
During system power-up, RS would be low, maintaining
all eight switches in the off state. After RS returned high
the DG428 maintains all switches in the off state.
When the system program performs a write operation to
the address assigned to the DG428, the address decoder
provides a CS active low signal which is gated with the
WRITE (WR) control signal. At this time the data on the
DATA BUS (that will determine which switch to close) is
stabilizing. When the WR signal returns to the high state,
(positive edge) the input latches of the DG428 save the
data from the DATA BUS. The coded information in the
A0, A1, A2 and EN latches is decoded and the appropriate
switch is turned on.
The EN latch allows all switches to be turned off under
program control. This becomes useful when two or more
DG428s are cascaded to build 16-line and larger
multiplexers.
DG428/429
12 Siliconix
S-56532—Rev. H, 19-Jan-98
Applications (Cont’d)
Data Bus
RESET
Address
Decoder
Address
Bus
+5 V
V+
V– D
+15 V
– 15 V
DG428
Processor
System
Bus
±15 V
Analog
Inputs
Analog
Output
WR
RS
S1
S8
A0, A1, A2, EN
WRITE
Figure 10. Bus Interface