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DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
DDR3 SDRAM Specification
240pin Unbuffered DIMM based on 1Gb F-die
64-bit Non-ECC
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
* Samsung Electronics reserves the right to change products or specification without notice.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
2 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
1.0 DDR3 Registered DIMM Ordering Information ..........................................................................5
2.0 Key Features ................................................................................................................................5
3.0 Address Configuration ................................................................................................................5
4.0 x64 DIMM Pin Configurations (Front side/Back side) ..............................................................6
5.0 x72 DIMM Pin Configurations (Front side/Back side) ..............................................................7
6.0 Pin Description ...........................................................................................................................8
7.0 SPD and Thermal Sensor for ECC UDIMMs ..............................................................................8
8.0 Input/Output Functional Description .........................................................................................9
8.1 Address Mirroring Feature ...........................................................................................................10
8.1.1 DRAM Pin Wiring Mirroring ...................................................................................................10
9.0 Function Block Diagram: ..........................................................................................................11
9.1 1GB, 128Mx64 Non ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs) .....................................11
9.2 1GB, 128Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ...................................................12
9.3 2GB, 256Mx64 Non ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ....................................13
9.4 2GB, 256Mx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAM) ............................................14
10.0 Absolute Maximum Ratings ....................................................................................................15
10.1 Absolute Maximum DC Ratings ..................................................................................................15
10.2 DRAM Component Operating Temperature Range ........................................................................15
11.0 AC & DC Operating Conditions ..............................................................................................15
11.1 Recommended DC Operating Conditions (SSTL - 15) ....................................................................15
12.0 AC & DC Input Measurement Levels ......................................................................................16
12.1 AC & DC Logic Input Levels for Single-ended Signals ...................................................................16
12.2 VREF Tolerances .......................................................................................................................17
12.3 AC & DC Logic Input Levels for Differential Signals ......................................................................18
12.3.1 Differential Signals Definition ..............................................................................................18
12.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................18
12.3.3 Single-ended Requirements for Differential Signals ...............................................................19
12.3.4 Differential Input Cross Point Voltage ...................................................................................20
12.4 Slew Rate Definition for Single-ended Input Signals ......................................................................20
12.5 Slew Rate Definition for Differential Input Signals .........................................................................20
13.0 AC & DC Output Measurement Levels ...................................................................................21
13.1 Single-ended AC & DC Output Levels ..........................................................................................21
13.2 Differential AC & DC Output Levels .............................................................................................21
13.3 Single-ended Output Slew Rate ..................................................................................................21
13.4 DIfferential Output Slew Rate ....................................................................................................22
14.0 IDD Specification Definition ....................................................................................................23
14.1 IDD SPEC Table ........................................................................................................................25
Table Contents
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DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
15.0 Input/Output Capacitance .......................................................................................................27
15.1 Non ECC UDIMM - 1GB(128Mx64) Module ....................................................................................27
15.2 ECC UDIMM - 1GB(128Mx74) Module ...........................................................................................27
15.3 Non ECC UDIMM - 2GB(256Mx64) Module ....................................................................................27
15.4 ECC UDIMM - 2GB(256Mx72) Module ...........................................................................................27
16.0 Electrical Characteristics and AC timing ..............................................................................28
16.1 Refresh Parameters by Device Density ........................................................................................28
16.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin .............................................28
16.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ..............................................28
16.3.1 Speed Bin Table Notes .......................................................................................................31
17.0 Timing Parameters by Speed Grade ......................................................................................32
17.1 Jitter Notes ..............................................................................................................................35
17.2 Timing Parameter Notes ............................................................................................................36
18.0 Physical Dimensions ...............................................................................................................37
18.1 128Mbx8 based 128Mx64/x72 Module (1 Rank) .............................................................................37
18.2 128Mbx8 based 256Mx64/x72 Module (2 Ranks) ...........................................................................38
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DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
Revision History
Revision Month Year History
0.9 September 2009 - Initial Release
5 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
1.0 DDR3 Registered DIMM Ordering Information
Note :
- "##" - F8/H9/K0
- F8 - 1066Mbps 7-7-7 & H9 - 1333Mbps 9-9-9 & K0 - 1600Mbps 11-11-11
2.0 Key Features
• JEDEC standard 1.5V ± 0.075V Power Supply
•V
DDQ = 1.5V ± 0.075V
• 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 6,7,8,9,10, 11
• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 6 (DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C
• Asynchronous Reset
3.0 Address Configuration
Part Number Density Organization Component Composition Number of
Rank Height
M378B2873FHS-CF8/H9/K0 1GB 128Mx64 128Mx8(K4B1G0846F-HC##)*8 1 30mm
M378B5673FH0-CF8/H9/K0 2GB 256Mx64 256Mx8(K4B1G0846F-HC##)*16 2 30mm
Speed DDR3-1066 DDR3-1333 DDR3-1600 Unit
7-7-7 9-9-9 11-11-11
tCK(min) 1.875 1.5 1.25 ns
CAS Latency 7911tCK
tRCD(min) 13.125 13.5 13.75 ns
tRP(min) 13.125 13.5 13.75 ns
tRAS(min) 37.5 36 35 ns
tRC(min) 50.625 49.5 48.75 ns
Organization Row Address Column Address Bank Address Auto Precharge
128x8(1Gb) based Module A0-A13 A0-A9 BA0-BA2 A10/AP
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DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
4.0 x64 DIMM Pin Configurations (Front side/Back side)
NC = No Connect; NF = No Function; NU = Not Usable; RFU = Reserved Future Use
1. S1, ODT1, CKE1: Used for dual-rank UDIMMs; NC on single-rank UDIMMs
2. CK1,NC2 and CK1,NC2 : Used for dual-rank UDIMMs; not used on single-rank UDIMMs, but terminated
3. TEST (pin 167) used by memory bus analysis tools (unused on memory DIMMs)
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
1VREFDQ 121 VSS 42 NC 162 NC 82 DQ33 202 VSS
2VSS 122 DQ4 43 NC 163 VSS 83 VSS 203 DM4
3 DQ0 123 DQ5 44 VSS 164 NC 84 DQS4 204 NC
4 DQ1 124 VSS 45 NC 165 NC 85 DQS4 205 VSS
5VSS 125 DM0 46 NC 166 VSS 86 VSS 206 DQ38
6DQS
0 126 NC 47 VSS 167 NC (TEST)387 DQ34 207 DQ39
7 DQS0 127 VSS 48 NC 168 Reset 88 DQ35 208 VSS
8VSS 128 DQ6 KEY 89 VSS 209 DQ44
9 DQ2 129 DQ7 49 NC 169 CKE1,NC190 DQ40 210 DQ45
10 DQ3 130 VSS 50 CKE0 170 VDD 91 DQ41 211 VSS
11 VSS 131 DQ12 51 VDD 171 NC 92 VSS 212 DM5
12 DQ8 132 DQ13 52 BA2 172 A14 93 DQS5 213 NC
13 DQ9 133 VSS 53 NC 173 VDD 94 DQS5 214 VSS
14 VSS 134 DM1 54 VDD 174 A12/BC 95 VSS 215 DQ46
15 DQS1 135 NC 55 A11 175 A9 96 DQ42 216 DQ47
16 DQS1 136 VSS 56 A7 176 VDD 97 DQ43 217 VSS
17 VSS 137 DQ14 57 VDD 177 A8 98 VSS 218 DQ52
18 DQ10 138 DQ15 58 A5 178 A6 99 DQ48 219 DQ53
19 DQ11 139 VSS 59 A4 179 VDD 100 DQ49 220 VSS
20 VSS 140 DQ20 60 VDD 180 A3 101 VSS 221 DM6
21 DQ16 141 DQ21 61 A2 181 A1 102 DQS6 222 NC
22 DQ17 142 VSS 62 VDD 182 VDD 103 DQS6 223 VSS
23 VSS 143 DM2 63 CK1,NC2183 VDD 104 VSS 224 DQ54
24 DQS2 144 NC 64 CK1,NC2184 CK0 105 DQ50 225 DQ55
25 DQS2 145 VSS 65 VDD 185 CK0 106 DQ51 226 VSS
26 VSS 146 DQ22 66 VDD 186 VDD 107 VSS 227 DQ60
27 DQ18 147 DQ23 67 VREFCA 187 NC 108 DQ56 228 DQ61
28 DQ19 148 VSS 68 NC 188 A0 109 DQ57 229 VSS
29 VSS 149 DQ28 69 VDD 189 VDD 110 VSS 230 DM7
30 DQ24 150 DQ29 70 A10/AP 190 BA1 111 DQS7 231 NC
31 DQ25 151 VSS 71 BA0 191 VDD 112 DQS7 232 VSS
32 VSS 152 DM3 72 VDD 192 RAS 113 VSS 233 DQ62
33 DQS3 153 NC 73 WE 193 S0 114 DQ58 234 DQ63
34 DQS3 154 VSS 74 CAS 194 VDD 115 DQ59 235 VSS
35 VSS 155 DQ30 75 VDD 195 ODT0 116 VSS 236 VDDSPD
36 DQ26 156 DQ31 76 S1, NC1196 A13 117 SA0 237 SA1
37 DQ27 157 VSS 77 ODT1, NC1197 VDD 118 SCL 238 SDA
38 VSS 158 NC 78 VDD 198 NC 119 SA2 239 VSS
39 NC 159 NC 79 NC 199 VSS 120 VTT 240 VTT
40 NC 160 VSS 80 VSS 200 DQ36
41 VSS 161 NC 81 DQ32 201 DQ37
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DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
5.0 Pin Description
*The VDD and VDDQ pins are tied common to a single power-plane on these designs.
Pin Name Description Pin Name Description
A0-A14 SDRAM address bus SCL I2C serial bus clock for EEPROM
BA0-BA2 SDRAM bank select SDA I2C serial bus data line for EEPROM
RAS SDRAM row address strobe SA0-SA2 I2C serial address select for EEPROM
CAS SDRAM column address strobe VDD*SDRAM core power supply
WE SDRAM write enable VDDQ*SDRAM I/O Driver power supply
S0, S1 DIMM Rank Select Lines VREFDQ SDRAM I/O reference supply
CKE0,CKE1 SDRAM clock enable lines VREFCA SDRAM command/address reference supply
ODT0, ODT1 On-die termination control lines VSS Power supply return (ground)
DQ0 - DQ63 DIMM memory data bus VDDSPD Serial EEPROM positive power supply
CB0 - CB7 DIMM ECC check bits NC Spare Pins(no connect)
DQS0 - DQS8 SDRAM data strobes
(positive line of differential pair) TEST Used by memory bus analysis tools
(unused on memory DIMMs)
DQS0-DQS8SDRAM differential data strobes
(negative line of differential pair) RESET Set DRAMs Known State
DM0-DM8 SDRAM data masks/high data strobes
(x8-based x72 DIMMs) EVENT Reserved for optional temperature-sensing hardware
CK0, CK1 SDRAM clocks
(positive line of differential pair) VTT SDRAM I/O termination supply
CK0, CK1 SDRAM clocks
(negative line of differential pair) RFU Reserved for future use
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DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
6.0 Input/Output Functional Description
Symbol Type Function
CK0-CK1
CK0-CK1SSTL
CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive
edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of
crossing)
CKE0-CKE1 SSTL Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low
initiates the Power Down mode, or the Self-Refresh mode
S0-S1SSTL
Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the
command decoder is disabled, new command are ignored but previous operations continue. This signal provides for
external rank selection on systems with multiple ranks.
RAS, CAS, WE SSTL RAS, CAS, and WE (ALONG WITH S) define the command being entered.
ODT0-ODT1 SSTL When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assuming the function is enabled in
the Extended Mode Register Set (EMRS).
VREFDQ Supply Reference voltage for SSTL 15 I/O inputs.
VREFCA Supply Reference voltage for SSTL 15 command/address inputs.
VDDQ Supply Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered
DIMM designs, VDDQ shares the same power plane as VDD pins.
BA0-BA2 SSTL Selects which SDRAM bank of eight is activated.
A0-A13 SSTL
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the column address, In addition to the column address,
AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a pre-
charge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used
to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop
(on-the-fly) will be performed (HIGH, no burst chop; Low, burst chopped).
DQ0-DQ63
CB0-CB7 SSTL Data and Check Bit Input/Output pins.
DM0-DM8 SSTL
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data
during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches
the DQ and DQS loading.
VDD,VSS Supply Power and ground for DDR3 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on
these modules.
DQS0-DQS8
DQS0-DQS8SSTL Data strobe for input and output data. For raw cards using x16 organized DRAMs, Pins DQ0-7 are associated with the
LDQS and LDQS pins and Pins DQ8-15 are associated with UDQS and UDQS pins.
SA0-SA2 - These signals and tied at the system planar to either VSS or VDDSPD to configure the serial SPD EERPOM address
range.
SDA - This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected
from the SDA bus line to VDDSPD to act as a pull-up on the system board.
SCL - This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL
bus time to VDDSPD to act as a pull-up on the system board.
VDDSPD Supply Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable
from 3.0V to 3.6V.
RESET - The RESET pin is connected to the RESET pin on each DRAM. When low, all DRAMs are set to a know state.
EVENT Output This signal indicates that a thermal event has been detected in the thermal sensing device. The system should guaran-
tee the electrical level requirement is met for the EVENT pin on TS/SPD part
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DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
6.1 Address Mirroring Feature
There is a via grid located under the DRAMs for wiring the CA signals (address, bank address, command, and control lines) to the DRAM pins. The length
of the traces from the vias to the DRAMs places limitations on the bandwidth of the module. The shorter these traces, the higher the bandwidth. To extend
the bandwidth of the CA bus for DDR3 modules, a scheme was defined to reduce the length of these traces.
The pins on the DRAM are defined in a manner that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical
support pins, do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are address pins A3, A4, A5,
A6, A7, A8 and bank address pins BA0 and BA1. Refer to Table . Rank 0 DRAM pins are wired straight, with no mismatch between the connector pin
assignment and the DRAM pin assignment. Some of the Rank 1 DRAM pins are cross wired as defined in the table. Pins not listed in the table are wired
straight.
6.1.1 DRAM Pin Wiring Mirroring
Figure 1 illustrates the wiring in both the mirrored and non-mirrored case. The lengths of the traces to the DRAM pins, is obviously shorter. The via grid is smaller as well.
Figure 1. Wiring Differences for Mirrored and Non-Mirrored Addresses
Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limi-
tations however. When writing to the internal registers with a "load mode" operation, the specific address is required. This requires the controller to know
if the rank is mirrored or not. This requires a few rules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a
requirement that the second rank be mirrored. There is a bit assignment in the SPD that indicates whether the module has been designed with the mir-
rored feature or not. See the DDR3 UDIMM SPD specification for these details. The controller must read the SPD and have the capability of de-mirroring
the address when accessing the second rank.
Connector Pin DRAM Pin
Rank 0 Rank 1
A3 A3 A4
A4 A4 A3
A5 A5 A6
A6 A6 A5
A7 A7 A8
A8 A8 A7
BA0 BA0 BA1
BA1 BA1 BA0
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DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
7.0 Function Block Diagram:
7.1 1GB, 128Mx64 Non ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs)
S0
DQS0
DQS0
DM0
DM CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
DQS1
DQS1
DM1
DM CS DQS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
DQS2
DQS2
DM2
DM CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
DQS3
DQS3
DM3
DM NU/ CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
DQS4
DQS4
DM4
DM CS DQS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DQS5
DQS5
DM5
DM CS DQS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQS6
DQS6
DM6
DM CS DQS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DQS7
DQS7
DM7
DM CS DQS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
Note :
1. DQ-to-I/O wiring is shown as recommended but may be
changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DM, DQS/DQS resistors: Refer to associated
topology diagram.
4. Refer to the appropriate clock wiring topology under the
DIMM wiring details section of this document.
5. Refer to section 7.1 of this document for details on
address mirroring.
6. For each DRAM, a unique ZQ resistor is connected to
ground. The ZQ resistor is 240 Ohm +/- 1%
7. One SPD exists per module.
VSS
D0 - D7
VDD/VDDQ D0 - D7
D0 - D7
VREFDQ
VDDSPD SPD
A0 - A13 A0-A13 : SDRAMs D0 - D7
RAS RAS : SDRAMs D0 - D7
CAS CAS : SDRAMs D0 - D7
WE WE : SDRAMs D0 - D7
CKE0 CKE : SDRAMs D0 - D7
BA0 - BA2 BA0-BA2 : SDRAMs D0 - D7
ODT0 ODT : SDRAMs D0 - D7
VREFCA
D0 - D7
CK0 CK : SDRAMs D0 - D7
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL
SDA
WP
11 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
7.2 2GB, 256Mx64 Non ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
S0
DQS0
DQS0
DM0
DM CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
DQS1
DQS1
DM1
DM CS DQS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
DQS2
DQS2
DM2
DM CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
DQS3
DQS3
DM3
DM CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
DQS4
DQS4
DM4
DM CS DQS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DQS5
DQS5
DM5
DM CS DQS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQS6
DQS6
DM6
DM CS DQS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DQS7
DQS7
DM7
DM CS DQS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D9
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D10
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D11
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D12
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D13
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D14
DM CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D15
S1
VSS
D0 - D15
VDD/VDDQ D0 - D15
D0 - D15
VREFDQ
VDDSPD SPD
A0 - A15 A0-A15 : SDRAMs D0 - D15
RAS RAS : SDRAMs D0 - D15
CAS CAS : SDRAMs D0 - D15
WE WE : SDRAMs D0 - D15
CKE0 CKE : SDRAMs D0 - D7
BA0 - BA2 BA0-BA2 : SDRAMs D0 - D15
ODT0 ODT : SDRAMs D0 - D7
VREFCA
D0 - D15
ODT1 ODT : SDRAMs D8 - D15
CK0 CK : SDRAMs D0 - D7
CK1 CK : SDRAMs D8 - D15
CKE1 CKE : SDRAMs D8 - D15
Note :
1. DQ-to-I/O wiring is shown as recommended but may be
changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DM, DQS/DQS resistors: Refer to associated
topology diagram.
4. Refer to section 7.1 of this document for details on
address mirroring.
5. For each DRAM, a unique ZQ resistor is connected to
ground. The ZQ resistor is 240 Ohm +/- 1%
6. One SPD exists per module.
ZQZQ ZQZQ
ZQZQ ZQZQ
ZQZQ ZQZQ
ZQZQ ZQZQ
A0
Serial PD
A1 A2
SA0 SA1 SA2
SCL
SDA
WP
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8.0 Absolute Maximum Ratings
8.1 Absolute Maximum DC Ratings
Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than
500mV; VREF may be equal to or less than 300mV.
8.2 DRAM Component Operating Temperature Range
Note :
1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the
JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case tem-
perature must be maintained between 0-85°C under all operating conditions
3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaran-
teed in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. It is also possible to specify a component
with 1X refresh (tREFI to 7.8us) in the Extended Temperature Range.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with
Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode
(MR2 A6 = 1b and MR2 A7 = 0b)
9.0 AC & DC Operating Conditions
9.1 Recommended DC Operating Conditions (SSTL - 15)
Note :
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
Symbol Parameter Rating Units Notes
VDD Voltage on VDD pin relative to VSS -0.4 V ~ 1.975 V V 1,3
VDDQ Voltage on VDDQ pin relative to VSS -0.4 V ~ 1.975 V V 1,3
VIN, VOUT Voltage on any pin relative to VSS -0.4 V ~ 1.975 V V 1
TSTG Storage Temperature -55 to +100 °C 1, 2
Symbol Parameter rating Unit Notes
TOPER Operating Temperature Range 0 to 95 °C 1, 2, 3
Symbol Parameter Rating Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.425 1.5 1.575 V 1,2
VDDQ Supply Voltage for Output 1.425 1.5 1.575 V 1,2
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10.0 AC & DC Input Measurement Levels
10.1 AC & DC Logic Input Levels for Single-ended Signals
Single Ended AC and DC input levels for Command and Address
Note :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See "Overshoot and Undershoot specifications" section.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
Single Ended AC and DC input levels for DQ and DM
Note :
1. For input only pins except RESET, VREF = VREFDQ(DC)
2. See 9.6 "Overshoot and Undershoot specifications" section.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
5. Single ended swing requirement for DQS - DQS is 350mV (peak to peak). Differential swing for DQS - DQS is 700mV (peak to peak).
Symbol Parameter DDR3-1066 DDR3-1333/1600 Unit Notes
Min. Max. Min. Max.
VIH.CA(DC) DC input logic high VREF + 100 VDD VREF + 100 VDD mV 1
VIL.CA(DC) DC input logic low VSS VREF - 100 VSS VREF - 100 mV 1
VIH.CA(AC) AC input logic high VREF + 175 -VREF + 175 -mV1,2
VIL.CA(AC) AC input logic low - VREF - 175 -VREF - 175 mV 1,2
VIH.CA(AC150) AC input logic high - - VREF+150 -mV1,2
VIL.CA(AC150) AC input logic low - - - VREF-150 mV 1,2
VREFCA(DC) Reference Voltage for ADD,
CMD inputs 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V3,4
Symbol Parameter DDR3-1066 DDR3-1333/1600 Unit Notes
Min. Max. Min. Max.
VIH.DQ(DC100) DC input logic high VREF + 100 VDD VREF + 100 VDD mV 1
VIL.DQ(DC100) DC input logic low VSS VREF - 100 VSS VREF - 100 mV 1
VIH.DQ(AC175) AC input logic high VREF + 175 -VREF + 150 - mV 1,2,5
VIL.DQ(AC175) AC input logic low - VREF - 175 -VREF - 150 mV 1,2,5
VIH.DQ(AC150) AC input logic high VREF + 150 Note 2 - - mV 1,2,5
VIL.DQ(AC150) AC input logic low Note 2 VREF - 150 - - mV 1,2,5
VREFDQ(DC) I/O Reference Voltage(DQ) 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V3,4
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10.2 VREF Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 2. It shows a valid reference voltage
VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of VREF
. Fur-
thermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD.
Figure 2. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF
.
"VREF" shall be understood as VREF(DC), as defined in Figure 2.
This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing
and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
voltage
VDD
VSS
time
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10.3 AC & DC Logic Input Levels for Differential Signals
10.3.1 Differential Signals Definition
Figure 3. Definition of differential ac-swing and "time above ac level" tDVAC
10.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)
Notes:
1. Used to define a differential signal slew-rate.
2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and VREFDQ; if a
reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet
Specification " on page20.
Allowed time before ringback (tDVAC) for CLK - CLK and DQS - DQS.
Symbol Parameter DDR3-1066/1333/1600 unit Note
min max
VIHdiff differential input high +0.2 note 3 V 1
VILdiff differential input low note 3 -0.2 V 1
VIHdiff(AC) differential input high ac 2 x (VIH(AC)-VREF)note 3 V 2
VILdiff(AC) differential input low ac note 3 2 x (VREF - VIL(AC)) V2
Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV
min max min max
> 4.0 75 - 175 -
4.0 57 - 170 -
3.0 50 - 167 -
2.0 38 - 163 -
1.8 34 - 162 -
1.6 29 - 161 -
1.4 22 - 159 -
1.2 13 - 155 -
1.0 0 - 150 -
< 1.0 0 - 150 -
0.0
tDVAC
VIH.DIFF.MIN
half cycle
Differential Input Voltage (i.e. DQS-DQS, CK-CK)
time
tDVAC
VIH.DIFF.AC.MIN
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
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10.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for
single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every
half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle
proceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD sig-
nals, then these ac-levels apply also for the single-ended signals CK and CK .
Figure 4. Single-ended requirement for differential signals
Note that while ADD/CMD and DQ signal requirements are with respect to VREF
, the single-ended components of differential signals have a requirement
with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common
mode characteristics of these signals.
Single ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
Notes:
1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs.
2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a
signal group, then the reduced level applies also here
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot
Specification"
Symbol Parameter DDR3-1066/1333/1600 Unit Notes
Min Max
VSEH
Single-ended high-level for strobes (VDD/2)+0.175 Note3 V 1, 2
Single-ended high-level for CK, CK (VDD/2)+0.175 Note3 V 1, 2
VSEL
Single-ended low-level for strobes Note3 (VDD/2)-0.175 V1, 2
Single-ended low-level for CK, CK Note3 (VDD/2)-0.175 V1, 2
VDD or VDDQ
VSEH min
VDD/2 or VDDQ/2
VSEL max
VSEH
VSS or VSSQ
VSEL
CK or DQS
time
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10.3.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signal to the mid level between of VDD and VSS.
Figure 5. VIX Definition
Cross point voltage for differential input signals (CK, DQS)
Note :
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing VSEL /
VSEH of at least VDD/2 =/-250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns. Refer to table 11 on page 17 for VSEL and VSEH
standard values.
10.4 Slew Rate Definition for Single-ended Input Signals
See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals.
See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.tDH nominal slew rate for a falling signal is defined
as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF
10.5 Slew Rate Definition for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.
Differential input slew rate definition
Note : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds
Figure 6. Differential Input Slew Rate definition for DQS, DQS and CK, CK
Symbol Parameter DDR3-1066/1333/1600 Unit Notes
Min Max
VIX Differential Input Cross Point Voltage relative to VDD/2 for CK,CK -150 150 mV
-175 175 mV 1
VIX Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS -150 150 mV
Description Measured Defined by
From To
Differential input slew rate for rising edge (CK-CK and DQS-DQS)VILdiffmax VIHdiffmin
VIHdiffmin - VILdiffmax
Delta TRdiff
Differential input slew rate for falling edge (CK-CK and DQS-DQS)VIHdiffmin VILdiffmax
VIHdiffmin - VILdiffmax
Delta TFdiff
VDD
CK, DQS
VDD/2
CK, DQS
VSS
VIX
VIX
VIX
VIHdiffmin
0
VILdiffmax
delta TRdiff
delta TFdiff
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11.0 AC & DC Output Measurement Levels
11.1 Single-ended AC & DC Output Levels
Single Ended AC and DC output levels
Note : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω
and an effective test load of 25Ω to VTT=VDDQ/2.
11.2 Differential AC & DC Output Levels
Differential AC and DC output levels
Note : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω
and an effective test load of 25Ω to VTT=VDDQ/2 at each of the differential outputs.
11.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in below.
Single Ended Output slew rate definition
Note : Output slew rate is verified by design and characterization, and may not be subject to production test.
Single Ended Output slew rate
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output
se : Singe-ended Signals, For Ron = RZQ/7 setting
Note 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all
remaining DQ signals in the same byte lane are static (i.e they stay at either high or low).
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respec-
tively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
Symbol Parameter DDR3-1066/1333/1600 Units Notes
VOH(DC) DC output high measurement level (for IV curve linearity) 0.8 x VDDQ V
VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5 x VDDQ V
VOL(DC) DC output low measurement level (for IV curve linearity) 0.2 x VDDQ V
VOH(AC) AC output high measurement level (for output SR) VTT + 0.1 x VDDQ V1
VOL(AC) AC output low measurement level (for output SR) VTT - 0.1 x VDDQ V1
Symbol Parameter DDR3-1066/1333/1600 Units Notes
VOHdiff(AC) AC differential output high measurement level (for output SR) +0.2 x VDDQ V1
VOLdiff(DC) AC differential output low measurement level (for output SR) -0.2 x VDDQ V1
Description Measured Defined by
From To
Single ended output slew rate for rising edge VOL(AC) VOH(AC) VOH(AC)-VOL(AC)
Delta TRse
Single ended output slew rate for falling edge VOH(AC) VOL(AC) VOH(AC)-VOL(AC)
Delta TFse
Parameter Symbol DDR3-1066 DDR3-1333 DDR3-1600 Units
Min Max Min Max Min Max
Single ended output slew rate SRQse 2.5 5 2.5 5 TBD 5 V/ns
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Figure 7. Single Ended Output Slew Rate definition
11.4 DIfferential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and
VOHdiff(AC) for differential signals as shown in below.
Differential Output slew rate definition
Note : Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output slew rate
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output
diff : Singe-ended Signals
For Ron = RZQ/7 setting
Figure 8. Differential Output Slew Rate definition
Description Measured Defined by
From To
Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC) VOHdiff(AC)-VOLdiff(AC)
Delta TRdiff
Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC) VOHdiff(AC)-VOLdiff(AC)
Delta TFdiff
Parameter Symbol DDR3-1066 DDR3-1333 DDR3-1600 Units
Min Max Min Max Min Max
Single ended output slew rate SRQse 5 10 5 10 TBD 10 V/ns
VOH(AC)
VOL(AC)
delta TRsedelta TFse
VTT
VOHdiff(AC)
VOLdiff(AC)
delta TRdiffdelta TFdiff
VTT
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12.0 IDD Specification Definition
Symbol Description
IDD0
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: 0; CS: High between ACT and PRE;
Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
tern
IDD1
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: 0; CS: High between ACT, RD
and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
tern
IDD2N
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Regis-
tersb); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
DD2NT
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Regis-
tersb); ODT Signal: toggling according to Table 35 ; Pattern Details: Refer to Component Datasheet for detail pattern
DDQ2NT Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
IDD2P0
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc)
IDD2P1
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc)
IDD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at 0
IDD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 34 on page 36 ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT
Signal: stable at 0
IDD4R
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable
at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDDQ4R Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
IDD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 37); Output Buffer and RTT: Enabled in Mode Registersb); ODT
Signal: stable at HIGH; Pattern Details: Refer to Component Datasheet for detail pattern
IDD5B
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: 0; CS: High between REF; Command,
Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38); Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD6
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabledd); Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK:
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING
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Unbuffered DIMM
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
c) Pecharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
g) IDD current measure method and detail patterns are described on DDR3 component datasheet
Symbol Description
IDD6ET
Self-Refresh Current: Extended Temperature Range (optional)f)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabledd); Self-Refresh Temperature Range (SRT): Extendede); CKE: Low; External clock: Off; CK and CK:
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING
IDD6TC
Auto Self-Refresh Current (optional)f)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Enabledd); Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK:
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING; DM:stable at 0;
Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING
IDD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 8a); AL: CL-1; CS: High
between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and
the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:
Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD8
RESET Low Current
RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :
FLOATING
22 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
12.1 IDD SPEC Table
M378B2873FHS : 1GB(128Mx64) Module
M378B5673FH0 : 2GB(256Mx64) Module
Symbol CF8
(DDR3-1066@CL=7)
CH9
(DDR3-1333@CL=9)
CK0
(DDR3-1333@CL=11) Unit Notes
IDD0 TBD TBD TBD mA
IDD1 TBD TBD TBD mA
IDD2P0(slow exit) TBD TBD TBD mA
IDD2P1(fast exit) TBD TBD TBD mA
IDD2N TBD TBD TBD mA
IDD2NT TBD TBD TBD mA
IDDQ2NT TBD TBD TBD mA
IDD2Q TBD TBD TBD mA
IDD3P(fast exit) TBD TBD TBD mA
IDD3N TBD TBD TBD mA
IDD4R TBD TBD TBD mA
IDDQ4R TBD TBD TBD mA
IDD4W TBD TBD TBD mA
IDD5B TBD TBD TBD mA
IDD6 TBD TBD TBD mA
IDD7 TBD TBD TBD mA
IDD8 TBD TBD TBD mA
Symbol CF8
(DDR3-1066@CL=7)
CH9
(DDR3-1333@CL=9)
CK0
(DDR3-1333@CL=11) Unit Notes
IDD0 TBD TBD TBD mA
IDD1 TBD TBD TBD mA
IDD2P0(slow exit) TBD TBD TBD mA
IDD2P1(fast exit) TBD TBD TBD mA
IDD2N TBD TBD TBD mA
IDD2NT TBD TBD TBD mA
IDDQ2NT TBD TBD TBD mA
IDD2Q TBD TBD TBD mA
IDD3P(fast exit) TBD TBD TBD mA
IDD3N TBD TBD TBD mA
IDD4R TBD TBD TBD mA
IDDQ4R TBD TBD TBD mA
IDD4W TBD TBD TBD mA
IDD5B TBD TBD TBD mA
IDD6 TBD TBD TBD mA
IDD7 TBD TBD TBD mA
IDD8 TBD TBD TBD mA
23 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
13.0 Input/Output Capacitance
13.1 Non ECC UDIMM - 1GB(128Mx64) Module
13.2 Non ECC UDIMM - 2GB(256Mx64) Module
Parameter Symbol
M378B2873FHS
Units NotesDDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Min Max Min Max Min Max Min Max
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)CIO - TBD - TBD - TBD - TBD pF
Input capacitance (CK and CK) CCK - TBD - TBD - TBD - TBD pF
Input capacitance (All other input-only pins) CI - TBD - TBD - TBD - TBD pF
Input/output capacitance of ZQ pin CZQ - TBD - TBD - TBD - TBD pF
Parameter Symbol
M378B5673FH0
Units NotesDDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Min Max Min Max Min Max Min Max
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)CIO - TBD - TBD - TBD - TBD pF
Input capacitance (CK and CK) CCK - TBD - TBD - TBD - TBD pF
Input capacitance (All other input-only pins) CI - TBD - TBD - TBD - TBD pF
Input/output capacitance of ZQ pin CZQ - TBD - TBD - TBD - TBD pF
24 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
14.0 Electrical Characteristics and AC timing
(0 °C<TCASE ≤95 °C, VDDQ = 1.5V ± 0.075V; VDD = 1.5V ± 0.075V)
14.1 Refresh Parameters by Device Density
Note :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or
requirements referred to in this material.
14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
14.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units Note
All Bank Refresh to active/refresh cmd time tRFC 110 160 300 350 ns
Average periodic refresh interval tREFI
0 °C ≤ TCASE ≤ 85°C7.8 7.8 7.8 7.8 µs
85 °C < TCASE ≤ 95°C3.9 3.9 3.9 3.9 µs 1
Speed DDR3-1066 DDR3-1333 DDR3-1600
Units Note
Bin (CL - tRCD - tRP) 7-7-7 9-9-9 11-11-11
Parameter min min min
CL 7911tCK
tRCD 13.13 13.5 13.75 ns
tRP 13.13 13.5 13.75 ns
tRAS 37.5 36 35 ns
tRC 50.63 49.5 48.75 ns
tRRD 7.5 6.0 6.0 ns
tFAW 37.5 30 30 ns
Speed DDR3-800
Units NoteCL-nRCD-nRP 6 - 6 - 6
Parameter Symbol min max
Internal read command to first data tAA 15 20 ns
ACT to internal read or write delay time tRCD 15 -ns
PRE command period tRP 15 -ns
ACT to ACT or REF command period tRC 52.5 -ns
ACT to PRE command period tRAS 37.5 9*tREFI ns 8
CL = 6 / CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3
Supported CL Settings 6nCK
Supported CWL Settings 5nCK
25 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
DDR3-1066 Speed Bins
DDR3-1333 Speed Bins
Speed DDR3-1066
Units NoteCL-nRCD-nRP 7 - 7 - 7
Parameter Symbol min max
Internal read command to first data tAA 13.125 20 ns
ACT to internal read or write delay time tRCD 13.125 -ns
PRE command period tRP 13.125 -ns
ACT to ACT or REF command period tRC 50.625 -ns
ACT to PRE command period tRAS 37.5 9*tREFI ns 8
CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,6
CWL = 6 tCK(AVG) Reserved ns 1,2,3,4
CL = 7 CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4
CL = 8 CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3
Supported CL Settings 6,7,8 nCK
Supported CWL Settings 5,6 nCK
Speed DDR3-1333
Units NoteCL-nRCD-nRP 9 -9 - 9
Parameter Symbol min max
Internal read command to first data tAA 13.5 (13.125)5,9 20 ns
ACT to internal read or write delay time tRCD 13.5 (13.125)5,9 -ns
PRE command period tRP 13.5 (13.125)5,9 -ns
ACT to ACT or REF command period tRC 49.5 (49.125)5,9 -ns
ACT to PRE command period tRAS 36 9*tREFI ns 8
CL = 6
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,7
CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,7
CWL = 7 tCK(AVG) Reserved ns 4
CL = 7
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,7
(Optional) Note 5,9
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,
CL = 8
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,7
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,
CL = 9 CWL = 5,6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4
CL = 10
CWL = 5,6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3
(Optional) ns 5
Supported CL Settings 6,7,8,9 nCK
Supported CWL Settings 5,6,7 nCK
26 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
DDR3-1600 Speed Bins
Speed DDR3-1600
Units NoteCL-nRCD-nRP 11-11-11
Parameter Symbol min max
Intermal read command to first data tAA 13.75
(13.125)5,9 20 ns
ACT to internal read or write delay time tRCD 13.75
(13.125)5,9 -ns
PRE command period tRP 13.75
(13.125)5,9 -ns
ACT to ACT or REF command period tRC 48.75
(48.125)5,9 -ns
ACT to PRE command period tRAS 35 9*tREFI ns
CL = 6
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,8
CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,8
CWL = 7, 8 tCK(AVG) Reserved ns 4
CL = 7
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,8
(Optional) Note 5,9
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,8
CWL = 8 tCK(AVG) Reserved ns 4
CL = 8
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,8
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,8
CWL = 8 tCK(AVG) Reserved ns 1,2,3,4
CL = 9
CWL = 5,6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4,8
(Optional) Note 9,10
CWL = 8 tCK(AVG) TBD ns 1,2,3,4
CL = 10
CWL = 5,6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,8
(Optional) Note 9,10
CWL = 8 tCK(AVG) Reserved ns 1,2,3,4
CL = 11 CWL = 5,6,7 tCK(AVG) Reserved ns 4
CWL = 8 tCK(AVG) 1.25 <1.5 ns 1,2,3,5
Supported CL Settings 6,7,8,9,10,11 nCK
Supported CWL Settings 5,6,7,8 nCK
27 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
14.3.1 Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
Note :
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be ful-
filled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequen-
cies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculat-
ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next "SupportedCL".
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns
or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
4. "Reserved" settings are not allowed. User must program a different value.
5. "Optional" settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier’s data sheet and/
or the DIMM SPD information if and how this setting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
9. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to
match. For example, DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte
16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should pro-
gram 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRC-
min (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and
48.125ns (tRASmin+tRPmin=35ns+13.125ns) for DDR3-1600(CL11).
28 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
15.0 Timing Parameters by Speed Grade
Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Note
Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX
Clock Timing
Minimum Clock Cycle Time (DLL off mode) tCK(DLL_OF
F) 8 - 8 - 8 - 8 - ns 6
Average Clock Period tCK(avg) See Speed Bins Table ps
Clock Period tCK(abs) tCK(avg)min + tJIT(per)min
tCK(avg)max + tJIT(per)max ps
Average high pulse width tCH(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)
Average low pulse width tCL(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)
Clock Period Jitter tJIT(per) -100 100 -90 90 -80 80 -70 70 ps
Clock Period Jitter during DLL locking period tJIT(per, lck) -90 90 -80 80 -70 70 -60 60 ps
Cycle to Cycle Period Jitter tJIT(cc) 200 180 160 140 ps
Cycle to Cycle Period Jitter during DLL locking period tJIT(cc, lck) 180 160 140 120 ps
Cumulative error across 2 cycles tERR(2per) - 147 147 - 132 132 - 118 118 -103 103 ps
Cumulative error across 3 cycles tERR(3per) - 175 175 - 157 157 - 140 140 -122 122 ps
Cumulative error across 4 cycles tERR(4per) - 194 194 - 175 175 - 155 155 -136 136 ps
Cumulative error across 5 cycles tERR(5per) - 209 209 - 188 188 - 168 168 -147 147 ps
Cumulative error across 6 cycles tERR(6per) - 222 222 - 200 200 - 177 177 -155 155 ps
Cumulative error across 7 cycles tERR(7per) - 232 232 - 209 209 - 186 186 -163 163 ps
Cumulative error across 8 cycles tERR(8per) - 241 241 - 217 217 - 193 193 -169 169 ps
Cumulative error across 9 cycles tERR(9per) - 249 249 - 224 224 - 200 200 -175 175 ps
Cumulative error across 10 cycles tERR(10per) - 257 257 - 231 231 - 205 205 -180 180 ps
Cumulative error across 11 cycles tERR(11per) - 263 263 - 237 237 - 210 210 -184 184 ps
Cumulative error across 12 cycles tERR(12per) - 269 269 - 242 242 - 215 215 -188 188 ps
Cumulative error across n = 13, 14 ... 49, 50 cycles tERR(nper) tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max ps 24
Absolute clock HIGH pulse width tCH(abs) 0.43 -0.43 -0.43 -0.43 -tCK(avg) 25
Absolute clock Low pulse width tCL(abs) 0.43 -0.43 -0.43 -0.43 -tCK(avg) 26
Data Timing
DQS,DQS to DQ skew, per group, per access tDQSQ -200 -150 -125 -100 ps 13
DQ output hold time from DQS, DQS tQH 0.38 -0.38 -0.38 -0.38 -tCK(avg) 13, g
DQ low-impedance time from CK, CK tLZ(DQ) -800 400 -600 300 -500 250 -450 225 ps 13,14, f
DQ high-impedance time from CK, CK tHZ(DQ) -400 -300 -250 -225 ps 13,14, f
Data setup time to DQS, DQS referenced to
VIH(AC)VIL(AC) levels tDS(base) 75 -25 -30 -10 ps d, 17
Data hold time to DQS, DQS referenced to
VIH(AC)VIL(AC) levels tDH(base) 150 -100 -65 -45 ps d, 17
DQ and DM Input pulse width for each input tDIPW 600 -490 -400 -360 ps 28
Data Strobe Timing
DQS, DQS READ Preamble tRPRE 0.9 Note 19 0.9 Note 19 0.9 Note 19 0.9 Note 19 tCK 13, 19, g
DQS, DQS differential READ Postamble tRPST 0.3 Note 11 0.3 Note 11 0.3 Note 11 0.3 Note 11 tCK 11, 13, b
DQS, DQS output high time tQSH 0.38 -0.38 -0.4 -0.4 -tCK(avg) 13, g
DQS, DQS output low time tQSL 0.38 -0.38 -0.4 -0.4 -tCK(avg) 13, g
DQS, DQS WRITE Preamble tWPRE 0.9 -0.9 -0.9 -0.9 - tCK
DQS, DQS WRITE Postamble tWPST 0.3 -0.3 -0.3 -0.3 - tCK
DQS, DQS rising edge output access time from rising
CK, CK tDQSCK -400 400 -300 300 -255 255 -225 225 ps 13,f
DQS, DQS low-impedance time (Referenced from RL-1) tLZ(DQS) -800 400 -600 300 -500 250 -450 225 ps 13,14,f
DQS, DQS high-impedance time (Referenced from
RL+BL/2) tHZ(DQS) -400 -300 -250 -225 ps 13,14,f
DQS, DQS differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg) 29, 31
DQS, DQS differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg) 30, 31
DQS, DQS rising edge to CK, CK rising edge tDQSS -0.25 0.25 -0.25 0.25 -0.25 0.25 -0.27 0.27 tCK(avg) c
DQS,DQS falling edge setup time to CK, CK rising edge tDSS 0.2 -0.2 -0.2 -0.18 -tCK(avg) c, 32
DQS,DQS falling edge hold time to CK, CK rising edge tDSH 0.2 -0.2 -0.2 -0.18 -tCK(avg) c, 32
29 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Note
Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX
Command and Address Timing
DLL locking time tDLLK 512 -512 -512 -512 -nCK
internal READ Command to PRECHARGE Command
delay tRTP
max
(4nCK,7.5ns
)
-
max
(4nCK,7.5ns
)
-
max
(4nCK,7.5ns
)
-max
(4nCK,7.5ns) - e
Delay from start of internal write transaction to internal
read command tWTR
max
(4nCK,7.5ns
)
-
max
(4nCK,7.5ns
)
-
max
(4nCK,7.5ns
)
-max
(4nCK,7.5ns) -e,18
WRITE recovery time tWR 15 -15 -15 -15 -ns e,18
Mode Register Set command cycle time tMRD 4 - 4 - 4 - 4 - nCK
Mode Register Set command update delay tMOD
max
(12nCK,15ns
)
-
max
(12nCK,15ns
)
-
max
(12nCK,15ns
)
-
max
(12nCK,15ns
)
-
CAS# to CAS# command delay tCCD 4 - 4 - 4 - 4 - nCK
Auto precharge write recovery + precharge time tDAL(min) WR + roundup (tRP / tCK(AVG)) nCK
Multi-Purpose Register Recovery Time tMPRR 1 - 1 - 1 - 1 - nCK 22
ACTIVE to PRECHARGE command period tRAS See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 40 ns e
ACTIVE to ACTIVE command period for 1KB page size tRRD max
(4nCK,10ns) -
max
(4nCK,7.5ns
)
-max
(4nCK,6ns) -max
(4nCK,6ns) - e
ACTIVE to ACTIVE command period for 2KB page size tRRD max
(4nCK,10ns) -max
(4nCK,10ns) -
max
(4nCK,7.5ns
)
-max
(4nCK,7.5ns) - e
Four activate window for 1KB page size tFAW 40 -37.5 -30 -30 -ns e
Four activate window for 2KB page size tFAW 50 -50 -45 -40 -ns e
Command and Address setup time to CK, CK refer-
enced to VIH(AC) / VIL(AC) levels tIS(base) 200 -125 -65 -45 -ps b,16
Command and Address hold time from CK, CK refer-
enced to VIH(AC) / VIL(AC) levels tIH(base) 275 -200 -140 -120 -ps b,16
Command and Address setup time to CK, CK refer-
enced to VIH(AC) / VIL(AC) levels
tIS(base)
AC150 200 + 150 -125 + 150 -65+125 -45+125 -ps b,16,27
Control & Address Input pulse width for each input tIPW 900 -780 -620 -560 -ps 28
Calibration Timing
Power-up and RESET calibration time tZQinitI 512 -512 -512 -512 -nCK
Normal operation Full calibration time tZQoper 256 -256 -256 -256 -nCK
Normal operation short calibration time tZQCS 64 -64 -64 -64 -nCK 23
Reset Timing
Exit Reset from CKE HIGH to a valid command tXPR max(5nCK,
tRFC + 10ns) -max(5nCK,
tRFC + 10ns) -max(5nCK,
tRFC + 10ns) -max(5nCK,
tRFC + 10ns) -
Self Refresh Timing
Exit Self Refresh to commands not requiring a locked
DLL tXS max(5nCK,t
RFC + 10ns) -max(5nCK,t
RFC + 10ns) -max(5nCK,t
RFC + 10ns) -max(5nCK,tR
FC + 10ns) -
Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(min) -tDLLK(min) -tDLLK(min) -tDLLK(min) -nCK
Minimum CKE low width for Self refresh entry to exit
timing tCKESR tCKE(min) +
1tCK -tCKE(min) +
1tCK -tCKE(min) +
1tCK -tCKE(min) +
1tCK -
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE) tCKSRE max(5nCK,
10ns) -max(5nCK,
10ns) -max(5nCK,
10ns) -max(5nCK,
10ns) -
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit tCKSRX max(5nCK,
10ns) -max(5nCK,
10ns) -max(5nCK,
10ns) -max(5nCK,
10ns) -
30 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Note
Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX
Power Down Timing
Exit Power Down with DLL on to any valid com-
mand;Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
tXP
max
(3nCK,
7.5ns)
-
max
(3nCK,
7.5ns)
-max
(3nCK,6ns) -max
(3nCK,6ns) -
Exit Precharge Power Down with DLL frozen to com-
mands requiring a locked DLL tXPDLL
max
(10nCK,
24ns)
-
max
(10nCK,
24ns)
-
max
(10nCK,
24ns)
-
max
(10nCK,
24ns)
- 2
CKE minimum pulse width tCKE
max
(3nCK,
7.5ns)
-
max
(3nCK,
5.625ns)
-
max
(3nCK,
5.625ns)
-max
(3nCK,5ns) -
Command pass disable delay tCPDED 1 - 1 - 1 - 1 - nCK
Power Down Entry to Exit Timing tPD tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCK 15
Timing of ACT command to Power Down entry tACTPDEN 1 - 1 - 1 - 1 - nCK 20
Timing of PRE command to Power Down entry tPRPDEN 1 - 1 - 1 - 1 - nCK 20
Timing of RD/RDA command to Power Down entry tRDPDEN RL + 4 +1 -RL + 4 +1 -RL + 4 +1 -RL + 4 +1 -
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF) tWRPDEN
WL + 4
+(tWR/
tCK(avg))
-
WL + 4
+(tWR/
tCK(avg))
-
WL + 4
+(tWR/
tCK(avg))
-
WL + 4
+(tWR/
tCK(avg))
-nCK 9
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF) tWRAPDEN WL + 4
+WR +1 -WL + 4
+WR +1 -WL + 4
+WR +1 -WL + 4 +WR
+1 -nCK 10
Timing of WR command to Power Down entry
(BL4MRS) tWRPDEN
WL + 2
+(tWR/
tCK(avg))
-
WL + 2
+(tWR/
tCK(avg))
-
WL + 2
+(tWR/
tCK(avg))
-
WL + 2
+(tWR/
tCK(avg))
-nCK 9
Timing of WRA command to Power Down entry
(BL4MRS) tWRAPDEN WL +2 +WR
+1 -WL +2 +WR
+1 -WL +2 +WR
+1 -WL +2 +WR
+1 -nCK 10
Timing of REF command to Power Down entry tREFPDEN 1 - 1 - 1 - 1 - 20,21
Timing of MRS command to Power Down entry tMRSPDEN tMOD(min) -tMOD(min) -tMOD(min) - tMOD(min) -
ODT Timing
ODT high time without write command or with write
command and BC4 ODTH4 4 - 4 - 4 - 4 - nCK
ODT high time with Write command and BL8 ODTH8 6 - 6 - 6 - 6 - nCK
Asynchronous RTT turn-on delay (Power-Down with
DLL frozen) tAONPD 28.5 28.5 28.5 28.5 ns
Asynchronous RTT turn-off delay (Power-Down with
DLL frozen) tAOFPD 28.5 28.5 28.5 28.5 ns
ODT turn-on tAON -400 400 -300 300 -250 250 -225 225 ps 7,f
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference tAOF 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) 8,f
RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) f
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining
mode is programmed tWLMRD 40 -40 -40 -40 - tCK 3
DQS/DQS delay after tDQS margining mode is pro-
grammed tWLDQSEN 25 -25 -25 -25 - tCK 3
Setup time for tDQSS latch tWLS 325 -245 -195 -165 -ps
Write leveling hold time from rising DQS, DQS cross-
ing to rising CK, CK crossing tWLH 325 -245 -195 -165 -ps
Write leveling output delay tWLO 09090907.5 ns
Write leveling output error tWLOE 0 2 0 2 0 2 0 2 ns
31 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
15.1 Jitter Notes
Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input
clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another
Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
Specific Note b These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge
to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per),
tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these param-
eters should be met whether clock jitter is present or not.
Specific Note c These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK) cross-
ing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the
clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
Specific Note d These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data strobe
signal (DQS(L/U), DQS(L/U)) crossing.
Specific Note e For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)},
which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the
device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge command at
Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.
Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input clock,
where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = + 193 ps,
then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(derated) =
tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) =
- 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=
12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.
Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (out-
put deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act =
2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x
tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x
tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/max usage!)
32 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
15.2 Timing Parameter Notes
1. Actual value dependant upon measurement level definitions which are TBD.
2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register
5. Value must be rounded-up to next higher integer value
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. For definition of RTT turn-on time tAON see "Device Operation"
8. For definition of RTT turn-off time tAOF see "Device Operation".
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles as programmed in MR0
11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See Device Operation Datasheet
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated
by TBD
13. Value is valid for RON34
14. Single ended signal parameter.
15. tREFI depends on TOPER
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,
VREF(DC) = VREFDQ(DC). FOr input only pins except RESET, VREF(DC)=VREFCA(DC).
See "Address/ Command Setup, Hold and Derating"
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,
VREF(DC)= VREFDQ(DC). For input only pins except RESET, VREF(DC)=VREFCA(DC).
See "Data Setup, Hold and Slew Rate Derating".
18. Start of internal write transaction is definited as follows ;
For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL
19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation"
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down
IDD spec will not be applied until finishing those operations.
21. Altough CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time
such as tXPDLL(min) is also required. See "Device Operation".
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming
the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-
ject to in the application, is illustrated. The interval could be defined by the following formula:
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% /°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu-
lated as:
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter-
nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
28. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC)
29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.
30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.
31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
0.5
(1.5 x 1) + (0.15 x 15) = 0.133
~
~
128ms
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate)
33 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
16.0 Physical Dimensions
16.1 128Mbx8 based 128Mx64 Module (1 Rank) - M378B2873FHS
133.35 ± 0.15
Max 4.0
Units : Millimeters
9.50
1.270 ± 0.10
128.95
(2)
(4X)3.00 ± 0.1
30.00 ± 0.15
2.30
17.30
The used device is 128M x8 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B1G0846F-HC∗∗
* Note : Tolerances on all dimensions ±0.15 unless otherwise specified.
AB
47.00 71.00
2.50
1.00
0.2 ± 0.15
2.50 ± 0.20
Detail B
5.00
Detail A
1.50±0.10
0.80 ± 0.05
3.80
2x 2.10 ± 0.15
2.50
SPD
N/A
(for x72)
(for x64)
ECC
54.675
34 of 34
DDR3 SDRAM
Rev. 0.9 September 2009
Unbuffered DIMM
16.2 128Mbx8 based 256Mx64 Module (2 Ranks) - M378B5673FH0
133.35 ± 0.15
Max 4.0
54.675
Units : Millimeters
9.50
128.95
(2)
(4X)3.00 ± 0.1
30.00 ± 0.15
2.30
17.30
The used device is 128M x8 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B1G0846E-HC∗∗
* Note : Tolerances on all dimensions ±0.15 unless otherwise specified.
AB
47.00 71.00
2.50
1.00
0.2 ± 0.15
2.50 ± 0.20
Detail B
5.00
Detail A
1.50±0.10
0.80 ± 0.05
3.80
2x 2.10 ± 0.15
2.50
SPD
N/A
(for x72)
(for x64)
ECC
1.270 ± 0.10
N/A
(for x64)
(for x72)
ECC
