AOD4130/AOI4130
60V N-Channel MOSFET
General Description Product Summary
V
DS
I
D
(at V
GS
=10V) 30A
R
DS(ON)
(at V
GS
=10V) < 24mΩ
R
DS(ON)
(at V
GS
=4.5V) < 30mΩ
100% UIS Tested
100% R
g
Tested
Symbol
V
DS
V
GS
I
DM
I
AS
, I
AR
E
AS
, E
AR
T
J
, T
STG
Symbol
t ≤ 10s
Steady-State
Steady-State
R
θJC
Maximum Junction-to-Case °C/W
°C/W
Maximum Junction-to-Ambient
A D
2.4 50
2.9
Power Dissipation
B
P
D
W
Power Dissipation
A
P
DSM
W
T
A
=70°C
52
1.6
T
A
=25°C
A
T
A
=25°C I
DSM
A
T
A
=70°C
I
D
30
20
T
C
=25°C
T
C
=100°C
Avalanche energy L=0.1mH
C
mJ
Avalanche Current
C
5
Continuous Drain
Current
36.5
6.5
A27
The AOD4130/AOI4130 combines advanced trench
MOSFET technology with a low resistance package to
provide extremely low R
DS(ON)
. This device is ideal for
boost converters and synchronous rectifiers for
consumer, telecom, industrial power supplies and LED
backlighting.
V
Maximum UnitsParameter
Absolute Maximum Ratings T
A
=25°C unless otherwise noted
60V
V±20Gate-Source Voltage
Drain-Source Voltage 60
Units
Maximum Junction-to-Ambient
A
°C/W
R
θJA
12.4
34 20
Junction and Storage Temperature Range -55 to 175 °C
Thermal Characteristics
74Pulsed Drain Current
C
Continuous Drain
Current
Parameter Typ Max
T
C
=25°C
2.5
25
T
C
=100°C
G
D
S
G
G
D
D
D
Top View
Bottom View
TO-251A
IPAK
TO252
DPAK
TopView Bottom View
G
G
D
D
D
Rev 1: June 2011 www.aosmd.com Page 1 of 6
AOD4130/AOI4130
Symbol Min Typ Max Units
BV
DSS
60 V
V
DS
=60V, V
GS
=0V 1
T
J
=55°C 5
I
GSS
100 nA
V
GS(th)
Gate Threshold Voltage 1.6 2.2 2.8 V
I
D(ON)
74 A
19.5 24
T
J
=125°C 37.5 45
24 30 mΩ
g
FS
55 S
V
SD
0.76 1 V
I
S
46 A
C
iss
1265 1582 1900 pF
C
oss
70 100 130 pF
C
rss
40 67 95 pF
R
g
1.8 3.6 5.4 Ω
Q
g
(10V) 23 28.3 34 nC
Q
g
(4.5V) 11 13.4 16 nC
Q
gs
3.6 4.5 5.4 nC
Q
gd
4.3 7.2 10 nC
t
D(on)
7.5 ns
t
r
6.5 ns
t
D(off)
33 ns
t
f
7.5 ns
t
rr
15 22 30 ns
Q
rr
53 76 100 nC
THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING
OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,
FUNCTIONS AND RELIABILITY WITHOUT NOTICE.
Body Diode Reverse Recovery Time
Drain-Source Breakdown Voltage
On state drain current
I
D
=250µA, V
GS
=0V
V
GS
=10V, V
DS
=5V
V
GS
=10V, I
D
=20A
Reverse Transfer Capacitance
I
F
=20A, dI/dt=500A/µs
V
GS
=0V, V
DS
=30V, f=1MHz
SWITCHING PARAMETERS
Electrical Characteristics (T
J
=25°C unless otherwise noted)
STATIC PARAMETERS Parameter Conditions
I
DSS
µA
V
DS
=5V,
I
D
=250µA
V
DS
=0V, V
GS
= ±20V
Zero Gate Voltage Drain Current
Gate-Body leakage current
Forward Transconductance
Diode Forward Voltage
R
DS(ON)
Static Drain-Source On-Resistance mΩ
I
S
=1A,V
GS
=0V
V
DS
=5V, I
D
=20A
V
GS
=4.5V, I
D
=20A
V
GS
=10V, V
DS
=30V, R
L
=1.5Ω,
R
GEN
=3Ω
Gate resistance V
GS
=0V, V
DS
=0V, f=1MHz
Turn-Off Fall Time
Total Gate Charge
V
GS
=10V, V
DS
=30V, I
D
=20A
Gate Source Charge
Gate Drain Charge
Total Gate Charge
Body Diode Reverse Recovery Charge I
F
=20A, dI/dt=500A/µs
Maximum Body-Diode Continuous Current
G
Input Capacitance
Output Capacitance
Turn-On DelayTime
DYNAMIC PARAMETERS
Turn-On Rise Time
Turn-Off DelayTime
A. The value of R
θJA
is measured with the device mounted on 1in
2
FR-4 board with 2oz. Copper, in a still air environment with T
A
=25°C. The
Power dissipation P
DSM
is based on R
θJA
and the maximum allowed junction temperature of 150°C. The value in any given application depends
on the user's specific board design, and the maximum temperature of 175°C may be used if the PCB allows it.
B. The power dissipation P
D
is based on T
J(MAX)
=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper
dissipation limit for cases where additional heatsinking is used.
C. Repetitive rating, pulse width limited by junction temperature T
J(MAX)
=175°C. Ratings are based on low frequency and duty cycles to keep
initial T
J
=25°C.
D. The R
θJA
is the sum of the thermal impedance from junction to case R
θJC
and case to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300µs pulses, duty cycle 0.5% max.
F. These curves are based on the junction-to-case thermal impedance which is measured with the device mounted to a large heatsink,
assuming a maximum junction temperature of T
J(MAX)
=175°C. The SOA curve provides a single pulse ratin g.
G. The maximum current rating is package limited.
H. These tests are performed with the device mounted on 1 in
2
FR-4 board with 2oz. Copper, in a still air environment with T
A
=25°C.
Rev 1: June 2011 www.aosmd.com Page 2 of 6
AOD4130/AOI4130
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
17
5
2
10
0
18
40
0
20
40
60
80
0123456
V
GS
(Volts)
Figure 2: Transfer Characteristics (Note E)
I
D
(A)
10
15
20
25
30
0 5 10 15 20 25 30
I
D
(A)
Figure 3: On-Resistance vs. Drain Current and Gate
Voltage (Note E)
R
DS(ON)
(mΩ
Ω
Ω
Ω)
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+01
1.0E+02
0.0 0.2 0.4 0.6 0.8 1.0 1.2
V
SD
(Volts)
Figure 6: Body-Diode Characteristics (Note E)
I
S
(A)
25°C
125°C
0.8
1.2
1.6
2
2.4
2.8
0 25 50 75 100 125 150 175 200
Temperature (°C)
Figure 4: On-Resistance vs. Junction Temperature
(Note E)
Normalized On-Resistance
V
GS
=4.5V
I
D
=20A
V
GS
=10V
I
D
=20A
0
10
20
30
40
50
60
2 4 6 8 10
V
GS
(Volts)
Figure 5: On-Resistance vs. Gate-Source Voltage
(Note E)
R
DS(ON)
(mΩ
Ω
Ω
Ω)
25°C
125°C
V
DS
=5V
V
GS
=4.5V
V
GS
=10V
I
D
=20A
25°C
125°C
0
20
40
60
80
0 1 2 3 4 5
V
DS
(Volts)
Fig 1: On-Region Characteristics (Note E)
I
D
(A)
V
GS
=3.5V
4V
6V
10V
4.5V
Rev 1: June 2011 www.aosmd.com Page 3 of 6
AOD4130/AOI4130
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
17
5
2
10
0
18
40
0
2
4
6
8
10
0 5 10 15 20 25 30
Q
g
(nC)
Figure 7: Gate-Charge Characteristics
V
GS
(Volts)
0
500
1000
1500
2000
2500
0 10 20 30 40 50 60
V
DS
(Volts)
Figure 8: Capacitance Characteristics
Capacitance (pF)
C
iss
0
100
200
300
400
500
0.0001 0.001 0.01 0.1 1 10
Pulse Width (s)
Figure 10: Single Pulse Power Rating Junction-to-
Case (Note F)
Power (W)
0.001
0.01
0.1
1
10
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10
Pulse Width (s)
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)
Z
θ
θ
θ
θJC
Normalized Transient
Thermal Resistance
C
oss
C
rss
V
DS
=30V
I
D
=20A
Single Pulse
D=T
on
/T
T
J,PK
=T
C
+P
DM
.Z
θJC
.R
θJC
T
on
T
P
D
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
T
J(Max)
=175°C
T
C
=25°C
10
µ
s
0.0
0.1
1.0
10.0
100.0
1000.0
0.01 0.1 1 10 100
V
DS
(Volts)
I
D
(Amps)
Figure 9: Maximum Forward Biased Safe
Operating Area (Note F)
10
µ
s
1ms
DC
R
DS(ON)
limited
T
J(Max)
=175°C
T
C
=25°C
100
µ
s
R
θJC
=2.9°C/W
Rev 1: June 2011 www.aosmd.com Page 4 of 6
AOD4130/AOI4130
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
17
5
2
10
0
18
40
0.001
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
Pulse Width (s)
Figure 16: Normalized Maximum Transient Thermal Impedance (Note H)
Z
θ
θ
θ
θJA
Normalized Transient
Thermal Resistance
Single Pulse
D=T
on
/T
T
J,PK
=T
A
+P
DM
.Z
θJA
.R
θJA
T
on
T
P
D
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
0
10
20
30
40
50
60
0 25 50 75 100 125 150 175
T
CASE
(°C)
Figure 13: Power De-rating (Note F)
Power Dissipation (W)
0
5
10
15
20
25
30
35
0 25 50 75 100 125 150 175
T
CASE
(°C)
Figure 14: Current De-rating (Note F)
Current rating I
D
(A)
1
10
100
1000
10000
0.00001 0.001 0.1 10 1000
Pulse Width (s)
Figure 15: Single Pulse Power Rating Junction-to-
Ambient (Note H)
Power (W)
T
A
=25°C
R
θJA
=50°C/W
10
100
1 10 100 1000
Time in avalanche, t
A
(µ
µµ
µs)
Figure 12: Single Pulse Avalanche capability (Note
C)
I
AR
(A) Peak Avalanche Current
T
A
=25°C
T
A
=150°C T
A
=100°C
T
A
=125°C
Rev 1: June 2011 www.aosmd.com Page 5 of 6
AOD4130/AOI4130
-
+
VDC
Ig
Vds
DUT
-
+
VDC
Vgs
Vgs
10V
Qg
Qgs Qgd
Charge
Gate Charge Test Circuit & Waveform
-
+
VDC
DUT Vdd
Vgs
Vds
Vgs
RL
Rg
Vgs
Vds
10%
90%
Resistive Switching Test Circuit & Waveforms
t t
r
d(on)
t
on
t
d(off)
t
f
t
off
Vdd
Vgs
Id
Vgs
Rg
DUT
-
+
VDC
L
Vgs
Vds
Id
Vgs
BV
I
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms
Ig
Vgs
-
+
VDC
DUT
L
Vds
Vgs
Vds
Isd
Isd
Diode Recovery Test Circuit & Waveforms
Vds -
Vds +
I
F
AR
DSS
2
E = 1/2 LI
dI/dt
I
RM
rr
Vdd
Vdd
Q = - Idt
AR
AR
t
rr
Rev 1: June 2011 www.aosmd.com Page 6 of 6