KA7500CD_NL - Fairchild Semiconductor

April 2009

KA7500C • Rev. 1.0.2

KA7500C — SMPS Controller

KA7500C

SMPS Controller

Features

 Internal Regulator Provides a Stable 5V Reference

Supply Trimmed to ±1% Accuracy

 Uncommitted Output TR for 200mA Sink or Source

Current

 Output Control for Push-Pull or Single-Ended

Operation

 Variable Duty Cycle by Dead-Time Control (Pin 4)

Complete PWM Control Circuit

 On-Chip Oscillator with Master or Slave Operation

 Internal Circuit Prohibits Double Pulse at Either

Output

Description

The KA7500C is used for the control circuit of the pulse-

width modulation switching regulator. The KA7500C

consists of 5V reference voltage circuit, two error

amplifiers, flip flop, an output control circuit, a PWM

comparator, a dead-time comparator, and an oscillator.

This device can be operated in the switching frequency

of 1kHz to 300kHz. The precision of voltage reference

(VREF) is improved up to ±1% with trimming. This

provides a better output voltage regulation. The

operating temperature range is -25°C ~ +85°C.

16-Lead DIP

16-Lead SOP

Ordering Information

Part Number Operating

Temperature Range Eco

Status Package Packing Method

KA7500C 16-Lead Dual Inline Package (DIP) Tube

KA7500CD Tube

KA7500CDTF

-25 to +85°C RoHS 16-Lead Small Outline Package (SOP) Tape and Reel

For Fairchild’s defini t i on of Eco St atus, pleas e visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

KA7500C • Rev. 1.0.2 2

KA7500C — SMPS Controller

Block Diagram

Figure 1. Block Diagram

KA7500C • Rev. 1.0.2 3

KA7500C — SMPS Controller

Typical Application

KA7500C

12

VCC

11

C2

8

C1

3

COMP IN PUT

-2

VREF 14

-15

+1

+16

CT

5

RT

6

D.T

4

GN D

7

E1

9

E2

10

O.C

13

KSA1010

VI=10V to 40V 1mH, 2A

VO=5V

IO=1A

GND

47Ω

150 Ω

1MΩ

5.1K

Ω

5. 1 KΩ

5.1KΩ

150 Ω

47KΩ0.001µF

+50µF

50V

+

0.1

+

50 µF

10 V

0.1µF

+

500µF

10V

Figure 2. Pulse-Width Modulated Step-Down Converter

KA7500C • Rev. 1.0.2 4

KA7500C — SMPS Controller

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 42 V

VC Collector Supply Voltage 42 V

IO Output Current 250 mA

VIN Amplifier Input Voltage VCC + 0.3 V

KA7500C 1

PD Power Dissipation KA7500CD 0.9 W

TOPR Operation Temperature Range -25 +85 °C

TSTG Storage Temperature Rang -65 +150 °C

TJ Junction Temperature +125 °C

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

VCC Power Supply Voltage 7 15 40 V

VC1, VC2 Collector Supply Voltage 30 40 V

IC1, IC2 Collector Output Current (Each Transition) 200 mA

VIN Amplifier Input Voltage 0.3 VCC - 2.0 V

IFB Current Into Feedback Terminal 0.3 mA

IREF Reference Output Terminal 10 mA

RT Timing Resistor 1.8 30.0 500.0

KΩ

CT Timing Capacitor 0.0047 0.0010 10.0000 µA

fOSC Oscillator Frequency 1 40 200 kHz

VIN_PWM PWM Input Voltage (Pins 3, 4, and 13) 0.3 5.3 V

KA7500C • Rev. 1.0.2 5

KA7500C — SMPS Controller

Electrical Characteristics

VCC = 20V, f = 10kHz, TA = -25°C to +85°C, unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

Reference Section

IREF=1mA, TA=25°C(1) 4.95 5.00 5.05

VREF Reference Output Voltage IREF=1mA 4.90 5.00 5.10

V

RLINE Line Regulation VCC=7V to 40V 2 25 mV

RLOAD Load Regulation IREF=1mA to 10mA 1 15 mV

ISC Short-Circuit Output Current VREF=0V 10 35 50 mA

Oscillation Frequency

CT=0.001µF, RT=30KΩ 40.0

CT=0.01µF, RT=12KΩ,

TA=25°C 9.2 10.0 10.8

fOSC Oscillation Frequency

CT=0.01µF, RT=12KΩ,

TA=TLOW to THIGH 9.0 12.0

kHz

Δf/Δt Frequency Change with Temperature CT=0.01µF, RT=12KΩ 2 %

Dead-Time Control Section

IBIAS Input Bias Current VCC=15V, 0V≤ V4≤ 5.25V -2 -10 µA

D(MAX) Maximum Duty Cycle VCC=15V, V4=0V, OC

Pin=VREF 45 %

Zero Duty Cycle 3.0 3.3

VITH Input Threshold Voltage Maximum Duty Cycle 0 V

Error Amplifier Section

VIO Input Offset Voltage V3=2.5V 2 10 mV

IIO Input Offset Current V3=2.5V 25 250 mA

IBIAS Input Bias Current V3=2.5V 0.2 1.0 µA

VCIM Common Mode Input Voltage 7V≤ VCC ≤ 40V -0.3 VCC V

GVO Open-Loop Voltage Gain 0.5V≤ V3 ≤ 3.5V 70 95 dB

BW Unit-Gain Bandwidth 650 kHz

PWM Comparator Section

VITH Input Threshold Voltage Zero Duty Cycle 4.0 4.5 V

ISINK Input Sink Current V3=0.7V -0.3 -0.7 mA

Output Section

VCE(SAT) Output Saturation Voltage Common

Emitter VE=0V, IC=200mA 1.0 1.3

VCC(SAT) Emitter-Follower VC=15V, IE=-200mA 1.5 2.5

V

IC(OFF) Collector Off-State Current VCC=40V, VCE=40V 2 100

IE(OFF) Emitter Off-State Current VCC=VC=40V, VE=40V -100

µA

Total Device

ICC Supply Current Pin6=VREF, VCC=15V 6 10 mA

Output Switching Characteristics

tR Rise Time, Common Emitter,

Common Collector 100 200

tF Fall Time, Common Emitter,

Common Collector 25 100

ns

Note:

1. This is guaranteed where the marking code of the package surface is over 027.

KA7500C • Rev. 1.0.2 6

KA7500C — SMPS Controller

Physical Dimensions

NOTES:

A) THIS DRAWING GOMPLIES WITH JEDEC MS-012

EXCEPT AS NOTED.

B) THIS DEMENSION IS OUTSIDE THE JEDEC MS-012 VALUE.

C) ALL DIMENSIONS ARE IN MILLIMETERS.

D) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,

AND TIE BAR EXTRUSIONS.

E) LANDPATTERN STANDARD: SOIC127P600X175-16AM.

F) DRAWING FILE NAME AND REVISION : M16EREV1

0.10 MAX C

0.303

0.153

LAND PATTERN RECOMMENDATION

(R0.20)

DETAIL A

SEE DETAIL A

0.90

0.50

(R0.10)

8¡Æ

TOP VIEW

SIDE VIEW

END VIEW

0.36

SEATING

PLANE

GAGE

PLANE

#1 8

916

9.08

8.68

10.10

9.70

6.00

1.27

(0.30) 0.51

0.36

4.15

3.75

A

B

0.20 CBA

1.80 MAX

1.65

1.45

0.05 MIN

c

1.75

1.27

0.65

5.60

B

#1

Figure 3. 16-Lead Small Outline Package (SOP)

Pack age drawings are provi ded as a servic e to customers considering Fairc h i l d components. Drawi ngs may change in any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emic onductor representative to v er ify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

KA7500C • Rev. 1.0.2 7

KA7500C — SMPS Controller

Physical Dimensions

16 9

81

NOTES: UNLESS OTHERWISE SPECIFIED

A THIS PACKAGE CONFORMS TO

JEDEC MS-001 VARIATION BB

B) ALL DIMENSIONS ARE IN MILLIMETERS.

D) CONFORMS TO ASME Y14.5M-1994

E) DRAWING FILE NAME: N16EREV1

19.68

18.66

6.60

6.09

C) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR PROTRUSIONS

3.42

3.17

3.81

2.92

(0.40)

2.54

17.78

0.58

0.35

1.78

1.14

5.33 MAX

0.38 MIN 8.13

7.62

0.35

0.20

15

0

8.69

A

TOP VIEW

SIDE VIEW

Figure 4. 16-Lead Dual Inline Package (DIP

Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor represent ative to v er ify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

KA7500C • Rev. 1.0.2 8

KA7500C — SMPS Controller