Data Sheet, V2.0, Oct. 2004
Microcontrollers
Never stop thinking.
C167CS-xC
16-Bit Single-Chip Microcontroller
C166 Family
Step CA
Edition 2004-10
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
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Terms of delivery and rights to technical change reserved.
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circuits, descriptions and charts stated herein.
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Data Sheet, V2.0, Oct. 2004
Microcontrollers
Never stop thinking.
C167CS-xC
16-Bit Single-Chip Microcontroller
C166 Family
Step CA
Template: mc_a5_ds_tmplt.fm / 4 / 2004-09-15
Controller Area Network (CAN): License of Robert Bosch GmbH
C167CS-xC (Bare Die Delivery)
Revision History: 2004-10 V2.0
Previous Version: V1.0, 2001-08 (Step BA)
Page Subjects (major changes since last revision)
all Layout of graphics and text structures has been adapted to company
documentation rules.
8ff Pad locations adapted to new silicon
20ff Die/Wafer characteristics adapted to new silicon
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
Data Sheet 3 V2.0, 2004-10
C167CS-xC Bare Die
Step CA
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Pad Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Mechanical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table of Contents
C167CS-xC16-Bit Single-Chip Microcontroller
C166 Family
Data Sheet 4 V2.0, 2004-10
1 Summary of Features
• High Performance 16-bit CPU with 4-Stage Pipeline
– 80/60 ns Instruction Cycle Time at 25/33 MHz CPU Clock
– 400/303 ns Multiplication (16 × 16 bit), 800/606 ns Division (32/16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 40/30 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input
• On-Chip Memory Modules
– 3 Kbytes On-Chip Internal RAM (IRAM)
– 8 Kbytes On-Chip Extension RAM (XRAM)
– 32 Kbytes On-Chip Program Mask ROM
• On-Chip Peripheral Modules
– 24-Channel 10-bit A/D Converter with Programmable Conversion Time
down to 7.8 µs
– Two 16-Channel Capture/Compare Units
– 4-Channel PWM Unit
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-
Synchronous)
– Two On-Chip CAN Interfaces (Rev. 2.0B active) with 2 ×15 Message Objects
(Full CAN/Basic CAN), can work on one bus with 30 objects
– On-Chip Real Time Clock
• Up to 16 Mbytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support
• Idle, Sleep, and Power Down Modes with Flexible Power Management
Data Sheet 5 V2.0, 2004-10
C167CS-xC Bare Die
Step CA
Summary of Features
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 111 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
Ordering Information
This document describes several derivatives of the C167 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
Note: The ordering codes for Mask-ROM versions are defined for each product after
verification of the respective ROM code.
For simplicity all versions are referred to by the term C167CS-xC throughout this
document.
Table 1 C167CS-xC Bare Die Derivative Synopsis (Step CA)
Type Ordering
Code
Program
Memory
Operating
Temperature
Wafers
SAK-C167CS-4RC Q67120-
D....
32 Kbytes ROM -40 to +125 °C Whole
SAK-C167CS-LC Q67120-
C2200
--- -40 to +125 °C Sawn
SAL-C167CS-LC1)
1) The designation SAL-… conforms to the valid ProElectron specification. These devices were named SAA-…
formerly.
Q67120-
C2274
--- -40 to +150 °C Sawn
SAL-C167CS-L33C1) Q67120-
C2275
--- -40 to +150 °C Sawn
C167CS-xC Bare Die
Step CA
General Device Information
Data Sheet 6 V2.0, 2004-10
2 General Device Information
2.1 Introduction
The C167CS-xC derivatives are high performance derivatives of the Infineon
C166 Family of full featured single-chip CMOS microcontrollers. They combine high
CPU performance (up to 16.5 million instructions per second) with high peripheral
functionality and enhanced IO-capabilities. They also provide clock generation via PLL
and various on-chip memory modules such as program ROM, internal RAM, and
extension RAM.
Figure 1 Logic Symbol
MCL04411
XTAL1
XTAL2
RSTOUT
ALE
NMI
RD
RSTIN
Port 0
16 Bit
16 Bit
Port 1
16 Bit
Port 2
15 Bit
Port 3
8 Bit
Port 4
VAREF AGND
V
WR/WRL
Port 5
16 Bit
Port 6
8 Bit
EA
READY
Port 7
8 Bit
8 Bit
Port 8
DD
VSS
V
C167CS-xC
Data Sheet 7 V2.0, 2004-10
C167CS-xC Bare Die
Step CA
General Device Information
2.2 Pad Configuration and Definition
Figure 2 Pad Configuration (top view)
Several pads of Port 4 and Port 8 can have CAN interface lines assigned to them.
Table 2 on the following pages lists the possible assignments.
C167CS-xC
Pad 1
Pad 146
y
x
0.0
0.0
Pad 36
Pad 37 Pad 73
Pad 111
Pad 110 Pad 74
Position of
Logo and Marking
C167CS-xC Bare Die
Step CA
General Device Information
Data Sheet 8 V2.0, 2004-10
Table 2 Pad Definitions and Functions
Symbol Pad
Num
In /
Out
Position [µm] Function
xy
VAREF 1 - 264 0 Reference voltage for the A/D converter.
VAGND 2 - 399 0 Reference ground for the A/D converter.
P5.10 3 I 533 0 Port 5 input, analog input AN10,
external up/down T6EUD.
P5.11 4 I 668 0 Port 5 input, analog input AN11,
external up/down T5EUD.
P5.12 5 I 802 0 Port 5 input, analog input AN12,
timer input T6IN.
P5.13 6 I 937 0 Port 5 input, analog input AN13,
timer input T5IN.
P5.14 7 I 1071 0 Port 5 input, analog input AN14,
external up/down T4EUD.
P5.15 8 I 1205 0 Port 5 input, analog input AN15,
external up/down T2EUD.
VSS 9 - 1355 0 Digital Ground.
VDD 10 - 1463 0 Digital Supply Voltage.
P2.0 11 I/O 1699 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC0IO.
P2.1 12 I/O 1854 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC1IO.
P2.2 13 I/O 2009 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC2IO.
P2.3 14 I/O 2164 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC3IO.
P2.4 15 I/O 2319 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC4IO.
P2.5 16 I/O 2475 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC5IO.
P2.6 17 I/O 2630 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC6IO.
P2.7 18 I/O 2785 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC7IO.
Data Sheet 9 V2.0, 2004-10
C167CS-xC Bare Die
Step CA
General Device Information
VSS 19 - 2940 0 Digital Ground.
VDD 20 - 3096 0 Digital Supply Voltage.
P2.8 21 I/O 3251 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC8IO,
Fast Interrupt EX0IN.
P2.9 22 I/O 3406 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC9IO,
Fast Interrupt EX1IN.
P2.10 23 I/O 3561 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC10IO,
Fast Interrupt EX2IN.
P2.11 24 I/O 3716 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC11IO,
Fast Interrupt EX3IN.
P2.12 25 I/O 3872 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC12IO,
Fast Interrupt EX4IN.
P2.13 26 I/O 4027 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC13IO,
Fast Interrupt EX5IN.
P2.14 27 I/O 4182 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC14IO,
Fast Interrupt EX6IN.
P2.15 28 I/O 4337 0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC15IO,
Fast Interrupt EX7IN, Timer T7 input T7IN.
P3.0 29 I/O 4493 0 Port 3 input/output (open drain, sp. threshold),
Timer T0 Input T0IN.
P3.1 30 I/O 4648 0 Port 3 input/output (open drain, sp. threshold),
Timer T6 Toggle Latch Output T6OUT.
P3.2 31 I/O 4803 0 Port 3 input/output (open drain, sp. threshold),
CAPREL Capture Input CAPIN.
P3.3 32 I/O 4958 0 Port 3 input/output (open drain, sp. threshold),
Timer T3 Toggle Latch Output T3OUT.
Table 2 Pad Definitions and Functions (cont’d)
Symbol Pad
Num
In /
Out
Position [µm] Function
xy
C167CS-xC Bare Die
Step CA
General Device Information
Data Sheet 10 V2.0, 2004-10
P3.4 33 I/O 5113 0 Port 3 input/output (open drain, sp. threshold),
Timer T3 ext.up/down T3EUD.
P3.5 34 I/O 5269 0 Port 3 input/output (open drain, sp. threshold),
Timer T4 Input T4IN.
VSS 35 - 5424 0 Digital Ground.
VDD 36 - 5579 0 Digital Supply Voltage.
P3.6 37 I/O 6011 432 Port 3 input/output (open drain, sp. threshold),
Timer T3 Input T3IN.
P3.7 38 I/O 6011 603 Port 3 input/output (open drain, sp. threshold),
Timer T2 Input T2IN.
P3.8 39 I/O 6011 773 Port 3 input/output (open drain, sp. threshold),
SSC Master-Rec./Slave-Transmit I/O MRST.
P3.9 40 I/O 6011 944 Port 3 input/output (open drain, sp. threshold),
SSC Master-Transmit/Slave-Rec. O/I MTSR.
P3.10 41 I/O 6011 1115 Port 3 input/output (open drain, sp. threshold),
ASC0 Clock/Data Output (Asyn./Syn.) TxD0.
P3.11 42 I/O 6011 1286 Port 3 input/output (open drain, sp. threshold),
ASC0 Data Input (Asyn.) or I/O (Syn.) RxD0.
P3.12 43 I/O 6011 1457 Port 3 input/output (open drain, sp. threshold).
44 O 6011 1628 High Byte Enable BHE,
High Byte Write Strobe WRH.
P3.13 45 I/O 6011 1798 Port 3 input/output (open drain, sp. threshold),
SSC Master(Slave) Clock Output(Input) SCLK.
P3.15 46 I/O 6011 1969 Port 3 input/output (open drain, sp. threshold).
47 O 6011 2140 System Clock Output (=CPU Clock) CLKOUT,
Programmable Frequency Output FOUT.
VDD 48 - 6011 2311 Digital Supply Voltage.
VSS 49 - 6011 2459 Digital Ground.
P4.0 50 I/O 6011 2594 Port 4 input/output, Segment Address Line A16.
P4.1 51 I/O 6011 2730 Port 4 input/output, Segment Address Line A17.
P4.2 52 I/O 6011 2865 Port 4 input/output, Segment Address Line A18.
P4.3 53 I/O 6011 3000 Port 4 input/output, Segment Address Line A19.
Table 2 Pad Definitions and Functions (cont’d)
Symbol Pad
Num
In /
Out
Position [µm] Function
xy
Data Sheet 11 V2.0, 2004-10
C167CS-xC Bare Die
Step CA
General Device Information
P4.4 54 I/O 6011 3136 Port 4 input/output, Segment Address Line A20,
CAN2 Receive Data Input CAN2_RxD.
P4.5 55 I/O 6011 3271 Port 4 input/output, Segment Address Line A21,
CAN1 Receive Data Input CAN1_RxD.
P4.6 56 I/O 6011 3407 Port 4 input/output, Segment Address Line A22
CAN1 Transmit Data Output CAN1_TxD
CAN2 Transmit Data Output CAN2_TxD.
P4.7 57 I/O 6011 3542 Port 4 input/output, Segment Address Line A23,
CAN1 Receive Data Input CAN1_RxD
CAN2 Transmit Data Output CAN2_TxD,
CAN2 Receive Data Input CAN2_RxD.
VDD 58 - 6011 3678 Digital Supply Voltage.
VSS 59 - 6011 3813 Digital Ground.
RD 60 O 6011 3949 External Memory Read Strobe RD.
WR(L) 61 O 6011 4084 External Memory Write(Low) Strobe WR (WRL).
READY 62 I 6011 4220 Ready Input.
ALE 63 O 6011 4355 Address Latch Enable Output.
EA 64 I 6011 4491 External Access Enable pin.
P0L.0 65 I/O 6011 4626 PORT0 input/output, Address/Data Line AD0.
P0L.1 66 I/O 6011 4761 PORT0 input/output, Address/Data Line AD1.
P0L.2 67 I/O 6011 4897 PORT0 input/output, Address/Data Line AD2.
P0L.3 68 I/O 6011 5032 PORT0 input/output, Address/Data Line AD3.
P0L.4 69 I/O 6011 5168 PORT0 input/output, Address/Data Line AD4.
P0L.5 70 I/O 6011 5303 PORT0 input/output, Address/Data Line AD5.
P0L.6 71 I/O 6011 5439 PORT0 input/output, Address/Data Line AD6.
P0L.7 72 I/O 6011 5574 PORT0 input/output, Address/Data Line AD7.
P0H.0 73 I/O 6011 5710 PORT0 input/output, Address/Data Line AD8.
VDD 74 - 5579 6141 Digital Supply Voltage.
VSS 75 - 5437 6141 Digital Ground.
P0H.1 76 I/O 5296 6141 PORT0 input/output, Address/Data Line AD9.
P0H.2 77 I/O 5154 6141 PORT0 input/output, Address/Data Line AD10.
Table 2 Pad Definitions and Functions (cont’d)
Symbol Pad
Num
In /
Out
Position [µm] Function
xy
C167CS-xC Bare Die
Step CA
General Device Information
Data Sheet 12 V2.0, 2004-10
P0H.3 78 I/O 5012 6141 PORT0 input/output, Address/Data Line AD11.
P0H.4 79 I/O 4871 6141 PORT0 input/output, Address/Data Line AD12.
P0H.5 80 I/O 4729 6141 PORT0 input/output, Address/Data Line AD13.
P0H.6 81 I/O 4587 6141 PORT0 input/output, Address/Data Line AD14.
P0H.7 82 I/O 4445 6141 PORT0 input/output, Address/Data Line AD15.
P1L.0 83 I/O 4304 6141 PORT1 input/output, Address Line A0,
analog input AN16.
P1L.1 84 I/O 4162 6141 PORT1 input/output, Address Line A1,
analog input AN17.
P1L.2 85 I/O 4020 6141 PORT1 input/output, Address Line A2,
analog input AN18.
P1L.3 86 I/O 3879 6141 PORT1 input/output, Address Line A3,
analog input AN19.
P1L.4 87 I/O 3737 6141 PORT1 input/output, Address Line A4,
analog input AN20.
P1L.5 88 I/O 3595 6141 PORT1 input/output, Address Line A5,
analog input AN21.
P1L.6 89 I/O 3454 6141 PORT1 input/output, Address Line A6,
analog input AN22.
P1L.7 90 I/O 3312 6141 PORT1 input/output, Address Line A7,
analog input AN23.
VDD 91 - 3170 6141 Digital Supply Voltage.
C167C
SMODE
92 I 3028 6141 Must be connected to VDD.1)
Standard oscillator mode, single-chip reset with
PORT0-configuration.
VSS 93 - 2887 6141 Digital Ground.
P1H.0 94 I/O 2745 6141 PORT1 input/output, Address Line A8.
P1H.1 95 I/O 2603 6141 PORT1 input/output, Address Line A9.
P1H.2 96 I/O 2462 6141 PORT1 input/output, Address Line A10.
P1H.3 97 I/O 2320 6141 PORT1 input/output, Address Line A11.
P1H.4 98 I/O 2178 6141 PORT1 input/output, Address Line A12,
Capture-Input/Compare-Output CC24.
Table 2 Pad Definitions and Functions (cont’d)
Symbol Pad
Num
In /
Out
Position [µm] Function
xy
Data Sheet 13 V2.0, 2004-10
C167CS-xC Bare Die
Step CA
General Device Information
P1H.5 99 I/O 2037 6141 PORT1 input/output, Address Line A13,
Capture-Input/Compare-Output CC25.
P1H.6 100 I/O 1895 6141 PORT1 input/output, Address Line A14,
Capture-Input/Compare-Output CC26.
P1H.7 101 I/O 1753 6141 PORT1 input/output, Address Line A15,
Capture-Input/Compare-Output CC27.
VDD 102 - 1611 6141 Digital Supply Voltage.
XTAL2 103 O 1480 6141 Output of the oscillator amplifier circuit.
XTAL1 104 I 1282 6141 Input to oscillator amplifier and internal clock
generator.
VSS 105 - 1140 6141 Digital Ground.
RSTIN 106 I/O 999 6141 Reset Input with Schmitt-Trigger characteristics,
output in bidirectional reset mode.
RST
OUT
107 O 857 6141 Internal Reset Indication Output.
NMI 108 I 715 6141 Non-Maskable Interrupt Input.
VSS 109 - 573 6141 Digital Ground.
VDD 110 - 432 6141 Digital Supply Voltage.
P6.0 111 I/O 0 5710 Port 6 input/output, Chip Select 0 Output CS0.
P6.1 112 I/O 0 5550 Port 6 input/output, Chip Select 1 Output CS1.
P6.2 113 I/O 0 5391 Port 6 input/output, Chip Select 2 Output CS2.
P6.3 114 I/O 0 5231 Port 6 input/output, Chip Select 3 Output CS3.
P6.4 115 I/O 0 5072 Port 6 input/output, Chip Select 4 Output CS4.
P6.5 116 I/O 0 4913 Port 6 input/output,
External Hold Request Input HOLD.
P6.6 117 I/O 0 4753 Port 6 input/output,
External Hold Acknowledge Output HLDA.
P6.7 118 I/O 0 4594 Port 6 input/output, Bus Request Output BREQ.
P8.0 119 I/O 0 4435 Port 8 input/output,
Capture-Input/Compare-Output CC16IO,
CAN1 Receive Data Input CAN1_RxD,
CAN2 Receive Data Input CAN2_RxD.
Table 2 Pad Definitions and Functions (cont’d)
Symbol Pad
Num
In /
Out
Position [µm] Function
xy
C167CS-xC Bare Die
Step CA
General Device Information
Data Sheet 14 V2.0, 2004-10
P8.1 120 I/O 0 4275 Port 8 input/output,
Capture-Input/Compare-Output CC17IO,
CAN1 Transmit Data Output CAN1_TxD,
CAN2 Transmit Data Output CAN2_TxD.
P8.2 121 I/O 0 4116 Port 8 input/output,
Capture-Input/Compare-Output CC18IO,
CAN1 Receive Data Input CAN1_RxD,
CAN2 Receive Data Input CAN2_RxD.
P8.3 122 I/O 0 3956 Port 8 input/output,
Capture-Input/Compare-Output CC19IO,
CAN1 Transmit Data Output CAN1_TxD,
CAN2 Transmit Data Output CAN2_TxD.
P8.4 123 I/O 0 3797 Port 8 input/output,
Capture-Input/Compare-Output CC20IO.
P8.5 124 I/O 0 3638 Port 8 input/output,
Capture-Input/Compare-Output CC21IO.
P8.6 125 I/O 0 3478 Port 8 input/output,
Capture-Input/Compare-Output CC22IO.
P8.7 126 I/O 0 3319 Port 8 input/output,
Capture-Input/Compare-Output CC23IO.
VDD 127 - 0 3160 Digital Supply Voltage.
VSS 128 - 0 3000 Digital Ground.
P7.0 129 I/O 0 2841 Port 7 input/output, (open drain, sp. threshold),
PWM Channel Output POUT0.
P7.1 130 I/O 0 2681 Port 7 input/output, (open drain, sp. threshold),
PWM Channel Output POUT1.
P7.2 131 I/O 0 2522 Port 7 input/output, (open drain, sp. threshold),
PWM Channel Output POUT2.
P7.3 132 I/O 0 2363 Port 7 input/output, (open drain, sp. threshold),
PWM Channel Output POUT3.
P7.4 133 I/O 0 2203 Port 7 input/output, (open drain, sp. threshold),
Capture-Input/Compare-Output CC28IO.
P7.5 134 I/O 0 2044 Port 7 input/output, (open drain, sp. threshold),
Capture-Input/Compare-Output CC29IO.
Table 2 Pad Definitions and Functions (cont’d)
Symbol Pad
Num
In /
Out
Position [µm] Function
xy
Data Sheet 15 V2.0, 2004-10
C167CS-xC Bare Die
Step CA
General Device Information
Note: All VSS pads and all VDD pads must be connected to the system ground and the
power supply, respectively.
The pad definitions and locations in this table are only valid for the indicated device
and design step.
P7.6 135 I/O 0 1884 Port 7 input/output, (open drain, sp. threshold),
Capture-Input/Compare-Output CC30IO.
P7.7 136 I/O 0 1725 Port 7 input/output, (open drain, sp. threshold),
Capture-Input/Compare-Output CC31IO.
P5.0 137 I 0 1474 Port 5 input, analog input AN0.
P5.1 138 I 0 1340 Port 5 input, analog input AN1.
P5.2 139 I 0 1205 Port 5 input, analog input AN2.
P5.3 140 I 0 1071 Port 5 input, analog input AN3.
P5.4 141 I 0 937 Port 5 input, analog input AN4.
P5.5 142 I 0 802 Port 5 input, analog input AN5.
P5.6 143 I 0 668 Port 5 input, analog input AN6.
P5.7 144 I 0 533 Port 5 input, analog input AN7.
P5.8 145 I 0 399 Port 5 input, analog input AN8.
P5.9 146 I 0 264 Port 5 input, analog input AN9.
1) Prepared to enable Enhanced Mode, i.e. low-power oscillator mode, single-chip reset with RD/ALE-
configuration.
Table 2 Pad Definitions and Functions (cont’d)
Symbol Pad
Num
In /
Out
Position [µm] Function
xy
C167CS-xC Bare Die
Step CA
General Device Information
Data Sheet 16 V2.0, 2004-10
Handling Of Unconnected Pads
Signal input stages may generate undesired switching noise and cross-current when left
open. Respect the following precautions for unconnected (not bonded) pads:
Table 3 Precautions for Unconnected Pads
Pad Type Recommended Action Related Pads
Power Supply Always connect! VDD, VSS, VAREF, VAGND
Standard IO pads Switch to output PORT0, PORT11), P2, P3,
P4, P6, P7, P8
1) The lower part of PORT1 (P1L) may be left open and its input stages can then be disabled via P1DIDIS.
Input port pads Disable input stages via P5DIDIS P5
Double-bond ports Connect port pad (43, 46), if the
alternate output (44, 47) is used.2)
2) Port pad is input in this case! If the port pad is used, the corresponding alternate output pad may be left open.
P3.12 (43/44), P3.15 (46/47)
Configuration lines Always connect! EA, C167CSMODE, RD3)
3) Pin RD can be used for configuration to disable the OWD. Otherwise it is held high by an internal pullup.
Required
control lines
Always connect! XTAL1, RSTIN, NMI
Optional
control lines
Can be left open RD3), WR(L), READY, ALE,
RSTOUT
Data Sheet 17 V2.0, 2004-10
C167CS-xC Bare Die
Step CA
Functional Description
3 Functional Description
As the standard packaged devices are made from this silicon the C167CS-xC dies
provide exactly the same functionality and behaviour. Also the DC characteristics and
AC characteristics are compatible with those of the packaged devices.
For a description of the functionality and the DC and AC parameters please refer to the
following documents (or later versions thereof):
• C167CS-4R/-L Data Sheet, Version 2.2, 2001-08
• C167CS Derivatives User’s Manual, Version 2.0, 2000-07
Figure 3 Block Diagram
C166-Core
CPU
Port 2
Interrupt Bus
XTAL
Osc / PLL
RTC WDT
32
16
Interrupt Controller 16-Level
Priority
PEC
External Instr. / Data
GPT
T2
T3
T4
T5
T6
SSC
BRGen
(SPI)
ASC0
BRGen
(USART)
ADC
10-Bit
16+8
Channels
PWM CCOM1
T0
T1
CCOM2
T7
T8
EBC
XBUS Control
External Bus
Control
IRAM
Dual Port
Internal
RAM
3 KByte
ProgMem
ROM
32 KByte
Data
Data
16
16
16
CAN1
Rev 2.0B active
Instr. / Data
Port 0
XRAM
6+2 KByte
Port 6
8
8
Port 1
16 16
16
Port 5 Port 3
15
Port 7
8
Port 8
8
Port 4
16
Peripheral Data Bus
16
CAN2
Rev 2.0B active
On-Chip XBUS (16-Bit Demux)
MCB04323_7CS
C167CS-xC Bare Die
Step CA
Electrical Parameters
Data Sheet 18 V2.0, 2004-10
4 Electrical Parameters
4.1 General Parameters
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the
voltage on VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Storage Conditions
The C167CS-xC dies may be stored for a certain time under the conditions described
below.
Table 4 Absolute Maximum Rating Parameters
Parameter Symbol Limit Values Unit Notes
min. max.
Storage temperature TST -65 150 °C
Junction temperature TJ-40 150 °C under bias
Voltage on VDD pins with
respect to ground (VSS)
VDD -0.5 6.5 V
Voltage on any pin with
respect to ground (VSS)
VIN -0.5 VDD + 0.5 V
Input current on any pin
during overload condition
-10 10 mA
Absolute sum of all input
currents during overload
condition
- |100| mA
Table 5 Bare Die Storage Conditions and Duration
Packing Environment Temperature Rel. Humidity Storage Time
Vacuum pack Air 15 … 30 °C < 60 % < 4 Months
Data Sheet 19 V2.0, 2004-10
C167CS-xC Bare Die
Step CA
Electrical Parameters
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the C167CS-xC. All parameters specified in the following sections refer to
these operating conditions, unless otherwise noticed.
Table 6 Operating Condition Parameters
Parameter Symbol Limit Values Unit Notes
min. max.
Digital supply voltage VDD 4.5 5.5 V Active mode,
fCPUmax = 33 MHz
2.5 1)
1) Output voltages and output currents will be reduced when VDD leaves the range defined for active mode.
5.5 V PowerDown mode
Digital ground voltage VSS 0 V Reference voltage
Overload current IOV -±5 mA Per pin 2) 3)
2) Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV >VDD+0.5V or VOV <VSS-0.5V). The absolute sum of input overload
currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,
etc.
3) Not subject to production test - verified by design/characterization.
Absolute sum of overload
currents
Σ|IOV|- 50 mA
3)
External Load
Capacitance
CL- 50 pF Pin drivers in
fast edge mode 4)
4) The timing is valid for pin drivers in high current or dynamic current mode. The reduced static output current
in dynamic current mode must be respected when designing the system.
Temperature of the
bottom side of the die
TD-40 150 °C SAL-C167CS-xC...
-40 125 °C SAK-C167CS-
xC...
C167CS-xC Bare Die
Step CA
Mechanical Parameters
Data Sheet 20 V2.0, 2004-10
5 Mechanical Parameters
Figure 4 Chip Outline
0.38
6.463
6.333
Dimensions in mm
0.082
0.082 0.108
x
y
0,0
min Typical
Data Sheet 21 V2.0, 2004-10
C167CS-xC Bare Die
Step CA
Mechanical Parameters
The wafers are glued to a plastic tape which is fixed within a metal frame (see Figure 5).
Wafers can be shipped in one piece or sawn into individual dies.
Note: Please refer also to the document "Bare Die Packing Information".
Table 7 Wafer Characteristics
Item Characteristic
Chips per wafer 674 (geometrically)
Metallization layers 2
Metallization material AlCu
Metallization thickness Met1: 400 nm, Met2: 800 nm
Metallization barrier material Ti
Metallization isolation SOG-CMP
Metallization material on pads AlSiCu (Al 98.5% - SI 1% - Cu 0.5%)
Passivation Oxide (200 nm) + nitride (300 nm)
+ polyimide (5.5±0.5 µm)
Backside metallization1)
1) The backside of the chip can either be left unconnected or must be connected to VSS.
None (silicon)
Inkdot diameter 1.0 - 1.3 typical
