1
Data sheet acquired from Harris Semiconductor
SCHS147I
Features
• Select One Of Eight Data Outputs
Active Low for 138, Active High for 238
• l/O Port or Memory Selector
• Three Enable Inputs to Simplify Cascading
• Typical Propagation Delay of 13 ns at VCC = 5 V,
CL = 15 pF, TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2 V to 6 V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5 V
• HCT Types
- 4.5-V to 5.5-V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8 V (Max), VIH = 2 V (Min)
- CMOS Input Compatibility, Il≤ 1µA at VOL, VOH
Description
The ’HC138, ’HC238, ’HCT138, and ’HCT238 are high-speed
silicon-gate CMOS decoders well suited to memory address
decoding or data-routing applications. Both circuits feature
low power consumption usually associated with CMOS
circuitry, yet have speeds comparable to low-power Schottky
TTL logic. Both circuits have three binary select inputs (A0,
A1, and A2). If the device is enabled, these inputs determine
which one of the eight normally high outputs of the
HC/HCT138 series go low or which of the normally low
outputs of the HC/HCT238 series go high.
Two active low and one active high enables (E1, E2, and E3)
are provided to ease the cascading of decoders. The
decoder’s eight outputs can drive ten low-power Schottky
TTL equivalent loads.
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC138F3A -55 to 125 16 Ld CERDIP
CD54HC238F3A -55 to 125 16 Ld CERDIP
CD54HCT138F3A -55 to 125 16 Ld CERDIP
CD54HCT238F3A -55 to 125 16 Ld CERDIP
CD74HC138E -55 to 125 16 Ld PDIP
CD74HC138M -55 to 125 16 Ld SOIC
CD74HC138MT -55 to 125 16 Ld SOIC
CD74HC138M96 -55 to 125 16 Ld SOIC
CD74HC238E -55 to 125 16 Ld PDIP
CD74HC238M -55 to 125 16 Ld SOIC
CD74HC238MT -55 to 125 16 Ld SOIC
CD74HC238M96 -55 to 125 16 Ld SOIC
CD74HC238NSR -55 to 125 16 Ld SOP
CD74HC238PW -55 to 125 16 Ld TSSOP
CD74HC238PWR -55 to 125 16 Ld TSSOP
CD74HC238PWT -55 to 125 16 Ld TSSOP
CD74HCT138E -55 to 125 16 Ld PDIP
CD74HCT138M -55 to 125 16 Ld SOIC
CD74HCT138MT -55 to 125 16 Ld SOIC
CD74HCT138M96 -55 to 125 16 Ld SOIC
CD74HCT238E -55 to 125 16 Ld PDIP
CD74HCT238M -55 to 125 16 Ld SOIC
CD74HCT238M96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
October 1997 - Revised August 2004
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
CD54/74HC138, CD54/74HCT138,
CD54/74HC238, CD54/74HCT238
High-Speed CMOS Logic 3- to 8-Line Decoder/
Demultiplexer Inverting and Noninverting
[ /Title
(CD74
HC138
,
CD74
HCT13
8,
CD74
HC238
,
CD74
HCT23
8)
/Sub-
ject
(High
Speed
2
Pinout
CD54HC138, CD54HCT138, CD54HC238, CD54HCT238
(CERDIP)
CD74HC138, CD74HCT138, CD74HCT238
(PDIP, SOIC)
CD74HC238
(PDIP, SOIC, SOP, TSSOP)
TOP VIEW
Signal names in parentheses are for ’HC138 and ’HCT138.
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
A1
A2
E1
E2
E3
GND
(Y7) Y7
VCC
Y1 (Y1)
Y2 (Y2)
Y3 (Y3)
Y4 (Y4)
Y5 (Y5)
Y6 (Y6)
Y0 (Y0)
15
14
13
12
10
7
9
11
1
2
3
5
6
4
E3
E2
E1
A2
A1
A0 Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
HC/HCT
238 HC/HCT
138
TRUTH TABLE ’HC138, ’HCT138
INPUTS
OUTPUTSENABLE ADDRESS
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
XXHXXXHHHHHHHH
LXXXXXHHHHHHHH
XHXXXXHHHHHHHH
HLLLLLLHHHHHHH
HLLLLHHLHHHHHH
HLLLHLHHLHHHHH
HLLLHHHHHLHHHH
HLLHLLHHHHLHHH
HLLHLHHHHHHLHH
HLLHHLHHHHHHLH
HLLHHHHHHHHHHL
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
TRUTH TABLE ’HC238, ’HCT238
INPUTS
OUTPUTSENABLE ADDRESS
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
XXHXXXLLLLLLLL
LXXXXXLLLLLLLL
XHXXXXLLLLLLLL
HLLLLLHLLLLLLL
HLLLLHLHLLLLLL
HLLLHLLLHLLLLL
HLLLHHLLLHLLLL
HLLHLLLLLLHLLL
HLLHLHLLLLLHLL
HLLHHLLLLLLLHL
HLLHHHLLLLLLLH
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Package Thermal Impedance, θJA (see Note 1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating, and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
- - ---- - - -V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- - ---- - - -V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
4
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2--2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC and
GND 0 5.5 - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
(Note 2) VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE:
2. For dual-supply systems, theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
A0-A2 1.5
E1, E2 1.25
E3 1
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC -55oC T O 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay tPLH, tPHL CL= 50pF 2 - - 150 - 190 - 225 ns
Address to Output 4.5 - - 30 - 38 - 45 ns
CL= 15pF 5 - 13 - - - - - ns
CL= 50pF 6 - - 26 - 33 - 38 ns
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
5
Enable to Output
HC/HCT138 tPLH, tPHL CL= 50pF 2 - - 150 - 190 - 265 ns
4.5 - - 30 - 38 - 53 ns
6 - - 26 - 33 - 45 ns
Output Transition Time
(Figure 1) tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Power Dissipation
Capacitance (Notes 3, 4) CPD CL= 15pF 5 - 67 - - - - - pF
Input Capacitance CIN - - - - 10 - 10 - 10 pF
HCT TYPES
Propagation Delay
Address to Output tPLH, tPHL CL= 50pF 4.5 - - 35 - 44 - 53 ns
CL= 15pF 5 - 14 - - - - - ns
Enable to Output
HC/HCT138 tPLH, tPHL CL= 50pF 4.5 - - 35 - 44 - 53 ns
Enable to Output
HC/HCT238 tPLH, tPHL CL= 15pF 4.5 - - 40 - 50 - 60 ns
Output Transition Time
(Figure 2) tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns
Power Dissipation
Capacitance (Notes 3, 4) CPD CL= 15pF 5 - 67 - - - - - pF
Input Capacitance CIN - - - - 10 - 10 - 10 pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD = VCC2 fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC -55oC T O 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
Test Circuits and Waveforms
FIGURE 7. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8688401EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8688401EA
CD54HC238F3A
CD54HC138F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC138F
CD54HC138F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8406201EA
CD54HC138F3A
CD54HC238F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8688401EA
CD54HC238F3A
CD54HCT138F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HCT138F
CD54HCT138F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8550401EA
CD54HCT138F3A
CD54HCT238F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8974501EA
CD54HCT238F3A
CD74HC138E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC138E
CD74HC138EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC138E
CD74HC138M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC138M
CD74HC138M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC138M
CD74HC138M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC138M
CD74HC138M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC138M
CD74HC138ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC138M
CD74HC138MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC138M
CD74HC138MT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC138M
CD74HC138MTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC138M
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD74HC138MTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC138M
CD74HC238E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC238E
CD74HC238EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC238E
CD74HC238M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M
CD74HC238M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M
CD74HC238M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M
CD74HC238M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M
CD74HC238ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M
CD74HC238MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M
CD74HC238MT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M
CD74HC238MTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M
CD74HC238MTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M
CD74HC238NSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M
CD74HC238NSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M
CD74HC238NSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M
CD74HC238PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ238
CD74HC238PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ238
CD74HC238PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ238
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD74HC238PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ238
CD74HC238PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ238
CD74HC238PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ238
CD74HC238PWT ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ238
CD74HC238PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ238
CD74HC238PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ238
CD74HCT138E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT138E
CD74HCT138EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT138E
CD74HCT138M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT138M
CD74HCT138M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT138M
CD74HCT138M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT138M
CD74HCT138M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT138M
CD74HCT138ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT138M
CD74HCT138MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT138M
CD74HCT238E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT238E
CD74HCT238EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT238E
CD74HCT238M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT238M
CD74HCT238M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT238M
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 4
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD74HCT238M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT238M
CD74HCT238M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT238M
CD74HCT238ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT238M
CD74HCT238MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT238M
CD74HCT238PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK238
CD74HCT238PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK238
CD74HCT238PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK238
CD74HCT238PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK238
CD74HCT238PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK238
CD74HCT238PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK238
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 5
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC138, CD54HC238, CD54HCT138, CD54HCT238, CD74HC138, CD74HC238, CD74HCT138, CD74HCT238 :
•Catalog: CD74HC138, CD74HC238, CD74HCT138, CD74HCT238
•Automotive: CD74HC138-Q1, CD74HC138-Q1
•Military: CD54HC138, CD54HC238, CD54HCT138, CD54HCT238
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC138M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC238M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC238NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC238PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC238PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT138M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT238M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT238PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC138M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HC238M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HC238NSR SO NS 16 2000 367.0 367.0 38.0
CD74HC238PWR TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC238PWT TSSOP PW 16 250 367.0 367.0 35.0
CD74HCT138M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HCT238M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HCT238PWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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