1
LTC3405
3405fa
■
High Efficiency: Up to 96%
■
Very Low Quiescent Current: Only 20
µ
A
During Operation
■
300mA Output Current at V
IN
= 3V
■
2.5V to 5.5V Input Voltage Range
■
1.5MHz Constant Frequency Operation
■
No Schottky Diode Required
■
Low Dropout Operation: 100% Duty Cycle
■
0.8V Reference Allows Low Output Voltages
■
Shutdown Mode Draws <1µA Supply Current
■
±2% Output Voltage Accuracy
■
Current Mode Operation for Excellent Line and
Load Transient Response
■
Overtemperature Protected
■
Low Profile (1mm) ThinSOT
TM
Package
The LTC
®
3405 is a high efficiency monolithic synchro-
nous buck regulator using a constant frequency, current
mode architecture. Supply current during operation is
only 20µA and drops to <1µA in shutdown. The 2.5V to
5.5V input voltage range makes the LTC3405 ideally suited
for single Li-Ion battery-powered applications. 100% duty
cycle provides low dropout operation, extending battery
life in portable systems.
Switching frequency is internally set at 1.5MHz, allowing
the use of small surface mount inductors and capacitors.
The internal synchronous switch increases efficiency and
eliminates the need for an external Schottky diode. Low
output voltages are easily supported with the 0.8V feed-
back reference voltage. The LTC3405 is available in a low
profile (1mm) ThinSOT package.
For new designs, refer to the LTC3405A data sheet. For
fixed 1.5V and 1.8V output versions, refer to the
LTC3405A-1.5/LTC3405A-1.8 data sheet.
■
Cellular Telephones
■
Personal Information Appliances
■
Wireless and DSL Modems
■
Digital Still Cameras
■
MP3 Players
■
Portable Instruments
Figure 1a. High Efficiency Step-Down Converter
1.5MHz, 300mA
Synchronous Step-Down
Regulator in ThinSOT
Figure 1b. Efficiency vs Load Current
VIN
CIN†
2.2µF
CER
VIN
2.7V
TO 5.5V
*
**
†
††
LTC3405
RUN
MODE
34.7µH**
22pF
887k
280k
3405 F01a
VOUT CONNECTED TO VIN FOR 2.7V < VIN < 3.3V
MURATA LQH3C4R7M34
TAIYO YUDEN LMK212BJ225MG
AVX TPSB336K006R0600
5
4
6
1
2
SW
VFB
GND
COUT††
33µF
VOUT*
3.3V
+
, LTC and LT are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation.
Protected by U.S. Patents, including 6580258, 5481178.
OUTPUT CURRENT (mA)
0.1
EFFICIENCY (%)
10 1000
100
95
90
85
80
75
70
65
60
3405 F01b
1 100
V
IN
= 3.6V
V
IN
= 4.2V
V
IN
= 5.5V
APPLICATIO S
U
FEATURES
TYPICAL APPLICATIO
U
DESCRIPTIO
U
2
LTC3405
3405fa
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
VFB
Feedback Current ●±30 nA
I
PK
Peak Inductor Current V
IN
= 3V, V
FB
= 0.7V, Duty Cycle < 35% 375 500 625 mA
V
FB
Regulated Feedback Voltage (Note 4) ●0.784 0.8 0.816 V
∆V
OVL
∆Output Overvoltage Lockout ∆V
OVL
= V
OVL
– V
FB
●20 50 80 mV
∆V
FB
Reference Voltage Line Regulation V
IN
= 2.5V to 5.5V (Note 4) ●0.04 0.4 %/V
V
LOADREG
Output Voltage Load Regulation 0.5 %
V
IN
Input Voltage Range ●2.5 5.5 V
I
S
Input DC Bias Current (Note 5)
Pulse Skipping Mode V
FB
= 0.7V, Mode = 3.6V, I
LOAD
= 0A 300 400 µA
Burst Mode® Operation V
FB
= 0.83V, Mode = 0V, I
LOAD
= 0A 20 35 µA
Shutdown V
RUN
= 0V, V
IN
= 4.2V 0.1 1 µA
f
OSC
Oscillator Frequency V
FB
= 0.8V ●1.2 1.5 1.8 MHz
V
FB
= 0V 210 kHz
R
PFET
R
DS(ON)
of P-Channel FET I
SW
= 100mA 0.7 0.85 Ω
R
NFET
R
DS(ON)
of N-Channel FET I
SW
= –100mA 0.6 0.90 Ω
I
LSW
SW Leakage V
RUN
= 0V, V
SW
= 0V or 5V, V
IN
= 5V ±0.01 ±1µA
V
RUN
RUN Threshold ●0.3 1 1.5 V
I
RUN
RUN Leakage Current ●±0.01 ±1µA
V
MODE
MODE Threshold ●0.3 1.5 2 V
I
MODE
MODE Leakage Current ●±0.01 ±1µA
Burst Mode is a registered trademark of Linear Technology Corporation.
LTC3405ES6
T
JMAX
= 125°C, θ
JA
= 250°C/ W
ORDER PART
NUMBER
(Note 1)
Input Supply Voltage .................................. –0.3V to 6V
MODE, RUN, V
FB
Voltages ......................... – 0.3V to V
IN
SW Voltage .................................. –0.3V to (V
IN
+ 0.3V)
P-Channel Switch Source Current (DC) ............. 400mA
N-Channel Switch Sink Current (DC) ................. 400mA
Peak SW Sink and Source Current .................... 630mA
Operating Temperature Range (Note 2) .. – 40°C to 85°C
Junction Temperature (Note 3)............................ 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
S6 PART MARKING
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 3.6V unless otherwise specified.
LTXQ
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
ELECTRICAL CHARACTERISTICS
RUN 1
GND 2
SW 3
6 MODE
5 V
FB
4 V
IN
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3405E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formula:
LTC3405: T
J
= T
A
+ (P
D
)(250°C/W)
Note 4: The LTC3405 is tested in a proprietary test mode that connects
V
FB
to the output of the error amplifier.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
3
LTC3405
3405fa
INPUT VOLTAGE (V)
2.5 3.0 4.0 5.0
EFFICIENCY (%)
4.5
95
90
85
80
75
70
65
60
55
50
3405 G02
3.5 5.5
Burst Mode OPERATION
V
OUT
= 1.8V
I
OUT
= 0.1mA
I
OUT
= 250mA
I
OUT
= 100mA
I
OUT
= 10mA
I
OUT
= 1mA
OUTPUT CURRENT (mA)
0.1
EFFICIENCY (%)
10 1000
100
90
80
70
60
50
40
30
20
10
0
3405 G03
1 100
V
IN
= 3.6V
V
IN
= 4.2V
V
IN
= 3.6V
V
IN
= 4.2V
V
OUT
= 1.8V
PULSE SKIPPING MODE
Burst Mode OPERATION
OUTPUT CURRENT (mA)
0.1
EFFICIENCY (%)
10 1000
100
90
80
70
60
50
40
3405 G04
1 100
V
IN
= 2.7V
V
IN
= 5.5V
V
IN
= 4.2V
V
IN
= 3.6V
V
OUT
= 1.8V
TYPICAL PERFOR A CE CHARACTERISTICS
UW
OUTPUT CURRENT (mA)
0.1
EFFICIENCY (%)
10 1000
100
90
80
70
60
50
40
3405 G05
1 100
V
IN
= 2.7V
V
IN
= 4.2V
V
OUT
= 1.3V
V
IN
= 3.6V
Efficiency vs Input Voltage Efficiency vs Output Current Efficiency vs Output Current
Efficiency vs Output Current
Reference Voltage vs
Temperature
Oscillator Frequency vs
Temperature
Oscillator Frequency vs
Supply Voltage Output Voltage vs Load Current RDS(ON) vs Input Voltage
TEMPERATURE (°C)
–50
REFERENCE VOLTAGE (V)
0.814
0.809
0.804
0.799
0.794
0.789
0.784 25 75
–25 0 50 100 125
V
IN
= 3.6V
3405 G06
TEMPERATURE (°C)
–50
FREQUENCY (MHz)
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
25 75
–25 0 50 100 125
V
IN
= 3.6V
3405 G07
SUPPLY VOLTAGE (V)
2
OSCILLATOR FREQUENCY (MHz)
1.8
1.7
1.6
1.5
1.4
1.3
1.2 34 56
3405 G08
LOAD CURRENT (mA)
0
OUTPUT VOLTAGE (V)
1.834
1.824
1.814
1.804
1.794
1.784
1.774 100 200 300 400
3405 G09
500 600
Burst Mode
OPERATION
PULSE SKIPPING MODE
V
IN
= 3.6V
INPUT VOLTAGE (V)
0
R
DS(0N)
(Ω)
245
3405 G10
13 67
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
MAIN SWITCH
SYNCHRONOUS
SWITCH
(From Figure1a Except for the Resistive Divider Resistor Values)
4
LTC3405
3405fa
RDS(ON) vs Temperature Dynamic Supply Current
Dynamic Supply Current
vs Temperature
Switch Leakage vs Temperature Switch Leakage vs Input Voltage
TEMPERATURE (°C)
–50
R
DS(ON)
(Ω)
1.2
1.0
0.8
0.6
0.4
0.2
025 75
–25 0 50 100 125
3405 G11
SYNCHRONOUS SWITCH
MAIN SWITCH
V
IN
= 2.7V V
IN
= 3.6V
V
IN
= 4.2V
SUPPLY VOLTAGE (V)
2
DYNAMIC SUPPLY CURRENT (µA)
1600
1400
1200
1000
800
600
400
200
0
34 56
3405 G12
VOUT = 1.8V
ILOAD = 0A
PULSE SKIPPING MODE
Burst Mode OPERATION
TEMPERATURE (°C)
–50
DYNAMIC SUPPLY CURRENT (µA)
600
500
400
300
200
100
025 75
–25 0 50 100 125
V
IN
= 3.6V
V
OUT
= 1.8V
I
LOAD
= 0A
3405 G13
PULSE SKIPPING MODE
Burst Mode OPERATION
TEMPERATURE (°C)
–50
SWITCH LEAKAGE (nA)
160
140
120
100
80
60
40
20
025 75
–25 0 50 100 125
V
IN
= 5.5V
RUN = 0V
3405 G14
MAIN SWITCH
SYNCHRONOUS
SWITCH
INPUT VOLTAGE (V)
0
SWITCH LEAKAGE (pA)
60
50
40
30
20
10
01234
3405 G15
56
RUN = 0V
MAIN SWITCH
SYNCHRONOUS
SWITCH
SW
5V/DIV
V
OUT
50mV/DIV
AC COUPLED
I
L
100mA/DIV
3405 G16
5µs/DIV
V
IN
= 3.6V
V
OUT
= 1.8V
I
LOAD =
20mA
SW
5V/DIV
V
OUT
20mV/DIV
AC
COUPLED
I
L
100mA/DIV
3405 G17
500ns/DIV
V
IN
= 3.6V
V
OUT
= 1.8V
I
LOAD =
20mA
RUN
2V/DIV
V
OUT
1V/DIV
I
L
200mA/DIV
3405 G18
100µs/DIV
V
IN
= 3.6V
V
OUT
= 1.8V
I
LOAD =
250mA
3405 G19
VOUT
100mV/DIV
AC
COUPLED
ILOAD
200mA/DIV
IL
200mA/DIV
40µs/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 0mA TO 250mA
PULSE SKIPPING MODE
TYPICAL PERFOR A CE CHARACTERISTICS
UW
(From Figure 1a Except for the Resistive Divider Resistor Values)
Burst Mode Operation
Pulse Skipping Mode Operation Start-Up from Shutdown Load Step
5
LTC3405
3405fa
UU
U
PI FU CTIO S
RUN (Pin 1): Run Control Input. Forcing this pin above
1.5V enables the part. Forcing this pin below 0.3V shuts
down the device. In shutdown, all functions are disabled
drawing <1µA supply current. Do not leave RUN floating.
GND (Pin 2): Ground Pin.
SW (Pin 3): Switch Node Connection to Inductor. This pin
connects to the drains of the internal main and synchro-
nous power MOSFET switches.
V
IN
(Pin 4): Main Supply Pin. Must be closely decoupled
to GND, Pin 2, with a 2.2µF or greater ceramic capacitor.
V
FB
(Pin 5): Feedback Pin. Receives the feedback voltage
from an external resistive divider across the output.
MODE (Pin 6): Mode Select Input. To select pulse skip-
ping mode, tie to V
IN
. Grounding this pin selects Burst
Mode operation. Do not leave this pin floating.
3405 G20
VOUT
100mV/DIV
AC
COUPLED
ILOAD
200mA/DIV
IL
200mA/DIV
40µs/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 20mA TO 250mA
PULSE SKIPPING MODE
VOUT
100mV/DIV
AC
COUPLED
ILOAD
200mA/DIV
IL
200mA/DIV
3405 G21
40µs/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 20mA TO 250mA
Burst Mode OPERATION 3405 G22
40µs/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 0mA TO 250mA
Burst Mode OPERATION
VOUT
100mV/DIV
AC
COUPLED
ILOAD
200mA/DIV
IL
200mA/DIV
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Load Step Load Step Load Step
(From Figure 1a Except for the Resistive Divider Resistor Values)
6
LTC3405
3405fa
FU CTIO AL DIAGRA
UU
W
+
–
+
–
+
–
+
–
OVDET
EA
+
–
I
RCMP
+–
I
COMP
5
1
RUN
OSC
SLOPE
COMP
OSC
FREQ
SHIFT
0.8V
0.85V
0.8V REF
SHUTDOWN
OV
0.4V
0.65V
SLEEP
V
IN
V
FB
6
MODE
EN
BURST
V
IN
S
R
RS LATCH SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
ANTI-
SHOOT-
THRU
Q
Q
5Ω
4
SW
3
GND
3405 BD
2
OPERATIO
U
(Refer to Functional Diagram)
Main Control Loop
The LTC3405 uses a constant frequency, current mode
step-down architecture. Both the main (P-channel
MOSFET) and synchronous (N-channel MOSFET) switches
are internal. During normal operation, the internal top
power MOSFET is turned on each cycle when the oscillator
sets the RS latch, and turned off when the current com-
parator, I
COMP
, resets the RS latch. The peak inductor
current at which I
COMP
resets the RS latch, is controlled by
the output of error amplifier EA. The V
FB
pin, described in
the Pin Functions section, allows EA to receive an output
feedback voltage from an external resistive divider. When
the load current increases, it causes a slight decrease in
the feedback voltage relative to the 0.8V reference, which
in turn, causes the EA amplifier’s output voltage to in-
crease until the average inductor current matches the new
load current. While the top MOSFET is off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse, as indicated by the current reversal
comparator I
RCMP
, or the beginning of the next clock
cycle.
7
LTC3405
3405fa
OPERATIO
U
until it reaches 100% duty cycle. The output voltage will then
be determined by the input voltage minus the voltage drop
across the P-channel MOSFET and the inductor.
Another important detail to remember is that at low input
supply voltages, the R
DS(ON)
of the P-channel switch
increases (see Typical Performance Characteristics). There-
fore, the user should calculate the power dissipation when
the LTC3405 is used at 100% duty cycle with low input
voltage (See Thermal Considerations in the Applications
Information section).
Low Supply Operation
The LTC3405 will operate with input supply voltages as
low as 2.5V, but the maximum allowable output current is
reduced at this low voltage. Figure 2 shows the reduction
in the maximum output current as a function of input
voltage for various output voltages.
(Refer to Functional Diagram)
Comparator OVDET guards against transient overshoots
>6.25% by turning the main switch off and keeping it off
until the fault is removed.
Burst Mode Operation
The LTC3405 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand. To enable Burst Mode operation, simply
connect the MODE pin to GND. To disable Burst Mode
operation and enable PWM pulse skipping mode, connect
the MODE pin to V
IN
or drive it with a logic high (V
MODE
>
1.5V). In this mode, the efficiency is lower at light loads,
but becomes comparable to Burst Mode operation when
the output load exceeds 25mA. The advantage of pulse
skipping mode is lower output ripple and less interference
to audio circuitry.
When the converter is in Burst Mode operation, the peak
current of the inductor is set to approximately 100mA re-
gardless of the output load. Each burst event can last from
a few cycles at light loads to almost continuously cycling
with short sleep intervals at moderate loads. In between
these burst events, the power MOSFETs and any unneeded
circuitry are turned off, reducing the quiescent current to
20µA. In this sleep state, the load current is being supplied
solely from the output capacitor. As the output voltage
droops, the EA amplifier’s output rises above the sleep
threshold signaling the BURST comparator to trip and turn
the top MOSFET on. This process repeats at a rate that is
dependent on the load demand.
Short-Circuit Protection
When the output is shorted to ground, the frequency of the
oscillator is reduced to about 210kHz, 1/7 the nominal
frequency. This frequency foldback ensures that the in-
ductor current has more time to decay, thereby preventing
runaway. The oscillator’s frequency will progressively
increase to 1.5MHz when V
FB
rises above 0V.
Dropout Operation
As the input supply voltage decreases to a value approach-
ing the output voltage, the duty cycle increases toward the
maximum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one cycle
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. Normally, this
results in a reduction of maximum inductor peak current
for duty cycles >40%. However, the LTC3405 uses a
patent-pending scheme that counteracts this compensat-
ing ramp, which allows the maximum inductor peak
current to remain unaffected throughout all duty cycles.
Figure 2. Maximum Output Current vs Input Voltage
SUPPLY VOLTAGE (V)
2.5
MAXIMUM OUTPUT CURRENT (mA)
600
500
400
300
200
100
03.0 3.5 4.0 4.5
3405 G23
5.0 5.5
V
OUT
= 1.8V
V
OUT
= 1.3V
V
OUT
= 2.5V
8
LTC3405
3405fa
APPLICATIO S I FOR ATIO
WUUU
The basic LTC3405 application circuit is shown in Figure 1.
External component selection is driven by the load require-
ment and begins with the selection of L followed by C
IN
and
C
OUT
.
Inductor Selection
For most applications, the value of the inductor will fall in
the range of 3.3µH to 10µH. Its value is chosen based on
the desired ripple current. Large value inductors lower
ripple current and small value inductors result in higher
ripple currents. Higher V
IN
or V
OUT
also increases the ripple
current as shown in equation 1. A reasonable starting point
for setting ripple current is ∆I
L
= 120mA (40% of 300mA).
∆=
()( )
−
⎛
⎝
⎜⎞
⎠
⎟
IfL
VV
V
L OUT OUT
IN
11
(1)
The DC current rating of the inductor should be at least
equal to the maximum load current plus half the ripple
current to prevent core saturation. Thus, a 360mA rated
inductor should be enough for most applications (300mA
+ 60mA). For better efficiency, choose a low DC-resistance
inductor.
The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the inductor current peaks fall to approximately
100mA. Lower inductor values (higher ∆I
L
) will cause this
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
Inductor Core Selection
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Tor-
oid or shielded pot cores in ferrite or permalloy materials
are small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
electrical characteristics. The choice of which style induc-
tor to use often depends more on the price vs size require-
ments and any radiated field/EMI requirements than on
what the LTC3405 requires to operate. Table 1 shows some
typical surface mount inductors that work well in LTC3405
applications.
Table 1. Representative Surface Mount Inductors
MAX DC
MANUFACTURER PART NUMBER VALUE CURRENT DCR HEIGHT
Taiyo Yuden LB2016T3R3M 3.3µH 280mA 0.2Ω1.6mm
Panasonic ELT5KT4R7M 4.7µH 950mA 0.2Ω1.2mm
Murata LQH3C4R7M34 4.7µH 450mA 0.2Ω2mm
Taiyo Yuden LB2016T4R7M 4.7µH 210mA 0.25Ω1.6mm
Panasonic ELT5KT6R8M 6.8µH 760mA 0.3Ω1.2mm
Panasonic ELT5KT100M 10µH 680mA 0.36Ω1.2mm
Sumida CMD4D116R8MC 6.8µH 620mA 0.23Ω1.2mm
C
IN
and C
OUT
Selection
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle V
OUT
/V
IN
. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
RMS capacitor current is given by:
CI
VVV
V
IN OMAX OUT IN OUT
IN
required IRMS ≅−
()
[]
12/
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that the capacitor
manufacturer’s ripple current ratings are often based on
2000 hours of life. This makes it advisable to further derate
the capacitor, or choose a capacitor rated at a higher
temperature than required. Always consult the manufac-
turer if there is any question.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). An ESR in the range of 100mΩ to
200mΩ is necessary to provide a stable loop. For the
LTC3405, the general rule for proper operation is:
0.1Ω ≤ C
OUT
required ESR ≤ 0.6Ω
ESR is a direct function of the volume of the capacitor; that
is, physically larger capacitors have lower ESR. Once the
ESR requirement for C
OUT
has been met, the RMS current
rating generally far exceeds the I
RIPPLE(P-P)
requirement.
The output ripple ∆V
OUT
is determined by:
∆≅∆ +
⎛
⎝
⎜⎞
⎠
⎟
V I ESR fC
OUT L OUT
1
8
9
LTC3405
3405fa
where f = operating frequency, C
OUT
= output capacitance
and ∆I
L
= ripple current in the inductor. For a fixed output
voltage, the output ripple is highest at maximum input
voltage since ∆I
L
increases with input voltage.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount configurations. In the case
of tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. An excellent choice is
the AVX TPS series of surface mount tantalum. These are
specially constructed and tested for low ESR so they give
the lowest ESR for a given volume. Other capacitor types
include Sanyo POSCAP, Kemet T510 and T495 series, and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
the output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input, V
IN
. At best, this ringing can couple to the output and
be mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause a
voltage spike at V
IN
, large enough to damage the part.
When ceramic capacitors are used at the output, their low
ESR cannot provide sufficient phase lag cancellation to
stabilize the loop. One solution is to use a tantalum
capacitor, with its higher ESR, to provide the bulk capaci-
tance and parallel it with a small ceramic capacitor to
reduce the ripple voltage as shown in Figure 3.
APPLICATIO S I FOR ATIO
WUUU
Another solution is to connect the feedback resistor to the
SW pin as shown in Figure 4. Taking the feedback informa-
tion at the SW pin removes the phase lag due to the output
capacitor resulting in a very stable loop. This configuration
lowers the load regulation by the DC resistance of the
inductor multiplied by the load current. This slight shift in
load regulation actually helps reduce the overshoot and
undershoot of the output voltage during a load transient.
V
IN
C
IN
2.2µF
CER
V
IN
2.7V
TO 4.2V LTC3405
RUN
MODE
34.7µH
22pF
887k
1M
3405 F03
5
4
6
1
2
SW
V
FB
GND
C
OUT1
1µF
CER
C
OUT2
22µF
TANT
V
OUT
1.5V
+
Figure 3. Paralleling a Ceramic with a Tantalum Capacitor
V
IN
C
IN
2.2µF
CER
V
IN
2.7V
TO 4.2V LTC3405
RUN
MODE
34.7µH
22pF
1M
887k
3405 F04
5
4
6
1
2
SW
V
FB
GND
C
OUT
4.7µF
CER
V
OUT
1.5V
Figure 4. Using All Ceramic Capacitors
A third solution is to use a high value resistor to inject a
feedforward signal at V
FB
mimicking the ripple voltage of
a high ESR output capacitor. The circuit in Figure 5 shows
how this technique can be easily realized. The feedforward
resistor, R2B, is connected to SW as in the previous
example. However, in this case, the feedback information
is taken from the resistive divider, R2A and R1, at the
output. This eliminates most of the load regulation degra-
dation due to the DC resistance of the inductor while
providing a stable operation similar to that obtained from
a high ESR tantalum type capacitor. Using this technique,
the extra feedforward resistor, R2B, must be accounted
for when calculating the resistive divider as follows:
RRARB
RA RB
RA RB
VV
R
R
OUT
22 2 22
22
08 1 2
1
==
+
=+
⎛
⎝
⎜⎞
⎠
⎟
|| •
.
Figure 5. Feedforward Injection in an
All Ceramic Capacitor Application
VIN
CIN
2.2µF
CER
VIN
2.7V
TO 4.2V LTC3405
RUN
MODE
34.7µH
22pF
R1
200k
R2B
1M
3405 F05
5
4
6
1
2
SW
VFB
GND
COUT1
4.7µF
CER
VOUT
1.5V
R2A
215k
10
LTC3405
3405fa
APPLICATIO S I FOR ATIO
WUUU
In pulse skipping mode, the LTC3405 is stable with a 4.7µF
ceramic output capacitor with V
IN
≤ 4.2V. For single Li-Ion
applications operating in pulse skipping mode, the circuit
shown in Figure 6 can be used
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
V
IN
C
IN
2.2µF
CER
V
IN
2.7V
TO 4.2V LTC3405
RUN
MODE
34.7µH
22pF
887k
1M
3405 F06
5
4
6
1
2
SW
V
FB
GND
C
OUT1
4.7µF
CER
V
OUT
1.5V
Figure 6. Using All Ceramic Capacitors in Pulse Skipping Mode
Output Voltage Programming
The output voltage is set by a resistive divider according
to the following formula:
VV
R
R
OUT =+
⎛
⎝
⎜⎞
⎠
⎟
08 1 2
1
.
(2)
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 7.
Figure 7. Setting the LTC3405 Output Voltage
Figure 8. Power Lost vs Load Current
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3405 circuits: V
IN
quiescent current and I
2
R
losses. The V
IN
quiescent current loss dominates the
efficiency loss at very low load currents whereas the I
2
R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 8.
V
FB
GND
LTC3405
0.8V ≤ V
OUT
≤ 5.5V
R2
R1
3405 F07
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
LOAD CURRENT (mA)
0.1
POWER LOST (W)
10 1000
1
0.1
0.01
0.001
0.0001
3405 F08
1 100
V
OUT
= 1.8V
V
IN
= 3.6V
V
OUT
= 3.3V
V
OUT
= 2.5V
V
OUT
= 1.3V
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger than
the DC bias current. In continuous mode, I
GATECHG
=
f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V
IN
and thus
their effects will be more pronounced at higher supply
voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
11
LTC3405
3405fa
ambient temperature of 70°C. From the typical perfor-
mance graph of switch resistance, the R
DS(ON)
of the
P-channel switch at 70°C is approximately 0.94Ω. There-
fore, power dissipated by the part is:
P
D
= I
LOAD2
• R
DS(ON)
= 84.6mW
For the SOT-23 package, the θ
JA
is 250°C/W. Thus, the
junction temperature of the regulator is:
T
J
= 70°C + (0.0846)(250) = 91.15°C
which is well below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (∆I
LOAD
• ESR), where ESR is the effective series
resistance of C
OUT
. ∆I
LOAD
also begins to charge or
discharge C
OUT
, which generates a feedback error signal.
The regulator loop then acts to return V
OUT
to its steady-
state value. During this recovery time V
OUT
can be moni-
tored for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C
LOAD
).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
APPLICATIO S I FOR ATIO
WUUU
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to
R
L
and multiply the result by the square of the average
output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
Thermal Considerations
In most applications the LTC3405 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3405 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such
as in dropout, the heat dissipated may exceed the maxi-
mum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.
To avoid the LTC3405 from exceeding the maximum
junction temperature, the user will need to do a thermal
analysis. The goal of the thermal analysis is to determine
whether the operating conditions exceed the maximum
junction temperature of the part. The temperature rise is
given by:
T
R
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3405 in dropout at an
input voltage of 2.7V, a load current of 300mA and an
12
LTC3405
3405fa
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3405. These items are also illustrated graphically in
Figures 9 and 10. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the V
IN
trace should be kept short, direct and
wide.
2. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of C
OUT
and ground.
3. Does the (+) plate of C
IN
connect to V
IN
as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node, SW, away from the sensitive
V
FB
node.
Design Example
As a design example, assume the LTC3405 is used in a
single lithium-ion battery-powered cellular phone
application. The V
IN
will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.25A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
and high load currents is important. Output voltage is
2.5V. With this information we can calculate L using
equation (1),
LfI
VV
V
LOUT OUT
IN
=
()
∆
()
−
⎛
⎝
⎜⎞
⎠
⎟
11
(3)
APPLICATIO S I FOR ATIO
WUUU
Figure 9. LTC3405 Layout Diagram
RUN
LTC3405
GND
SW
6
L1
R2
R3*
R1
C
FWD
BOLD LINES INDICATE HIGH CURRENT PATHS
*ADD R3 FOR APPLICATIONS USING A CERAMIC C
OUT
V
IN
V
OUT
3405 F09
4
5
1
3
+
–2
MODE
V
FB
V
IN
C
IN
+
–
C
OUT
LTC3405
GND
3405 F10
*ADD R3 WHEN USING CERAMIC C
OUT
PIN 1
V
OUT
V
IN
V
FB
VIA TO V
OUT
SW
VIA TO V
IN
VIA TO SW NODE VIA TO GND
C
OUT
C
IN
L1
R2
C
FWD
R3* R1
Figure 10. LTC3405 Suggested Layout
13
LTC3405
3405fa
APPLICATIO S I FOR ATIO
WUUU
Figure 11a Figure 11b
V
IN
C
IN†
2.2µF
CER
V
IN
2.7V
TO 4.2V LTC3405
RUN
MODE
36.8µH*
22pF
887k
412k
3405 F11a
5
4
6
1
2
SW
V
FB
GND
C
OUT
**
33µF
TANT
V
OUT
2.5V
+
*SUMIDA CMD4D11-6R8MC
** AVX TPSB336K006R0600
†
TAIYO YUDEN LMK212BJ225MG
TYPICAL APPLICATIO S
U
4.7µH*
22pF
200k
1M C
OUT
†
4.7µF
CER
332k
V
IN
C
IN
**
1µF
CER
*
**
†
MURATA LQH3C4R7M34
TAIYO YUDEN CERAMIC JMK107BJ105MA
TAIYO YUDEN CERAMIC JMK212BJ475MG
V
IN
2.7V
TO 4.2V LTC3405
RUN
MODE
3
3405 TA01a
5
4
6
1
2
SW
V
FB
GND
V
OUT
1.8V
Single Li-Ion to 1.8V/300mA Regulator
Optimized for Small Footprint and High Efficiency
Substituting V
OUT
= 2.5V, V
IN
= 4.2V, ∆I
L
= 100mA and
f = 1.5MHz in equation (3) gives:
LV
MHz mA
V
VH=−
⎛
⎝
⎜⎞
⎠
⎟≅µ
25
1 5 100 125
42 68
.
.( )
.
..
For best efficiency choose a 300mA or greater inductor
with less than 0.3Ω series resistance.
C
IN
will require an RMS current rating of at least 0.125A ≅
I
LOAD(MAX)
/2 at temperature and C
OUT
will require an ESR
of less than 0.6Ω and greater than 0.1Ω. In most cases,
a tantalum capacitor will satisfy this requirement.
OUTPUT CURRENT (mA)
0.1
EFFICIENCY (%)
10 1000
100
90
80
70
60
50
40
30
3405 F11b
1 100
V
IN
= 2.7V
V
IN
= 4.2V
V
IN
= 3.6V
OUTPUT CURRENT (mA)
0.1
EFFICIENCY (%)
10 1000
100
90
80
70
60
50
40
30
3405 TA01b
1 100
V
IN
= 2.7V
V
IN
= 4.2V
V
IN
= 3.6V
3405 TA01c
40µs/DIV
V
IN
= 3.6V
I
LOAD =
100mA TO 250mA
V
OUT
100mV/DIV
AC COUPLED
I
LOAD
200mA/DIV
I
L
200mA/DIV
For the feedback resistors, choose R1 = 412k. R2 can
then be calculated from equation (2) to be:
RVR k use
OUT
208 1 1 875 5 8=−
⎛
⎝
⎜⎞
⎠
⎟=
.. ; 87k
Figure 11 shows the complete circuit along with its
efficiency curve.
14
LTC3405
3405fa
TYPICAL APPLICATIO S
U
V
IN
C
IN
**
2.2µF
CER
V
IN
2.7V
TO 4.2V LTC3405
RUN
MODE
34.7µH*
22pF
887k
698k
3405 TA02a
5
4
6
1
2
SW
V
FB
GND
C
OUT1
***
1µF
CER
C
OUT2
†
22µF
TANT
V
OUT
1.8V
+
*
**
***
†
MURATA LQH3C4R7M34
TAIYO YUDEN CERAMIC LMK212BJ225MG
TAIYO YUDEN CERAMIC JMK107BJ105MA
AVX TAJA226M006R
Single Li-Ion to 1.8V/300mA Regulator
Using Ceramic and Tantalum Output Capacitors
VIN
CIN**
1µF
CER
*
**
†
TAIYO YUDEN LB2016T3R3M
TAIYO YUDEN CERAMIC JMK107BJ105MA
TAIYO YUDEN CERAMIC JMK212BJ475MG
VIN
2.7V
TO 4.2V LTC3405
RUN
MODE
33.3µH*
22pF
200k
1M
3405 TA03a
5
4
6
1
2
SW
VFB
GND
COUT
†
4.7µF
CER
VOUT
1.8V
332k
Single Li-Ion to 1.8V/200mA Regulator
Using All Ceramic Capacitors Optimized for Smallest Footprint
OUTPUT CURRENT (mA)
0.1
EFFICIENCY (%)
10 1000
100
90
80
70
60
50
40
30
3405 TA02b
1 100
V
IN
= 2.7V
V
IN
= 4.2V
V
IN
= 3.6V
OUTPUT CURRENT (mA)
0.1
EFFICIENCY (%)
10 1000
100
90
80
70
60
50
40
30
3405 TA03b
1 100
V
IN
= 2.7V
V
IN
= 4.2V
V
IN
= 3.6V
V
OUT
100mV/DIV
AC COUPLED
I
LOAD
200mA/DIV
I
L
200mA/DIV
3405 TA03c
40µs/DIV
V
IN
= 3.6V
I
LOAD =
100mA TO 250mA
V
OUT
100mV/DIV
AC COUPLED
I
LOAD
200mA/DIV
I
L
200mA/DIV
40µs/DIV
V
IN
= 3.6V
V
OUT
= 1.8V
I
LOAD =
100mA TO 250mA
3405 TA02c
15
LTC3405
3405fa
U
PACKAGE DESCRIPTIO
TYPICAL APPLICATIO S
U
Single Li-Ion to 1.8V/300mA Regulator
Using All Ceramic Capacitors Optimized for Lowest Profile, ≤1.2mm High
*
**
PANASONIC ELT5KT4R7M
TAIYO YUDEN CERAMIC JMK107BJ105MA
VIN
CIN**
1µF
CER
VIN
2.7V
TO 4.2V LTC3405
RUN
MODE
34.7µH*
200k
1M
5
4
6
1
2
SW
VFB
GND
COUT**
1µF
CER
COUT**
1µF
CER
VOUT
1.8V
22pF
332k
3405 TA04a
OUTPUT CURRENT (mA)
0.1
EFFICIENCY (%)
10 1000
100
90
80
70
60
50
40
30
3405 TA04b
1 100
V
IN
= 2.7V
V
IN
= 4.2V
V
IN
= 3.6V
V
OUT
100mV/DIV
AC COUPLED
I
LOAD
200mA/DIV
I
L
200mA/DIV
40µs/DIV
V
IN
= 3.6V
I
LOAD =
100mA TO 250mA
3405 TA04c
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
16
LTC3405
3405fa
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
LT/TP 0604 1K REV A • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2001
Single Li-Ion to 1.8V/300mA Regulator
All Ceramic Capacitors with Lowest Parts Count
V
OUT
100mV/DIV
AC COUPLED
I
LOAD
200mA/DIV
I
L
200mA/DIV
3405 TA05c
40µs/DIV
V
IN
= 3.6V
I
LOAD =
100mA TO 250mA
OUTPUT CURRENT (mA)
0.1
EFFICIENCY (%)
10 1000
100
90
80
70
60
50
40
30
3405 TA05b
1 100
V
IN
= 2.7V
V
IN
= 4.2V
V
IN
= 3.6V
4.7µH*
22pF
698k
887k COUT†
4.7µF
CER
VIN
CIN**
2.2µF
CER
*
**
†
MURATA LQH3C4R7M34
TAIYO YUDEN CERAMIC LMK212BJ225MG
TAIYO YUDEN CERAMIC JMK212BJ475MG
VIN
2.7V
TO 4.2V LTC3405
RUN
MODE
3
3405 TA05a
5
4
6
1
2
SW
VFB
GND
VOUT
1.8V
TYPICAL APPLICATIO S
U
