NEC's LOW POWER GPS RF RECEIVER BIPOLAR ANALOG + INTEGRATED CIRCUIT UPB1009K DESCRIPTION The PB1009K is a silicon monolithic IC developed for GPS receivers. This IC integrates a full VCO, second IF filter, 4-bit ADC, and digital control interface to reduce cost and mounting space. In addition, its power consumption is low. Moreover, use of a TCXO with frequency of 16.368 MHz/16.384 MHz, 14.4 MHz, 19.2 MHz, or 26 MHz switchable with an on-chip divider is possible. NEC's stringent quality assurance and test procedures ensure the highest reliability and performance. FEATURES * Double conversion : fREFin = 16.368 MHz, f1stIFin = 61.380 MHz, f2ndIFin = 4.092 MHz : fREFin = 14.4, 16.384, 19.2, 26 MHz, f1stIFin = 62.980 MHz, f2ndIFin = 2.556 MHz * Multiple system clocks : On-chip switchable frequency divider (1/N = 100, 3/256, 9/1024, 65/4096) * A/D converter : On-chip 4-bit A/D converter * High-density RF block : On-chip VCO tank circuit and 2ndIF filter * Supply voltage : VCC = 2.7 to 3.3 V * Low current consumption : ICC = 26.0 mA TYP. @ VCC = 3.0 V, N = 100 * High-density surface mountable : 44-pin plastic QFN APPLICATIONS * Consumer use GPS receiver of reference frequency 16.368 MHz, 2nd IF frequency 4.092 MHz * Consumer use GPS receiver of reference frequency 14.4, 16.384, 19.2, 26 MHz, 2ndIF frequency 2.556 MHz UPB1009K ORDERING Part Number PB1009K-E1-A INFORMATION Package 44-pin plastic QFN Supplying Form * 12 mm wide embossed taping * Pin 1 indicates pull-out direction of tape * Qty 1.5 kpcs/reel, Dry pack specification Remark To order evaluation samples, contact your nearby sales office. Part number for sample order: PB1009K 2 UPB1009K PRODUCT Type Clock Frequency Specific 1 chip IC LINE-UP (T A = +25C, VC C = 3.0 V) Part Number Functions (Frequency unit: MHz) VCC (V) ICC (mA) PB1009K Pre-amplifier + RF/IF downconverter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092 REF = 14.4, 16.384, 19.2, 26 1stIF = 62.980/2ndIF = 2.556 On-chip 4-bit ADC 2.7 to 3.3 26.0 PB1008K LNA + Pre-amplifier + RF/IF down-converter + PLL synthesizer REF = 27.456 1stIF = 175.164/2ndIF = 0.132 On-chip 2-bit ADC 2.7 to 3.3 18.0 PB1007K Pre-amplifier + RF/IF downconverter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092 2.7 to 3.3 25.0 PB1005K REF = 16.368 1stIF = 61.380/2ndIF = 4.092 CG (dB) Package 44-pin plastic QFN 100 to 120 Status New Device 36-pin plastic QFN 100 to 120 36-pin plastic QFN Available 36-pin plastic QFN Remark Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail. SYSTEM APPLICATION EXAMPLE GPS receiver RF block diagram PD1 and PD2 in the figure are Power Save Mode control pins. MS1 and MS2 in the figure are TXCO (GPS, W-CDMA, PDC, GSM) control pins. Caution This diagram schematically shows only the PB1009K's internal functions on the system. This diagram does not present the actual application circuits. 3 UPB1009K PIN 4 CONNECTION AND INTERNAL BLOCK DIAGRAM UPB1009K PIN EXPLANATION Pin No. Pin Name Function and Application 1 PreAMPout Output pin of preamplifier. 2 Rext Connect a resistor for the reference constantcurrent power supply to this pin. Ground this pin at 22 k. 3 RegGND Ground pin for regulator. 42 PreAmpVCC Power supply voltage pin for preamplifier. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 43 PreAmpGND Ground pin of preamplifier. 44 PreAmpin Input pin of preamplifier. 4 1stMIXin 1stMIX input pin. 5 1stMIXGND Ground pin for first MIX. 40 1stMIXVCC Power supply voltage pin for RF mixer. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 41 1stIFout Output pin of RF mixer. Insert an IFSAW filter between this pin and pin 37. The VCO oscillation signal can be monitored on this pin. Internal Equivalent Circuit 5 UPB1009K Pin No. 6 12 Pin Name MS1 MS2 Function and Application Low : 0 to 0.3 (V) MS1 : L MS2 : L TCXO : 16.368, 16.384 MHz High : VCC - 0.3 to MS1 : L TCXO : 19.2 MHz MS2 : H VCC (V) MS1 : H TCXO : 14.4 MHz MS2 : L MS1 : H TCXO : 26 MHz MS2 : H 6 11 CPout Output pin of charge pump. Connect external R and C to this pin to set a dumping factor and natural angular frequency (Isink = Isource = 0.45 mA). 13 Refin Reference frequency input pin. Connect an external reference transmitter (such as TCXO) to this pin. 14 PLLVCC Power supply voltage pin of PLL. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 15 PLLGND Ground pin of PLL. 16 CLKout Clock (fTCXO) output pin (IC test pin). Internal Equivalent Circuit UPB1009K Pin No. Pin Name Function and Application 7 LoVCC Power supply voltage pin of VCO. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 8 9 VCO1 VCO2 IC test pin. Leave this pin open when the PB1009K is mounted on board. 10 LoGND Ground pin of VCO. 17 IFGND Ground pin of IF block. 18 2ndIFout Output pin of IF amplifier. 38 1stIFin Input pin of second IF mixer. 39 IFVCC Power supply voltage pin of IF block. Internal Equivalent Circuit 7 UPB1009K Pin No. 8 Pin Name Function and Application 19 2ndIFin Input pin of ADC buffer amplifier. 20 DCOFFout Output pin of DC trimming OP amplifier. 21 DCOFFin DC trimming pulse input pin. Connect this pin to pin 20 via a capacitor to convert an input pulse signal into DC. 22 23 GNDana GNDbuf Ground pin for OP amplifier and ADC power supply. 24 VDDana Power supply pin for OP amplifier and ADC comparator. 25 VDDbuf Power supply pin for output driver amplifier of ADC. Connect this pin to the ground pin of the A/D converter via a bypass capacitor to reduce the high-frequency impedance. 26 GNDsub Ground pin of CMOS substrate. 27 28 29 30 D0 D1 D2 D3 Digital signal output pins. LSB = D0, MSB = D3 31 SCKin Sampling clock signal input pin. 32 AGCin AGC control pulse signal input pin. 33 AGCout AGC control signal output pin. Internal Equivalent Circuit UPB1009K Pin No. Pin Name Function and Application 34 VDDlogi Power supply voltage pin for power control logic. 35 GNDlogi Ground pin for power control logic. 36 37 PD1 PD2 Low : 0 to 0.3 (V) PD1 : L PD2 : L Sleep mode (all circuits off). High : VCC - 0.3 to PD1 : L PD2 : H Warm-up mode (PLL on). VCC (V) PD1 : H PD2 : L Calibration mode PD1 : H PD2 : H Active mode (all circuits on). Internal Equivalent Circuit . 9 UPB1009K ABSOLUTE MAXIMUM Parameter RATINGS Symbol Supply Voltage Test Conditions Ratings Unit VCC TA = +25C 3.6 V ICCTotal TA = +25C 100 mA Power Dissipation PD TA = +25C 266 mW Operating Ambient Temperature TA -40 to +85 C Storage Temperature Tstg -55 to +125 C Total Circuit Current Note N o t e Mounted on double-sided copper-clad 50 x 50 x 1.6 mm epoxy glass PWB RECOMMENDED OPERATING Parameter RANGE Symbol MIN. TYP. MAX. Unit Supply Voltage VCC 2.7 3.0 3.3 V Operating Ambient Temperature TA -30 +25 +85 C RF Input Frequency fRFin - 1 575.42 - MHz 1st LO Oscillating Frequency f1stLOin - 1 636.8/1 638.4 - MHz 1st IF Input Frequency f1stIFin - 61.38/62.98 - MHz 2nd LO Input Frequency f2ndLOin - 65.472/65.536 - MHz 2nd IF Input Frequency f2ndIFin - 4.092/2.556 - MHz Reference Input/Output Frequency fREFin fREFout - TCXO - MHz Clock mode control voltage (Low Level) VIL1 0 - 0.3 V Clock mode control voltage (High Level) VIH1 VCC - 0.3 - VCC V Power-down control voltage (Low Level) VIL2 0 - 0.3 V Power-down control voltage (High Level) VIH2 VCC - 0.3 - VCC V 10 UPB1009K POWER-DOWN CONTROL MODE The PB1009K consists of an RF block, an IF block, and a PLL block. By controlling reduction of power to each block (by applying a voltage to the PD1 and PD2 pins), the following four modes can be used. Mode No. Mode Name 1 Test Conditions RF Block IF Block (IF + ADC) PLL Block PD1 PD2 Active mode L H ON ON ON 2 Calibration mode H H OFF ON ON 3 Warm-up mode H L OFF OFF ON 4 Sleep mode L L OFF OFF OFF Caution To use only the active mode and sleep mode, fix PD1 to L and select the desired mode with PD2. REFERENCE CLOCK CONTROL MODE The divided frequency can be selected as follows so that it can be shared with the TCXO of each system. TCXO Frequency Test Conditions 1/N Phase Comparison Frequency PD1 PD2 16.368 MHz (GPS) 16.384 MHz (GPS) L L 1/100 16.368 MHz 16.384 MHz 19.2 MHz (W-CDMA) L H 3/256 19.2 MHz 14.4 MHz (PDC) H L 9/1024 14.4 MHz 26 MHz (GSM) H H 65/4096 26 MHz Caution When the reference clock frequency is 16.368 MHz, the 1stIF frequency and 2ndIF frequency are 61.38 MHz and 4.092 MHz, respectively. They are respectively 62.98 MHz and 2.556 MHz in all other cases. 11 UPB1009K ELECTRICAL CHARACTERISTICS (T A = +25C, VC C = 3.0 V) Parameter Rest current of overall IC in each mode Symbol Test Conditions MIN. TYP. MAX. Unit Rest status without input signal, including sampling clock. MS1 = L, MS2 = L Sleep mode Note Is PD1 = L, PD2 = L 1.3 2.2 3.5 mA Warm-up mode Iw PD1 = H, PD2 = L 10.5 13.0 15.5 mA Calibration mode Ic PD1 = H, PD2 = H 18.0 22.0 25.3 mA Active mode Ia PD1 = L, PD2 = H 22.1 26.0 30.0 mA Rest current of PLL block in each clock mode Current of PLL block. Overall current in calibration mode and active mode increases from that in basic mode (MS1 = L, MS2 = L). PD1 = H, PD2 = L. Current when 1/100 divider is used Iw1 MS1 = L, MS2 = L 5.3 6.5 7.6 mA Current when 256/3 divider is used Iw2 MS1 = L, MS2 = H 9.7 11.3 12.6 mA Current when 1024/9 divider is used Iw3 MS1 = H, MS2 = L 10.2 12.1 13.5 mA Current when 4096/65 divider is used Iw4 MS1 = H, MS2 = H 10.4 12.3 13.9 mA H application - - 20 A L application -20 - - A H application - - 20 A L application -20 - - A H application - - 1 A L application -1 - - A H application - - 1 A L application -1 - - A Maximum mode control pin current 6 pin MS1 12 pin MS2 36 pin PD1 37 pin PD2 <Pre-amplifier> fRFin = 1 575.42 MHz Circuit Current 1 ICC1 No Signals, 1-pin current 1.9 2.3 2.7 mA Power Gain GLNA PRFin = -40 dBm 12.5 15.0 17.5 dB Noise Figure NFLNA fRFin = 1 575 MHz - 3.0 3.5 dB -4.0 -2.7 - dBm Saturated Output Power PO(SAT)LNA PRFin = -10 dBm Input 1dB Compression Level PLNA-1 fRFin = 1 575.42 MHz -25 -21.8 - dBm Input 3rd Order Intercept Point IIP3LNA fRFin = 1 575.42 MHz, 1 576.42 MHz -12 -9.5 - dBm Input Inpedance ZinLNA - 11.2 - j21.5 - Output Inpedance ZoutLNA Calculated from S-parameter where input DC cut capacitance = 1 nF, output load L = 100 n, and DC cut capacitance = 1 nF - 16.4 - j136.6 - N o t e Most of the current flows into the ADC ladder resistor (VDDana GNDana) in the sleep mode, and the sleep mode current between other VCC (VDD) and GND is 10 A maximum. 12 UPB1009K ELECTRICAL CHARACTERISTICS (T A = +25C, VC C = 3.0 V) Parameter <RF mixer> Symbol MIN. TYP. MAX. Unit fRF = 1 575.42 MHz, f1stLOin = 1 636.80 MHz, f1stIF = 61.38 MHz Circuit Current 2 RF Conversion Gain Test Conditions ICC2 CGRF No Signals, 40 pin current 2.0 2.5 3.0 mA PRFMIXin = -40 dBm 14.0 16.1 19.0 dB - 12.8 16.0 dB Noise Figure SSBNF = 10*log (2*DSBNF (Linear value) -1) MHz Maximum IF Output PRFMIXin = -10 dBm -4.0 -0.8 - dBm Input 1dB Compression Level PRFMIX-1 fRFMIXin = 1 575.42 MHz -29.0 -25.5 - dBm Input 3rd Order Intercept Point IIP3RFMIX fRFMIXin = 1 575.42 MHz, 1 576.42 MHz f1stLO = 1 636.8 MHz -19.0 -17.2 - dBm Leakage of 1 636.8 MHz frequency when VCO oscillates correctly. - -34.5 -30 dBm - -54.7 -30 dBm Calculated from S-parameter where input DC cut capacitance = 1 nF and output DC cut capacitance = 1 nF - 50.1 - j22.3 - - 57.3 + j2.6 - 6.3 7.3 8.5 mA CG (GV) IF VAGC = 0.5 V 66.0 70.3 75.0 dB VAGC = 1.5 V 45.0 51.2 58.0 dB VAGC = 2.5 V 19.5 26.4 33.5 dB - 0.7 1.0 dB LO Leakage to IF Pin LOIF LO Leakage to RF Pin LORF Input Inpedance ZinMIX Output Inpedance ZoutMIX <IF mixer, LPF, IFamp> f1stFin = 61.38 MHz, f2ndLOin = 65.472 MHz, ZL = 2 k Circuit Current 3 IF Conversion Gain ICC3 No Signals, 39 pin current In Band Gain Fluctuation CG1 3.092 to 5.092 MHz Out Of Band Attenuation CG2 Gain difference at 4.092 MHz and 9.092 MHz, VAGC = 0.5 V 20.0 25.0 - dB Conversion Gain Range CG Range VAGC = 0 to 2.5 V 32.5 43.9 - dB - 13.7 17.5 dB 1.0 1.3 - VPP VAGC = 0.5 V -70.5 -64.4 - dBm VAGC = 1.5 V -53.5 -44.9 - dBm VAGC = 2.5 V -37.0 -30.6 - dBm f1stIFin1 = 61.28 MHz VAGC = 0.5 V -56.0 -51.3 - dBm f1stIFin2 = 61.38 MHz VAGC = 1.5 V -38.0 -30.7 - dBm f2ndLO = 65.472 MHz VAGC = 2.5 V -27.0 -21.4 - dBm - 69.3 - j4.8 - - 163 + j3.8 - IF SSB Noise Figure Maximum 2ndIF Output Input 1dB Compression Level Input 3rd Order Intercept Point NFIF V VAGC = 0.5 V (at maximum gain) Pin = -50 dBm, VAGC = 0.5 V PIF-1 IIP3IF Input Inpedance ZinIF Output Inpedance ZoutIF f1stIFin = 61.38 MHz Calculated from S-parameter where input DC cut capacitance = 1 nF and output DC cut capacitance = 100 nF 13 UPB1009K ELECTRICAL CHARACTERISTICS (T A = +25C, VC C = 3.0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit 8.0 9.5 10.6 mA -0.55 -0.45 -0.35 mA 0.35 0.45 0.55 mA Loop Filer Output (High Level) VCC-0.3 - - V Loop Filer Output (Low Level) - - 0.2 V - 0.2 1.6 VPP - 100 - MHz <PLL Synthesizer> Circuit Current 4 ICC4 Charge Pump Output Current Icpsink PLL, VCO current, MS1 = L, MS2 = L V13 pin = VCC/2 I cpsource Reference Input Level VREFin VCO Modulation Sensitivity KV Center frequency VCO Control Voltage VT When PLL is Locked 0.5 1.3 2.0 V C/N C/N 10 kHz 70.0 81.0 - dBc/Hz ICC5 3.1 4.1 5.4 mA ResAD - 4 - bits Sampling Clock fs - - 20 MHz Input Band Width ADBW 5.1 - - MHz - 0.2 1.0 LSB <A/D Converter> Circuit Current 5 Resolution Integral Non-linear Error INL DC characteristics Signal-to-noise Ratio SNR IF = 5.17 MHz, fs = 20.48 MHz 22.0 25.3 - dB Signal-to-noise + Distortion Ratio SINAD IF = 5.17 MHz, fs = 20.48 MHz 20.0 25.1 - dB Number ENOB ENOB = (SINAD-1.763)/6.02 3.0 3.9 - bits - -40 -30 dBc Total Harmonic Distortion Ratio THD IF = 5.17 MHz, fs = 20.48 MHz Second-degree to fifth-degree distortion components Remarks 1. Timing characteristics of ADC during normal operation A buffer amplifier is internally inserted before the ADC core of the PB1009K. The bias of this buffer amplifier is controlled by the signal input from the DC trim pin, and is used to eliminate the DC offset of the ADC. Because the ladder resistor of the ADC is directly connected between VDDana and GNDana, changes in VDDana affect the resolution of the ADC. 14 UPB1009K As illustrated in the operation timing chart below, the data of SampleN is pipeline delayed by 1.5 clocks during normal operation, and is output at the rising edge of the sample clock with output delay time Tod. When the operation is changed from normal operation to power-down operation, the status of the output data immediately before the power-down operation is retained (drive status). The following table shows each timing parameter for reference purposes. Symbol Parameter Test Conditions MIN. TYP. MAX. Unit CL = 10 pF, fclk = 19.2 MHz - - 12 ns T od Output Delay Tpld Pipeline Delay - 1.5 - clock T ds Sampling Delay (Aperture Delay) - 2 - ns T oh Output Hold Time 2 - - ns 15 UPB1009K Remarks 2. Power-down timing characteristics of ADC The output code of the ADC of the PB1009K is undefined for 7.5 clocks after the power-down signal is cleared when the ADC returns from the power-down status to normal operation. N o t e The output data is undefined from the start of the power-down operation to the 7.5th clock from the falling edge of the clock at which the power-down operation is cleared. 16 UPB1009K TYPICAL CHARACTERISTICS (T A = +25C, VC C = 3.0 V, unless otherwise specified) IC TOTAL CHARACTERISTICS Remark The graphs indicate nominal characteristics. 17 UPB1009K PRE-AMPLIFIER BLOCK CHARACTERISTICS Remark The graphs indicate nominal characteristics. 18 UPB1009K RF MIX BLOCK CHARACTERISTICS Remark The graphs indicate nominal characteristics. 19 UPB1009K IF BLOCK CHARACTERISTICS Remark The graphs indicate nominal characteristics. 20 UPB1009K VCO MODULATION SENSITIVITY C/N CHARACTERISTICS CHARACTERISTICS Remark The graphs indicate nominal characteristics. 21 UPB1009K SINAD MHz) CHARACTERISTICS OF A/D Remark The graphs indicate nominal characteristics. 22 CONVERTOR (IFin = 5.17 MHz, SCLKin = 20.48 UPB1009K MEASUREMENT CIRCUIT 23 UPB1009K DESCRIPTION OF Pin No. 24 PINS Pin Function OF TEST CIRCUIT Pin Name Pin No. Pin Function Pin Name 1 Preamplifier Input PreAmpin 14 DC Offset Input DCOFFin 2 Preamplifier Output PreAmpout 15 Digital Signal Output Pin D0 3 RF Mixer Input 1stMIXin 16 D1 4 MS1 MS1 17 D2 5 Prescaler Input Presin 18 D3 6 VCO Power Control Pin VCOc 19 Sampling Signal Input SCKin 7 VT Measurement Pin (Charge Pump CPout Output) 20 AGC Input AGCin 8 MS2 MS2 21 AGC Control Voltage Output AGCout 9 Reference Clock Input REFin 22 PD1 Output (Default onboard : GND) PD1 10 Clock Output CLKout 23 PD1 Output (Default on board : VCC) PD2 11 2ndIF Output 2ndIFout 24 1stIF Input 1stIFin 12 2ndIF Input 2ndIFin 25 1stIF Output 1stIFout 13 DC Offset Output DCOFFout UPB1009K APPLICATION PD1 PD2 0 0 1 CIRCUIT Power-down mode MS1 MS2 TCXO N Sleep mode (full off) 0 0 16.368/16.384 MHz 100 0 Warm-up mode (PLL on) 0 1 19.2 MHz 256/3 1 1 Calibration mode (PLL on) 1 0 14.4 MHz 1024/9 0 1 Active mode (full on) 1 1 26.0 MHz 4096/65 25 UPB1009K PACKAGE 44-PIN DIMENSIONS PLASTIC QFN (UNIT: mm) Caution The island pins located on the corners are needed to fabricate products in our plant, but do not serve any other function. Consequently the island pins should not be soldered and should remain non-connection pins. 26 UPB1009K NOTES ON CORRECT USE (1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent abnormal oscillation). (3) Keep the wiring length of the ground pins as short as possible. (4) Connect a bypass capacitor to the VCC pin. (5) High-frequency signal I/O pins must be coupled with the external circuit using a coupling capacitor. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your nearby sales office. Soldering Method Soldering Conditions Condition Symbol Infrared Reflow Peak temperature (package surface temperature) Time at peak temperature Time at temperature of 220C or higher Preheating time at 120 to 180C Maximum number of reflow processes Maximum chlorine content of rosin flux (% mass) : 260C or below : 10 seconds or less : 60 seconds or less : 12030 seconds : 3 times : 0.2%(Wt.) or below IR260 VPS Peak temperature (package surface temperature) Time at temperature of 200C or higher Preheating time at 120 to 150C Maximum number of reflow processes Maximum chlorine content of rosin flux (% mass) : 215C or below : 25 to 40 seconds : 30 to 60 seconds : 3 times : 0.2%(Wt.) or below VP215 Wave Soldering Peak temperature (molten solder temperature) Time at peak temperature Preheating temperature (package surface temperature) Maximum number of flow processes Maximum chlorine content of rosin flux (% mass) : 260C or below : 10 seconds or less : 120C or below : 1 time : 0.2%(Wt.) or below WS260 Partial Heating Peak temperature (pin temperature) Soldering time (per side of device) Maximum chlorine content of rosin flux (% mass) : 350C or below : 3 seconds or less : 0.2%(Wt.) or below HS350 Caution Do not use different soldering methods together (except for partial heating). 27 4590 Patrick Henry Drive Santa Clara, CA 95054-1817 Telephone: (408) 919-2500 Facsimile: (408) 988-0279 Subject: Compliance with EU Directives CEL certifies, to its knowledge, that semiconductor and laser products detailed below are compliant with the requirements of European Union (EU) Directive 2002/95/EC Restriction on Use of Hazardous Substances in electrical and electronic equipment (RoHS) and the requirements of EU Directive 2003/11/EC Restriction on Penta and Octa BDE. CEL Pb-free products have the same base part number with a suffix added. The suffix -A indicates that the device is Pb-free. The -AZ suffix is used to designate devices containing Pb which are exempted from the requirement of RoHS directive (*). In all cases the devices have Pb-free terminals. All devices with these suffixes meet the requirements of the RoHS directive. This status is based on CEL's understanding of the EU Directives and knowledge of the materials that go into its products as of the date of disclosure of this information. Restricted Substance per RoHS Concentration Limit per RoHS (values are not yet fixed) Concentration contained in CEL devices -A Not Detected Lead (Pb) < 1000 PPM Mercury < 1000 PPM Not Detected Cadmium < 100 PPM Not Detected Hexavalent Chromium < 1000 PPM Not Detected PBB < 1000 PPM Not Detected PBDE < 1000 PPM Not Detected -AZ (*) If you should have any additional questions regarding our devices and compliance to environmental standards, please do not hesitate to contact your local representative. Important Information and Disclaimer: Information provided by CEL on its website or in other communications concerting the substance content of its products represents knowledge and belief as of the date that it is provided. CEL bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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