M25P32-VME6TG - STMicroelectronics

1/39October 2004

M25P32

32 Mbit, Low Voltage, Serial Flash Memory

With 50MHz SPI Bus Interface

FEATURES SUMMARY

■32Mb it of Flash Memory

■Page Program ( up to 256 Bytes) i n 1.4ms

(typical)

■Sector Erase (512Kbit)

■Bul k Erase (32Mbit)

■2.7 to 3.6V Single Supply Vo ltage

■SPI Bus Compatible Serial Interface

■50MH z Clock Rate (maximum)

■D eep Power-down Mod e 1µA (typical)

■Ele ctronic Signatures

– JEDEC Standard Two-Byte Signature

(2016h)

– RES Inst ruction, One-Byt e, Signature

(15 h), for ba c k w ar d compa tibility

■More than 100,000 Erase/Program Cycles per

Sector

■More than 20 Yea r Data Retention

Figure 1. Packages

VDFPN8 (ME)

8x6mm (MLP8)

SO16 (MF)

300 mil width

M25P32

2/39

TABLE OF CONTENTS

FEATUR ES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. VDFPN Connect ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

SPI MOD ES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Bus Master an d Memory Devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Page Programmin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Sec tor Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Po lling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Status Re gister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. Prote cted Area Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 7. Hold Condition Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Figure 8. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Table 3. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

Write Enable (WR EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4

3/39

M25P32

Figure 9. Write Enable (WREN) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10.Write Disable (WRDI) Inst ruction Sequenc e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read Id entific ation (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Read Identification (RD ID) Data-Out Seque nce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 11.Read I dentification (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . . 15

Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

Table 6. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.Read S tatus Register (RDSR) Instruction Sequence and Data-O ut Sequen ce . . . . . . . 16

Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 13.Write Status Registe r (WRSR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 7. P rote ction Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 14.Read Dat a Bytes (READ) Instruction Sequen ce and Data-Out Sequence . . . . . . . . . . . 19

Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 15.Read Data Bytes at Higher Speed (FAST_READ ) Instruction Sequenc e and Data-Out Se-

quence 20

Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 16.P age Pro gram (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Sec tor Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2

Figure 17.S ector Eras e (SE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 18.B ulk Erase (BE) Instruction Sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Deep Power-down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 19.Deep P ower-down (DP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Releas e from D e e p Power-do w n and R e a d El e c t r onic Sig n atu re (RES ) . . . . . . . . . . . . . . . . . 25

Figure 20.Release from Deep Power-down and Read Electronic Signature (RES) Instruction Se-

quenc e and Data-Out Seque nce25

Figure 21.Release from Deep Power-down (RES) Instruction Sequence. . . . . . . . . . . . . . . . . . . . 26

POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 22.Power-up Tim ing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 8. Power-Up Tim ing and VWI Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 9. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0

Table 10. Operating C onditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 11. A C Measurement Condition s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

M25P32

4/39

Figure 23.AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0

Table 13. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 14. AC C haracteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 24.S erial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3

Figure 25.Write Protect Setup and Hold Timing during WRSR when SRW D=1 . . . . . . . . . . . . . . . 33

Figure 26.Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4

Figure 27.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PACKAGE M ECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5

Figure 28.M LP 8, 8-lead Very thin Dual Flat Pack age No lead, 8x6mm , Package Out line . . . . . . . 35

Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm , Package Mechanical Data35

Figure 29.S O16 wide – 16-lead Plastic Small Outline, 300 mils body width, Package Outline. . . . 36

Table 16. S O16 wide – 16-lead Plastic Small Outline, 300 mils body width, Mechanical Data. . . . 36

PAR T NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 17. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

REVISIO N HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 18. Document Revision Histo ry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5/39

M25P32

S UM MARY DESCR IPTION

The M25P32 is a 32Mbit (4M x 8) Serial Flash

Memory, with advanced write protection mecha-

nisms, acces se d by a high spee d SPI -compatible

bus.

The memory can be programmed 1 to 256 bytes at

a time, using the Page Progr am instruction.

The memory is organized as 64 sectors, each con-

taining 256 p ages. Each page is 256 bytes wide.

Thus, the whole memory can be viewed as con-

sisting of 16384 pages, or 4,194,304 bytes.

The whole mem ory can b e erased usi ng the Bulk

Erase instruction, or a sector a t a time, using the

Sector Erase instruction.

Figure 2. Logic Diagram

Table 1. Signal Names

Figu re 3. V DFPN Conn e ct i on s

Note : 1. There is an expose d die paddle on the u nderside of the

MLP8 package. This is pulled, internally, to VSS, and

must not be allowed to be connected to any other voltage

or si gnal line on the PCB.

2. See PACKAGE MECHANICAL section for package di-

mens i ons, and how to identify pi n-1.

Figu re 4. S O Connecti ons

N ot e: 1. DU = Don’t Use

2. See PACKAGE MECHANICAL section for package di-

mens i ons, and how to identify pi n-1.

C Serial Clock

D Serial Data Input

Q Serial Data Outp ut

SChip Select

W Write Protect

HOLD Hold

VCC Supply Voltage

VSS Ground

AI07483

VCC

M25P32

HOLD

VSS

AI08518

5DVSS C

HOLDQ

M25P32

AI07484B

DU DU

VCC

HOLD

DUDU

M25P32

9WQ VSS

M25P32

6/39

SIGNAL DESCRIPTION

Serial Data Output (Q). This output signal is

used to transfer data serially out of the device.

Data is shifted out on the falling edge of Serial

Clock (C).

Serial Data I n put (D). Thi s input signal is used to

transfer data seriall y into t he devi ce. It receives in-

structions, addresses, and the data to be pro-

grammed. Values are latched on the rising edge of

Serial Clock (C).

Serial Clock (C). This input signal provides the

timing of the s erial interface. Instr uctions, address-

es, or data present at Serial Data Input (D) are

latched on the ris ing edge of Serial Clock ( C). Data

on Serial Data Output (Q) changes after the falling

edge of Serial Clock (C).

Chip Select (S). When this input signal is High,

the device is deselected and Serial Data Output

(Q) is at high impedance. Unless an internal Pro-

gram, Erase or Write Status Register cycle is in

progress, the device wi ll b e in the Stan dby Power

mode (this is not the Deep Power-down mode).

Driving Chip Select (S) Low enables the device,

placing it in the Active Power mode.

After Power-up, a falling ed ge on Chip Select (S)

is required prior to the start of any instruction.

Hold (HOLD). The Hold (HOLD) signal is used to

pause any serial communications with the device

without deselecti ng the device.

During the Hold condition, the Serial Data Ou tput

(Q) is high impedance, and Serial Data Input (D)

and Serial Clock (C) are Don’t Care.

To start the Hol d condit ion, the device must be se-

lected, wit h C h ip S e lec t (S) driven Low.

Write Protect (W). The main purpose of this in-

put signal is to freeze the size of the area of m em-

ory that is protected against program or erase

instructions (as specified by the values in t he BP2,

BP1 and BP0 bits of the Stat us Register).

7/39

M25P32

SPI MODES

These dev ices can be drive n by a microcont ro ller

with its SPI peripheral running in either of the two

following modes:

– CPOL=0, CPHA=0

– CPOL=1, CPHA=1

For these two modes, input data is latched in on

the rising edge of Serial Clock (C), and output data

is available from the falling edge of Serial Clock

(C).

The difference between t he two modes, as shown

in Figure 6., is the clock polarity when the bus

master is in Stand-by mode and not transferring

data:

– C remains at 0 for (CPOL=0, CPHA=0)

– C remains at 1 for (CPOL=1, CPHA=1)

Figure 5. Bus Master and Memo ry Devices on the SPI Bus

Note: The Write Protect (W) an d Hold ( HOLD) signal s should b e driven, Hi gh or Low as appropri ate.

Figure 6. SPI Mo des S upport ed

AI03746D

Bus Master

(ST6, ST7, ST9,

ST10, Others) SPI Memory

Device

SDO

SDI

SCK

CQD

SPI Memory

Device

CQD

SPI Memory

Device

CQD

CS3 CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

WHOLD WHOLD WHOLD

AI01438B

MSB

CPHA

CPOL

MSB

M25P32

8/39

OPERAT ING FEA TURES

Page P rogramm i ng

To program one dat a byte, two ins tructions ar e re-

quired: Write Enable (WREN), which is one byte,

and a Page Program (PP) sequence, which con-

sists of four bytes plus data. This is followed by the

internal Program cycle (of duration tPP).

To spread this overhead, the Page P rogram (PP)

instruction allows up to 256 bytes to be pro-

grammed at a time (changing bits from 1 to 0), pro-

vided that they lie in consecutive addresses on the

same page of memory.

Sector Erase and Bulk Eras e

The Page Program (PP) instruction allows bits to

be reset from 1 to 0. Before this can be applied, the

bytes of memo ry need to hav e been erased to a ll

1s (FFh). This can be achieved either a s ector at a

time, using the Sector Erase (SE) instruction, or

throughout the entire memory, using the Bulk

Erase (BE) instruction. This starts an internal

Erase cycle (of duration tSE or tBE).

The Erase instruction must be preceded by a Write

Enable (WREN) instruction.

Polling Duri ng a Write, Program or Erase Cycle

A further improvement in the time to Write Status

BE) can be achieved by not waiting for the worst

case delay (tW, tPP, tSE, or tBE). The Write In

Progress (WIP) bit is provi ded in the S tatus Regis-

ter so tha t the application program can m onitor its

value, polling it to establish when the previous

Write cycle, Program cycle or Erase cycle is com-

plete.

Active Power, Standby Power and Deep

Power- Down Modes

When Chip Select (S) is Low, the device is select-

ed, and in the A ctive Power mode.

When Chip Sel ec t ( S) is High, the device is dese-

lected, but could remain i n t he Acti ve P ower mode

until all internal cycles have completed (Pro gram,

Erase, Write Status Register). The device then

goes in to the Standby Power mode. The device

consumption drops to ICC1.

The Deep Power-down mode is ente red when the

specific ins truction (the Deep Power-down (DP) in-

struction) is executed. The device consumption

drops further to ICC2. The device remains in this

mode until another specific instruction (the Re-

lease from Deep Power-down and Read Elec tron-

ic Signature (RES) instruct ion) is executed.

All other instructions are igno red while the device

is in the Deep Power-down mode. This can be

used as an ext ra soft ware protection mecha nism,

when the device is not in active use, to protect the

device from inadvertent Write, Program or Erase

instructions.

Status Reg ister

The Status Register contains a number of status

and control bits that can be read or set (as appro-

priate) by specific instructions.

WIP bit. The Write In Progress (WIP) bit indicates

whether the memory is busy with a Write Status

WE L bi t. The Write Enable Latch (WEL) bit indi-

cates the status of the int ernal Write Enable Latch.

BP2, BP1, BP0 bits. The Block Protect (BP2,

BP1, BP0) bits are non-volatile. They define the

size of the area to be software protected against

Program and Eras e instructions.

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware

Protected mode. In this mode, the non-volatile bits

of the Status Register (SRWD, BP2, BP1, BP0)

become read-only bits.

9/39

M25P32

P rotec t i on Modes

The environments where non-vol atile memory de-

vices are used can be very noisy. No SPI device

can operate correct ly in the presence of excessive

noise. To help combat this, the M25P32 features

the following data protection m echanisms:

■Powe r On Reset and an internal timer (tPUW)

can provide protecti on against inadvertant

changes while the power supply is outside the

operat ing specificatio n.

■Program , Erase and Write Status Regis ter

instructions are checked that they c onsi st of a

numb er of clock pulses that is a multipl e of

eight, before they are accepted for execution.

■All instructions that modify data must be

prece ded by a Write Enable (WREN)

instruction to set the Write Enable Latch

(WE L) bit. This bit is returned to its reset state

by the following events:

– Power-up

– Write Disable (WRDI) instruction

completion

– Write Status Register (WRSR) instr uction

completion

– Page Progr am (PP) instruction completion

– Sector Erase (SE) instruction comple tion

– Bulk Erase (BE) i nstruction completion

■The Bl oc k Pr o te ct (BP2, BP1, BP0 ) b its allow

part of the memory to be configured as read-

only. This is the Software Protected Mode

(SPM).

■The Write Protect (W) si gnal allows the Bl ock

Protec t (BP2, BP1, BP0) bits and Status

Regi st er Write Di sable (SRWD) bit to be

protected. This is the Hardware Protected

Mode (HPM).

■In addition to the low power consumption

feature, the Deep Power-down mode offers

extra software protection from inad vertant

Wri t e, Program and Erase instructions, as all

instructions are ignored ex cept one parti cular

instruction (t he Release from Deep Power-

down instruction).

Table 2. Protected Area Sizes

Note: 1. The device is r eady to accept a Bu lk E rase in st ruction if, a nd only if, all Block Protect (BP2, BP1, BP0) are 0.

Status Register

Content Memory Content

BP2

Bit BP1

Bit BP0

Bit Protected Area Unprotected Area

0 0 0 none All sectors1 (64 sectors: 0 to 63)

0 0 1 Upper 64th (Sector 63) Lower 63/64ths (63 sectors: 0 to 62)

0 1 0 Upper 32nd (two sectors: 62 and 63) Lower 31/32nds (62 sectors: 0 to 61)

0 1 1 Upper sixteenth (four sectors: 60 to 63) Lower 15/16ths (60 sectors: 0 to 59)

1 0 0 Upper eighth (eight sectors: 56 to 63) Lower seven-eighths (56 sectors: 0 to 55)

1 0 1 Upper quarter (sixteen sectors: 48 to 63) Lower three-quarters (48 sectors: 0 to 47)

1 1 0 Upper half (thirty-two sectors: 32 to 63) Lower half (32 sectors: 0 to 31)

1 1 1 All sectors (64 sectors: 0 to 63) none

M25P32

10/39

Hold Condition

The Hold (HOLD) signal is used to pause any se-

rial comm unication s with the device without reset-

ting the clocking sequence. However, taking this

signal Low does not terminate any Write Status

in progress.

To enter the Hold condition, the device must be

sele c te d , wit h C hip Select (S) Low.

The Hold condit ion start s on the falling edge of the

Hold (HOLD) signal, provided that this coincides

with Serial Clock (C) bei ng L ow (as shown in Fig-

ure 7.).

The Hold condition ends on the rising edge of the

Hold (HOLD) signal, provided that this coincides

with Serial Clock (C) being Low.

If the falling edge does not coincide with Serial

Clock (C) being Low, the Hold condition s tarts af-

ter Serial Clock (C) nex t goes Low. Simil arly, if the

rising edge does not coi ncide with Seri al Clock (C)

being Low, the Hold condition ends after Serial

Clock (C) next goes Low. (This is shown in Figure

7.).

During the Hold condition, the Serial Data Ou tput

(Q) is high impedance, and Serial Data Input (D)

and Serial Clock (C) are Don’t Care.

Normally, the device is kept selected, with Chip

Select (S) driven Low, for the whole duration of the

Hold condition. This is to ensure that the state of

the internal logic remains unchanged f rom the mo-

ment of entering the Hold condition.

If Chip Select ( S) go es High while t he d ev ice is in

the Hold c ondition, this has the effect of resett ing

the internal logic of the device. To restart commu-

nication with the device, it is necessary to drive

Hold (HOLD) High, and then to drive Chip Select

(S) Low. This prevent s t he device from going back

to the Ho ld condition.

Figure 7. Hold Condition Activation

AI02029D

HOLD

Hold

Condition

(standard use)

Hold

Condition

(non-standard use)

11/39

M25P32

ME M ORY ORGANIZATION

The memory is organized as:

■4,194, 304 bytes (8 bits each)

■64 sectors (512Kbit s, 65536 bytes each)

■16384 pages (256 bytes each).

Each page can be individually programmed (bits

are programmed from 1 to 0). The device is S ec tor

or Bulk Erasable (bi ts are erased from 0 to 1) but

not Page Erasable.

Figu re 8. Blo ck Diagram

AI08519

HOLD

WControl Logic High Voltage

Generator

I/O Shift Register

Address Register

and Counter 256 Byte

Data Buffer

256 Bytes (Page Size)

X Decoder

Y Decoder

Size of the

read-only

memory area

Status

00000h

3FFFFFh

000FFh

M25P32

12/39

Table 3. Memory Organization

Sector Address Range

63 3F0000h 3FFFFFh

62 3E0000h 3EFFFFh

61 3D0000h 3DFFFFh

60 3C0000h 3CFFFFh

59 3B0000h 3BFFFFh

58 3A0000h 3AFFFFh

57 390000h 39FFFFh

56 380000h 38FFFFh

55 370000h 37FFFFh

54 360000h 36FFFFh

53 350000h 35FFFFh

52 340000h 34FFFFh

51 330000h 33FFFFh

50 320000h 32FFFFh

49 310000h 31FFFFh

48 300000h 30FFFFh

47 2F0000h 2FFFFFh

46 2E0000h 2EFFFFh

45 2D0000h 2DFFFFh

44 2C0000h 2CFFFFh

43 2B0000h 2BFFFFh

42 2A0000h 2AFFFFh

41 290000h 29FFFFh

40 280000h 28FFFFh

39 270000h 27FFFFh

38 260000h 26FFFFh

37 250000h 25FFFFh

36 240000h 24FFFFh

35 230000h 23FFFFh

34 220000h 22FFFFh

33 210000h 21FFFFh

32 200000h 20FFFFh

31 1F0000h 1FFFFFh

30 1E0000h 1EFFFFh

29 1D0000h 1DFFFFh

28 1C0000h 1CFFFFh

27 1B0000h 1BFFFFh

26 1A0000h 1AFFFFh

25 190000h 19FFFFh

24 180000h 18FFFFh

23 170000h 17FFFFh

22 160000h 16FFFFh

21 150000h 15FFFFh

20 140000h 14FFFFh

19 130000h 13FFFFh

18 120000h 12FFFFh

17 110000h 11FFFFh

16 100000h 10FFFFh

15 0F0000h 0FFFFFh

14 0E0000h 0EFFFFh

13 0D0000h 0DFFFFh

12 0C0000h 0CFFFFh

11 0B0000h 0BFFFFh

10 0A0000h 0AFFFFh

9 090000h 09FFFFh

8 080000h 08FFFFh

7 070000h 07FFFFh

6 060000h 06FFFFh

5 050000h 05FFFFh

4 040000h 04FFFFh

3 030000h 03FFFFh

2 020000h 02FFFFh

1 010000h 01FFFFh

0 000000h 00FFFFh

Sector Address Range

13/39

M25P32

INSTRUCTIONS

All instructions, addresses and data are s hifted in

and out of the device, most significant bit f irst.

Serial Data Input (D) is sampled on the first rising

edge of Serial Clock (C) after Chip Select (S) is

driven Low. Then, the one-byte instruction code

must be shifted in t o the device, most signif icant bit

first, on Serial Data Input (D), each bit being

latched on the rising edges of Serial Clock (C).

The instruct i on set is listed in Tab le 4..

Every instruction sequence s tarts with a one-byte

instruction code. Depending on the instruction,

this might be f ollowed by address bytes, or by data

bytes, or by both or none.

In the case of a Read Data Bytes (READ), Read

Data Bytes at Higher Speed (Fast_Read), Read

Status Register (RDSR), Read Identification

(RDID) or Release from Deep Power-down, and

Read Electronic Signature (RES) instruction, the

shifted-in instruction sequence is followed by a

data-out sequenc e. Chip Select (S) c an be driven

High after any b it of the dat a-out sequence is be-

ing shifted out.

In the case of a Page Program (PP), Sector Erase

(SE), Bulk Erase (BE), Write Status Register

(WRSR), Write Enable (WREN), Write Disable

(WRDI) or Deep Power-down (DP) instruction,

Chip Select (S) must be driven High exactly at a

byte bounda ry, otherwise the instruction is reject-

ed, and is not executed. That is, Chip Select (S)

must driven High when the number of clock pulses

after Chip Select ( S) being driven Low is an ex act

multiple of eight.

All attempts to access t he memory arra y du ring a

Write Status Register cycle, Program cycle or

Erase cycle are ignored, and the internal Write

Status Register cycle, Program cycle or Erase cy-

cle cont i nues unaf fected.

Table 4. Instruction Set

Instruction Description One-byte Instruction Code Address

Bytes Dummy

Bytes Data

Bytes

WREN Write Enable 0000 0110 06h 0 0 0

WRDI Write Disable 0000 0100 04h 0 0 0

RDID Read Identification 1001 1111 9Fh 0 0 1 to 3

RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞

WRSR Write Status Register 0000 0001 01h 0 0 1

READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞

FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞

PP Page Program 0000 0010 02h 3 0 1 to 256

SE Sector Erase 1101 1000 D8h 3 0 0

BE Bulk Erase 1100 0111 C7h 0 0 0

DP Deep Power-down 1011 1001 B9h 0 0 0

RES Release from Deep Po wer-down,

and Read Electronic Signature 1010 1011 ABh 0 3 1 to

∞

Release from Deep Power-down 0 0 0

M25P32

14/39

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 9.)

sets the Write E nable Latch (WEL ) bit.

The Write Enabl e Latch (WEL) bi t must be set pri-

or to every Page Program (PP), Sector Erase

(SE), Bulk Erase (BE) and Write Status Register

(WRSR) instruction.

The Write Enable (WREN) instruction is entered

by driving Chip Select (S) Low, sending the in-

struction code, and then driving Chip Select (S)

High.

Figure 9. Write Enable (WREN) Instruction Sequen ce

Write Disabl e (WRDI)

The Write Disable (WRDI) i nstruction (Figu re 10.)

resets the Write Enable Latch (W EL ) bit.

The Write Disable (WRDI) inst ruction is entered by

driving Chip Select (S) Low, sending the instruc-

tion code, and then driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under

the following conditions:

–Power-up

– Write Disable (WRDI) instruction completion

– Write Stat us Register (WRSR) instruction

completion

– Page Program ( PP) instruction compl etion

– Sector Erase (SE) instruction completion

– Bulk Erase (BE) instruction c ompletion

Figure 10. Write Disable (WRDI) Instructio n Sequ ence

AI02281E

21 34567

High Impedance

Instruction

AI03750D

21 34567

High Impedance

Instruction

15/39

M25P32

Read Identification (RDID)

The Read Identification (RDID) instruction allows

the 8-bit manufacturer identification to be read, fol-

lowed by two bytes of device identification. The

manufacturer identification is assigned by JEDEC,

and has the value 20h for STMicroelectronics. The

device identification is assigned by the device

manufacturer, and indicates the memory type in

the first by te (20h), and the memory capacity of the

device in the second byte (16h).

Any Read Identification (RDID) instruction while

an Erase or Program cycle is in progress, is not

decoded, and has no ef fect on the cycle that is in

progress.

The device is first selected by driving Chip Sele ct

(S) Low. Then, the 8-bit i nst ruction code for the i n-

struction is shi fted in. This is followed by the 24-bit

device identification, stored in the memory, be ing

shifted out on Serial Data Output (Q), each b it be-

ing shifted out during the falling edge of Serial

Clock (C).

The instruct i on sequence is shown in Figure 11..

The Read Identification (RDID) instruction is termi-

nated b y driving Chip Select ( S) High at any time

during data output.

When Chip Select (S) i s dri ven Hi gh, the device is

put in the Standby Power mode. Once in the

Standby Power mode, the device waits to be se-

lected, so that it can receive, decode and execut e

instructions.

Table 5. Read Identification (RDID) Data-Out Sequence

Figure 11. Read Identification (RDID) Instruction Sequence and Data-Out Sequence

Manufacturer Identification Device Identification

Memory Type Memory Capacity

20h 20h 16h

21 3456789101112131415

Instruction

AI06809

Manufacturer Identification

High Impedance

MSB

15 1413 3210

Device Identification

MSB

16 16 18 28 29 30 31

M25P32

16/39

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction al-

lows the Status Register to be read. The Status

Program, Eras e or Writ e Status Register cycle is in

progress. When one of these cycl es i s in pr ogress,

it is recommended to check the Write I n Progress

(WIP) bit before sending a new instruction to the

device. It is also possibl e to read the Status Reg-

ister continuously, as shown in Figure 12..

Table 6. Status Regi ster Format

The status and cont rol bits of t he Status Register

are as fol l ows:

WIP bit. The Write In Progress (WIP) bit indicates

whether the memory is busy with a Write Status

such a cycle is in progress, when reset to 0 no

suc h cycle is in pro gress.

WE L bi t. The Write Enable Latch (WEL) bit indi-

cates the status of the int ernal Write Enable Latch.

When set to 1 the internal Write Enable Latch is

set, when s et to 0 the inte rnal W r ite Enabl e Latch

is reset and no Write Status Reg ister, P rogram or

Erase instruction is accepted.

BP2, BP1, BP0 bits. The Block Protect (BP2,

BP1, BP0) bits are non-volatile. They define the

size of the area to be software protected against

Program and Erase instructions. These bits are

written with the Write Status Register (WRSR) in-

struction. When one or more o f the Block Protect

(B P2, BP1, BP0) bit s i s set t o 1, the rel evan t me m-

ory area (as defined in Table 2.) bec omes protect-

ed against Page Progra m (PP) and Sector Erase

(SE) instructions. The Block Protect (BP2, BP1,

BP0) bits can be written provided that the Hard-

ware Protected m ode has not been set. T he Bulk

Erase (BE) instruction is executed if, and only if, all

Block Protect (BP2, BP1, BP0) bits are 0.

SRWD bit. The Status Register Write Disable

(SRWD) bit is operated in conjunction with the

Write Protect (W) signal. The Status Register

Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware

Protected mode (when the Status Register Write

Disable (SRWD) bit is set to 1, and Write Protect

(W) is driven Low). In this mode, the non-volatile

bits of the Status Register (SRWD, BP2, BP1,

BP0) bec ome read-on ly bits and t he Write S tatus

for execution.

Figure 12. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence

b7 b0

SRWD 0 0 BP2 BP1 BP0 WEL WIP

Status Regis ter

Write Protect

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

21 3456789101112131415

Instruction

AI02031E

Q76543210

Status Register Out

High Impedance

MSB

76543210

Status Register Out

MSB

17/39

M25P32

Write Status Regist er (WRSR)

The Write Status Register (WRSR) instruction al-

lows new val ues to be written to the Status Regis-

ter. Before it can be accepted, a Write Enable

(WREN) instruction must previously have been ex-

ecuted. After the Wri te Enable (WREN) instruction

has been d ecoded and ex ecuted, the de vice sets

the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is

entered by driving Chip Select (S) Low, followed

by the instruction code and the dat a byt e on Serial

Data Input (D).

The instruct i on sequence is shown in Figure 13..

The Write Stat us Regi ster (WRSR) i nstruction has

no effect on b6, b5, b1 and b0 of the Status Reg-

ister. b6 and b5 are always read as 0.

Chip Select (S) must be driven High after the

eighth bit of the data byte has been latched in. If

not, the W rite Status Regi ster (WRSR) i nstruction

is not executed. As soon as Chip Select (S) is driv-

en Hi gh, th e self -timed Write Status Regist er cycl e

(whose du ration is t W) is init iate d. Wh ile the Wr ite

Status Register cycle is in progress, the Status

Write In P rogress (WIP) bi t. T he Write In Progress

(WIP) bit is 1 during the self-timed Write Status

When the cycle is completed, the Write Enable

Latch (WEL) is reset.

The Write Status Register (WRSR) instruction al-

lows the user to change the values of the Block

Protect (BP2, BP1, BP0) bits, to define the size of

the area that is to b e treated as read-only, as de-

fined in Table 2.. The Write Status Register

(WRSR) instruction also allows the user to set or

reset the Status Register Write Disable (SRWD)

bit in accordance with the Write Protect (W) signal.

The Status Register Wri te Disable (SRWD) bit and

Write Protect (W) signal allow the device to be put

in the Hardware Protected Mode (HPM). The Write

Status Register (WRSR) in struction is n ot execu t-

ed once the Hardware Protected Mode (HPM) is

entered.

Figure 13. Write Status Register (WRSR) Instruction Sequence

AI02282D

21 3456789101112131415

High Impedance

Instruction Status

765432 0

MSB

M25P32

18/39

Table 7. Protection Mode s

Note: 1. As def i ned by th e values in the Block Pr ot ect (BP2, BP1, BP 0) bits of th e Status Registe r, as shown in Tabl e 2..

The prot ection f eatures of t he device are su mma-

rized in Table 7..

When the Status Register Write Disable (SRWD)

bit of the Status Register is 0 (its initial delivery

state), it is possible to write to the Status Regi ster

provided that the Write Enable Latch (WEL) bit has

previously been set by a Write Enable (WREN) in-

struction, rega rd less of th e whether W rite Prote ct

(W) i s driven High or Low.

When the Status Register Write Disable (SRWD)

bit of the Status Register is set to 1, two cases

need to be considered , depending on the st ate of

Write Protect (W):

– If Wr ite Protect (W) is driven High, it is

pos sible to write to the Status Register

provided that the Write Enable Latch (WEL) bit

has previously been set by a Write E nable

(WREN ) instruction.

– If Wr ite Protect (W) is driven Low, it is not

poss ible to write to the Status Regist er even if

the Write Enable Latch (WEL) bit has

previously been set by a Write Enable

(WREN ) instruction. (Attempts to write to th e

Stat us Register are rejected, and are not

accept ed for execution). As a consequence,

all the data bytes in the memory area t hat are

software protected (SPM) by the Block Protect

(BP2, BP1, BP0) bits of the St atus Register,

are also hardware protected agai nst data

modification.

Regardless of the order of the two events, the

Hardware Protected Mode (HPM) can be entered:

– by setting the Status Register Write Disable

(SRWD) bit after driving Write Protect (W) Low

– or by driving Write Protect (W) Low after

setting th e Status Register Writ e Disable

(SRWD) bit.

The only way to exit the Hardware Protect ed Mode

(HPM) once entered is to pull Write Protect (W)

High.

If Write Protect (W) is permanently tied High, the

Hardware Protected Mode (HPM) can never be

activated, and only the Software Protected Mode

(SPM), using the Block Protect (BP2, BP1, BP0)

bits of the Status Register, can be used.

Signal SRWD

Bit Mode Write Protection of the

Status Register

Memory Content

Protected Area1Unprotected Area1

Software

Protected

(SPM)

Status Register is Writable

(if the WREN instruction

has set the WEL bit)

The values in the SRWD,

BP2, BP1 and BP0 bits

can be changed

Protected against Page

Program, Sector Erase

and Bulk Erase

Ready to accept Page

Program and Sector Erase

instructions

Hardware

Protected

(HPM)

Status Register is

Hardware write protected

The values in the SRWD,

BP2, BP1 and BP0 bits

cannot be changed

Protected against Page

Program, Sector Erase

and Bulk Erase

Ready to accept Page

Program and Sector Erase

instructions

19/39

M25P32

Read Data Bytes (READ)

The device is first selected by driving Chip Sele ct

(S) Low. The instruction code for the Read Data

Bytes (READ) instruction is followed by a 3-byte

address (A23-A0), each bit being latched-in dur ing

the rising edge of Serial Cl ock (C). Then the mem-

ory contents , at that address, is shifted out on Se-

rial Data Output (Q), eac h b it bein g s hifted out, at

a maximum frequency fR, during the falling edge of

Serial Clock (C).

The instruct i on sequence is shown in Figure 14..

The first byte addressed can be at any location.

The address is automatically incremented to the

next higher address after each byte of data is shift-

ed out. The whole memory can, ther efore, be read

with a singl e Read Data Byt es (READ) i nst ruction.

When the highes t address is reached, the address

counter rolls over to 000000h, allowing the read

sequence to be continued indefinitely.

The Read Data Bytes (READ) instruction is termi-

nated by driving Chi p Select (S) High. Chip Select

(S) can be driven High at any time during data out-

put. Any Read Data Bytes (READ) instruction,

while an Erase, Program or Write cycle is in

progress, is rej ected without having any ef fects on

th e cycle tha t is in pro gr es s.

Figure 14. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequ ence

Note: Address bi ts A23 to A22 are Don’ t Care.

AI03748D

21 345678910 2829303132333435

2221 3210

36 37 38

76543 1 7

High Impedance Data Out 1

Instruction 24-Bit Address

MSB

Data Out 2

M25P32

20/39

Read Data Bytes at H igher Speed

(FAST_READ)

The device is first selected by driving Chip Sele ct

(S) Low. The instruction code for the Read Data

Bytes at Higher Speed (FAST_READ) instruction

is followed by a 3-byte address (A23-A0) and a

dummy byte, each bit being latched-in during the

rising edge of S erial Clock (C). Then the memory

contents, at that address, is shifted out on Serial

Data Output (Q), each bit being shifted out, at a

maximum frequency fC, during the falling edg e of

Serial Clock (C).

The instruct i on sequence is shown in Figure 15..

The first byte addressed can be at any location.

The address is automatically incremented to the

next higher address after each byte of data is shift-

ed out. The whole memory can, ther efore, be read

with a single Read Data Bytes at Higher Speed

(FAST_READ) instruction. When the highest ad-

dress is reached, the address counter rolls over to

000000h, allowing the read sequence to be contin-

ued indefinitely.

The Read Data Bytes at Higher Speed

(FAST_READ) instruction is terminated by driving

Chip Select (S) High. Chip Select (S) can be driv-

en High at any time during data output. Any Read

Data Bytes at Higher Speed (FAST_READ) in-

struction, while an Erase, Program or Write cycle

is in progress, is rejected without having any ef-

fects on the cycle that is in progress.

Figure 15. Read Data Bytes at Hi gher Speed (FAST_READ) Instruction Sequence and Data-Ou t

Sequence

Note: Address bi ts A23 to A22 are Don’ t Care.

AI04006

21 345678910 28293031

2221 3210

High Impedance

Instruction 24 BIT ADDRESS

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy Byte

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

21/39

M25P32

Page Program (PP)

The Page Pr ogram (PP) instruction allows bytes to

be programmed in the memory ( changing bits from

1 to 0). Before i t can be acc epted, a Wri te Enab le

(WREN) instruction must previously have been ex-

ecuted. After the Wri te Enable (WREN) instruction

has been decoded , the device sets the Write En-

able Latch (WEL).

The Page Program (PP) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, three address bytes and at least

one data byte on Serial Data Input (D). If the 8

least significant address bits (A7-A0) are not all

zero, all transmitted dat a that goes beyond the end

of the current page are programmed from the st ar t

address of the same page (from the address

whose 8 l east si gnificant bits (A7-A0) are all zero).

Chip Select ( S) must be driven Low for the entire

duration of the seq uenc e.

The instruct i on sequence is shown in Figure 16..

If more than 256 bytes are sent to the device, pre-

viously latched data are discarded and the last 256

data bytes are guaranteed to be programmed cor-

rectly within the sam e page. If less than 2 56 Dat a

bytes are sent to device, they are correctly pro-

grammed at the request ed addres ses without hav-

ing any effects on the other bytes of the same

page.

Chip Select (S) must be driven High after the

eighth bi t of the last data byte has been l atched in,

otherwise the Page Program (PP) instr uction is not

executed.

As soon as Chip Select (S ) is dr iv en Hi gh, th e self -

timed Page Pr ogram cycle (wh os e dura ti o n is tPP)

is initiated. While the Page Program cycle is in

progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit .

The Write In Progress ( WIP) bit is 1 during the self-

timed Page Program cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is completed, the Write Enabl e Latch (WEL)

bit is rese t.

A Page Program (PP) instruction applied to a page

which is protected by the B lock Protect (BP2, BP1,

BP0) bits (see Table 2. and Table 3. ) is not ex ec ut-

ed.

Figu re 16 . P age Program ( P P) In st ruction Sequence

Note: Address bi ts A23 to A22 are Don’ t Care.

AI04082B

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3 Data Byte 256

2079

2078

2077

2076

2075

2074

2073

765432 0

2072

MSB MSB

MSB MSB MSB

M25P32

22/39

Sector Erase (SE)

The Sector E rase (SE) instruction sets t o 1 (FFh)

all bits inside the chosen sector. Before it can be

accepted, a Write Enable (WREN) instruction

must previously have been executed. After the

Write Enable (WREN) instruction has been decod-

ed, the device sets the Wr ite Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, and three address by tes on Serial

Data Input (D). Any address inside the Sector (see

Table 3.) is a valid address for the Sector Erase

(SE) instruction. Chip Select (S) must be driven

Low for th e entire duration of the sequence.

The instruct i on sequence is shown in Figure 17..

Chip Select (S) must be driven High after the

eighth bit of the last address byt e has been latched

in, otherwise the Sector Erase (SE) instruction is

not executed. As soon as Chip Sel ect (S) is driven

High, the self-timed Sector E rase cycle (whose du-

ration is tSE) is initiated. While the Sector Erase cy-

cle is in progress, the Stat us Register may be read

to check the value of the Write In Progress (WIP)

bit. The Wri t e In Progress (WIP) bit is 1 dur ing the

self-timed Secto r Erase cycle, and is 0 when it is

completed. At some unspecified time before the

cycle is completed, the Write Enabl e Latch (WEL)

bit is rese t.

A Sector Erase (SE) in struction applied to a p age

which is protected by the B lock Protect (BP2, BP1,

BP0) bits (see Table 2. and Table 3. ) is not ex ec ut-

ed.

Figure 17. Sector Erase (SE) Instruction Sequence

Note: Address bi ts A23 to A22 are Don’ t Care.

24 Bit Address

AI03751D

21 3456789 293031

Instruction

23 22 2 0

MSB

23/39

M25P32

Bulk Erase ( BE)

The Bulk Erase (BE) instruction sets all bits to 1

(FFh). Before it can be accepted, a Write Enab le

(WREN) instruction must previously have been ex-

ecuted. After the Wri te Enable (WREN) instruction

has been decoded , the device sets the Write En-

able Latch (WEL).

The Bulk Erase (BE) instruction is entered by driv-

ing Chip Select (S) Low, followed by the instruction

code on Serial Data Input (D). Chip Select (S)

must be driven Low for the entire duration of the

sequence.

The instruct i on sequence is shown in Figure 18..

Chip Select (S) must be driven High after the

eighth bi t of the instruction code has been l atched

in, otherwise the Bulk Erase instruction is not exe-

cuted. As soon as Chip Select (S) is driven High,

th e self-timed Bulk Era se cycle (whose durat ion i s

tBE) is initiated. While the Bulk Erase cycle is in

progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit .

The Write In Progress ( WIP) bit is 1 during the self-

timed Bulk Erase cycle, and is 0 when it is com-

pleted. At some unspecified time before the cycle

is completed, the Write Enable Latch (WEL) bit is

reset.

The Bulk Erase (BE) instruction is executed only if

all Block Protect (BP2, BP1, BP0) bits a re 0. The

Bulk Erase (BE) instruction is ignored if one, or

more, sectors are protected.

Figure 18. Bulk E rase (BE) Instruction Sequence

AI03752D

21 345670

Instruction

M25P32

24/39

Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction

is the only way to put the device in t he lowest con-

sumption mode (the Deep Power-down mode). It

can also be used as an extra software protection

mechanism, while the device is not in active use,

since in this mode, the device ignores all Write,

Program and Eras e instructions.

Driving Chip Select (S) High deselects the device,

and puts the device i n the Standby Power mode (if

there is no internal cycle currently in progress). But

this mode is not t he Deep Power-down mode. The

Deep Power-down mode can only be entered by

executing the Deep Power-down (DP) instru ction,

subsequently reducing the standby current (from

ICC1 to ICC2, as specified in Table 13.).

Once the device has entered the Deep Power-

down mode, all instructions are ignored except the

Release from Deep Power-down and Read Elec-

tronic Signature (RES) instruction. This releases

the device from this mode. The Release from

Deep Power-down and Read Electronic Signature

(RES) instruction al so allows the Electronic Signa-

ture of the device to be output on Serial Data Out-

put (Q).

The Deep P ower-down m ode automaticall y stops

at Power-down, and the device always Powers-up

in the S tandby Power mode.

The Deep Power-down (DP) instructi on is entered

by driving Chip Select (S) Low, followed by the in-

struction code on Serial Data Input (D). Chip Se-

lect (S) m ust be d riven Low for the entire durat ion

of the seq uenc e.

The instruct i on sequence is shown in Figure 19..

Chip Select (S) must be driven High after the

eighth bi t of the instruction code has been l atched

in, otherwise t he Deep Power-down (DP) instruc-

tion is not executed. As soon as Chip Select (S) is

driven High, it requires a delay of tDP before the

supply current is reduced to ICC2 and the Deep

Power-down mode is entered.

Any Deep Power-down (DP) instruction, while an

Erase, Program or Write cycle is in progress, is re-

jected wi th o ut havi n g any effec ts o n the cycl e tha t

is in progr ess.

Figure 19. Deep Power-down ( DP) Instru ction Sequence

AI03753D

21 345670tDP

Deep Power-down Mode

Stand-by Mode

Instruction

25/39

M25P32

Release from Deep Power-down and Read

Electronic Signature (RES)

Once the device has entered the Deep Power-

down mode, all instructions are ignored except the

Release from Deep Power-down and Read Elec-

tronic Signature (RES) instruction. Executing this

instruction takes the device out of the Deep Pow-

er-down mode.

The instruction can also be used to read, on Ser ial

Data Out put (Q), the ol d-style 8-bit El ect ronic Sig-

nature, whose value for the M25P32 is 15h.

Please note that this is not the same as, or even a

subset of, the JEDEC 16-bit Electronic Signature

that is read by the Rea d Identifier (RDID) instruc-

tion. The old-style Electronic Signature is support-

ed for reasons of backward compatibility, only, and

should not be used for new designs. New designs

should, instead, make use of the JEDEC 16-bit

Electronic Signature, and the Read Identifier

(RDID) instruction.

Except while an Erase, Program or Write Status

Deep Power-down and Read Electronic Signature

(RES) instruction always provides access to the

old-style 8-bit Electronic Signature of the device,

and can be a pplie d even if the Deep Po wer-down

mode has not been entered.

Any Release from Deep Power-down and Read

Electronic Signature (RES) instruction while an

Erase, Program or Wr ite Stat us Register cycle is in

progress, is not decoded, and has no effect on the

cycle that i s in progress.

The device is first selected by driving Chip Sel ect

(S) Low. The instruction code is followed by 3

dummy bytes, each bit being latched-in on Serial

Data Input (D) during the rising edge of Serial

Clock (C). Then, the old-st yle 8-bit Elect ronic Sig-

nature, stor ed in the memory, is shifted out on Se-

rial Data Output (Q), each bit being shifted out

during the fall ing edge of Serial Clock (C).

The instruct i on sequence is shown in Figure 20..

The Release from Deep Power-down and Read

Electronic Si gnature (RES) instruction is terminat-

ed by driving Chip Select (S) High after the Elec-

tronic Signature has been read at least once.

Sending additional clock cycles on Serial Clock

(C), while Chip Select (S) is dr iven Low, cause the

Electronic Signature to be output repeatedly.

When Chip Select (S) i s dri ven Hi gh, the device is

put in the Standby Power mode. If the device was

not previously in the Deep Power-down mode, the

transition to the Standby Power mode is immedi-

ate. If the device was previously in t he Deep Pow-

er-down mode, though, the transition to the

Standby Power mode is delayed by tRES2, and

Chip Select (S) must remain High for at least

tRES2(max), as spec ified in Table 14 .. Once in the

Standby Power mode, the device waits to be se-

lected, so that it can receive, decode and execut e

instructions.

Figure 20. Rel ease from Deep Po wer-d ow n and Read Electro nic Signatur e (RES) Instruction

Sequence and Dat a- Out Sequ ence

Note: T he val ue of the 8-bit Electro ni c S i gnature, for the M2 5P32, is 15h.

AI04047C

21 345678910 2829303132333435

2221 3210

36 37 38

765432 0

High Impedance Electronic Signature Out

Instruction 3 Dummy Bytes

MSB

Stand-by Mode

Deep Power-down Mode

MSB

tRES2

M25P32

26/39

Figure 21. Rel ease from Deep Power-down (RES) Instruction Sequen ce

Driving Chip Select (S) High after the 8-bi t inst ruc-

tion byte has been received by the device, but be-

fore the whole of the 8-bit Electronic Signature has

been transmit ted for the first time (as shown in Fig-

ure 21.), still ensures that the device is put into

Standby Power mode. If the device was not previ-

ously in the Deep Power-down mode, the transi-

tion to the Standby Power mode is immediate. If

the device was previously in the Deep Power-

down mode, thoug h, the transition to the Standby

Po wer mode is delayed by tRES1, and C hip Selec t

(S) must remain High for at least tRES1(max), as

specified in Table 14.. Once in the Standby Power

mode, the device waits to be selected, so that it

can receive, decode and execut e instructions.

AI04078B

21 345670tRES1

Stand-by Mode

Deep Power-down Mode

QHigh Impedance

Instruction

27/39

M25P32

POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must

not be selected (that is Chip Select (S ) must follow

the volt age appl ied on VCC) until V CC reac he s the

correct value:

–V

CC(min) at Power-up, and then for a further

delay of tVSL

–V

SS at P o wer-down

Usually a simple pull-up resistor on Chip Select (S)

can be used to en sure safe and proper P ower-up

and Power-down.

To avoid data corruption and inadvertent write op-

erations during Power-up, a Power On Reset

(POR) circuit i s included. Th e logic i nside the de-

vice is held reset while VCC is less than the Power

On Reset (POR) threshold voltage, V WI – all oper-

ations are disabled, and the device does not re-

spond to any instruction.

Moreover, the device ignores all Write Enable

(WREN), Page Program (PP), Sector Erase (SE),

Bulk Erase (BE) and Write Status Register

(WRSR) instructions until a time delay of tPUW has

elapsed after the moment that VCC rises above the

VWI threshold. However, the correct operation of

the device is not guaranteed if, by t his time, VCC is

still below VCC(min). No Write Status Register,

Program or Erase instructions should be sent until

the later of:

–t

PUW after VCC passed the VWI threshold

–t

VSL after VCC passed the VCC(min) level

These values are specified in Table 8..

If the delay, tVSL, has el apsed, after VCC has risen

above VCC(min), the device can be selected for

READ instructions even if the tPUW delay is not y et

fully elapsed.

At Power-up, the d evice is in the following state:

– The device is in the Standby Power mode (not

the Deep Power-down m ode).

– The Write Enable Latch (WEL) bit is reset.

Normal precautions must be taken for supply rail

decoupli ng, to stabilize the VCC supply. Each de-

vice in a system should have the VCC rail dec ou-

pled by a suitable capacitor close to the package

pins. (Generally, this capacitor is of the order of

0.1µF).

At Power-down, when VCC drops from the operat-

ing voltage, to below the Power On Reset (POR)

threshold voltage, VWI, all operati ons are disabled

and the device does not respond to any instruc-

tion. (The designer needs to be aware that if a

Power-down occurs while a Write, Program or

Erase cycle is in progress, some data corruption

can result.)

Figure 22. Power-up Timing

VCC

AI04009C

VCC(min)

VWI

Reset State

of the

Device

Chip Selection Not Allowed

Program, Erase and Write Commands are Rejected by the Device

tVSL

tPUW

time

Read Access allowed Device fully

accessible

VCC(max)

M25P32

28/39

Table 8. Power-Up Timing and VWI Thresh ol d

Note: 1. These parameters are characte rized onl y.

INITIAL DEL IVE RY STATE

The device is delivered with the memory array

erased: all bits are set to 1 (each byte contains FFh). The Status Register c ontains 00h (all Stat us

Symbol Parameter Min. Max. Unit

tVSL1VCC(min) to S low 30 µs

tPUW1Time delay to Write instruction 1 10 ms

VWI1Write Inhibit Voltage 1.5 2.5 V

29/39

M25P32

MAXI MUM RAT IN G

Stressing the device outside the ratings listed in

Table 9. may cause permanent damage to the de-

vice. These are stress ratings only, and o peration

of the device at these, or any other conditions out-

side those indicated in the Operating sections of

this specification, is not implied. Exposure to Ab-

solute Maximum Rating conditions for extended

periods may af fect dev ice reliability. Refer also to

the STMicroelectroni cs SURE Program and other

relevant quali ty documents.

Table 9. Absolute Maxi mum Ratings

Note : 1. Comp liant wit h JEDEC Std J- STD- 020 B (for sm all bod y, Sn -Pb or Pb asse mbly ), the ST ECOP ACK ® 71913 95 spec i f ic at i on, and

the Eu ropean di rectiv e on Restr i ct i ons on Haz ardous S ubstan ces (RoH S ) 2002/95/EU

2. JED EC St d J ESD22 -A 114A (C 1=100 pF, R1=1500 Ω, R2=500 Ω)

Symbol Parameter Min. Max. Unit

TSTG Storage Temperature –65 150 °C

TLEAD Lead Temperature during Soldering See note 1°C

VIO Input and Output Voltage (with respect to Ground) –0.6 4.0 V

VCC Supply Voltage –0.6 4.0 V

VESD Electrostatic Discharge Voltage (Human Body model) 2–2000 2000 V

M25P32

30/39

DC AND A C PARAMETERS

This section summarizes the operating and mea-

surement condition s, and t he DC a nd AC charac-

teristics of the device. The parameters i n the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. Des igners shoul d c heck that the operating

conditions in t heir circuit matc h the measurem ent

conditions when relying on the quoted parame-

ters.

Table 10. Operating Conditions

Table 11. AC Measurement Conditions

Note: O ut put Hi-Z is define d as the p oi nt where data ou t is n o l onger driven.

Figu re 23. AC Measurement I/O W av eform

Table 12. Capacitanc e

Note: Samp l ed only, not 100% tested, at TA= 25°C and a f requency of 20MHz.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.7 3.6 V

TAAmb ient Operati ng Temperatur e –40 85 °C

Symbol Parameter Min. Max. Unit

CLLoad Capacitance 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input Timing Reference Voltages 0.3VCC to 0.7VCC V

Output Timing Refer ence Volta ges VCC / 2 V

Symbol Parameter Test Condition Min.Max.Unit

COUT Output Capacitance (Q) VOUT = 0V 8 pF

CIN Input Capacitance (other pins) VIN = 0V 6 pF

AI07455

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

0.5VCC

31/39

M25P32

Table 13. DC Characteristics

Table 14. AC Characteristics

Symbol Parameter Test Condition

(in addition to those in Table 10.)Min. Max. Unit

ILI Input Leakage Current ± 2 µA

ILO Output Leakage Current ± 2 µA

ICC1 Standby Current S = VCC, VIN = VSS or VCC 50 µA

ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 10 µA

ICC3 Operating Current (READ)

C=0.1V

CC / 0.9.VCC at 50MHz,

Q = open 8mA

C=0.1V

CC / 0.9.VCC at 20MHz,

Q = open 4mA

ICC4 Operating Current (PP) S = VCC 15 mA

ICC5 Operating Current (WRSR) S = VCC 15 mA

ICC6 Operating Current (SE) S = VCC 15 mA

ICC7 Operating Current (BE) S = VCC 15 mA

VIL Input Low Voltage – 0.5 0.3VCC V

VIH Input High Volta ge 0.7VCC VCC+0.4 V

VOL Output Low Voltage IOL = 1.6mA 0.4 V

VOH Output High Voltage IOH = –100µAV

CC–0.2 V

Test conditions specified in Table 10. and Table 11.

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfCClock Frequency for the following instructions:

FAST_READ, PP, SE, BE, DP, RES,

WREN, WRDI, RDID, RDSR, WRSR D.C. 50 MHz

fRClock Fre quen cy for READ instruc tions D.C. 20 MH z

tCH 1tCLH Clock High Time 9 ns

tCL 1tCLL Cl ock Low Time 9 ns

tCLCH 2Cl ock Rise Time3 (peak to peak) 0.1 V/ns

tCHCL 2Cl ock Fall Time3 (peak to peak) 0.1 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 5 ns

tCHSL S Not Active Hold Time (relative to C) 5 ns

tDVCH tDSU Data In Setup Time 2 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 5 ns

tSHCH S Not Active Setup Time (relative to C) 5 ns

tSHSL tCSH S Deselect Time 100 ns

M25P32

32/39

Note: 1. tCH + tCL must be gr eat er than or equal to 1/ f C(max)

2. Value guaranteed by characterization, not 100% tested i n product i on.

3. Expressed as a slew-rate.

4. Only applicab l e as a constrai nt for a WRSR instr uction when SRWD is set at 1.

tSHQZ 2tDIS Output Disable Time 8 ns

tCLQV tVClock Low to Output Valid 8 ns

tCLQX tHO O utput Hold Time 0 ns

tHLCH HOLD Setup Time (relative to C) 5 ns

tCHHH HOLD Hold Time (relative to C) 5 ns

tHHCH HOLD Setup Time (relative to C) 5 ns

tCHHL HOLD Hold Time (relative to C) 5 ns

tHHQX 2tLZ HOLD to Output Low-Z 8 ns

tHLQZ 2tHZ HOLD to Output High-Z 8 ns

tWHSL 4Write Protect Setup Time 20 ns

tSHWL 4Write Protect Hold Time 100 ns

tDP 2S High to Deep Power-down Mode 3 µs

tRES1 2S High to Sta ndby Power mode without

Electronic Signature Read 30 µs

tRES2 2S High to Sta ndby Power mode with Electronic

Signature Read 30 µs

tWWrite Status Register Cycle Time 5 15 ms

tPP Page Program Cycle Time 1.4 5 ms

tSE Sector Erase Cycle Time 1 3 s

tBE Bulk Erase Cycle Time 34 80 s

Test conditions specified in Table 10. and Table 11.

Symbol Alt. Parameter Min. Typ. Max. Unit

33/39

M25P32

Figu re 24 . Seri a l Input Timing

Figu re 25. W ri t e Pr ot ect Setup an d Hol d Ti m in g during WRS R when SR WD =1

AI01447C

MSB IN

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

High Impedance

tWHSL tSHWL

AI07439

M25P32

34/39

Figu re 26 . Hol d T im i ng

Figu re 27. Ou t pu t Tim i ng

AI02032

HOLD

tCHHL

tHLCH

tHHCH

tCHHH

tHHQXtHLQZ

AI01449D

LSB OUT

ADDR.LSB IN

tSHQZ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

tCLQX

tCLQV

35/39

M25P32

P ACKAGE ME CHANICA L

Figure 28. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Packa ge Outline

No te : Drawing is not to scal e.

Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6m m , Packag e Mechanical Data

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 0.85 1.00 0.0335 0.0394

A1 0.00 0.05 0.0000 0.0020

b 0.40 0.35 0.48 0.0157 0.0138 0.0189

D 8.00 0.3150

D2 6.40 0.2520

ddd 0.05 0.0020

E 6.00 0.2362

E2 4.80 0.1890

e 1.27 – – 0.0500 – –

K 0.20 0.0079

L 0.50 0.45 0.60 0.0197 0.0177 0.0236

L1 0.15 0.0059

N8 8

VDFPN-02

A1 ddd

M25P32

36/39

Figure 29. SO16 wide – 16-lead Plastic Small Outline, 300 mils bo dy width, Package Outline

No te : Drawing is not to scal e.

Table 16. SO16 wide – 16-lead Plastic Small Ou tline, 300 mils body width, Mec han ica l Data

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 2.35 2.65 0.093 0.104

A1 0.10 0.30 0.004 0.012

B 0.33 0.51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 10.10 10.50 0.398 0.413

E 7.40 7.60 0.291 0.299

e1.27––0.050––

H 10.00 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.40 1.27 0.016 0.050

q0808

ddd 0.10 0.004

SO-H

LA1

ddd

h x 45˚

37/39

M25P32

PART NUMBERING

Table 17. Ordering Information Scheme

For a list of available options (speed, package,

etc.) or for further i nf ormation on any aspect of this device, please c ontact your neares t ST Sales O f-

fice.

Example: M25P32 – V MF 6 T P

Device Type

M25P = Serial Flash Memory for Code Storage

Device Function

32 = 32Mbit (4M x 8)

Operating Voltage

V = VCC = 2.7 to 3.6V

Package

MF = SO16 (300 mil width)

ME = VDFPN8 8x6mm (MLP8)

Device Grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

Option

blank = Standard Packing

T = Tape and Reel Packing

Plating Technology

blank = Standard SnPb plating

P = Lead-Free and RoHS compliant

G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free

M25P32

38/39

REVISION HISTORY

Table 18. Document Revi sion History

Date Rev. Description of Revision

28-Apr-2003 0.1 Target Specification Document written in brief form

15-May-2003 0.2 Target Specification Document written in full

20-Jun-2003 0.3 8x6 MLP8 and SO16(300 mil) packages added

18-Jul-2003 0.4 tPP, tSE and tBE revised

24-Sep-2003 0.5 SO16 package code changed. Output Timing Reference Voltage changed.

04-Dec-2003 0.6 Table of contents, warning about exposed paddle on MLP8, and Pb-free options added.

Value of tVSL(min) VWI, tPP(typ) and tBE(typ) changed. Change of naming for VDFPN8

package.

10-Dec-2003 1.0 Document promoted to Product Preview

01-Apr-2004 2.0 Document promoted to Preliminary Data. Soldering temperature information clarified f or RoHS

compliant devices. Device grade information clarified

05-Aug-2004 3.0 Device grade information further clarified

01-Oct-2004 4.0 Document promoted to mature datasheet. Footnotes removed from P and G options in

Ordering Information table. Minor wording improvements made.

39/39

M25P32

Information furnished is believed to b e accurate and reliable. However, S TMicroelectronics assumes no re sponsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication ar e s ub j ect

to change without notice. This publication supersedes and replaces all information previously supplied. STMi croelectronics product s are not

authorized for us e as critical components in lif e s upport devices or sy stems w i thout express written approval of STMi cr oel ectro nics.

The ST l ogo is a registered tra dem ark of STMi croelectron ic s .

All other names are th e property of their respective o wners

STM i croelectron ics g roup of com panies

Aus tralia - Belg i um - Brazil - Canad a - China - Cze ch R epublic - Finland - France - Germ any - Hong Kong - India - Israel - Italy - Japan -

Malaysia - M a l t a - Moroc co - Singapore - Spain - S weden - S wi tzerland - Uni ted Kingdom - Un i ted States of Am eri ca