LT8711 Micropower Synchronous Multitopology Controller with 42V Input Capability DESCRIPTION FEATURES Easily Configurable as a Synchronous Buck, Boost, SEPIC, ZETA or Nonsynchronous Buck-Boost Converter nn Wide Input Range: 4.5V to 42V (V Can Operate IN to 0V, when EXTVCC > 4.5V) nn Automatic Low Noise Burst Mode(R) Operation nn Low I in Burst Mode Operation (15A Operating) Q nn Input Voltage Regulation for High Impedance Source nn 100% Duty Cycle in Dropout (Buck Mode) nn 2A Gate Drivers (BG and TG) nn Adjustable Soft-Start with One Capacitor nn Frequency Programmable from 100kHz to 750kHz nn Can Be Synchronized to External Clock nn Available in 20-Lead TSSOP and 20-Lead 3mmx4mm QFN Packages The LT(R)8711 is a multitopology current mode PWM controller that can easily be configured as a synchronous buck, boost, SEPIC, ZETA or as a nonsynchronous buck-boost converter. Its dual gate drive voltage inputs optimize gate driver efficiency. nn The 15A no-load quiescent current with the output voltage in regulation extends operating run time in battery powered systems. Low ripple Burst Mode operation enables high efficiency at very light loads while maintaining low output voltage ripple. The LT8711's fixed switching frequency can be set from 100kHz to 750kHz or can be synchronized to an external clock. The additional features include 100% duty cycle capability when in buck mode, a topology selection pin and adjustable soft-start. LT8711 is available in the 20-lead TSSOP and 20-lead 3mm x 4mm QFN packages. APPLICATIONS All registered trademarks and trademarks are the property of their respective owners. General Purpose DC/DC Conversion nn Automotive Systems nn Industrial Supplies nn Solar Panel Power Converter nn TYPICAL APPLICATION 400kHz 5V to 40V Input/12V Output Nonsynchronous Buck Boost VIN 5V TO 40V Efficiency vs Load Current 100pF VOUT 2.2F VIN BIAS EN/FBIN INTVEE EXTVCC LT8711 TG OPMODE 330nF 100pF 2.2nF 110k 80 M1 ISN L1 4.7H D2 4m RT SYNC ISP GND SS VC 90 D1 INTVCC 60.4k 100 2.2F BG CSP CSN 1M M2 69.8k VOUT 12V, 3.5A (VIN >16V) 2.5A (9V < VIN < 16V) 1.5A (VIN < 9V) 100F x2 16V, X7R EFFICIENCY (%) 10F x6 50V, X7R 70 60 50 40 30 VIN = 5V VIN = 12V VIN = 24V VIN = 36V 20 10 0 0.001 4m 0.01 0.1 LOAD CURRENT (A) 1 4 8711 TA01b FB 8711 TA01a Rev A Document Feedback For more information www.analog.com 1 LT8711 ABSOLUTE MAXIMUM RATINGS (Note 1) VIN Voltage ................................................. -0.3V to 42V BIAS Voltage............................................... -0.3V to 42V EXTVCC Voltage.......................................... -0.3V to 42V BG, TG Voltage ......................................................Note 2 FB Voltage.................................................. -0.3V to 5.5V VC Voltage ................................................. -0.3V to 2.5V EN/FBIN Voltage.................. -0.3V to MAX(VIN, EXTVCC) SYNC Voltage ............................................ -0.3V to 5.5V OPMODE Voltage....................................... -0.3V to 5.5V INTVEE Voltage..................................................... Note 2 CSP Voltage................................................ -0.3V to 42V CSN Voltage............................ CSP - 0.3V to CSP + 0.3V ISP Voltage............................... ISN - 0.3V to ISN + 0.3V ISN Voltage................................................-0.3V to BIAS INTVCC Voltage.......................................... -0.3V to 5.5V RT Voltage................................................. -0.3V to 5.5V SS Voltage ................................................ -0.3V to 5.5V Operating Junction Temperature Range LT8711E.............................................. -40C to 125C LT8711I............................................... -40C to 125C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec).................... 300C PIN CONFIGURATION 19 SYNC VC 3 18 NC SS 4 17 CSP OPMODE 5 ISP 6 ISN 7 14 VIN INTVEE 8 13 INTVCC BIAS 9 12 NC TG 10 11 BG 20 19 18 17 16 CSN 16 CSP 15 CSN OPMODE 3 15 EXTVCC 14 EXTVCC 21 GND ISP 4 13 VIN 12 INTVCC ISN 5 11 NC 9 10 BG 8 NC 7 TG INTVEE 6 FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 125C, JA = 38C/W, JC = 10C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION VC 1 SS 2 BIAS 21 GND SYNC 20 RT 2 RT 1 FB FB EN/FBIN EN/FBIN TOP VIEW TOP VIEW UDC PACKAGE 20-LEAD (3mm x 4mm) PLASTIC QFN TJMAX = 125C, JA = 52C/W, JC = 6.8C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB http://www.linear.com/product/LT8711#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8711EFE#PBF LT8711EFE#TRPBF LT8711 FE 20-Lead TSSOP -40C to 125C LT8711IFE#PBF LT8711IFE#TRPBF LT8711 FE 20-Lead TSSOP -40C to 125C LT8711EUDC#PBF LT8711EUDC#TRPBF LGQJ 20-Lead 3mm x 4mm QFN -40C to 125C LT8711IUDC#PBF LT8711IUDC#TRPBF LGQJ 20-Lead 3mm x 4mm QFN -40C to 125C Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 Rev A For more information www.analog.com LT8711 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 12V, VBIAS = 12V, unless otherwise noted (Note 3). PARAMETER CONDITIONS VIN Operating Voltage Range VEXTVCC = 0V VEXTVCC = 4.5V Quiescent Current in Normal Operation (IVIN + IEXTVCC + IBIAS) VEN/FBIN = 2.5V, Not Switching Quiescent Current in Burst Mode Operation (IVIN + IEXTVCC + IBIAS) Quiescent Current in Shutdown (IVIN + IEXTVCC + IBIAS) MIN TYP UNITS V V 2.0 2.5 mA VFB = VFB_REG + 3mV 15 25 A VEN/FBIN = 0V 1 2 A 800 800 816 805 mV mV 0.01 0.05 %/V 0 50 FB Output Regulation Voltage, VFB_REG l FB Line Regulation 4.5V VIN 42V FB Pin Input Bias Current VFB = 0.8V Error Amp Transconductance I = 5A l 4.5 0 MAX 42 42 l l 784 795 -50 250 Error Amp Voltage Gain nA mhos 90 dB Maximum Current Sense Voltage, VCSP - VCSN Minimum Duty Cycle Maximum Duty Cycle l l 46 26 50 33 54 40 mV mV Switching Frequency, fOSC RT = 30.3k RT = 247k l l 675 85 750 100 825 115 kHz kHz Switching Frequency Range Free-Running Synchronizing l l 85 140 825 750 kHz kHz SYNC Input Voltage High l 1.3 SYNC Input Voltage Low l SYNC Clock Pulse Duty Cycle VSYNC = 0V to 2V, fSYNC = 500kHz V 20 Recommended SYNC Ratio fSYNC/fOSC 0.8 INTVCC Voltage IINTVCC = 10mA INTVCC Line Regulation 6V VIN 42V, VEXTVCC = 0, IINTVCC = 10mA 6V VEXTVCC 42V, VVIN = 0, IINTVCC = 10mA INTVCC Load Regulation IINTVCC = 0mA to 40mA INTVCC Maximum External Load Current Internal Load Current = 40mA INTVCC Undervoltage Lockout INTVCC Rising INTVCC Falling l 4.75 0.4 V 80 % 1.2 5 5.25 V -0.003 -0.003 -0.03 -0.03 %/V %/V -1 -2 10 l l 3.9 3.45 INTVCC Undervoltage Lockout Hysteresis 4.1 3.6 % mA 4.3 3.75 500 V V mV INTVEE Voltage, VBIAS - VINTVEE IINTVEE = 10mA l 4.85 5.15 5.4 V INTVEE Undervoltage Lockout, VBIAS - VINTVEE VBIAS - VINTVEE Rising VBIAS - VINTVEE Falling l l 3.6 3.4 3.85 3.6 4.1 3.8 V V INTVEE Undervoltage Lockout Hysteresis, VBIAS - VINTVEE 250 mV BG Rise Time CBG = 3.3nF (Note 4) 14 ns BG Fall Time CBG = 3.3nF (Note 4) 12 ns TG Rise Time CTG = 3.3nF (Note 4) 11 ns TG Fall Time CTG = 3.3nF (Note 4) 14 ns BG and TG Non-Overlap Time TG Rising to BG Rising, CBG = CTG = 3.3nF (Note 4) 70 ns BG and TG Non-Overlap Time BG Falling to TG Falling, CBG = CTG = 3.3nF (Note 4) 70 ns Minimum On-Time CBG = CTG = 3.3nF 100 ns Rev A For more information www.analog.com 3 LT8711 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 12V, VBIAS = 12V, unless otherwise noted (Note 3). PARAMETER CONDITIONS MIN TYP VSS = 0V, Current Flows Out of SS pin l SS Charge Current SS Low Detection Voltage 6 10 15 A Part Exiting Undervoltage Lockout l 65 85 105 mV EN/FBIN Active Mode EN/FBIN Rising l 1.28 1.35 1.42 V EN/FBIN Chip Enable EN/FBIN Rising EN/FBIN Falling l l 0.97 0.94 1.03 1 1.11 1.08 V V EN/FBIN Input Voltage Low Shutdown Mode l EN/FBIN Current Limit Adjustment Voltage Full Current Limit Near Zero Current Limit l l 1.12 EN/FBIN Pin Input Bias Current VEN/FBIN = 12V l -50 EN/FBIN Amp Transconductance VFB = 0.6V 40 mhos EN/FBIN Amp Voltage Gain VFB = 0.6V 100 V/V EN/FBIN Chip Enable Hysteresis 30 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Do not apply a positive or negative voltage or current source to BG, TG and INTVEE pins, otherwise permanent damage may occur. Note 3: The LT8711E is guaranteed to meet performance specifications from 0C to 125C junction temperature. Specifications over the -40C to 125C operating temperature range are assured by design, 4 MAX 0 UNITS mV 0.2 V 1.27 V V 50 nA characterization and correlation with statistical process controls. The LT8711I is guaranteed over the full -40C to 125C operating junction temperature range. Note 4: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation over the specified maximum operating junction temperature may impair device reliability. Rev A For more information www.analog.com LT8711 TYPICAL PERFORMANCE CHARACTERISTICS Maximum Current Limit vs Duty Cycle (CSP-CSN) Maximum Current Limit vs SS (CSP-CSN) 55 Output Voltage Regulation (VFB_REG) 60 805 804 50 41 34 27 803 802 40 VFB_REG (mV) MAX CSP - CSN (mV) 48 MAX CSP - CSN (mV) TA = 25C, unless otherwise noted. 30 20 801 800 799 798 797 10 796 20 0 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 0 8711 G01 1.04 1.205 1.200 1.195 1.190 1.185 0 25 50 75 TEMPERATURE (C) 100 1.365 RISING 1.03 1.02 1.01 1.00 0.99 FALLING 0.98 0.97 1.360 1.355 1.350 1.345 1.340 1.335 0.95 -50 125 -25 0 25 50 75 TEMPERATURE (C) 100 8711 G04 125 1.330 -50 180 1.5 160 1.1 1.0 0.60 EN/FBIN (V) VISP = VISN=12V 300 140 120 100 0.70 0.75 FB (V) 0.80 0.85 0.90 60 -50 250 200 150 80 0.65 125 ISN Bias Current ISN BIAS CURRENT (A) CSN BIAS CURRENT (A) 1.2 100 350 VCSP = VCSN = 12V 1.3 0 25 50 75 TEMPERATURE (C) 8711 G06 CSN Bias Current 1.6 1.4 -25 8711 G05 Input Voltage Regulation vs FB (EN/FBIN) 125 EN/FBIN Active Mode Threshold 0.96 -25 100 1.370 EN/FBIN ACTIVE MODE (V) 1.215 EN/FBIN CHIP ENABLE (V) EN/FBIN VOLTAGE (V) 1.05 0 25 50 75 TEMPERATURE (C) 8711 G03 EN/FBIN Chip Enable Threshold 1.220 1.210 -25 8711 G02 Input Voltage Regulation (EN/FBIN) 1.180 -50 795 -50 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.0 SS (V) -25 0 25 50 75 TEMPERATURE (C) 100 8711 G07 125 8711 G08 100 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 8711 G09 Rev A For more information www.analog.com 5 LT8711 TYPICAL PERFORMANCE CHARACTERISTICS Oscillator Frequency vs Temperature 5.0 800 4.5 700 4.0 BG Transition Time vs Cap Load 60 RT = 30.3k 50 BG TRANSITION TIME (ns) DCM Thresholds (ISP-ISN) 600 3.5 VISN = 0V 3.0 2.5 FOSC (kHz) ISP -ISN (mV) TA = 25C, unless otherwise noted. VISN = 12V 2.0 1.5 500 400 300 200 1.0 RT = 247k 0 -50 -25 0 25 50 75 TEMPERATURE (C) 100 0 -50 125 -25 0 25 50 75 TEMPERATURE (C) 100 8711 G10 TG Transition Time vs Cap Load RISING FALLING 5.20 4.4 5.15 RISING 4.1 4.0 3.9 3.8 FALLING 1 2 3 4 5 6 7 CAP LOAD (nF) 8 9 10 3.5 -50 70 -25 0 25 50 75 TEMPERATURE (C) 100 3.8 3.7 FALLING 3.6 3.5 -50 -25 0 25 50 75 TEMPERATURE (C) INTVCC Current Limit vs VIN or EXTVCC 125 40 30 20 IINTVCC = 10mA 5.00 4.95 -25 0 25 50 75 TEMPERATURE (C) 100 125 INTVCC Dropout from VIN or EXTVCC 0.30 0.25 0.20 0.15 0.10 0.05 5 10 15 20 25 30 INPUT VOLTAGE (V) 35 8711 G16 6 10 0.35 50 0 9 5.05 0.40 10 100 8 8711 G15 POWER INPUT - INTVCC (V) INTVCC (V) 3.9 4 5 6 7 CAP LOAD (nF) INTVCC vs Temperature 4.80 -50 125 60 INTVCC CURRENT LIMIT (mA) 4.1 RISING 3 8711 G14 INTVCC UVLO vs Temperature 4.0 2 4.85 8711 G13 4.2 1 4.90 3.6 0 0 5.10 4.2 3.7 10 FALLING 8711 G12 INTVCC (V) VIN OR VEXTVCC (V) TG TRANSITION TIME (ns) 0 125 4.5 4.3 30 0 20 Minimum Operating Input Voltage 50 20 30 8711 G11 60 40 RISING 10 100 0.5 40 40 8711 G17 0 0 10 20 30 INTVCC LOAD CURRENT (mA) 40 8711 G18 Rev A For more information www.analog.com LT8711 TYPICAL PERFORMANCE CHARACTERISTICS INTVEE vs Temperature 3.9 IINTVEE = 10mA 5.15 80 RISING 5.05 5.00 4.95 4.90 3.7 3.6 4.85 -25 0 25 50 75 TEMPERATURE (C) 100 125 3.5 -50 -25 0 25 50 75 TEMPERATURE (C) 100 8711 G19 0.7 60 50 40 30 20 10 FALLING 4.80 -50 INTVEE Current Limit vs BIAS 70 3.8 BIAS - INTVEE (V) 5.10 BIAS - INTVEE (V) INTVEE UVLO vs Temperature INTVEE CURRENT LIMIT (mA) 5.20 TA = 25C, unless otherwise noted. 0 125 5 10 15 20 25 BIAS (V) 30 8711 G20 INTVEE Dropout (BIAS = 6V) 20 35 40 8711 G21 IQ_BURST vs VIN or EXTVCC 20.00 IQ_BURST vs Temperature BIAS = 6V 0.6 18 18.00 0.4 0.3 IQ_BURST (A) IQ_BURST (A) INTVEE (V) 0.5 16 14 16.00 14.00 0.2 12 0.1 0 0 10 20 30 40 50 INTVEE LOAD CURRENT (mA) 60 8711 G22 10 12.00 5 10 15 20 25 30 INPUT VOLTAGE (V) 35 40 8711 G23 10.00 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 8711 G24 Rev A For more information www.analog.com 7 LT8711 PIN FUNCTIONS (TSSOP/QFN) EN/FBIN (Pin 1/Pin 19): Enable and Input Voltage Regulation Pin. In conjunction with the UVLO (undervoltage lockout) circuit, this pin is used to enable/disable the chip and restart the soft-start sequence. The EN/FBIN pin is also used to limit the switching regulator current to avoid collapsing the input supply. Drive below 0.2V to disable the chip with very low quiescent current. Drive above 1.03V (typical) to activate the chip. The commanded input current will adjust when the EN/FBIN pin voltage is between 1.12V and 1.27V. Drive above 1.35V (typical) to activate switching with no reduction in input current and restart the soft-start sequence. See the Block Diagram and Applications section for more information. Do not float this pin. TG (Pin 10/Pin 8): PFET Gate Drive Pin. Low and high levels are INTVEE and BIAS respectively with a 2A drive capability. BG (Pin 11/Pin 10): NFET Gate Drive Pin. Low and high levels are GND and INTVCC respectively with a 2A drive capability. NC (Pin 12/Pin 9): No Connection. Do not connect. Must be floated. FB (Pin 2/Pin 20): Feedback Input Pin. The LT8711 regulates the FB pin to 0.8V. Connect the feedback resistor divider tap to this pin. INTVCC (Pin 13/Pin 12): 5V Dual Input LDO Regulator Pin. Must be locally bypassed with a minimum capacitance of 2.2F to GND. Logic will choose to run INTVCC from the VIN or EXTVCC pins. A maximum 10mA external load can connect to the INTVCC pin. The undervoltage lockout on INTVCC is 3.6V (typical). The BG gate driver can begin switching when INTVCC exceeds 4.1V (typical). VC (Pin 3/Pin 1): Error Amplifier Output Pin. Tie external compensation network to this pin. VIN (Pin 14/Pin 13): Input Supply Pin. Must be locally bypassed. Can run down to 0V as long as EXTVCC > 4.5V. SS (Pin 4/Pin 2): Soft Start Pin. Place a soft-start capacitor here. Upon start-up, the SS pin will be charged by a 410k resistor to about 4.3V. During an overtemperature or UVLO condition, the SS pin will be quickly discharged to reset the part. Once those conditions are clear, the part will attempt to restart. EXTVCC (Pin 15/Pin 14): Alternate Input Supply Pin. Must be locally bypassed. Can run down to 0V as long as VIN > 4.5V. OPMODE (Pin 5/Pin 3): Topology Selection Pin. Tie this pin to ground to select buck/ZETA mode. Tie to INTVCC to select SEPIC/boost mode. Tie to a 100pF capacitor to GND to select nonsynchronous buck-boost mode. ISP & ISN (Pins 6 & 7/ Pins 4 & 5): Current Sense Positive and Negative Input Pins respectively. Kelvin connect ISP and ISN pins to a sense resistor. INTVEE (Pin 8/Pin 6): 5V Below BIAS LDO Regulator Pin. Must be locally bypassed with a minimum capacitance of 2.2F to BIAS. This pin sets the bottom rail for the TG gate driver. The TG gate driver can begin switching when BIAS - INTVEE exceeds 3.6V (typical). BIAS (Pin 9/Pin 7): Power Supply for the TG PFET Driver. Must be locally bypassed with a minimum capacitance of 2.2F to INTVEE. The BIAS pin sets the top rail for the TG gate driver. 8 CSN & CSP (Pins 16 & 17/ Pins 15 & 16): Current Sense Negative and Positive Input Pins Respectively. Kelvin connect CSN and CSP pins to a sense resistor to limit the input current. The maximum sense voltage at low duty cycle is 50mV. NC (Pin 18/Pin 11): No Connection. Do not connect. Must be floated. SYNC (Pin 19/Pin 17): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock must exceed 1.3V, and the low level must be less than 0.4V. Drive this pin to less than 0.4V to revert to the internal free running clock. See the Applications Information section for more information. RT (Pin 20/Pin 18): Timing Resistor Pin. Adjusts the LT8711's switching frequency. Place a resistor from this pin to ground to set the frequency to a fixed free running level. Do not float this pin. GND (Pin 21/Pin 21): Ground. Must be soldered directly to the local ground plane. Rev A For more information www.analog.com LT8711 BLOCK DIAGRAM CINTVEE VIN CIN VIN BIAS UVLO LDO INTVEE BIAS + - IREC x RSENSE CURRENT SENSE PROCESSOR ISW x RSENSE LOGIC 1.35V RIN2 + - UVLO LDO LOGIC W3 CINTVCC INTVCC SYNC S 1.215V REF W4 LDO SYNC BLOCK RT START-UP DISABLE DRIVER AND FAULT LOGIC A2 + - ISN ISP RFB1 FB 0.88V RFB2 Q R PWM COMP EN/FBIN 1.2V QUICK DISCHARGE + - COUT IS RAMP GENERATOR ADJUSTABLE OSCILLATOR CLK RT SS_L CSN + - VOUT + - DIE TEMP 165C D2 EXTVCC VOUT M1 NFET SS_L D1 RSENSE CSP A1 + - RIN1 + - M2 PFET L1 INTVCC DRIVER BG IS CS EN/FBIN DRIVER TG LEVEL SHIFT + EA2 - D6 D4 + - OPMODE BUCK/ZETA BOOST/SEPIC MODE DETECTION BUCK-BOOST REV COMP EA1 410k R CHARGE 0.8V 85mV Q1 PNP SS VC 8711 BD CSS CC RC CF Rev A For more information www.analog.com 9 LT8711 START-UP AND FAULT SEQUENCE EN/FBIN < 1.0V (TYP) OR VIN AND EXTVCC < 4.5V OR TJUNCTION > 165C CHIP OFF * ALL SWITCHES OFF EN/FBIN > 1.0V (TYP) AND VIN OR EXTVCC > 4.5V AND TJUNCTION < 160C INITIALIZE * SS PULLED LOW * INTVCC CHARGES UP RESET EN/FBIN > 1.35V(TYP) AND INTVCC > 4.1V (TYP) AND BIAS-INTVEE > 3.85V (TYP) (BUCK/BUCK-BOOST/ZETA) ACTIVE MODE * SS CHARGES UP RESET RESET DETECTED * SS DISCHARGES QUICKLY * SWITCHER DISABLED SS < 50mV BEGIN SWITCHING * NFET BEGINS SWITCHING * PFET BEGINS SWITCHING WHEN INTVEE REGULATOR IS OUT OF UVLO RESET OVER RESET * NO RESET CONDITIONS DETECTED RESET = UVLO ON VIN OR EXTVCC (<4.5V MAX) UVLO ON INTVCC (<3.6V TYP) UVLO ON INTVEE (BUCK/BUCK-BOOST/ZETA) (<3.6V TYP) EN/FBIN < 1.35V (TYP) AT 1ST POWER-UP EN/FBIN < 1.00V (TYP) AFTER ACTIVE MODE SET STATUS CHANGE ON OPMODE PIN OVERTEMPERATURE (TJ > 165C) 8711 F01 Figure 1. State Diagram 10 Rev A For more information www.analog.com LT8711 OPERATION OPERATION--OVERVIEW The LT8711 uses a constant frequency, current mode control scheme to provide excellent line and load regulation. The part's undervoltage lockout (UVLO) function, together with soft-start, offers a controlled means of starting up. Output voltage and input voltage have control over the commanded peak current which allows a wide range of applications to be built using the LT8711. Synchronous switching makes high efficiency and high output current applications possible. When operating at light load condition, the LT8711 will enter burst mode to minimize switching loss. Refer to the Block Diagram and the State Diagram (Figure 1) for the following description of the part's operation. latched so that if EN/FBIN drops between 1.03V to 1.35V (typical), the SS pin is not pulled low by the EN/FBIN pin. The EN/FBIN pin is also used for input voltage regulation which is at 1.200V (typical). Input voltage regulation is explained in more detail in the Operation--Regulation section. Taking the EN/FBIN pin below 0.2V shuts down the chip, resulting in extremely low quiescent current. See Figure 2 that illustrates the different EN/FBIN voltage thresholds. ACTIVE MODE (NORMAL OPERATION) (MODE LATCHED UNTIL EN/FBIN DROPS BELOW CHIP ENABLE TRESHOLD) 1.42V ACTIVE MODE THRESHOLD (TOLERANCE) 1.28V NORMAL OPERATION IF ACTIVE MODE SET OPERATION--TOPOLOGY SELECTING The 8711 can be configured as a synchronous buck, boost, SEPIC, ZETA or nonsynchronous buck-boost converter by configuration of the OPMODE pin. EN/FBIN (V) 1.27V INPUT VOLTAGE REGULATION (ONLY IF ACTIVE MODE SET) 1.12V SWITCH OFF, INTVCC AND INTVEE ENABLED, SS CAP DISCHARGED IF ACTIVE MODE NOT SET 1.11V CHIP ENABLE THRESHOLD (HYSTERSIS AND TOLERANCE) When the OPMODE pin is connected to GND, the controller operates in buck/ZETA mode. 0.94V When the OPMODE pin is connected to the INTVCC pin, the controller operates in SEPIC/boost mode. 0.2V When the OPMODE pin is tied to a 100pF capacitor to GND, the controller operates in nonsynchronous buckboost mode. LOCKOUT (SWITCH OFF, SS CAP DISCHARGED, INTVCC AND INTVEE DISABLED) SHUTDOWN (LOW QUIESCENT CURRENT) 0V 8711 F03 Figure 2. EN/FBIN Modes of Operation Undervoltage Lockout (UVLO) OPERATION--START-UP Several functions are provided to enable a very clean start-up of the LT8711. The LT8711 has internal UVLO circuitry that disables the chip when the greater of VIN or EXTVCC < 3.6V (typical). The EN/ FBIN pin can also be used to create a configurable UVLO. Precise Turn-On Voltages Soft-Start of Switch Current The EN/FBIN pin has two voltage levels for activating the part: one that enables the part and allows internal rails to operate and a 2nd voltage threshold which activates a soft-start cycle and switching can begin. To enable the part, take the EN/FBIN pin above 1.03V (typical). This comparator has 50mV of hysteresis to protect against glitches and slow ramping. To activate a soft-start cycle and allow switching, take EN/FBIN above 1.35V (typical). When EN/FBIN exceeds 1.35V (typical), the logic state is The soft-start circuitry provides for a gradual ramp-up of the switch current (refer to Max Current Limit vs SS in Typical Performance Characteristics). When the part is brought out of shutdown, the external SS capacitor is first discharged which resets the states of the logic circuits in the chip. Once the chip is in active mode, an integrated 410k resistor pulls the SS pin to ~4.3V at a ramp rate set by the external capacitor connected to the pin. Typical values for the soft-start capacitor range from 100nF to 1F. Rev A For more information www.analog.com 11 LT8711 OPERATION OPERATION--REGULATION Input Voltage Regulation Use the Block Diagram when stepping through the following description of the LT8711 operating in regulation. The LT8711 has two modes of regulation: A resistor divider from the converter's input voltage to the EN/FBIN pin sets the input voltage regulation point. The EN/FBIN pin voltage connects to the positive input of amplifier EA2. The VC pin voltage is set by EA2, which is the amplified difference between the EN/FBIN pin voltage and an internal 1.200V reference voltage. In this manner, the EN/FBIN error amplifier sets the correct peak current level to maintain input voltage regulation. 1. Output Voltage (via FB pin) 2. Input Voltage (via EN/FBIN pin) Both of these regulation loops control the peak commanded current. At the start of each oscillator cycle, the SR latch is set, which first turns off the external rectifier switch (NFET in Block Diagram), and then turns on the external main switch (PFET in Block Diagram). The PFET's current flows through an external current sense resistor (RSENSE) generating a voltage proportional to the PFET switch current. This voltage is then amplified by A1 and added to a stabilizing ramp. The resulting sum is fed into the positive terminal of the PWM comparator. When the voltage on the positive input of the PWM comparator exceeds the voltage on the negative input (VC pin), the SR latch is reset, turning off the PFET and then turning on the NFET. The voltage on the VC pin is controlled by one of the regulation loops, or a combination of regulation loops. Slope compensation provides stability in constant frequency current mode control architectures by preventing subharmonic oscillations at high duty cycles. This is accomplished internally by adding a compensating ramp to the positive terminal of the PWM comparator. Output Voltage Regulation The error amplifier servos the VC node by comparing the voltage on the FB pin with an internal 0.800V reference. When the load current increases it causes a reduction in the feedback voltage relative to the reference causing the error amplifier to raise the VC voltage. In this manner, the FB error amplifier sets the correct peak current level to maintain output voltage regulation. 12 OPERATION--RESET CONDITIONS The LT8711 has three reset cases. When the part is in reset, the SS pin is pulled low and both power switches, NFET and PFET, are forced off. Once all of the reset conditions are gone, the part is allowed to begin a soft-start sequence and switching can commence. Each of the following events can cause the LT8711 to be in reset: 1. UVLO a. The greater of VIN and EXTVCC is < 4.5V (maximum) b. UVLO on INTVCC. INTVCC < 3.6V (typical) c. UVLO on INTVEE. VBIAS - VINTVEE < 3.6V (typical) unless BOOST/SEPIC topology is selected d. EN/FBIN < 1.35V (typical) at first power-up e. EN/FBIN < 1.00V (typical) after active mode set 2. OPMODE pin status changes 3. Die Temperature > 165C OPERATION--POWER SWITCH CONTROL The external PFET and NFET switches are never on at the same time (except buck-boost mode), and there is a nonoverlap time of about 100ns to prevent cross conduction. Rev A For more information www.analog.com LT8711 OPERATION Light Load Operation Modes OPERATION--LDO REGULATORS (INTVCC AND INTVEE) The SYNC pin can be used to tell the LT8711 to operate in FCM regardless of load current, or operate in DCM and Burst Mode at light loads. The INTVCC LDO regulates at 5.0V (typical) and is used as the top rail for the BG gate driver. The INTVCC LDO can run from VIN or EXTVCC and will intelligently select to run from the best rail to minimize power loss in the chip, but at the same time, select the proper input for maintaining INTVCC as close to 5.0V as possible. The INTVCC regulator also has safety features to limit the power dissipation in the internal pass device and also to prevent it from damage if the pin is shorted to ground. The UVLO threshold on INTVCC is 3.6V (typical), and the LT8711 will be in reset until the LDO comes out of UVLO. SYNC = logic high: FCM SYNC = logic low: DCM or Burst Mode operation If a clock is applied to the SYNC pin the part will synchronize to an external clock frequency and operate in FCM mode. OPERATION--AUTOMATIC LOW NOISE Burst Mode OPERATION At no load or very light load condition, high FB voltage causes VC to decrease. When VC voltage is lower than a threshold voltage, the controller operates in Burst Mode to minimize switching loss. Between bursts, all circuitry associated with controlling the output switch is shut down, reducing the average input supply current to 15A in a typical application. Low standby power and higher conversion efficiency is thus achieved. To optimize the quiescent current performance at light loads, the current in the feedback resistor divider must be minimized as it appears to the output as load current. The INTVEE regulator regulates to 5.15V (typical) below the BIAS pin voltage. The BIAS and INTVEE voltages are used for the top and bottom rails of the TG gate driver respectively. Just like the INTVCC regulator, the INTVEE regulator has a safety feature to limit the power dissipation in the internal pass device. The TG pin can begin switching only after the INTVEE regulator comes out of UVLO (3.85V typical across the BIAS and INTVEE pins). When the INTVEE regulator is in UVLO, for the boost and SEPIC topologies, the bottom switch is allowed to switch. The output current would flow through the body diode of the PFET. To protect the PFET from thermal damage under this condition, the maximum commanded current is folded back to 27mV (typical) across the CSP-CSN pins. Rev A For more information www.analog.com 13 LT8711 APPLICATIONS INFORMATION BUCK CONVERTER COMPONENT SELECTION Table 1. Buck Design Equations The LT8711 can be configured as a buck converter as in Figure 3. Parameters/Equations Step 1: Inputs For a desired output current and output voltage over a given input voltage range, Table 1 is a step-by-step set of equations to calculate component values for the LT8711 when operating as a buck converter. Refer to more detail in this section and the Appendix for further information on the design equations presented in Table 1. Step 3: VCSPN Variable Definitions: Step 5: L Step 2: DCMAX Step 4: RSENSE VIN(MAX) = Maximum Input Voltage IOUT = Output Current of Converter 2.2F EXTVCC INTVEE LT8711 OPMODE TG INTVCC RT 60.4k 47nF 68pF 1.5nF 51k BG RT SYNC Step 7: CIN L1 4.7H M2 CSP CSN ISP ISN ) R SENSE * V IN(MIN) 40m * f ( * 2VOUT - VIN(MIN) VOUT R SENSE * V IN(MIN) - VOUT 2.5m * f )* VOUT V IN(MIN) COUT CIN 1- DCMIN 8 * L * f2 * 0.005 IOUT * DCMAX f * VIN VIN is acceptable maximum input ripple voltage. RSENSE 4.5m GND SS VC Step 6: COUT 2.2F M1 ( RSENSE * VIN(MIN) - VOUT V * OUT 12.5m * f VIN(MIN) * The minimum value of the L range is the higher of LTYP and LMIN. VCSPN = Current Limit Voltage at DCMAX VOUT VCSPN IOUT * Solve equations 1 to 4 for a range of L values. DCMAX = Power Switch Duty Cycle at VIN(MIN) EN/FBIN VIN BIAS RSENSE 0.75 * L MAX = f = Switching Frequency VOUT VIN(MIN) See Max Current Limit vs Duty Cycle plot in Typical Performance Characteristics to find VCSPN at DCMAX. L MIN = VOUT = Output Voltage CIN 10F x5 DCMAX L TYP = VIN(MIN) = Minimum Input Voltage VIN 5V TO 40V Pick VIN, VOUT, IOUT, and f to calculate equations below. VOUT 3.3V, 6.5A Step 8: RFB1/RFB2 COUT 100F x2 Step 9: RT RFB1 1M V RFB1 = OUT - 1 * RFB2 0.8V RT = 25000 f - 2: f is in kHz and R T is in k NOTE: The final values for COUT and CIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. The COUT and CIN equations assume zero ESR, so increase the capacitance accordingly based on the combined ESR. RFB2 316k FB 8711 F03 ADDITIONAL 470F, 6.3V ELECTROLYTIC CAP ON VOUT 47F, 50V ELECTROLYTIC CAP ON VIN Figure 3. Buck Converter--The Component Values Given Are Typical Values for a 400kHz, 5V-40V to 3.3V/6.5A Buck 14 Rev A For more information www.analog.com LT8711 APPLICATIONS INFORMATION BOOST CONVERTER COMPONENT SELECTION Table 2. Boost Design Equations The LT8711 can be configured as a boost converter as in Figure 4. Parameters/Equations Step 1: Inputs For a desired output current and output voltage over a given input voltage range, Table 2 is a step-by-step set of equations to calculate component values for the LT8711 when operating as a boost converter. Refer to more detail in this section and the Appendix for further information on the design equations presented in Table 2. Step 3: VCSPN Variable Definitions: Step 5: L Step 2: DCMAX Step 4: RSENSE VIN(MIN) = Minimum Input Voltage VIN(MAX) = Maximum Input Voltage VOUT = Output Voltage IOUT = Output Current of Converter Pick VIN, VOUT, IOUT, and f to calculate equations below. DCMAX 1- VCSPN = Current Limit Voltage at DCMAX VIN 10.8V TO 13.2V CIN 10F x6 VOUT 2.2F OPMODE RT 60.4k 330nF 42pF 1nF EN/FBIN VIN CSP ISP ISN EXTVCC LT8711 CSN 187k BIAS INTVCC RSENSE 0.63 * BG L TYP = RSENSE * VIN(MIN) VIN(MIN) * 1- 12.5m * f VOUT LMIN = RSENSE * VOUT 40m * f Step 6: COUT VOUT L1 8.2H M2 2.2F RFB1 1M M1 RFB2 34k VOUT 24V, 3A COUT 6.8F x4 TG VC VIN(MIN) * 1- VOUT - VIN(MIN) LMAX1 = RSENSE * VIN(MIN) VIN(MIN) * 1- 5m * f VOUT LMAX2 = RSENSE * VIN(MAX ) VIN(MAX ) * 1- 5m * f VOUT * Solve equations 1 to 4 for a range of L values. RSENSE 4m GND SS VCSPN (1- DCMAX ) IOUT * The minimum value of the L range is the higher of LTYP and LMIN. The maximum of the L value range is the lower of LMAX. INTVEE RT SYNC VOUT See Max Current Limit vs Duty Cycle plot in Typical Performance Characteristics to find VCSPN at DCMAX. f = Switching Frequency DCMAX = Power Switch Duty Cycle at VIN(MIN) VIN(MIN) FB 8711 F04 ADDITIONAL 270F, 50V ELECTROLYTIC CAP ON VOUT 47F, 50V ELECTROLYTIC CAP ON VIN Step 7: CIN Step 8: RFB1/RFB2 Step 9: RT COUT CIN IOUT * DCMAX f * 0.005 * VOUT DCMAX 8 * L * f2 * 0.005 V RFB1 = OUT - 1 * RFB2 0.8V RT = 25000 f - 2: f is in kHz and R T is in k NOTE: The final values for COUT and CIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. The COUT and CIN equations assume zero ESR, so increase the capacitance accordingly based on the combined ESR. Figure 4. Boost Converter--The Component Values Given are Typical Values for a 400kHz, 12V to 24V/3A Boost Rev A For more information www.analog.com 15 LT8711 APPLICATIONS INFORMATION SEPIC CONVERTER COMPONENT SELECTION Table 3. SEPIC Design Equations The LT8711 can be configured as a SEPIC converter as in Figure 5. For a desired output current and output voltage over a given input voltage range, Table 3 is a step-by-step set of equations to calculate component values for the LT8711 when operating as a SEPIC converter. Refer to more detail in this section and the Appendix for further information on the design equations presented in Table 3. Parameters/Equations Step 1: Inputs Step 2: DCMAX Step 3: VCSPN Step 4: RSENSE Pick VIN, VOUT, IOUT, and f to calculate equations below. DCMAX See Max Current Limit vs Duty Cycle plot in Typical Performance Characteristics to find VCSPN at DCMAX. RSENSE 0.63 * Step 5: L VIN(MIN) = Minimum Input Voltage L TYP = VIN(MIN) RSENSE * VOUT * 12.5m * f VIN(MIN) + VOUT LMIN = 2 V RSENSE * VOUT IN(MIN) * 1- 40m * f VOUT VIN(MAX) = Maximum Input Voltage VOUT = Output Voltage IOUT = Output Current of Converter VIN(MIN) *V R L MAX = SENSE OUT * 5m * f V IN(MIN) + VOUT f = Switching Frequency DCMAX = Power Switch Duty Cycle at VIN(MIN) * Solve equations 1 to 4 for a range of L values. VCSPN = Current Limit Voltage at DCMAX CIN 10F EN/FBIN VIN BIAS x2 2.2F INTVEE EXTVCC LT8711 OPMODE INTVCC RT 118k 470nF 100pF 4.7nF * The minimum value of the L range is the higher of LTYP and LMIN. The maximum of the L value range is the lower of LMAX. L1 8.2H VOUT 49.9k BG RT SYNC CSP SS CSN GND VC * L = L1 = L2 for coupled inductors. VOUT 2.2F C1 10F x3 * L = L1 || L2 for uncoupled inductors. M2 RSENSE 2m RFB1 1M M1 L2 15H RFB2 71.5k VOUT 12V, 4A COUT 22F x3 Step 6: C1 Step 7: COUT Step 8: CIN RSENSE1 2m FB Step 9: RFB1/RFB2 TG ISP ISN Step 10: RT 8711 F05 ADDITIONAL 270F, 25V ELECTROLYTIC CAP ON VOUT 56F, 50V ELECTROLYTIC CAP ON VIN Figure 5. SEPIC Converter--The Component Values Given Are Typical Values for a 200kHz, 4.5V-40V to 12V/4A SEPIC 16 VCSPN (1- DCMAX ) IOUT RSENSE1 = RSENSE2 = RSENSE Variable Definitions: VIN 4.5V TO 40V VOUT VIN(MIN) + VOUT C1 10F (Typical); VRATING > VIN COUT CIN IOUT * DCMAX f * 0.005 * VOUT DCMAX 8 * L * f2 * 0.005 V RFB1 = OUT - 1 * RFB2 0.8V RT = 25000 f - 2: f is in kHz and R T is in k NOTE: The final values for COUT and CIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. The COUT and CIN equations assume zero ESR, so increase the capacitance accordingly based on the combined ESR. Rev A For more information www.analog.com LT8711 APPLICATIONS INFORMATION ZETA CONVERTER COMPONENT SELECTION The LT8711 can be configured as a ZETA converter as in Figure 6. For a desired output current and output voltage over a given input voltage range, Table 4 is a step-by-step set of equations to calculate component values for the LT8711 when operating as a ZETA converter. Refer to more detail in this section and the Appendix for further information on the design equations presented in Table 4. Table 4. ZETA Design Equations Parameters/Equations Step 1: Inputs Step 2: DCMAX Step 3: VCSPN Step 4: RSENSE Pick VIN, VOUT, IOUT, and f to calculate equations below. DCMAX See Max Current Limit vs Duty Cycle plot in Typical Performance Characteristics to find VCSPN at DCMAX. RSENSE 0.63 * Step 5: L VIN(MIN) = Minimum Input Voltage L TYP = VIN(MIN) RSENSE * VOUT * 12.5m * f VIN(MIN) + VOUT LMIN = 2 V RSENSE * VOUT IN(MIN) * 1- 40m * f VOUT VIN(MAX) = Maximum Input Voltage VOUT = Output Voltage IOUT = Output Current of Converter VIN(MIN) *V R L MAX = SENSE OUT * 5m * f V IN(MIN) + VOUT f = Switching Frequency DCMAX = Power Switch Duty Cycle at VIN(MIN) * Solve equations 1 to 4 for a range of L values. VCSPN = Current Limit Voltage at DCMAX CIN 10F EN/FBIN VIN BIAS x6 VOUT 2.2F RT 118k 470nF 100pF 2.2nF 20k EXTVCC INTVEE LT8711 TG OPMODE 2.2F * L = L1 || L2 for uncoupled inductors. CSN Step 6: C1 L1A 2.2H Step 7: COUT CSP CSN L1B 2.2H BG SS ISN RSENSE2 3.5m VC * L = L1 = L2 for coupled inductors. RSENSE1 3.5m C1 10F x3 CSP CSN FB * The minimum value of the L range is the higher of LTYP and LMIN. The maximum of the L value range is the lower of LMAX. CSP INTVCC RT SYNC VCSPN (1- DCMAX ) IOUT RSENSE1 = RSENSE2 = RSENSE Variable Definitions: VIN 5V TO 40V VOUT VIN(MIN) + VOUT ISP GND RFB1 1M RFB2 69.8k VOUT 12V, 3.5A (VIN > 16V) 2.5A (9V < VIN < 16V) 1.5A (VIN < 9V) Step 8: CIN COUT 22F x4 Step 9: RFB1/RFB2 8711 F06 ADDITIONAL 270F, 25V ELECTROLYTIC CAP ON VOUT 56F, 50V ELECTROLYTIC CAP ON VIN Figure 6. ZETA Converter--The Component Values Given Are Typical Values for a 200kHz, 5V-40V to 12V/3.5A ZETA Step 10: RT C1 10F (Typical); VRATING > VIN COUT CIN IOUT * DCMAX f * 0.005 * VOUT DCMAX 8 * L * f2 * 0.005 V RFB1 = OUT - 1 * RFB2 0.8V RT = 25000 f - 2: f is in kHz and R T is in k NOTE: The final values for COUT and CIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. The COUT and CIN equations assume zero ESR, so increase the capacitance accordingly based on the combined ESR. Rev A For more information www.analog.com 17 LT8711 APPLICATIONS INFORMATION BUCK-BOOST CONVERTER COMPONENT SELECTION The LT8711 can be configured as a buck-boost converter as in Figure 7. For a desired output current and output voltage over a given input voltage range, Table 5 is a step-by-step set of equations to calculate component values for the LT8711 when operating as a buck-boost converter. Refer to more detail in this section and the Appendix for further information on the design equations presented in Table 5. Table 5. Buck-Boost Design Equations Parameters/Equations Step 1: Inputs Step 2: DCMAX Step 3: VCSPN Step 4: RSENSE Pick VIN, VOUT, IOUT, and f to calculate equations below. DCMAX See Max Current Limit vs Duty Cycle plot in Typical Performance Characteristics to find VCSPN at DCMAX. RSENSE 0.63 * Step 5: L VIN(MIN) = Minimum Input Voltage L TYP = VIN(MIN) RSENSE * VOUT * 12.5m * f VIN(MIN) + VOUT LMIN = 2 V RSENSE * VOUT IN(MIN) * 1- 40m * f VOUT VIN(MAX) = Maximum Input Voltage VOUT = Output Voltage IOUT = Output Current of Converter VIN(MIN) *V R L MAX = SENSE OUT * 5m * f V IN(MIN) + VOUT f = Switching Frequency DCMAX = Power Switch Duty Cycle at VIN(MIN) * Solve equations 1 to 4 for a range of L values. VCSPN = Current Limit Voltage at DCMAX CIN 10F EN/FBIN VIN BIAS x6 100pF VOUT 2.2F RT 60.4k 330nF 100pF 2.2nF M1 L1 4.7H VC D2 D1 RFB1 1M ISN RSENSE2 4m ISP GND BG 110k 2.2F INTVCC SS CSP FB CSN 10nF * The minimum value of the L range is the higher of LTYP and LMIN. The maximum of the L value range is the lower of LMAX. Step 6: COUT INTVEE EXTVCC LT8711 TG OPMODE RT SYNC VCSPN (1- DCMAX ) IOUT RSENSE1 = RSENSE2 = RSENSE Variable Definitions: VIN 5V TO 40V VOUT VIN(MIN) + VOUT RFB2 69.8k VOUT 12V, 3.5A (VIN >16V) 2.5A (9V < VIN < 16V) 1.5A (VIN < 9V) COUT 100F x2 M2 10 10 RSENSE1 4m 10nF 8711 F07 Step 7: CIN Step 8: RFB1/RFB2 Step 9: RT COUT CIN IOUT * DCMAX f * 0.005 * VOUT DCMAX 8 * L * f2 * 0.005 V RFB1 = OUT - 1 * RFB2 0.8V RT = 25000 f - 2: f is in kHz and R T is in k NOTE: The final values for COUT and CIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. The COUT and CIN equations assume zero ESR, so increase the capacitance accordingly based on the combined ESR. Figure 7. Buck-Boost Converter--The Component Values Given Are Typical Values for a 400kHz, 5V-40V to 12V/2.5A Buck-Boost 18 Rev A For more information www.analog.com LT8711 APPLICATIONS INFORMATION SETTING THE OUTPUT VOLTAGE REGULATION The LT8711 output voltage is set by a resistor divider between VOUT, FB, and GND. VOUT R = 0.8V * 1+ FB1 RFB2 FROM SYSTEM VOUT LT8711 RFB1 FB RFB2 R2 0.8V INTVCC 5V RNTC where RFB1 and RFB2 are shown in the Block Diagram. See the Electrical Characteristics for tolerances on the FB regulation voltage. SETTING THE INPUT VOLTAGE REGULATION OR UNDERVOLTAGE LOCKOUT By connecting a resistor divider between VIN, EN/FBIN, and GND, the EN/FBIN pin provides a means to regulate the input voltage or to create an undervoltage lockout function. Referring to error amplifier EA2 in the block diagram, when EN/FBIN is lower than the 1.2V reference, VC is pulled low. For example, if VIN is provided by a relatively high impedance source (e.g. a solar panel) and the current draw pulls VIN below a preset limit, VC will be reduced, thus reducing current draw from the input supply and limiting the input voltage drop. To set the minimum or regulated input voltage use: + EA1 - VC R1 8711 F08 Figure 8. Temperature Dependent Output Using an NTC Resistor Divider The FB voltages regulates to 0.8V (typical). For an accurate room temperature output voltage, size the resistor divider off the INTVCC pin to give 0.8V such that the current through R2 is ~0 at room temperature. Choose RNTC(25) 10k and use the equations below to calculate R1, RFB1, and VOUT at room temperature and RFB2 for a desired VOUT change over temperature. R1= RNTC(25) 0.8V 5.0V - 0.8V VOUT 0.8V + RFB1 R2 RFB1 R1 * 0.8V - 5.0V * + 0.8V * R1+ RNTC(25) RFB2 R VIN(MIN-REG) = 1.2V * 1+ IN1 RIN2 where RIN1 and RIN2 are shown in the Block Diagram. Temperature Dependent Output Voltage Using NTC Resistor It may be desirable to regulate the converter's output based on the ambient temperature. The INTVCC LDO regulated voltage is 5.0V 4% (see Electrical Characteristics), and a negative temperature coefficient (NTC) resistor can be used to sum into the FB pin to create an output voltage that decreases with temperature. See Figure 8 for the necessary connections. 1 1 * - T T25 RNTC = RNTC(25) * e VOUT = -5.0V * RFB1 * R1 R2 1 1 - * R1+ RNTC(T(MAX)) R1+ RNTC(T(MIN)) -5.0V * RFB1 * R1 VOUT 1 1 - * R1+ RNTC(T(MAX)) R1+ RNTC(T(MIN)) R2 = Rev A For more information www.analog.com 19 LT8711 APPLICATIONS INFORMATION ISP-ISN CURRENT SENSING where: RNTC(25) = Resistance of the NTC resistor at 25C = Material-specific constant of NTC resistor. Specified at two temperatures such as 25/85. If more than two s are specified, use the most appropriate for the application. T = Absolute temperature in Kelvin T25 = Room temperature in Kelvin (298.15K) SWITCH CURRENT LIMIT (CSP-CSN CURRENT SENSING) The external current sense resistor (RSENSE) sets the maximum peak current. The maximum voltage across RSENSE is 50mV (typical) at very low switch duty cycles, and then slope compensation decreases the current limit as the duty cycle increases (see the Max Current Limit vs Duty Cycle (CSP-CSN) plot in the Typical Performance Characteristics). The equation below gives the switch current limit for a given duty cycle and current sense resistor (find VCSPN at the operating duty cycle in the plot mentioned). ISW (LIMIT ) = = Converter efficiency (assume ~90%) VCSPN = Max current limit voltage (see Max Current Limit vs Duty Cycle (CSP-CSN) plot in the Typical Performance Characteristics) = Converter load current DCMAX = Switching duty cycle at minimum VIN (see Power Switch Duty Cycle in Appendix) iRIPPLE = Peak-to-peak inductor ripple current percentage at minimum VIN (recommended to use 25%) 20 The ISP-ISN circuitry delays switching if the rectifier switch current goes too high. This mechanism also protects the part during short-circuit and overload conditions by keeping the current through the inductor under control. Let's see a buck mode example. CIN EN/FBIN VIN BIAS VOUT EXTVCC INTVEE LT8711 OPMODE TG M1 BG M2 INTVCC RT RT SYNC VC L1 RSENSE GND SS R SENSE V i RSENSE 0.74 * * CSPN * (1- DCMAX ) * 1- RIPPLE IOUT 2 IOUT ISP/ISN current sensing monitors the current of the rectifier switch and helps protect the circuit from overload conditions. VCSPN To provide a desired load current for any given application, RSENSE must be sized appropriately. The equation below calculates RSENSE for a desired output current: CSP/CSN current sensing is used in switching regulator peak current control. CSP CSN ISP ISN RFB1 COUT RFB2 FB 8711 F09 Figure 9. ISP-ISN Current Sensing Example A potential controllability problem could occur under short-circuit conditions without rectifier switch current sensing. If the power supply output is short circuited, the feedback amplifier (EA) responds to the low output voltage by raising the control voltage, VC, to its peak current limit value. Ideally, the top switch would be turned on, and then turned off as its current exceeded the value indicated by VC. However, there is finite response time involved in both the current comparator and turnoff of the top switch. These result in a minimum on time, tON(MIN). When combined with high VIN, the potential exists for a loss of control. Rev A For more information www.analog.com LT8711 APPLICATIONS INFORMATION Expressed mathematically the requirement to maintain control is: f * tON VR(SENSE)_L + VDS_NMOS + I * R VIN where: f = switching frequency tON = switch minimum on time VR(SENSE)_L = voltage drop on high side sense resistor VDS_NMOS = voltage drop on high side PMOS switch VIN = Input voltage I * R = inductor I * R voltage drop If this condition is not observed, the current will not be limited at IPK, but will cycle-by-cycle ratchet up to some higher value. With rectifier switch current sensing, the current through the inductor would be controlled under the whole clock cycle. The switching will only resume once rectifier switch current has fallen below IPK. ISP-ISN current sensing is also used in reverse current detecting for DCM operation. Table 6. CSP/CSN, ISP/ISN Bias Current: VCM = 0V VCM > 3V I_CSP (typ) 0A 4A ~ 25A I_CSN (typ) -4A ~ -25A 110A I_ISP (typ) 0A 4A ~ 25A I_ISN (typ) -4A ~ -25A 220A When VCM changes from 0V to 3V, bias current changes gradually from low side values to high side values as shown in Table 6. CSN/ISN bias current at high side is proportional to temperature (see the CSN/ISN Bias Current vs Temperature plots in the Typical Performance Characteristics). Positive bias currents flow into the pins. Negative bias currents flow out of the pins. Bias current of 4A ~ 25A and -4A ~ -25A in the table changes according to the VC voltage. 4A (-4A) corresponds to the minimum VC voltage. 25A (-25A) corresponds to the maximum VC voltage. 5.1 RSENSE1, RSENSE2 CURRENT SENSE FILTERING CSP OR ISP 2.2nF LT8711 CSN OR ISN 5.1 8710 F10a Certain applications may require filtering of the current sense signals due to excessive switching noise that can appear across RSENSE1 and/or RSENSE2. Higher operating voltages, higher inductor current, higher values of RSENSE, and more capacitive MOSFETs will all contribute additional noise across RSENSE when MOSFETs transition. The CSP/ CSN and/or the ISP/ISN sense signals can be filtered by adding one of the RC networks shown in Figure 10. The filter shown in Figure 10a filters out differential noise, whereas the filter in Figure 10b filters out the differential and common mode noise at the expense of an additional capacitor and approximately twice the capacitance value. It is recommended to Kelvin tie the ground connection directly to the paddle of the LT8711 if using the filter in Figure 10b. The filter network should be placed as close as possible to the LT8711. Resistors greater than 10 should be avoided as this can Increase the offset voltages at the CSP/CSN and ISP/ISN pins. Figure 10a. Differential RC Filter on CSP/CSN and/or ISP/ISN Pins 5.1 CSP OR ISP 4.7nF LT8711 RSENSE1, RSENSE2 4.7nF 5.1 CSN OR ISN 8711 F10b Figure 10b. Differential and Common Mode RC Filter on CSP/ CSN and/or ISP/ISN Pins SWITCHING FREQUENCY The LT8711 uses a constant frequency architecture whose frequency can be between 100kHz and 750kHz. The frequency can be set using the internal oscillator or can be synchronized to an external clock source. Selection of Rev A For more information www.analog.com 21 LT8711 APPLICATIONS INFORMATION the switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. For high power applications, consider operating at lower frequencies to minimize MOSFET heating from switching losses. The switching frequency can be set by placing an appropriate resistor from the RT pin to ground and tying the SYNC pin low. The frequency can also be synchronized to an external clock source driven into the SYNC pin. The following sections provide more details. Oscillator Timing Resistor (RT) The operating frequency of the LT8711 can be set by the internal free-running oscillator. When the SYNC pin is driven low (< 0.4V), the frequency of operation is set by a resistor from the RT pin to ground. The oscillator frequency is calculated using the following formula: f= 25000 RT + 2 where f is in kHz and RT is in k. Conversely, RT can be calculated from the desired frequency using: RT = 25000 f -2 Clock Synchronization An external source can set the operating frequency of the LT8711 by providing a digital clock signal into the SYNC pin (RT resistor still required). The LT8711 will operate at the SYNC clock frequency. The LT8711 will revert to its internal free-running oscillator clock when the SYNC pin is driven below 0.4V for a few free-running clock periods. The LT8711 will operate in FCM mode with internal free-running oscillator clock if driving SYNC high for an extended period of time. The duty cycle of the SYNC signal must be between 20% and 80% for proper operation. Also, the frequency of the SYNC signal must meet the following two criteria: 1. SYNC may not toggle outside the frequency range of 140kHz to 750kHz unless it is stopped below 0.4V to enable the free-running oscillator. 22 2. The SYNC frequency can always be higher than the freerunning oscillator frequency (as set by the RT resistor), fOSC, but should not be less than 20% below fOSC. LDO REGULATORS The LT8711 has two linear regulators to run the BG and TG gate drivers. The INTVCC LDO regulates 5V (typical) above ground, and the INTVEE regulator regulates 5.15V (typical) below the BIAS pin. INTVCC LDO Regulator The INTVCC LDO is used as the top rail for the BG gate driver. An external capacitor greater than 2.2F must be placed from the INTVCC pin to ground. The capacitor should have low ESR, such as a ceramic capacitor. The INTVCC LDO can run off VIN or EXTVCC and will intelligently select to run off the best rail for minimizing chip power loss, but at the same time, select the proper input for maintaining INTVCC as close to 5V as possible. For example, Figure 11 is a plot that shows how VIN or EXTVCC is selected. Overcurrent protection circuitry typically limits the maximum current draw from the LDO to ~50mA. If the selected input voltage is greater than 24V (typical), then the current limit of the LDO reduces linearly with input voltage to limit the maximum power in the INTVCC pass device. See the INTVCC Current Limit vs VIN or EXTVCC plot in the Typical Performance Characteristics. EXTVCC 40V POWERED BY VIN POWERED BY EXTVCC 5.5V 0 0 5.5V VIN, EXTVCC POWER SELECTION 40V VIN 8711 F11 Figure 11. INTVCC Input Voltage Selection For more information www.analog.com Rev A LT8711 APPLICATIONS INFORMATION Power dissipated in the INTVCC LDO should be minimized to improve efficiency and prevent overheating of the LT8711. The current limit reduction with input voltage circuit helps prevent the part from overheating, but these guidelines should be followed. The maximum current drawn through the INTVCC LDO occurs under the following conditions: because the LT8711 doesn't have to supply gate drive to the PFET. Figure 12 shows the recommended connections for using the LT8711 as a nonsynchronous boost converter, however the same concept can be used for any other converter topology. VIN 1. Large (capacitive) MOSFETs being driven at high frequencies CIN VOUT 2. The converter's switch voltage (VIN for BUCK, VOUT for BOOST and BUCK-BOOST, VIN + VOUT for SEPIC converters) is high, thus requiring more charge to turn the MOSFET gates on and off. OPMODE INTVCC In general, use appropriately sized MOSFETs and lower the switching frequency for higher voltage applications to keep the INTVCC current at a minimum. Overcurrent protection circuitry typically limits the maximum current draw from the regulator to ~80mA. If the BIAS voltage is greater than 15V (typical), then the current limit of the regulator reduces linearly with input voltage to limit the maximum power in the INTVEE pass device. See the INTVEE Current Limit vs BIAS plot in the Typical Performance Characteristics. The same thermal guidelines from the INTVCC LDO Regulator section apply to the INTVEE regulator as well. VOUT BIAS L1 VOUT INTVEE RFB1 M1 GND FB COUT RFB2 8711 F12 Figure 12. Simplified Schematic of a Nonsynchronous Boost Converter LAYOUT GUIDELINES FOR BUCK, BOOST, SEPIC, ZETA AND BUCK-BOOST TOPOLOGIES General Layout Guidelines * To optimize thermal performance, solder the exposed pad of the LT8711 to the ground plane with multiple vias around the pad connecting to additional ground planes. * High speed switching path (see specific topology below for more information) must be kept as short as possible. * The FB, VC and RT components should be placed as close to the LT8711 as possible, while being far away as practically possible from switching nodes. The ground for these components should be separated from the switch current path. * Place bypass capacitors for the VIN and EXTVCC pins (1F or greater) as close as possible to the LT8711. * Place bypass capacitors for the INTVCC and INTVEE (between BIAS and INTVEE) pins (2.2F or greater) as close as possible to the LT8711. NONSYNCHRONOUS CONVERTER It may be desirable in some applications to replace the external PFET with a Schottky diode to make a nonsynchronous converter. One example would be a high output voltage application because the voltage drop across the rectifier has a small effect on the efficiency of the converter. In fact, for high output voltage applications, replacing the PFET with a Schottky may result in higher efficiency RSENSE BG INTVEE LDO Regulator The BIAS and INTVEE voltages are used for the top and bottom rails of the TG gate driver respectively. An external capacitor greater than 2.2F must be placed between the BIAS and INTVEE pins. The capacitor should have low ESR, such as ceramic capacitor. EN/FBIN VIN CSP ISP ISN EXTVCC CSN LT8711 Rev A For more information www.analog.com 23 LT8711 APPLICATIONS INFORMATION * The load should connect directly to the positive and negative terminals of the output capacitor for best load regulation. SEPIC Topology Specific Layout Guidelines * Keep length of loop (high speed switching path) governing RSENSE1, MN, C1, MP, RSENSE2, COUT, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. BUCK Topology Specific Layout Guidelines * Keep length of loop (high speed switching path) governing MN, MP, CIN, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. VIN C1 L VIN VOUT PFET NFET RSENSE2 RSENSE1 COUT2 CIN1 VOUT COUT1 L PFET RSENSE CIN1 CIN2 GND COUT1 NFET LT8711 CIN2 COUT2 GND GND 8711 F15 LT8711 GND Figure 15. Suggested Component Placement for SEPIC Topology ZETA Topology Specific Layout Guidelines 8711 F13 Figure 13. Suggested Component Placement for Buck Topology * Keep length of loop (high speed switching path) governing RSENSE1, MN, C1, MP, RSENSE2, CIN, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. Boost Topology Specific Layout Guidelines * Keep length of loop (high speed switching path) governing MN, MP, COUT, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. VIN RSENSE VOUT L C VIN VOUT PFET CIN1 RSENSE2 NFET COUT1 L PFET CIN1 CIN2 COUT1 RSENSE1 COUT2 GND NFET CIN2 COUT2 LT8711 GND GND 8711 F16 LT8711 GND Figure 16. Suggested Component Placement for ZETA Topology 8711 F13 Figure 14. Suggested Component Placement for Boost Topology 24 For more information www.analog.com Rev A LT8711 APPLICATIONS INFORMATION Buck-Boost Topology Specific Layout Guidelines THERMAL CONSIDERATIONS * Overview * Keep length of loop (high speed switching path) governing RSENSE1, DIO1, MP, CIN, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. Keep length of loop (high speed switching path) governing RSENSE2, MN, DIO2, COUT, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. VIN VOUT L PFET DI01 CIN1 CIN2 DI02 NFET COUT1 RSENSE2 RSENSE1 COUT2 GND The primary components on the board that consume the most power and produce the most heat are the power switches, MN and MP, the power inductor, the Schottky diodes in the nonsynchronous buck-boost converter and the LT8711 IC. It is imperative that a good thermal path be provided for these components to dissipate the heat generated within the packages. This can be accomplished by taking advantage of the thermal pads on the underside of the packages. It is recommended that multiple vias in the printed circuit board be used to conduct heat away from each of these components and into a copper plane with as much area as possible. For the case of the power switches, the copper area of the drain connections shouldn't be too big as to create a large EMI surface that can radiate noise around the board. Power MOSFET Loss and Thermal Calculations LT8711 GND 8711 F17 Figure 17. Suggested Component Placement for Buck-Boost Topology Current Sense Resistor Layout Guidelines * * Route the CSP/CSN and ISP/ISN lines differentially (close together) from the chip to the current sense resistor as shown in Figure 17. Place the vias that connect the CSP/CSN and ISP/ISN lines directly at the terminals of the current sense resistor as shown in Figure 17. RSENSE1, 2 TO CURRENT SENSE PINS The LT8711 requires two external power MOSFETs, an NFET switch for the BG gate driver and a PFET switch for the TG gate driver. Important parameters for estimating the power dissipation in the MOSFETs are: 1. On-resistance (RDS(ON)) 2. Gate-to-drain charge (QGD) 3. PFET body diode forward voltage (VBD) 4. VDS of the FETs during their Off-Time 5. Switch current (ISW) 6. Switching frequency (f) The power loss in each power switch has a DC and AC term. The DC term is when the power switch is fully on, and the AC term is when the power switch is transitioning from on-off or off-on. 8705 F20 Figure 18. Suggested Routing and Connections of CSP/CSN and ISP/ISN Lines Rev A For more information www.analog.com 25 LT8711 APPLICATIONS INFORMATION The following applies for both the NFET and PFET power switches. Below are the equations for the power loss in MN and MP. PMOSFET = P2 + PSWITCHING IR PMN = IN2 * RDS(ON) + VDS *IN * f * tRF + PRR-N I PMP = IP2 * RDS(ON) + VBD * IPK + VY * f * 140nx + PRR-N 1.6 iRIPPLE i ; IVY = ISW - RIPPLE 2 2 V *I * t * f PRR-N DS RR RR 2 V *I * t * f PRR-P DS RR RR 2 IPK = ISW + Typical values for tRF are 10ns to 40ns depending on the MOSFET capacitance and drain voltage. In general, the lower the QGD of the MOSFET, the faster the rise and fall times of its drain voltage. For best calculations, measure the rise and fall times in the application. PFET body diode reverse recovery power loss is dependent on many factors and can be difficult to quantify in an application. In general, this power loss increases with higher VDS and/or higher switching frequency. Chip Power and Thermal Calculations Power dissipation in the LT8711 chip comes from three primary sources: INTVCC and INTVEE LDOs providing gate drive to the BG and TG pins and the chip quiescent current. The average current through each LDO is determined by the gate charge of the power switches, MN and MP, and the switching frequency. Below are the equations for calculating the chip power loss. where: f = Switching Frequency IN = NFET RMS Current IP = PFET RMS Current tRF = Average of the rise and fall times of the NFET's drain voltage ISW = Average switch current during its on-time PINTVCC_BG = QMN * f * VSELECT IPK = Peak inductor current PINTVCC_Q = 2mA * VSELECT IVY = Valley inductor current PINTVEE = QMP * f * VBIAS iRIPPLE = Inductor ripple current where: DC = Switch duty cycle (see Power Switch Duty Cycle section in Appendix) VBD = PFET body diode forward voltage at ISW VDS = Voltage across the FET when it's off. PRR-N = PFET body diode reverse recovery power loss in the NFET PRR-P = PFET body diode reverse recovery power loss in the PFET IRR = Current needed to remove the PFET body diode charge tRR = Reverse recovery time of PFET body diode 26 The INTVCC LDO primarily supplies voltage for the BG gate driver. The BIAS and INTVEE voltages supply the top and bottom rails of the TG gate driver respectively. The chip Q current comes from INTVCC. Below are the chip power equations: f = Switching frequency QMN = Total gate charge of NFET power switch (MN) QMP = Total gate charge of PFET power switch (MP) = INTVCC LDO selected input VSELECT voltage, VIN or EXTVCC (see LDO Regulators section) Thermal Lockout If the die temperature reaches ~165C, the part will go into shutdown, so the power switches turn off and the soft-start capacitor will be discharged. The LT8711 will come out of shutdown when the die temperature drops by ~5C (typical). Rev A For more information www.analog.com LT8711 APPENDIX POWER SWITCH DUTY CYCLE The external power main switch (PFET in the Block Diagram) cannot remain off for 100% of each clock cycle, and will turn on for a minimum on time (MinOnTime) when in regulation. This MinOnTime governs the minimum allowable duty cycle given by: DCMIN = (MinOnTime) TP * 100% where TP is the clock period and MinOnTime (found in the Electrical Characteristics) is 100ns (typ). The application should be designed such that the operating duty cycle is higher than DCMIN. Duty cycle equations for different topologies are given below. to handle the peak inductor current without saturating. Note that in some applications, the current handling requirements of the inductor can be lower, such as in the SEPIC topology where each inductor carries a fraction of the total switch current. Molded chokes or chip inductors do not have enough core area to support peak inductor currents in the 5A to 15A range. To minimize radiated noise, use a toroidal or shielded inductor. See Table 7 for a list of inductor manufacturers. Table 7. Inductor Manufacturers Coilcraft MSS1278, XAL1010, and MSD1278 Series www.coilcraft.com Cooper Bussmann DRQ127, DR127, and HCM1104 Series www.cooperbussmann.com Vishay IHLP Series www.vishay.com Wurth WE-DCT Series WE-CFWI Series www.we-online.com For the Buck topology (see Figure 3): DCBUCK VOUT VIN Minimum Inductance Although there can be a trade-off with efficiency, it is often desirable to minimize board space by choosing smaller inductors. When choosing an inductor, there are two conditions that limit the minimum inductance; (1) providing adequate load current, and (2) avoidance of subharmonic oscillation. For the Boost topology (see Figure 4): DCBOOST 1- VIN VOUT For the SEPIC topology (see Figures 6): DCSEPIC VOUT VIN + VOUT Adequate Load Current Small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to the load. For the ZETA topology (see Figures 7): DCZETA VOUT VIN + VOUT Avoiding Subharmonic Oscillations For the Buck-Boost topology (see Figures 8): DCBUCK-BOOST VOUT VIN + VOUT INDUCTOR SELECTION For high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. Additionally, choose inductors with more volume for a given inductance. The inductor should have low DCR (copperwire resistance) to reduce I2R losses, and must be able The LT8711's internal slope compensation circuit will prevent subharmonic oscillations that can occur when the duty cycle is greater than 50%, provided that the inductance exceeds a minimum value. In applications that operate with duty cycles greater than 50%, the inductance must be at least: LMIN LMIN VIN * RSENSE * ( 2 * DC - 1) , Buck Topology 40m * DC * f VIN * RSENSE * ( 2 * DC - 1) , Other Topologies 40m * DC * f * (1- DC) Rev A For more information www.analog.com 27 LT8711 APPENDIX where LMIN = L1 for buck, boost and buck-boost topologies LMIN = L1 = L2 for coupled dual inductor topologies (SEPIC and ZETA) LMIN = L1 || L2 for uncoupled dual inductor topologies (SEPIC and ZETA) Inductor Current Rating The inductor(s) must have a rating greater than its (their) peak operating current to prevent inductor saturation, which would result in efficiency losses. POWER MOSFET SELECTION The LT8711 requires two external power MOSFETs, an NFET switch for the BG gate driver and a PFET switch for the TG gate driver. It is important to select MOSFETs for optimizing efficiency. For choosing an NFET and PFET, the important device parameters are: 1. Breakdown voltage (BVDSS) 2. Gate threshold voltage (VGSTH) 3. On-resistance (RDS(ON)) 4. Total gate charge (QG) 5. Turn-off delay time (tD(OFF)) 6. Package has exposed paddle If operating close to the BVDSS rating of the MOSFET, check the leakage specifications on the MOSFET because leakage can decrease the efficiency of the converter. The NFET and PFET gate-to-source drive is 5V typical. The BG gate driver can begin switching when the INTVCC voltage exceeds ~4.1V, so ensure the selected NFET is in the linear mode of operation with 4.1V of gate-to-source drive to prevent possible damage to the NFET. The TG gate driver can begin switching when the BIASINTVEE voltage exceeds ~3.85V, so it is optimal that the PFET be in the linear mode of operation with 3.85V of gate-to-source drive. Try to choose a PFET with a low body diode reverse recovery time to minimize stored charge in the PFET. The stored charge in the PFET body diode gets 28 removed when the NFET switch turns on and can lead to efficiency hits especially in applications where the VDS of the PFET (during off-time) is high. For these applications, it may be beneficial to put a Schottky diode across the PFET to reduce the amount of charge in the PFET body diode. Power MOSFET on-resistance and total gate charge go hand-in-hand and are typically inversely proportional to each other; the lower the on-resistance, the higher the total gate charge. Choose MOSFETs with an on-resistance to give a voltage drop to be less than 300mV at the peak current. At the same time, choose MOSFETs with a lower total gate charge to reduce LT8711 power dissipation and MOSFET switching losses. The turn-off delay time (tD(OFF)) of available NFETs is generally smaller than the LT8711's non-overlap time. However, the turn-off time of the available PFETs should be looked at before deciding on a PFET for a given application. The turn-off time must be less than the non-overlap time of the LT8711 or else the NFET and PFET could be on at the same time and damage to external components may occur. If the PFET turn-off delay time as specified in the data sheet is less than the LT8711 non-overlap time, then the PFET is good to use. If the turn-off delay time is longer than the non-overlap time, it doesn't necessarily mean it can't be used. It may be unclear how the PFET manufacturer measures the turn-off delay time, so it is best to measure the PFET turn-off delay time with respect to the PFET gate voltage. Finally, both the NFET and PFET power MOSFETs should be in a package with an exposed paddle for the drain connection to be able to dissipate heat. The on-resistance of MOSFETs is proportional to temperature, so it's more efficient if the MOSFETs are running cool with the help of the exposed paddle. See Table 8 for a list of power MOSFET manufacturers. Table 8. Power MOSFET (NFET and PFET) Manufacturers Fairchild Semiconductor www.fairchildsemi.com On-Semiconductor www.onsemi.com Vishay www.vishay.com Diodes Inc. www.diodes.com Rev A For more information www.analog.com LT8711 APPENDIX INPUT AND OUTPUT CAPACITOR SELECTION Input and output capacitance is necessary to suppress voltage ripple caused by discontinuous current moving in and out of the regulator. A parallel combination of capacitors is typically used to achieve high capacitance and low ESR (equivalent series resistance). Tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Capacitors with low ESR and high ripple current ratings, such as OS-CON and POSCAP are also available. Ceramic capacitors should be placed near the regulator input and output to suppress high frequency switching noise. A minimum 1F ceramic capacitor should also be placed from VIN to GND and from EXTVCC to GND as close to the LT8711 pins as possible. Due to their excellent low ESR characteristics, ceramic capacitors can significantly reduce ripple voltage and help reduce power loss in the higher ESR bulk capacitors. X5R or X7R dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. Many ceramic ca- pacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired operating voltage. COMPENSATION - ADJUSTMENT To compensate the feedback loop of the LT8711, a series resistor capacitor network in parallel with an optional single capacitor should be connected from the VC pin to GND. For most applications, choose a series capacitor in the range of 0.47nF to 10nF with 2.2nF being a good starting value. The optional parallel capacitor should range in value from 47pF to 220pF with 100pF being a good starting value. The compensation resistor, RC, is usually in the range of 10k to 100k. A good technique to compensate a new application is to use a 100k potentiometer in place of the series resistor RC. With the series and parallel capacitors at 2.2nF and 100pF respectively, adjust the potentiometer while observing the transient response and the optimum value for RC can be found. The series capacitor can be reduced or increased from 2.2nF to speed up the converter or slow down the converter, respectively. Rev A For more information www.analog.com 29 LT8711 TYPICAL APPLICATIONS 400kHz, 5V-40V Input to 3.3V/6.5A Buck VIN 5V TO 40V CIN 10F x5 EN/FBIN VIN BIAS VOUT 2.2F EXTVCC INTVEE LT8711 OPMODE TG INTVCC RT 60.4k 47nF 51k M1 L1 4.7H RSENSE 5m VOUT 3.3V, 6.5A M2 COUT 100F x2 GND SS 68pF 1.5nF BG RT SYNC 2.2F CSP CSN ISP ISN VC RFB1 1M RFB2 316k FB 8711 TA02a L1: COILCRAFT 4.7H XAL7070-472 M1: ST STL42P6LLF6 M2: FAIRCHILD FDMC86520L Efficiency vs Load Current CIN: 10F, 50V, X7R ADDITIONAL 47F, 50V ELECTROLYTIC CAP ON VIN COUT: 100F, 6.3V, X7R ADDITIONAL 470F, 16V ELECTROLYTIC CAP ON VOUT Transient Response with 2A to 5.5A to 2A Output Load Step 100 90 LOAD STEP 5A/DIV EFFICIENCY (%) 80 70 VOUT 200mV/DIV 60 50 40 30 VIN = 5V VIN = 12V VIN = 24V VIN = 36V 20 10 0 0.001 IL1 5A/DIV 0.01 0.1 LOAD CURRENT (A) 1 200s/DIV 8711 TA02c 7 8711 TA02b 30 Rev A For more information www.analog.com LT8711 TYPICAL APPLICATIONS 400kHz, 12V Input to 24V/3A Boost Converter VIN 10.8V TO 13.2V CIN 10F x6 EN/FBIN VIN CSP ISP ISN EXTVCC CSN LT8711 VOUT 2.2F OPMODE INTVCC RT 60.4k VOUT L1 8.2H BG 42pF RFB1 1M M1 RFB2 34k GND SS VOUT 24V, 3A M2 2.2F INTVEE RT SYNC 330nF 1nF BIAS RSENSE 4m COUT 6.8F x4 TG 187k VC FB 8711 TA03a L1: WURTH 8.2H WE-HCI 7443550820 M1: INFINEON BSC026N04 M2: ST STL60P4LLF6 Efficiency vs Load Current CIN: 10F, 50V, X7R ADDITIONAL 47F, 50V ELECTROLYTIC CAP ON VIN COUT: 6.8F, 50V, X7R ADDITIONAL 270F, 50V ELECTROLYTIC CAP ON VOUT Transient Response with 1A to 2.5A to 1A Output Load Step (VIN = 12V) 100 90 LOAD STEP 2A/DIV EFFICIENCY (%) 80 70 60 VOUT 500mV/DIV 50 40 30 20 10 0 0.001 IL1 5A/DIV VIN = 5V VIN = 12V VIN = 20V 0.01 0.1 LOAD CURRENT (A) 1 500s/DIV 8711 TA03c 3 8711 TA03b Rev A For more information www.analog.com 31 LT8711 TYPICAL APPLICATIONS 200kHz, 4.5V-40V Input to 12V/4A SEPIC VIN 4.5V TO 40V CIN 10F x2 VOUT 2.2F INTVEE EXTVCC LT8711 OPMODE INTVCC RT 118k 470nF 100pF 4.7nF VOUT EN/FBIN VIN BIAS 49.9k BG RT SYNC CSP SS CSN GND VC 2.2F L1 8.2H C1 10F x3 M1 RSENSE2 2m M2 RFB1 1M L2 15H RFB2 71.5k RSENSE1 2m VOUT 12V, 4A (VIN > 5V) COUT 22F x3 TG ISP ISN FB 8711 TA04a L1: COILCRAFT 8.2H XAL1510-822ME L2: COILCRAFT 15H XAL1510-153ME M1: VISHAY SiR826ADP M2: ST STL42P6LLF6 Efficiency vs Load Current CIN: 10F, 50V, X7R ADDITIONAL 56F, 50V ELECTROLYTIC CAP ON VIN COUT: 22F, 25V, X7R ADDITIONAL 270F, 25V ELECTROLYTIC CAP ON VOUT Transient Response with 2A to 4A to 2A Output Load Step (VIN = 12V) 100 90 EFFICIENCY (%) 80 70 VOUT 500mV/DIV 60 50 LOAD STEP 2A/DIV 40 30 10 0 0.001 IL1 5A/DIV VIN = 5V VIN = 12V VIN = 24V VIN = 36V 20 0.01 0.1 1 LOAD CURRENT (A) 500s/DIV 8711 TA04c 10 8711 TA04b 32 Rev A For more information www.analog.com LT8711 TYPICAL APPLICATIONS 200kHz, 5V-40V Input to 12V/3.5A ZETA Converter VIN 5V TO 40V CIN 10F EN/FBIN VIN BIAS x6 CSP EXTVCC INTVEE LT8711 TG OPMODE CSP 2.2F CSN INTVCC CSN VOUT RT 118k 330nF 100pF 1nF 62k RT SYNC BG CSP CSN L1A 10H M2 C1 10F x3 L1B 10H SS RSENSE2 3.5m ISP GND VC VOUT 12V, 3.5A (VIN > 16V) 2.5A (9V < VIN < 16V) 1.5A (VIN < 9V) M1 ISN RFB1 1M RFB2 69.8k FB COUT 22F x4 8711 TA05a L1: COILCRAFT 10H MSD1583-103 M1: VISHAY SiR826ADP M2: VISHAY Si7461DP Efficiency vs Load Current CIN: 10F, 50V, X7R ADDITIONAL 56F, 50V ELECTROLYTIC CAP ON VIN COUT: 22F, 25V, X7R ADDITIONAL 270F, 25V ELECTROLYTIC CAP ON VOUT Transient Response with 1.5A to 3A to 1.5A Output Load Step (VIN = 16V) 100 90 LOAD STEP 2A/DIV 80 EFFICIENCY (%) RSENSE1 3.5m 2.2F 70 VOUT 200mV/DIV 60 50 40 IL1 2A/DIV 30 20 VIN = 6V VIN = 12V VIN = 24V 10 0 0.001 0.01 0.1 LOAD CURRENT (A) 1 400s/DIV 8711 TA05c 4 8711 TA05b Rev A For more information www.analog.com 33 LT8711 TYPICAL APPLICATIONS 400kHz, 5V-40V Input to 12V/3.5A Buck-Boost Converter VIN 5V TO 40V CIN 10F x6 100pF VOUT 2.2F EN/FBIN VIN BIAS 330nF 100pF 2.2nF 110k L1 4.7H ISN D2 RSENSE2 4m RT SYNC RFB1 1M ISP GND SS VC M1 D1 INTVCC RT 60.4k 2.2F INTVEE EXTVCC LT8711 TG OPMODE M2 BG CSP RFB2 69.8k 10 10 CSN 10nF FB VOUT 12V, 3.5A (VIN >16V) 2.5A (9V < VIN < 16V) 1.5A (VIN < 9V) COUT 100F x2 RSENSE1 4m 10nF 8711 TA06a L1: COILCRAFT 4.7H XAL8080-472ME M1: ST STL60P4LLF6 M2: FAIRCHILD FDMC86520L D1, D2: VISHAY SS10P6M3 Efficiency vs Load Current Transient Response with 1.5A to 3A to 1.5A Output Load Step (VIN = 9V) 100 90 LOAD STEP 2A/DIV 80 EFFICIENCY (%) CIN: 10F, 50V, X7R ADDITIONAL 47F, 50V ELECTROLYTIC CAP ON VIN COUT: 100F, 16V, X7R ADDITIONAL 390F, 16V ELECTROLYTIC CAP ON VOUT 70 60 VOUT 200mV/DIV 50 40 30 10 0 0.001 IL1 5A/DIV VIN = 5V VIN = 12V VIN = 24V VIN = 36V 20 0.01 0.1 LOAD CURRENT (A) 1 500s/DIV 8711 TA06c 3 8711 TA06b 34 Rev A For more information www.analog.com LT8711 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LT8711#packaging for the most recent package drawings. FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev K) Exposed Pad Variation CB DETAIL A 6.40 - 6.60* (.252 - .260) 3.86 (.152) 3.86 (.152) 0.60 (.024) REF 0.28 (.011) REF 20 1918 17 16 15 14 13 12 11 6.60 0.10 2.74 (.108) 4.50 0.10 DETAIL A 6.40 2.74 (.252) (.108) BSC SEE NOTE 4 0.45 0.05 DETAIL A IS THE PART OF THE LEAD FRAME FEATURE FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 1.05 0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 RECOMMENDED SOLDER PAD LAYOUT 4.30 - 4.50* (.169 - .177) 0.09 - 0.20 (.0035 - .0079) 0.25 REF 0.50 - 0.75 (.020 - .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 1.20 (.047) MAX 0 - 8 0.65 (.0256) BSC 0.195 - 0.30 (.0077 - .0118) TYP 0.05 - 0.15 (.002 - .006) FE20 (CB) TSSOP REV K 0913 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE Rev A For more information www.analog.com 35 LT8711 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LT8711#packaging for the most recent package drawings. UDC Package 20-Lead Plastic QFN (3mm x 4mm) (Reference LTC DWG # 05-08-1742 Rev O) 0.70 0.05 3.50 0.05 2.10 0.05 1.50 REF 2.65 0.05 1.65 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.50 REF 3.10 0.05 4.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3.00 0.10 0.75 0.05 1.50 REF 19 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.25 x 45 CHAMFER 20 0.40 0.10 1 PIN 1 TOP MARK (NOTE 6) 4.00 0.10 2 2.65 0.10 2.50 REF 1.65 0.10 (UDC20) QFN 1106 REV O 0.200 REF 0.00 - 0.05 R = 0.115 TYP 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 36 Rev A For more information www.analog.com LT8711 REVISION HISTORY REV DATE DESCRIPTION A 04/18 Changed from 25mV to 27mV in last sentence. PAGE NUMBER 13 Rev A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 37 LT8711 TYPICAL APPLICATION Boost Pre-Regulator for Automotive Stop-Start/Idle VIN 3V TO 36V CIN 10F x6 VOUT 2.2F RT 100k L1: WURTH 5.6H WE-HCI 7443557560 M1: FAIRCHILD FDS8447 M2: FAIRCHILD FDD4141 D1: FAIRCHILD MBRS340 CIN: 10F, 50V, X7R ADDITIONAL 56F, 50V ELECTROLYTIC CAP ON VIN COUT: 22F, 25V, X7R ADDITIONAL 270F, 25V ELECTROLYTIC CAP ON VOUT 330nF 100pF 2.2nF 100k EN/FBIN VIN CSP ISP ISN EXTVCC LT8711 CSN OPMODE INTVCC BIAS RSENSE 3.5m VOUT L1 5.6H BG GND SS TG VC VOUT 9VMIN, 3A M2 2.2F INTVEE RT SYNC D1 RFB1 560k 2 M1 RFB2 55k COUT 22F x4 2 FB 8711 TA07a No-Load Supply Current Transient VIN and VOUT Waveforms 150 INPUT CURRENT (A) 120 90 VOUT 5V/DIV VIN 5V/DIV 60 0V 30 0 10ms/DIV 0 5 10 15 20 25 INPUT VOLTAGE (V) 30 8711 TA07c 35 8711 TA07b RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT3757A Boost, Flyback, SEPIC and Inverting Controller 2.9V VIN 40V, 100kHz to 1MHz Programmable Operating Frequency, 3mm x 3mm DFN-10 and MSOP-10E LT3758A Boost, Flyback, SEPIC and Inverting Controller 5.5V VIN 100V, 100kHz to 1MHz Programmable Operating Frequency, 3mm x 3mm DFN-10 and MSOP-10E LT3957A Boost, Flyback, SEPIC and Inverting Converter with 5A, 40V Switch 3V VIN 40V, 100kHz to 1MHz Programmable Operating Frequency, 5mm x 6mm QFN LT3958 Boost, Flyback, SEPIC and Inverting Converter with 3.3A, 84V Switch 5V VIN 80V, 100kHz to 1MHz Programmable Operating Frequency, 5mm x 6mm QFN LT8705A 80V VIN and VOUT Synchronous 4-Switch Buck-Boost DC/DC Controller 2.8V VIN 80V, 100kHz to 400kHz Programmable Operating Frequency, 5mm x 7mm QFN-38 and TSSOP-38 LT8709 Negative Input Synchronous Multitopology DC/DC Control -80V VIN -4.5V, Up to 400kHz Programmable Operating Frequency, TSSOP-20 LT8710 Synchronous SEPIC/Inverting/Boost Controller with Output Current Control 4.5V VIN 80V, 100kHz to 1MHz Programmable Operating Frequency, TSSOP-20 LT8714 Bipolar Output Synchronous Controller with Seamless Four Quadrant Operation 4.5V VIN 80V, Output Can Source or Sink Current for Any Output Voltage, Switching Frequency Up to 750kHz, 20-Lead TSSOP 38 Rev A D16855-0-4/18(A) For more information www.analog.com www.analog.com ANALOG DEVICES, INC. 2017-2018