82551IT Fast Ethernet PCI
Controller
Networking Silicon - 82551IT
Datasheet
Product Features
1 This device is lead-free. That is, lead ha s not been intentionally added, but lead may still exist as an
impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the
concentration of other Restriction on Hazardous Substances (RoHS)-banned materials, is available at:
ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks
In addition, this device has been tested and conforms to the same parametric specifications as previous
versions of the device.
For m ore information regarding lead-free products from Intel Corporation, contact your Intel Field Sales
representative.
Enhanced IP Protocol Support
— TCP, UDP, IPv4 checksum offload
— Received chec ksum verification
Quality of Service (QoS)
— Multiple priority transmit queues
Optimum Integration for Lowest Cost Solution
— Integrated IEEE 802.3 10BASE-T and
100BASE-TX compatible PHY
— 32-bit PCI master interface
— Thin BGA 15mm2 package
Integrated power management functions
— ACPI and PCI power management standards
compliance
— W ake on “interesting” packets and link status
change support
PHY detects polari ty , MDI-X, and cable len gths.
Auto MDI, MDI-X crossover at all speeds
XOR tree mode support
High Performance Networking Functions
— Early release
— 8255x controller family chained memory
structure
— Improved dynamic transmit chaining with
multiple prioriti es tra n smit queues
— Full pin compatibility with the 82559 and
82559ER controllers
— Backward compatible software to 8255xER
controllers
— Full duplex support at 10 and 100 Mbps
— IEEE 802.3u auto-negotiation support
— 3 KB transmit and receive FIF Os
— Fast back-to-back transmission support with
minimum interframe spacin g
— IEEE 802.3x 100BASE-TX flow control
support
— Adaptive Technology
Low Power Features
— Advanced Power Management (APM)
capabilities
— Low power 3.3 V device
— Efficient dynamic standby mode
— Deep power-down support
— Clockrun protocol support
82551IT Enhancements
— Wider operating temperature range
— Improved bit error rate performance
— HWI support
— Deep power-down state power reduction
Lead-free1 196-pin Ball Grid Ar ray (BGA).
Devices that are lead-free are marked with a
circled “e1” and have the product code:
LUxxxxxx.
317801-004
Revision 4.1
ii Datasheet
Revision History
Revision Date Revision Description
Oct 2003 3.0 • Initial draft for release (non-classifie d).
Sep 2004 3.1 • Added references to the MDI/MDI-X feature.
• Added lead-free information.
• Removed EEPROM Map bit d escriptions. These description s can now be found in
the 82551QM/ER/IT EE PROM Map and Programming Informati on.
• Added 82551IT Test Port Functionality (Chapter 10).
• Added new values for RBI AS100 and RBIAS10. RBIAS100 = 649 and RBIAS10
= 619 .
• Removed all refe rences to th e 8 2551 ER and 8 2551 QM con trollers. 82 551ER an d
82551QM information can now be found in their respective datasheets.
Nov 2004 3.2 • Updated the section describing “Multiple Priority Transmit Queu es”.
• Updated the section describing “VLAN Support”.
• Added information a bout migrating f rom a 2-layer 0. 36 mm wide-trace substra te to
a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Package and Pin-
out Informati on.
• Added statement that no changes to existing soldering processes are needed for
the 2-layer 0.32 mm wide-trace substrate change in the section describing “Pack-
age Information”.
Jan 2005 3. 3 • Added a note for PHY signals RBIAS1 00 and RBIAS10 to Table 8.
April 2005 3.4 • Corrected the not e i n sect ion 11stati ng t hat the maximum rating fo r t he Ca se Tem-
perature under Stress for the 82551QM/ ER is 70° C instead of 85° C.
July 2005 3.5 • Corrected the X1 Clock Specifications for symbol Tx1_pr from ±50 ppm to ±30
ppm.
Oct 2006 3.6 • Added Figure 28 “196 PB GA P ackage Pa d Detail”. The figure sh ows solder r esist
opening and metal diameter dimensions.
Feb 2007 3.7 • Updated section 11.1 “Absolute Maximum Ratings”.
Sept 2007 3.8 • Added Section 13 “Ref erence Schematics”, u pdated Section 11.1 (changed Tcase
to ambient) and added ordering information to Section 1.4.
Sept 2007 3. 9 • Updat ed Figur es 31 and 32. Added Digital I/O and Crystal Input One (X1) Charac-
teristics (Tables 52 and 53). Updated Section 5.6.4.
March 2008 4.0 • Updated Figure 32: changed TEST pull down resistor value (62 K to 1 K).
Nov 2008 4.1 • Updated Table 12 (changed words 30h:33h to reserved).
• Updated Table 8 (X1 and X2 pin descriptions).
• Updated Tables 52 and 53 (Digital I/O and crystal input one (X1) characteristics).
Information in this document is provided in connection with Intel products . No license , express or implied , by estop pel or othe rwise, to an y intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warra nty, relating to sale and/or u se of Intel p rodu cts including liabi l ity or warranties r elating to
fitness for a particular pur pose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustainin g applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "r eserved" or "undefined." Intel reserves these for
future definition and shall have no resp onsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82551IT may contain design defects or errors known as errat a which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specification s and before placing your product order.
Copies of documents which have an ordering number and are refer enced in this document, or other Intel literature, may be obtained f rom:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800 -548-4725 , Europe 44-0-1793-431- 155, France 44- 0-1793-4 21-777, German y 44-0-1793- 421-333, oth er Countries 7 08-
296-9333
Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
Copyright © 2008, Intel Corporation.
* Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owners’ benefit, without
intent to infringe.
Datasheet iii
Networking Silicon — 82551IT
Contents
1.0 Introduction.........................................................................................................................1
1.1 Overview ...............................................................................................................1
1.2 Byte Ordering........................................................................................................1
1.3 References............................................................................................................1
1.4 Product Ordering Codes........................................................................................2
2.0 Architectural Overview .............. ... ... .... ... ................ ... .... ... ... ... ... .... ... ... ................ ... .... ... ... ..3
2.1 Parallel Subsystem Overview................................................................................3
2.2 FIFO Subsystem Overview ...................................................................................3
2.3 10/100 Mbps Serial CSMA/CD Unit Overview ......................................................4
2.4 10/100 Mbps Physical Layer Unit..........................................................................4
3.0 Performance Enhancements..............................................................................................5
3.1 Multiple Priority Transmit Queues.........................................................................5
3.2 Early Release........................................................................................................5
3.3 Hardware Integrity Support ...................................................................................6
3.4 Management Data Interface MD I/MDI -X Feature................ ... ... ................ .... ... ... ..6
4.0 Signal Descriptions. ... ... ... .... ... ................ ... ... .... ... ... ... ................ .... ... ... ... .... ... ................ .....7
4.1 Signal Type Definitions ... ... .... ... ... ... ................. ... ... ... ... .... ... ................ ... ... .... ... ... ..7
4.2 PCI Bus Interface Signals .....................................................................................8
4.2.1 Address and Data Signals .......................................................................8
4.2.2 Interface Control Signals .........................................................................8
4.2.3 System and Power Management Signals ...............................................9
4.3 Local Memory Interface Signals..........................................................................10
4.4 Test Port Signals ................................................................................................11
4.5 PHY Signals .......................................................................................................12
4.6 Power and Ground Signals .................................................................................13
5.0 Media Access Control Functional Description..................................................................15
5.1 Device Initialization..............................................................................................15
5.1.1 Initialization Effects.................................................................................15
5.2 PCI Interface .......... ... ... ... ... .... ... ................ ... .... ... ... ................ ... .... ... ... ... .............16
5.2.1 Bus Operations.......................................................................................16
5.2.2 Clock Run Signal....................................................................................24
5.2.3 Power Management Event.....................................................................25
5.3 PCI Power Management................. ................. ... ... ... ... .... ... ... ... .... ................ ... ...25
5.3.1 Power States..........................................................................................25
5.3.2 Wake-up Events.....................................................................................29
5.4 Parallel Flash.......................................................................................................30
5.5 Serial EEPROM Interface... .................................................................................30
5.5.1 EEPROM Address Map..........................................................................32
5.6 10/100 Mbps CSMA/CD Unit...............................................................................32
5.6.1 Full Duplex .............................................................................................33
5.6.2 Flow Control.......... .... ................ ... ... .... ... ... ... ................ .... ... ... ... ... .... ......33
5.6.3 Address Filtering Modifications ..............................................................33
5.6.4 VLAN Support ........................................................................................33
82551IT — Networking Silicon
iv Datasheet
5.7 Media Independent Interface (MII) Management Interface.......... .... ... ... ... ... .... ...34
6.0 Physical Layer Functional Description.............................................................................35
6.1 100BASE-TX PHY Unit.......................................................................................35
6.1.1 100BASE-TX Transmit Clock Generation..............................................35
6.1.2 100BASE-TX Transmit Blocks ...............................................................35
6.1.3 100BASE-TX Receive Blocks ................................................................35
6.1.4 100BASE-TX Link Integrity Auto-Negotiation.........................................36
6.2 10BASE-T PHY Functions ..................................................................................36
6.2.1 10BASE-T Transmit Clock Generation...................................................36
6.2.2 10BASE-T Transmit Blocks....................................................................36
6.2.3 10BASE-T Receive Blocks.....................................................................36
6.2.4 10BASE-T Link Integrity and Full Duplex...............................................37
6.3 Auto-Negotiation .................................................................................................37
6.3.1 Description .............................................................................................37
6.3.2 Parallel Detect and Auto-Negotiation.....................................................37
6.4 LED Description . ... .... ... ................ ... ... .... ... ... ... ................ .... ... ... ... .... ... ................38
7.0 Configuration Registers....................................................................................................41
7.1 Function 0: LAN (Ethernet) PCI Configuration Space......... ... ... ... .... ................ ...41
7.1.1 PCI Vendor ID and Device ID Registers ................................................41
7.1.2 PCI Command Register .........................................................................42
7.1.3 PCI Status Register................................................................................43
7.1.4 PCI Revision ID Register........................................................................45
7.1.5 PCI Class Code Register .......................................................................45
7.1.6 PCI Cache Line Size Register................................................................45
7.1.7 PCI Latency Timer .................................................................................45
7.1.8 PCI Header Type ...................................................................................45
7.1.9 PCI Base Address Registers..................................................................46
7.1.10 Base Address Registry Summary .......................... ... ... ... .... ... ... ... ... .... ...47
7.1.11 PCI Subsystem Vendor ID and Subsystem ID Registers.......................47
7.1.12 Capability Pointer...................................................................................48
7.1.13 Interrupt Line Register............................................................................48
7.1.14 Interrupt Pin Register .............................................................................48
7.1.15 Minimum Grant Register ........................................................................49
7.1.16 Maximum Latency Register....................................................................49
7.1.17 Capability ID Register ............................................................................49
7.1.18 Next Item Pointer ...................................................................................49
7.1.19 Power Management Capabilities Register.............................................49
7.1.20 Power Management Control/Status Register (PMCSR).........................50
7.1.21 Data Register .........................................................................................51
8.0 Control/Status Registers..................................................................................................53
8.1 LAN (Ethernet) Control/Status Registers ............................................................53
8.1.1 System Control Block Status Word........................................................54
8.1.2 System Control Block Command Word..................................................55
8.1.3 System Control Block General Pointer...................................................55
8.1.4 PORT .....................................................................................................55
8.1.5 Flash Control Register ...........................................................................55
8.1.6 EEPROM Control Register.... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... .............56
8.1.7 Management Data Interface Control Register........ ................ ... ... ... .... ...56
Datasheet v
Networking Silicon — 82551IT
8.1.8 Receive Direct Memory Access Byte Count. ... .... ... ... ... .... ... ... ... ... .... ... ...56
8.1.9 Flow Control Register......... .... ................ ... ... ... .... ... ... ... .... ... ................ ...56
8.2 Statistical Counters ......... ... .... ... ... ... ....................................................................57
9.0 PHY Unit Registers ..........................................................................................................61
9.1 MDI Registers 0 - 7 .............................................................................................61
9.1.1 Register 0: Control Register ..................................................................61
9.1.2 Register 1: Status Register ...................................................................62
9.1.3 Register 2: PHY Identifier Register .......................................................63
9.1.4 Register 3: PHY Identifier Register .......................................................63
9.1.5 Register 4: Auto-Negotiation Advertisement Register ...........................63
9.1.6 Register 5: Auto-Negotiation Link Partner Ability R egister . ... ... ... .... ... ...64
9.1.7 Register 6: Auto-Negotiation Expansion Register .................................64
9.2 MDI Registers 8:15..............................................................................................64
9.3 MDI Register 16:31 .............................................................................................65
9.3.1 Register 16: PHY Unit Status and Control Register ..............................65
9.3.2 Register 17: PHY Unit Special Control Register ...................................65
9.3.3 Register 18: PHY Address Register.......................................................66
9.3.4 Register 19: 100BASE-TX Receive False Carrier Counter ...................66
9.3.5 Register 20: 100BASE-TX Receive Disconnect Counter ......................67
9.3.6 Register 21: 100BASE-TX Receive Error Frame Counter ....................67
9.3.7 Register 22: Receive Symbol Error Counter .........................................67
9.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error Coun-
ter ..........................................................................................................67
9.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter .............67
9.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter .....................68
9.3.11 Register 26: Equalizer Control and Status Register ..............................68
9.3.12 Register 27: PHY Unit Special Control Register ...................................68
9.3.13 Register 28: MDI/MDI-X Control Register ..............................................69
9.3.14 Register 29: Hardware Integrity Control Register ..................................69
10.0 82551IT Test Port Functionality .......................................................................................71
10.1 Introduction..........................................................................................................71
10.2 Test Function Description....................................................................................71
10.2.1 Tristate ...................................................................................................71
10.2.2 XOR Tree...............................................................................................72
11.0 Electrical and Timing Specifications................. ... ... ... .... ... ... ... ... .... ... ... ... .... ................ ... ...75
11.1 Absolute Maximum Ratings.................................................................................75
11.2 DC Specifications ...............................................................................................76
11.3 AC Specifications................................................................................................80
11.4 Timing Specifications ...... ... .... ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... ... .... ... ...81
11.4.1 Clocks Specifications ......... .... ... ... ... .... ... ... ... ... .... ... ................ ... ... .... ... ...81
11.4.2 Timing Parameters....... ... ... .... ... .............................................................82
82551IT — Networking Silicon
vi Datasheet
12.0 Package and Pinout Information......................................................................................89
12.1 Package Information ...........................................................................................89
12.2 Pinout Information. .... ... ... ... ... .... ................ ... ... .... ... ... ... ................ .... ... ... ... ... .... ...91
12.2.1 Pin Assignments ...................................................................................91
12.2.2 Ball Grid Array Diagram .........................................................................93
13.0 Reference Schematics.....................................................................................................94
Networking Silicon — 82551IT
Datasheet 1
1.0 Introduction
This datasheet is applicable to the Intel® 82551IT Fast Ethernet PCI Contro ller, a mem ber of the
8255x Fast Ethernet Controller family.
1.1 Overview
The 82551IT is an evolutionary addition to Intel’ s family of 8255x controllers. It provides excellent
performance by offloading TCP, UDP and IP checksums and supports TCP segmentation off-load
for operations such as Large Send. The 82551IT provides an extended operating temperature in
addition to all of the same capabilities and features as the 82551ER to address applications
requiring a wider operating temperature range.
Its optimized 32-bit interface and efficient scatter-gather bus mastering capabilities enable the
82551IT to perform high speed data transfers over the PCI bus. This capability accelerates the
processing of high level comm ands and operations, which lowers CPU utilization. Its architecture
enables data to flow efficiently from the bus interface unit to the 3 KB Transmit and Receive
FIFOs, providing the perfect balance between the wire and system bus. In addition, multiple
priority queues are provided to prevent data underru ns and overruns.
The 82551IT includes both a MAC and PHY. In also has a s imple interface to the analog front end,
which allows cost effective designs requiring minimal board real estate. The 82551IT is pin
compatible with the 82559 family of controllers and is offered with software that provides
backwards compatibility with previous 825 5xER controllers.
1.2 Byte Ordering
TCP and IP Internet Engineering Task Force (IETF) Request for Comments (RFCs) and literature
use big endian (BE) byte ordering. This document uses big endi an ordering for all IP and TCP
frame formats. However, little endian byte ordering is used for referencing 82551IT memory
resident structures and intern al structures.
1.3 References
The following documents may provide further information on topics discussed in this document.
•10/100 Mbit Ethernet Cont roller Family Software Developer’s Manual. In tel Corporation.
•Advanced Configuration and Power Interface Specification, Revision 1.0. Intel Corporation,
Microsoft Corporation, and Toshiba.
•IEEE 802.3x and 802.1y Standards.
•Network Device Class Power Management Reference Specification, Revision 1.0a. AMD, Inc.
and Microsoft Corporation.
82551IT — Networking Silicon
2 Datasheet
1.4 Product Ordering Codes
Product ordering codes for the 82551IT Fast Ethernet PCI controller:
•GD82551IT (Leaded)
•LU82551IT (Lead Free)
Figure 1. 82551IT Component Markings
Legend:
GRP1LINE1 - 82551IT
GRP1LINE2 - (FPO)
GRP1LINE3 - Blank
GRP1LINE4 - (M) (C) ‘01 (l eaded); (M) (C) ‘01 (e1) (lead free)
Device Stepping MM Number Specification Notes
LU82551IT A0 860607 Production (Tray)
LU82551IT A0 860615 S L7G3 Production (Tape and Reel)
GD82551IT A0 855622 S L77C Production (Tray)
GD82551IT A0 855623 S L77D Production (Tape and Reel)
GRP1LINE1
GRP1LINE2
GRP1LINE3
GRP1LINE4
PIN 1
BSMC
BSMC = Bottom-Side Mark Code
Networking Silicon — 82551IT
Datasheet 3
2.0 Architectural Overview
The Intel® 82551IT is divided into four main subsystems: a parallel subsystem, a FIFO subsystem,
a 10/100 Mbps Carrier Sense Multiple Access with Collision Detect (CSMA/CD) unit , and a 10/
100 Mbps physical layer (PHY) unit.
2.1 Parallel Subsystem Overview
The parallel subsystem is comprised of several functional blocks: a PCI bus master interface, a
micromachine processing unit and its corresponding micro code ROM, and a PCI Target Control/
Flash/EEPROM interface. The parallel subsystem also interfaces to the FIFO subsystem, passing
data (such as transmit, receive, and configuration data) and command and status parameters
between these two blocks.
The PCI bus master interface provides a complete glueless interface to a PCI bus and is compliant
with the PCI Bus Specification, Revision 2.2. The 82551IT provides 32 bits of addressing and data,
as well as the PCI control interface. As a PCI target, it conforms to the PCI configuration scheme,
which allows all accesses to the 82551IT to be automatically mapped into free memory and I/O
space upon initializati on of a PCI system. When transmit and receive data is processed, the
82551IT operates as a master on the PCI bus, initiating zero wait state transfers.
The 82551IT Control/Status Register Block is part of the PCI target element. The Control/Status
Register block consists of the following 8 255 1IT internal control registers: System Control Block
(SCB), PORT, Flash Control, EEPROM Control, and Management Data Interface (MDI) Control.
An embedded micromachine consisting of independent transmit and receive processing units allow
the 82551IT to execute commands and receive incoming frames with no real time CPU
intervention.
The 82551IT contains a multiplexed interface to connect an external serial EEPROM and Flash
memory. The Flash interface, which can also be used to connect to any standard 8-bit device,
provides up to 128 KB of addressing to the Flash. Both read and write accesses are supported. The
Flash can be used for remote boot functio ns, network statistical and diag nosti cs functions, and
management functions. The Flash is mapped into host system memory (anywhere within the 32-bit
memory address space) for software accesses. It is also mapped into an available boot expansion
ROM location during boot time of the system . More information on the Flash interface is detailed
in Section 5.4, “Parallel Flash”. The serial EEPROM is used to store relevant information for a
LAN connection such as node address, as well as board manufacturing and configuration
information. Both read and write accesses to the EEPROM are supported by the 82551IT.
Information on the EEPROM interface is detailed in Section 5.5, “Serial EEPROM Interface”.
2.2 FIFO Subsystem Overview
The 82551IT FIFO subsystem consists of independent 3 KB transmit and receive FIFOs. Each
FIFO provides a temporary buffer for frames as they are transmitted or received. Transmit frames
queued within the transmit FIFO allow back-to -back transmission within the minimum Interframe
Spacing (IFS). The FIFOs allow the 82551IT to withstand long PCI bus laten c ies without losing
incoming data. Additional attributes of the FIFOs that enhance performance and functionality are:
82551IT — Networking Silicon
4 Datasheet
•Tunable transmit FIFO threshold allows elim in at ion of underruns while concurrent transmits
are being performed.
•Extended PCI zero wait state burst accesses to and from the 82551IT for both transmit and
receive FIFOs
•Efficient re-transmission of data directly from the transmit FIFO when physical or data link
errors (collision detection or data underrun) are encountered, in creasing performance by
eliminating the need to re-access the data from host memory
•Automatic discard of incoming runt receive frames
2.3 10/100 Mbps Serial CSMA/CD Unit Overview
The 82551IT’s CSMA/CD unit allows it to be connected to a 10 or 100 Mbps Ethernet network at
half or full duplex. The CSMA/CD unit performs all of the functions of the 802.3 protocol such as
frame formatting, frame stripping, collision handling, deferral to link traffic, etc.
2.4 10/100 Mbps Physical Layer Unit
The integrated Physical Layer (PHY) uni t of the 82551IT allows connection to either a 10 or 100
Mbps Ethernet network. The PHY supports Auto-Nego tiation for 100BASE-TX Full Duplex,
100BASE-TX Half Duplex, 10BASE-T Full Duplex, and 10BASE-T Hal f Duplex. Three LED
pins indicate link status, network activity, and speed.
Networking Silicon — 82551IT
Datasheet 5
3.0 Performance Enhancements
All of Intel’ s Fast Ethernet controllers have the ability to support full wire speeds. The 82551IT has
been designed to provide improved networking throughput. Performance is limited to the system’s
ability to feed data to the network controller.
As networks grow, the task of servicing the network becomes a large burden on the platform.
System bottlenecks prevent optimal perfo rm a nce in typ ical operatin g conditions. Thus, to help
alleviate these issues, Network Operating System (NOS) vendors are establishing normalized off-
load specifications. These specifications define the types of off-load support required by the OS
and interface between the network drivers. The 82551IT prov ides support for these initiatives and
enables an improvement in platform network efficiency. W ith the pervasiveness of Internet
Protocols, the off-load capabilities have focused on improving IP efficiency. As part of this effort,
the 82551IT includes support for Multiple Priorit y Transmit Queues.
3.1 Multiple Priority Transmit Queues
The 82551IT supports two queues: High Priority Queue (HPQ) and Low Priority Queue (LPQ).
The 82551IT provides a method for the driver to modify the HPQ while processing data. A new
read only register is defined in the Control/Status Register (CSR) that enables the driver to change
the transmit priority of elements within the HPQ. When software reads this register, the address of
the next Command Block to be processed by the 82551IT on the HPQ is returned. After reading
this register , software can freely modify the next Command Block (for example, overwrite it with a
different Command Block) and any subsequent Command Block, without any conflict with the
82551IT.
Note: The 82551IT Windows* driver supports the Command Bloc k Pointer register (in the CSR).
3.2 Early Release
Like the 82558, 82559 and 82550, the 825 51IT s upports a 3 KB transmit FIFO. The 8255 1IT
provides a transmit FIFO enhancement called “early release” that effectively increases the amount
of free capacity in the transmit FIFO. The enabling of early release is controlled through
configuration space and occurs when the following conditions are met:
1. The transmitted frame is the oldest one in the queue (in other words, it is located at the head of
the queue).
2. The transmitted frame has been completely transferred to the XMT-SRAM and processed (for
example, XSUM). Large frames (greater than 3 KB) are never candidates for an early release.
3. When the preemptive queue mechanism is on, a frame which satisfies condi tion 2 may not
satisfy condition 1 and therefore will not benefit from an early release.
4. More than 128 bytes have already been transferred to the XMT-SYNC-FIFO. This condition
guarantees that at least one slot time elapsed (collision window).
82551IT — Networking Silicon
6 Datasheet
3.3 Hardware Integrity Support
Cabling problems are a common cause for network downtime situations. Hardware Integrity
(HWI) can help reduce this by locating cabling problems. It uses transmission line theory to
measure the arrival time and electrical characteristics of the wave reflected from an incident test
wave launched on the media. With these measurements, opens, shorts, and degraded cable quality
can be located along the wire.
HWI is controlled and activated by software. The Hardware Integrity Control, register 29 of the
MDI Registers, is used for activating HWI (Section 9.3.14, “Register 29: Hardware Integrity
Control Register”).
3.4 Management Data Interface MDI/MDI-X Feature
The 82551IT controller MDI/MDI-X feature provides the ability to automatically detect the
required cable connection type and configure the controller -side MAU to the cable type. This
feature effectively allows all properly wired Ethernet cables usable with any Ethernet device to be
connected to the 82551IT withou t any addi tional external logic.
This advanced feature enables auto-correction of incorrect cabling with respect to cross-over
versus straight-through cables. The 82551IT can identify the cable connecti on type and adjust its
MDI port to the cable by switching between the TD and RD pairs. The auto-switching is done prior
to the start of the hardware auto negot iati on algorithm.
In a standard straight-through RJ-45 port configuration, the transmit pair is on contacts 1 and 2, and
the receive pair on contacts 3 and 6. These are defined by Clause 23.7.1 of the IEEE 802.3u
standard.
Table 1 lists the connections for both straight-through and cross-over RJ-45 ports for comparison.
Table 1. RJ-45 Connections
RJ-45
Contact Straight-Through
MDI Signala
a. Straight-through connections used on DTE applications.
Cross-Over MDIX
Signalb
b. Cross-over connections used on Hub and Switch applications.
1 TD+ RD+
2 TD- RD-
3RD+ TD+
4 Not Used Not Used
5 Not Used Not Used
6RD- TD-
7 Not Used Not Used
8 Not Used Not Used
Networking Silicon — 82551IT
Datasheet 7
4.0 Signal Descriptions
4.1 Signal Type Definitions
Table 2. Signal Type Descriptions
Type Name Description
IN Input The input pin is a standard input only signal.
OUT Output The output pin is a Totem Pole Output pin and is a standard
active driver.
TS Tri-State The tri-state pin is a bidirectional, input/output pin.
STS Sustained Tri-State
The sustained tri-state pin is an active low tri-state signal owned
and driven by one agent at a time. The agent asserting the STS
pin low must drive it high at least one clock cycle before floating
the pin. A new agent can only assert an STS signal low one
clock cycle after it has been tri-stated by the previous owner.
OD Open Drain The open drain pin allows multiple devices to share this signal
as a wired-OR.
AI Analog Input The analog input pin is used for analog input signals.
AO Analog Output The analog output pin is used for analog output signals.
B Bias The bias pin is an input bias.
DPS Digital Power
Supply Digital power or ground for the device.
APS Analog Power
Supply Analog power or ground for the device.
82551IT — Networking Silicon
8 Datasheet
4.2 PCI Bus Interface Signals
4.2.1 Address and Data Signals
4.2.2 Interface Control Signals
Table 3. Address and Data Signals
Symbol Type Name and Func tion
AD[31:0] TS
Address and Data. The address and data lines are multiplexed on
the same PCI pins. A bus transaction consists of an address phase
followed by one or more data phases. During the address phase, the
address and data lines contain the 32-bit physical address. For I/O,
this is a byte address; for configuration and memory, it is a Dword
address. The 82551IT uses little-endian byte ordering (in other words,
AD[31:24] contain the most significant byte and AD[7:0] contain the
least significant byte). During the data phases, the address and data
lines contain data.
C/BE#[3:0] TS
Command and Byte Enable. The bus command and byte enable
signals are multiplexed on the same PCI pins. During the address
phase, the C/BE# lines define the bus command. During the data
phase, the C/BE# lines are used as Byte Enables. The Byte Enables
are valid for the entire data phase and determine which byte lanes
carry meaningful data.
PAR TS
Parity. Parity is even across AD[31:0] and C/BE#[3:0] lines. It is stable
and valid one clock after the address phase. For data phases, PAR is
stable and valid one clock after either IRDY# is asserted on a write
transaction or TRDY# is asserted on a read transaction.Once PAR is
valid, it remains valid until one clock after the completion of the current
data phase. The master drives PAR for address and write data
phases; and the target, for read data phases.
Table 4. Interface Control Signals
Symbol Type Name and Func tion
FRAME# STS
Cycle Frame. The cycle frame signal is driven by the current master
to indicate the beginning and duration of a transaction. FRAME# is
asserted to indicate the start of a transaction and de-asserted during
the final data phase.
IRDY# STS
Initiator Ready. The initiator ready signal indicates the bus master’s
ability to complete the current data phase and is used in conjunction
with the target ready (TRDY#) signal. A data phase is completed on
any clock cycle where both IRDY# and TRDY# are sampled asserted
(low) simultaneously.
TRDY# STS
Target Ready. The target ready signal indicates the selected device’s
ability to complete the current data phase and is used in conjunction
with the initiator ready (IRDY#) signal. A data phase is completed on
any clock cycle where both IRDY# and TRDY# are sampled asserted
(low) simultaneously.
STOP# STS
Stop. The stop signal is driven by the target to indicate to the initiator
that it wishes to stop the current transaction. As a bus slave, STOP# is
driven by the 82551IT to inform the bus master to stop the current
transaction. As a bus master, STOP# is received by the 82551IT to
stop the current transaction.
Networking Silicon — 82551IT
Datasheet 9
4.2.3 System and Power Management Signals
IDSEL IN
Initialization Device Select. The initialization device select signal is
used by the 82551IT as a chip select during PCI configuration read
and write transactions. This signal is provided by the host in PCI
systems.
DEVSEL# STS
Device Select. The device select signal is asserted by the target once
it has detected its address. As a bus master, the DEVSEL# is an input
signal to the 82551IT indicating whether any device on the bus has
been selected. As a bus slave, the 82551IT asserts DEVSEL# to
indicate that it has decoded its address as the target of the current
transaction.
REQ# TS Request. The request signal indicates to the bus arbiter that the
82551IT desires use of the bus. This is a point-to-point signal and
every bus master has its own REQ#.
GNT# IN Grant. The grant signal is asserted by the bus arbiter and indicates to
the 82551IT that access to the bus has been granted. This is a point-
to-point signal and every master has its own GNT#.
INTA# OD Interrupt A. The interrupt A signal is used to request an interrupt by
the 82551IT. This is an active low, level-triggered interrupt signal.
SERR# OD System Error. The system error signal is used to report address
parity errors. When an error is detected, SERR# is driven low for a
single PCI clock.
PERR# STS
Parity Error. The parity error signal is used to report data parity errors
during all PCI transactions except a S pecial Cycle. The parity error pin
is asserted two clock cycles after the error was detected by the device
receiving data. The minimum duration of PERR# is one clock for each
data phase where an error is detected. A device cannot report a parity
error until it has claimed the access by asserting DEVSEL# and
completed a data phase.
Table 5. System and Power Management Signals
Symbol Type Name and Function
CLK IN
Clock. The Clock signal provides the timing for all PCI transactions
and is an input signal to every PCI device. The 82551IT requires a PCI
Clock signal (frequency greater than or equal to 16 MHz) for nominal
operation. The 82551IT supports Clock signal suspension using the
Clockrun protocol.
CLK_RUN# IN/OUT
OD
Clockrun. The Clock Run signal is used by the system to pause or
slow down the PCI Clock signal. It is used by the 82551IT to enable or
disable suspension of the PCI Clock signal or restart of the PCI clock.
When the Clock Run signal is not used, this pin should be connected
to an external pull-down resistor.
RST# IN
Reset. The PCI Reset pin is used to place PCI registers, sequencers,
and signals into a consistent state. When RST# is asserted, the
82551IT ignores other PCI signals and all PCI output signals will be
tristated. The PCI Reset pin should be pulled high to the main digital
power supply.
PME# OD Power Management Event. The Power Management Event signal
indicates that a power management event has occurred in a PCI bus
system.
Table 4. Interface Control Signals
Symbol Type Name and Function
82551IT — Networking Silicon
10 Datasheet
4.3 Local Memory Interface Signals
Note: All unused Flash Address and Data pins MUST be left floating. Some of these pins have
undocumented test functionality and can cause unpredictable behavior if they are
unnecessarily connected to a pull-up or pull-down resistor.
ISOLATE# IN
Isolate. The Isolate pin is used to isolate the 82551IT from the PCI
bus. It also provides PCI Reset pin functionality . When Isolate is active
(low), the 82551IT does not drive its PCI outputs (except PME#) or
sample its PCI inputs (including CLK and RST#). The ISOLATE# pin
should be driven by the PCI Reset signal.
ALTRST# IN Alternate Reset. The Alternate Reset pin is used to reset the 82551IT
on power-up. The Alternate Reset signal should be pulled high to the
main digital power supply.
VIO B
IN
Voltage Input/Output. The VIO pin is the voltage bias pin and should
be connected to a 5 V supply in a 5 V PCI signaling environment and a
3.3 V supply in 3.3 V signaling environment.
Table 6. Local Memory Interface Signals
Symbol Type Name and Func tion
FLD7:0 IN/OUT Flash Data Input/Output. These pins are used for the Flash data
interface. These pins should be left floating if the Flash is not used.
FLA16/
CLK25 IN/OUT
Flash Address 16/25 MHz Clock. This multiplexed pin is controlled
by the status of the Flash Address 7 (FLA7) pin. If FLA7 is left floating,
this pin is used as FLA16; otherwise, if FLA7 is connected to a pull-up
resistor, this pin is used as a 25 MHz clock output. This pin should be
left floating if the Flash and the CLK25 functionality are not used.
FLA15/EESK OUT
Flash Address 15/EEPROM Data Output. During Flash accesses,
this multiplexed pin acts as the Flash Address 15 output signal. During
EEPROM accesses, it acts as the serial shift clock output to the
EEPROM.
FLA14/
EEDO IN/OUT
Flash Address 14/EEPROM Data Output. During Flash accesses,
this multiplexed pin acts as the Flash Address 14 output signal. During
EEPROM accesses, this pin accepts serial input data from the
EEPROM Data Output pin.
FLA13/EEDI OUT
Flash Address 13/EEPROM Data Input. During Flash accesses, this
multiplexed pin acts as the Flash Address 13 output signal. During
EEPROM accesses, this pin provides serial output data to the
EEPROM Data Input pin.
FLA12:8 IN/OUT Flash Address 12:8. These pins act as Flash address outputs. They
should be left floating if Flash is not used.
FLA7/
CLKEN IN/OUT
Flash Address 7/Clock Enable. This multiplexed pin acts as the
Flash Address 7 output signal during nominal operation. When the
power-on reset of the 82551IT is active, this pin acts as input control
over the FLA16/CLK25 output signal. If the FLA7/CLKEN pin is
connected to a pull-up resistor (3.3 K), a 25 MHz clock signal is
provided on the FLA16/CLK25 output; otherwise, it is used as FLA16
output. For systems that do not use the 25 MHz clock output or Flash,
this pin should be left floating.
Table 5. System and Power Management Signals
Symbol Type Name and Func tion
Networking Silicon — 82551IT
Datasheet 11
4.4 Test Port Signals
Note: These test port signals are not JTAG compatible. As a result, a BSDL file is not required.
FLA6:2 OUT Flash Address 6:2. These pins are used as Flash address outputs.
These pins should be left floating if the Flash is not used.
FLA1/
AUXPWR TS
Flash Address 1/Auxiliary Power. This multiplexed pin acts as the
Flash Address 1 output signal during nominal operation. When the
power-on reset of the 82551IT is active (low), it acts as the power
supply indicator. If the 82551IT is fed by auxiliary power, it should be
connected to VCC through a pull-up resistor (3.3 K). Otherwise, this
pin should be left floating.
FLA0/
PCIMODE# TS
Flash Address 0/PCI Mode. This multiplexed pin acts as the Flash
Address 0 output signal during nominal operation. When power-on
reset of the 82551IT is active (low), it acts as the input system type.
For PCI systems that do not use Flash, this pin should be left floating.
EECS OUT EEPROM Chip Select. The EEPROM Chip Select signal is used to
assert chip select to the serial EEPROM.
FLCS# OUT Flash Chip Select. The Flash Chip Sele ct pin provides an active low
Flash chip select signal. This pin should be left floating if Flash is not
used.
FLOE# OUT Flash Output Enable. This pin provides an active low output enable
control (read) to the Flash memory. This pin should be left floating if
Flash is not used.
FLWE# OUT Flash Write Enable. This pin provides an active low write enable
control to the Flash memory. This pin should be left floating if Flash is
not used.
Table 7. Test Port Signals
Symbol Type Name and Function
TEST IN Test Port. If this input pin is high, the 82551IT will enable the test port.
During nominal operation this pin should be connected to a 1K pull-
down resistor.
TCK IN Test Port Clock. This pin is used for the Test Port Clock signal.
TI IN Test Port Data Input. This pin is used for the Test Port Data Input
signal.
TEXEC IN Test Port Execute Enable. This pin is used for the Test Port Execute
Enable signal.
TO OUT Test Port Data Output. This pin is used for the Test Port Data Output
signal.
Table 6. Local Memory Interface Signals
Symbol Type Name and Function
82551IT — Networking Silicon
12 Datasheet
4.5 PHY Signals
Table 8. PHY Signals
Symbol Type Name and Func tion
X1 AI Crystal Input One. X1 and X2 can be driven by an external 25 MHz
crystal. Otherwise, X1 may be driven by an external 3.3 V metal-oxide
semiconductor (MOS) level 25 MHz oscillator when X2 is left floating.
X2 AO Crystal Input Two. X1 and X2 can be driven by an external 25 MHz
crystal. Otherwise, X1 may be driven by an external 3.3 V MOS level
25 MHz oscillator when X2 is left floating.
TDP
TDN AO
Analog Twisted Pair Ethernet Transmit Differential Pair. These
pins transmit the serial bit stream for transmission on the Unshielded
Twisted Pair (UTP) cable. The current-driven differential driver can be
two-level (10BASE-T) or three-level (100BASE-TX) signals depending
on the mode of operation. These signals interface directly with an
isolation transformer.
RDP
RDN AI
Analog Twisted Pair Ethernet Receive Differential Pair. These pins
receive the serial bit stream from the isolation transformer. The bit
stream can be two-level (10BASE-T) or three-level (100BASE-TX)
signals depending on the mode of operation.
ACTLED# OUT Activity LED. The Activity LED pin indicates either transmit or receive
activity. When activity is present, the activity LED is on (ACTLED#
active low); when no activity is present, the activity LED is off.
LILED# OUT Link Integrity LED. The Link Integrity LED pin indicates link integrity.
If the link is valid in either 10 or 100 Mbps, the LED is on (LILED#
active low); if link is invalid, the LED is off.
SPDLED# OUT Speed LED. The S peed LED pin indicates the speed. The speed LED
will be on at 100 Mbps (SPDLED# active low) and off at 10 Mbps.
RBIAS100 B Reference Bias Resistor (100 Mbps). This pin should be connected
to a pull-down resistor.a
a. Based on some board d esigns, RBIAS100 and RBIAS10 values may need to be increased/ decreased to com-
pensate for high/l ow MDI transmit amplitude. See the 82562EZ(EX)/825 51ER(IT) & 82541ER Combined Foot-
print LOM Design Guide for more information.
RBIAS10 B Reference Bias Resistor (10 Mbps). This pin should be connected
to a pull-down resistor.a
VREF B
Voltage Reference. This pin is connected to a 1.25 V ± 1% external
voltage reference generator. To use the internal voltage reference
source, this pin should be left floating. Under normal circumstances,
the internal voltage reference should be used and this pin would be left
open.
Networking Silicon — 82551IT
Datasheet 13
4.6 Power and Ground Signals
Table 9. Power and Ground Signals
Symbol Type Name and Function
VCC DPS
Digital 3.3 V Power. The VCC pins should be connected to the main
digital power supply. This is 3.3 VAUX in systems with an auxiliary
power supply and PCI power in systems without an auxiliary power
supply. The power source is configured through the FLA[1]/AUXPWR
pin.
VCCR APS Analog Power. These pins should be connected directly to VCC.
VSSPL,
VSSPP,
VSSPT, VSS DPS Digital Ground. These pins should be connected to the main digital
ground plane.
NC DPS No Connect. These pins should not be connected to any circuit. Pull-
up or pull-down resistors should not be used.
82551IT — Networking Silicon
14 Datasheet
Note: This page is intentionally left blank.
Networking Silicon — 82551IT
Datasheet 15
5.0 Media Access Control Functional Description
5.1 Device Initialization
The 82551IT has six sources for initialization. They are listed according to their precedence:
1. Internal Power-on Reset (POR)
2. ALTRST# pin
3. RST# pin
4. ISOLATE# pin
5. Software Reset (Software Command)
6. Selective Reset (Software Command)
5.1.1 Initialization Effects
The following table lists the effect of each of the different initialization sources on major portions
of the 82551IT. The initialization sources are listed in order of precedence. For example, any
resource that is initialized by the software reset is also initialized by the D3 to D0 transition and
ALTRST# and PCI RST# but not necessarily by the selective reset.
Table 10. Initialization Effects
Internal
POR ALTRST# RST# ISOLATE# D3 to D0
Transition Software
Reset Selective
Reset
EEPROM read
and initialization ????
-- -- --
Loadable
microcode
decoded/reset ??????
--
MAC
configuration
reset and
multicast hash
??????
--
Memory
pointers and
mircomachine
state reset
???????
PCI
Configuration
register reset ?????
-- --
PHY
configuration
reset ???
-- -- -- --
82551IT — Networking Silicon
16 Datasheet
5.2 PCI Interface
5.2.1 Bus Operations
After configuration, the 82551IT is ready for its normal operation. As a Fast Ethernet Controller,
the role of the 82551IT is to access transmitted data or deposit received data. In both cases the
82551IT, as a bus master device, will initiate memory cycles by wa y of the PCI bus.
To perform these actions, the 82551IT is controlled and exam in ed by the CPU through its control
and status structures and registers. Some of these structures reside in the 82551IT and some reside
in system memory. For access to the 82551IT’s Control/Status Registers (CSR), the 82551IT acts
as a slave device. The 82551IT serves as a slave also while the CPU accesses its 128 KB Flash
buffer or its EEPROM.
Section 5.2.1.1 describes the 82551IT slave operation. It is followed by a description of the
82551IT operation as a bus master (initiator) in Section 5.2.1.2.
5.2.1.1 Bus Slave Operation
The 82551IT serves as a target device in the following cases:
•CPU accesses to the 82551IT System Control Block (SCB) Control/Status Registers (CSR)
•CPU accesses to the EEPROM through its CSR
•CPU accesses to the 82551IT PORT address through the CSR
•CPU accesses to the MDI control register in the CSR
•CPU accesses to the Flash control register in the CSR
•CPU accesses to the 128 KB Flash
The CSR and the 1 MB Flash buffer are considered by the 82551IT as totally separated memory
spaces. The 82551IT provides separate Base Address Registers (BARs) in the configuration space
to distinguish between them. The size of the CSR memory space is 4 KB in the memory space and
64 bytes in the I/O space. The 82551IT treats accesses to these memory spaces differently.
Power
management
event reset ??
Clear only
if no
auxiliary
power
present
Clear only
if no
auxiliary
power
present
-- -- --
Statistic
counters reset ??????
--
Sampling of
configuration
input pins ???
-- -- -- --
Table 10. Initialization Effects
Internal
POR ALTRST# RST# ISOLATE# D3 to D0
Transition Software
Reset Selective
Reset
Networking Silicon — 82551IT
Datasheet 17
5.2.1.1.1 Control/Status Register (CSR) Accesses
The 82551IT supports zero wait state single cycle memory or I/O mapped accesses to its CSR
space. Separate BARs request 4 KB of memory space and 64 bytes of I/O space to accomplish
these accesses. The 82551IT provides 4 valid KB of CSR space, which include the following
elements:
•System Control Block (SCB) regist ers
•PORT register
•Flash control register
•EEPROM control register
•MDI control register
•Flow control registers
The following figures show CSR zero wait state I/O read and write cycles. In the case of accessing
the Control/Status Registers, the CPU is the initiator and the 825 51IT is the target of the
transaction.
Read Accesses: The CPU, as the initiator, drives addr ess lines AD[31:0], the comma nd and byte
enable lines C/BE#[3:0] and the control lines IRDY # and FRAME#. As a slave, the 8 2551IT
controls the TRDY# signal and provides valid data on each data access. The 82551IT allows the
CPU to issue only one read cycle when it accesses the Control/Status Registers, generating a
disconnect by asserting the STOP# signal. The CPU can insert wait states by de-asserting IRDY#
when it is not ready.
Figure 2. CSR I/O Read Cycle
CLK
FRAME#
C/BE#
IRDY#
TRDY#
DEVSEL#
AD
3421 56789
ADDR DATA
I/O RD BE#
STOP#
82551IT SYSTEM
82551IT — Networking Silicon
18 Datasheet
Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and
byte enable lines C/BE#[3:0] and the contro l lines IRD Y# and FRAME#. It also provides the
82551IT with valid data on each data access immediately after asserting IRDY#. The 82551IT
controls the TRDY# signal and asserts it from the data access. The 82551IT allows the CPU to
issue only one I/O write cycle to the Control/S tatus Registers, generating a disconnect by asserting
the STOP# signal. This is true for both memory mapped and I/O mapped accesses.
Figure 3. CSR I/O Write Cycle
CLK
FRAME#
C/BE#
IRDY#
TRDY#
DEVSEL#
AD
3421 56789
ADDR DATA
I/O WR BE#
STOP#
82551IT SYSTEM
Networking Silicon — 82551IT
Datasheet 19
5.2.1.1.2 Flash Buffer Accesses
The CPU accesses to the Flash buffer are very slow and the 82551IT issues a target-disconnect at
the first data access. The 82551IT asserts the STOP# signal to indicate a target-disconnect. The
figures below illustrate memory CPU read and write accesses to the 128 KB Flash buffer. The
longest burst cycle to the Flash buffer contains one data access only.
Read Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and
byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82551IT controls the
TRDY# signal and de-asserts it for a certain number of clocks until valid data can be read from the
Flash buffer. When TRDY# is asserted, the 82551IT drives valid data on the AD[31:0] lines. The
CPU can also insert wait states by de-asserting IRDY# until it is ready. Flash buffer read accesses
can be byte or word length.
Figure 4. Flash Buffe r Re ad Cyc le
CLK
FRAME#
C/BE#
IRDY#
TRDY#
DEVSEL#
AD ADDR DATA
MEM RD BE#
STOP#
82551IT SYSTEM
82551IT — Networking Silicon
20 Datasheet
Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and
byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. It also provides the 82551IT
with valid data immediately after asserting IRDY#. The 82551IT controls the TRDY# signal and de-
asserts it for a certain number of clocks until valid data is written to the Flash buffer. By asserting
TRDY#, the 82551IT signals the CPU that the current data access has completed. Flash buffer write
accesses can be byte length only.
Figure 5. Flash Buffer Write Cycle
CLK
FRAME#
C/BE#
IRDY#
TRDY#
DEVSEL#
AD ADDR
MEM WR BE#
STOP#
DATA
82551IT SYSTEM
Networking Silicon — 82551IT
Datasheet 21
5.2.1.1.3 Retry Premature Accesses
The 82551IT responds with a Retry to any configuration cycle accessing the 82551IT before the
completion of the automatic read of the EEPRO M. The 82551IT may continue to Retry any
configuration accesses until the EEPROM read is complete. The 82551IT does not enforce the rule
that the retry master must attempt to access the same address again to complete any delayed
transaction. Any master access to the 82551IT after the completion of the EEPROM read will be
honored. Figure 6 below show s ho w a Retry lo oks when it occurs.
Note: The 82551IT is considered the target in the above diagram; thus, TRDY# is not asserted.
5.2.1.1.4 Error Handling
Data Parity Errors: The 82551IT checks for data parity errors while it is the target of the
transaction. If an error was detected, the 82551IT always sets the Detected Parity Error bit in the
PCI Configuration Status register, bit 15. The 82551IT also asserts PERR#, if the Parity Error
Response bit is set (PCI Configuration Command register, bit 6). The 82551IT does not attempt to
terminate a cycle in which a parity error was detected. This gives the initiator the option of
recovery.
Target-Disconnect: The 82551IT prematurel y term inates a cycle in the following cases:
•After accesses to the Flash buffer
•After accesses to its CSR
•After accesses to the configuration space
System Error: The 82551IT reports parity error during the address phase using the SERR# pin. If
the SERR# Enable bit in the PCI Configuration Command register or the Parity Error Response bit
is not set, the 82551IT only sets the Detected Parity Error bit (PCI Configuration Status register , bit
15). If SERR# Enable and Parity Error Response bits are both set, the 82551IT sets the Signaled
System Error bit (PCI Configuration Status register, bit 14) as well as the Detected Parity Error bit
and asserts SERR# for one clock.
Figure 6. PCI Retry Cycle
CLK
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
82551IT SYSTEM
82551IT — Networking Silicon
22 Datasheet
Note: The 82551IT detects a system error for any parity error duri ng an address phase, whether or not it is
involved in the current transaction.
5.2.1.2 Bus Master Operation
As a PCI Bus Master , the 82551IT initiates memory cycles to fetch data for transmission or deposit
received data and to access the memory resident control structures. The 82551IT performs zero
wait state burst read and write cycles to the host main memory. Figure 7 and Figure 8 show
memory read and write burst cycles. For bus master cycles, the 82551IT is the initiator and the host
main memory (or the PCI host bridge, depending on the configuration of the system) is the target.
The CPU provides the 82551IT with action com man ds and poi nters to the data buffers that reside
in host main memory. The 82551IT indepen dent ly man a ges these structures and initiat es burst
memory cycles to transfer data to and from them. The 82551IT uses the Memory Read Multiple
(MR Multiple) command for burst accesses to data buffers and the Memory Read Line (MR Line)
Figure 7. Memory Read Burst Cycle
CLK
FRAME#
C/BE#
IRDY#
TRDY#
DEVSEL#
AD
3421 5678910
ADDR DATA
MR BE# BE#
DATA DATA DATA DATA
SYSTEM 82551IT
Figure 8. Memory Write Burst Cycle
CLK
FRAME#
C/BE#
IRDY#
TRDY#
DEVSEL#
AD
3421 5678910
ADDR DATA
MW BE# BE#
DATA DATA DATA DATA
82551ITSYSTEM
Networking Silicon — 82551IT
Datasheet 23
command for burst accesses to control structures. For all write accesses to the control structure, the
82551IT uses the Memory Write (MW) command. For write accesses to data structure, the
82551IT may use either the Memory Write or Memory Write and Invalidate (MWI) commands.
Read Accesses: The 82551IT performs block transfers from host system memory to perform frame
transmission on the serial link. In this case, the 82551IT initiates zero wait state memory read burst
cycles for these accesses. The length of a burst is bounded by the system and the 82551IT’s internal
FIFO. The length of a read burst may also be bounded by the value of the Transmit DMA
Maximum Byte Count in the Configure comm and. The Transmit DMA Maximum Byte Count
value indicates the maximum number of transmit DMA PCI cycles that will be completed after an
82551IT internal arbitrat ion.
The 82551IT, as the initiator, drives the address lines AD[31:0], the command and byte enable
lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82551IT asserts IRDY# to
support zero wait state burst cycles. The target signals the 82551IT that valid data is ready to be
read by asserting the TRDY# signal.
Write Acces ses: The 82551IT performs block transfers to host system memory during frame
reception. In this case, the 82551IT initiates memory write burst cycles to deposit the data, usually
without wait states. The length of a burst is bounded by the system and the 82551IT’ s internal FIFO
threshold. The length of a write burst may also be bounded by the value of the Receive DMA
Maximum Byte Count in the Configure command. The Receive DMA Maximum Byte Count value
indicates the maximum number of receive DMA PCI transfers that will be completed before the
82551IT internal arbitrat ion.
The 82551IT, as the initiator, drives the address lines AD[31:0], the command and byte enable
lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82551IT asserts IRDY# to
support zero wait state burst cycles. The 82551IT also drives valid data on AD[31:0] lines during
each data phase (from the first clock and on). The target controls the length and signals completion
of a data phase by de-assertion and assertion of TRDY#.
5.2.1.2.1 Memory Write and Invalidate
The 82551IT has four Direct Memory Access (DMA) channels. Of these four channels, the
Receive DMA is used to deposit the large number of data bytes received from the link into system
memory. The Receive DMA uses both the Memory Write (MW) and the Memory Write and
Invalidate (MWI) commands. To use MWI, the 82551IT must guarantee the following:
1. Minimum transfer of one cache line
2. Active byte enable bits (or BE[3:0]# are all low) during MWI access
3. The 82551IT may cross th e cache line boundary only if it intends to transfer the next cache
line too.
To ensure the above conditions, the 82551IT may use the MWI command only if the following
conditions are true:
1. The Cache Line Size (CLS) written in the CLS register during PCI configuration is 8 or 16
Dwords.
2. The accessed address is cache line aligned.
3. The 82551IT has at least 8 or 16 Dwords of data in its receive FIFO.
4. There are at least 8 or 16 Dwords of data space left in the system memory buffer.
5. The MWI Enable bit in the PCI Configurat ion Command register, bit 4, must be set to 1b.
82551IT — Networking Silicon
24 Datasheet
6. The MWI Enable bit in the 82551IT Configure comman d mu st be set to 1b.
If any one of the above conditions is not true, the 82551IT uses the MW command. If an MWI
cycle has started and one of the conditions is no longer valid (for example, the data space in the
memory buffer is now less than CLS), then the 82551IT terminates the MWI cycle at the end of the
cache line. The next cycle is either an MW or MWI cycle depending on the conditions listed above.
If the 82551IT started a MW cycle and reached a cache line boundary, it either continues or
terminates the cycle depending on the Terminate Write on Cache Line configuration bit of the
82551IT Configure command (byte 3, bit 3). If this bit is set, the 82551IT terminates the MW cycle
and attempts to start a new cycle. The new cycle is an MWI cycle if this bit is set and all of the
above conditions are met. If the bit is not set, the 82551IT continues the MW cycle across the cache
line boundary if required.
5.2.1.2.2 Read Align
The Read Align feature enhances the 82551IT’s performance in cache line oriented systems. In
these particular systems, starting a PCI transaction on a non-cache line aligned address may cause
low performance.
To resolve this performance anomaly, the 82551IT attempts to terminate transmit DMA cycles on a
cache line boundary and start the next transaction on a cache line aligned address. This feature is
enabled when the Read Align Enable bit is set in the 82551IT Configure command (byte 3, bit 2).
If this bit is set, the 82551IT operates as follows:
•When the 82551IT is almost out of resources on the transmit DMA (that is, the transmit FIFO
is almost full), it attempts to terminate the read transaction on the nearest cache line boundary.
•When the arbitration counter’s feature is enabled (in other words, the Transmit DMA
Maximum Byte Count value is set in the Configure command), the 82551IT switches to other
pending DMAs on cache line boundary only.
This feature is not recommended for use in non-cache line oriented systems since it may cause
shorter bur s ts and lower perfor mance. If this feature is used, it is recommended that the CLS
register in PCI Configuration space is set to 8 or 16.
5.2.1.2.3 Error Handling
Data Parity Errors: As an initiator, the 82551IT checks and detects data parity errors that occur
during a transaction. If the Parity Error Response bit is set (PCI Configuration Comma nd register,
bit 6), the 82551IT also asserts PERR# and sets the Data Parity Detected bi t (PCI Configuration
Status register, bit 8). In addition, if the error was detected by the 82551IT during read cycles, it
sets the Detected Parity Error bit (PCI Configuration Status register, bit 15).
5.2.2 Clock Run Signal
This signal is active in PCI bus operating modes. The Clock Run signal is an open drain I/O signal.
It is used as a bi-directional channel between the host an d the devi ces.
•The host de-asserts the CLK_RUN# signal to indicate that the clock is about to be stopped or
slowed down to a non-operational frequency.
•The host asserts the CLK_RUN# signal when the clock is either running at a normal operating
frequency or about to be started.
Networking Silicon — 82551IT
Datasheet 25
•The 82551IT asserts the CLK_RUN# signal to indicate that the PCI clock must prevent the
host from stopping or to request that the ho st restore the clock if it was previously stopped.
Proper operation requires that the system latency from the nominal PCI CLK to CLK_RUN#
assertion should be less than 0.5 µs. If the system latency is longer than 0.5 µs, there is an increase
in receive overruns. In these types of systems, the Clock Run functionality should be disabled. In
this case, the 82551IT will claim th e PCI cloc k even during idle time. If the CLK_RUN# signal is
not used, it must be connected to a pull-down resistor.
5.2.3 Power Management Event
The 82551IT supports power management indicatio ns in the PCI mode. The PME# output pin
provides an indication of a power management event in PCI systems.
5.3 PCI Power Management
The 82551IT supports int e resting packet wake-up and the capability to wake the system on a link
status change from a low power st ate. The 82551IT enables the host system to be in a sleep state
and remain virtually connected to the network. After a power management event or link status
change is detected, the 82551IT will wa ke the host system . The sections below descri be these
events, the 82551IT power states, and estimated power consumption at each power state.
5.3.1 Power States
The 82551IT has one set of PCI power management registers and implements all four power states
as defined in the Power Management Network Device Class Reference Specification, Revision 1.0.
The four device power states, D0 through D3, vary from maximum power consumption at D0 to
the minimum power consumption at D3.
PCI transactions are only allowed in the D0 state, except for host accesses to the 82551IT’s PCI
configuration registers. The D1 and D2 power management states enable intermediate power
savings while providing the system wake-up capabilities. In the D3 cold state, the 82551IT can
provide wake-up capabilities onl y if auxi liary power is supplied. Wake-up indications from the
82551IT are provided by the Power Management Event (PME#) signal in PCI implementatio ns.
5.3.1.1 D0 Power State
As defined in the Network Device Class Reference Specification, the device is fully functional in
the D0 power state. In this state, the 82551IT receives full power and should be providing full
functionality. In the 82551IT the D0 state is partitioned into two substates, D0 Uninitialized (D0u)
and D0 Active (D0a).
D0u is the 82551IT’s initial power state following a Power-on Reset (POR) event and before the
Base Address Registers (BARs) are accessed. Initialization of the CSR, Memory, or I/O Base
Address Registers in the PCI Configuration space switches the 82551IT from the D0u state to the
D0a state.
In the D0a state, the 82551IT pro vides its full functionality and cons umes nom inal power. In
addition, the 82551 IT supports wake on link status change (Section 5.3.2, “Wake-up Events”).
While it is active, the 82551IT requires a nominal PCI clock signal (in other words, a clock
frequency greater than 16 MHz) for proper operation. During idle time, the 82551IT supports a PCI
82551IT — Networking Silicon
26 Datasheet
clock signal suspension usin g the Clockrun signal mechanism . The 82551IT supports a dynamic
standby mode. In this mode, the 82551IT is able to save almost as much power as it does in the
static power-down states. The transition to or from standby is done dynami cally by the 82551IT
and is transparent to the software.
5.3.1.2 D1 Power State
For a device to meet the D1 power state requirements, as specified in th e Advanced Configuration
and Power Interf ace ( A CP I) Specif i cation, Revision 1.0, it must not allow bus transmission or
interrupts; however, bus reception is allowed. Therefore, device context may be lost and the
82551IT does not initiate any PCI activity. In this state, the 82551IT responds only to PCI accesses
to its configuration space and system wake-up events.
The 82551IT retains link integrity and moni tors the link for any wake-up events such as wake-up
packets or link status change. Fo llowing a wake-up event, the 8255 1IT asserts the PME# signal to
alert the PCI system.
5.3.1.3 D2 Power State
The ACPI D2 power state is similar in functionality to the D1 power state. If the bus is in the B2
bus power state, the 82551IT will consume less current th an it does in th e D1 state. In addit ion to
D1 functionality, the 82551IT can provide a lower power mode with wake-on-link status change
capability. The 82551 IT may enter this mode if the link is down while the 82551IT is in the D2
state. In this state, the 82551IT monitors the link for a transition from an invalid link to a valid link.
The 82551IT will not attempt to keep the lin k alive by transmitting idle symbols or link integrity
pulses.1 The sub-10 mA state due to an invalid link can be enabled or disabled by a configuration
bit in the Power Management Driver Register (PMDR).
5.3.1.4 D3 Power State
In the D3 power state, the 82551IT has the same capabilities and consumes the same amount of
power as it does in the D2 state. However, it enables the PCI system to be in the Bus Power 3 (B3)
state. If the PCI system is in the B3 state (in other words, no PCI power is present), the 82551IT
provides wake-up capabilities if it is connect ed to an auxiliary power source in the system. If
PME# is disabled, the 82551IT does not provide wa ke-up capability or maintain link integrity. In
this mode, the 82551 IT consumes minimal power.
The 82551IT enables a system to be in a sub-5 watt state (low power state) and still be virtually
connected. More specifically, the 82551IT supports full wake-up capabil ities while it is in the D3
cold state. The 82551IT can be connected to an auxiliary power source (VAUX), which enables it to
provide wake-up functionality wh ile the PCI power is off. The typical current consumption of the
82551IT is 125 mA at 3.3 V and a dual power plane is not required. If connected to an auxiliary
power source, the 82551IT receives all of its power from the auxiliary source in all power states.
When connected to an auxiliary power supply, the 82551IT must have a status indicator of whether
the power supply is valid (in other words, auxiliary power is stable). The indication is received at
the AUXPWR pin, as descri bed next.
1. For a topolo gy of two 82551I T devices connected by a crossed twisted-pair Ether net cable, the deep power-do wn mode should be disabled.
If it is enabled, the two devices may not detect each other if the operating system places them into a low power state before both nodes
become active.
Networking Silicon — 82551IT
Datasheet 27
5.3.1.4.1 Auxiliary Power Signal
The 82551IT senses whether it is connected to the PCI power supply or to an auxiliary power
supply (VAUX) through the FLA1/AUXPWR pin. The auxiliary power detection pin (multiplexed
with FLA1) is sampled when the 82551IT power-on reset is active. An external pull-up resistor
should be connected to the 82551IT if it is fed by VAUX; otherwise, the FLA1/AUXPWR pin
should be left floating. The presence of AU XPWR affects the value reported in the Power
Management Capability Register (PCI Configuration Space, offset DEh). The Power Management
Capability Register is described in more detail in Section 7.1.19, “Power Management Capabilities
Register”.
5.3.1.4.2 Alternate Reset Signal
The 82551IT’s ALTRST# input pin functions as a power-on reset input. Following ALTRST#
being driven low, th e 82551IT is initialized to a known state. While this function is required, this
pin is not needed for it. Since this functio nalit y is pro vided by the 82551IT’s internal power-on
reset signal, this pin should be pulled high to the main digital power supply.
Note: A separate internal power-on reset signal is generated when power is applied to the device. This
signal is active while it provides the 82551IT power-on reset function and is also used for sampling
configuration inputs.
5.3.1.4.3 Isolate Signal
When the 82551IT is connected to VAUX, it can be powered on while the PCI bus is powered off. In
this case, the 82551IT isolates itself from the PCI bus. The 82551IT has a dedicated ISOLATE# pin
that must be connected to the PCI Reset signal. Whenever the PCI Bus is in the B3 state, the PCI
Reset signal becomes active and the 82551IT isolates it self from the PCI bus. During this state, the
82551IT ignores all PCI signals including the RST# and CLK input signals. It also tristates all PCI
outputs, except the PME# signal. In the transition to an active PCI power state (in other words,
from B3 bus power state to B0 bus power state), the PCI Reset signal shifts high. This generates an
internal hardware reset, which initializes the device (described in Section 5.1.1, “Initialization
Effects”).
Some designs in existence may implement the previous recommendation s for the RST#,
ISOLATE# and ALTRST# input pins. In these cases, the PCI Reset signal is connected to the RST#
pin, the PCI power source’s stable power (power good) to the ISOLATE# pin, and the auxiliary
power source’s stable power (auxiliary power good) to the ALTRST# pin. It is not necessary for
existing working designs to make changes for these signals; however, it is recommended that the
changes contained in this document should be included when possible. New designs should
implement the recommendat ions contained in this document.
5.3.1.4.4 PCI Reset Signal
The PCI RST# signal can be activated in one of the following cases:
•Power-up
•Warm bo ot
•Wak e-up (B3 to B0 transition)
•Set to power-down (B0 to B3 transition)
82551IT — Networking Silicon
28 Datasheet
If PME# is enabled (in the PCI power management registers), the RST# signal does not affect any
PME# related circu its (in other words, the PCI power manag ement registers, and the wake-up
packet would not be affected).
Note: The PCI Specification, Revision 2.2, states that the PCI RST# signal should be active low in the B3
state. (In PCI Specification, Revision 2.1, the PCI RST# signal is undefined during the B3 state.)
The transition from the B3 bus power state to the B0 bus power state occurs on the trailing edge of
the PCI RST# signal.
The initialization signal is generated internally in the following cases:
•Active RST# signal while the 82551IT is the D0, D1, or D2 power state
•RST# trailing edge while the 82551IT is in th e D3 power stat e
•ISOLATE# trailing edge
The internal initialization signal resets the PCI Configuration Space, MAC configuration, and
memory structure.
The behavior of the RST# and ISOLATE# pins and the internal 82551IT initialization signal are
shown in the following figure.
Figure 9. Initialization upon RST# and ISOLATE#
RST#
Internal hardware
reset
RST#
Internal hardware
reset
ISOLATE#
Internal hardware
reset
D0 - D2 power state
D3 power state
Internal reset
due to ISOLATE#
640 ns
640 ns
Networking Silicon — 82551IT
Datasheet 29
The following tables list the functionality at the different power states for the 82551IT.
5.3.2 Wake-up Events
There are two types of wake-up events: “Interesting” Packets and Link Status Change. These two
events are detailed below.
Note: The wake-up event is suppo rted only if the PME Enable bit in the Power Management Control/
Status (PMCSR) register is set.
5.3.2.1 “Interesting” Packet Event
In the power -down state, the 82551IT is capable of recognizing “interesting” packets. The 82551IT
supports pre-defined and programmable packets th at can be defined as any of the following:
•Address Resolution Protocol (ARP) Packets (with Multiple IP addresses)
•Direct Packets (with or without type qualification)
•Neighbor Discovery Multicast Address Packet (“ARP” in IPv6 environment)
•NetBIOS over TCP/IP (NBT) Query Packet (under IPv4)
•Internetwork Package Exchange* (IPX*) Diagnostic Packet
This allows the 82551IT to handle various packet types. In general, the 82551IT supports
programmable filtering of any packet in the first 128 by tes.
Table 11. Functionality at the Different Power States
Power State Link Functionality
D0u Don’t care • Power-up state
• PCI slave access
D0a Valid Full functionality at full power and wake on an
invalid link
Invalid Full functionality at full power and wake on a valid
link
D1 Valid • Wake-up on “interesting” packets and link
invalid
• PCI configuration access
Invalid • Wake on link valid
• PCI configuration access
D2 Valid Same functionality as D1 (link valid)
Invalid Detection for valid link and no link integrity
D3 (with power) Valid Same functionality as D1 (link valid)
Invalid Detection for valid link and no link integrity
Dx (x>0 without
PME#) Don’t care No wake-up functionality.
82551IT — Networking Silicon
30 Datasheet
5.3.2.2 Link Status Change Event
The 82551IT link status indication circuit is capable of issuing a PME on a link status change from
a valid link to an invalid link condition or vice versa. The 82551IT reports a PME link status event
in all power states. The PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA
Configure command.
5.4 Parallel Flash
The 82551IT’s parallel interface is used for a Flash interface. The 82551IT supports a glueless
interface to an 8-bit wide, 128 KB, parallel memory device.
The Flash (or boot PROM) is read from or written to whenever the host CPU performs a read or a
write operation to a memory location that is within the Flash mapping window. All accesses to the
Flash, except read accesses, require the appropriate command sequence for the device used. (Refer
to the specific Flash data sheet for more details on reading from or writing to the Flash device.) The
accesses to the Flash are based on a direct decode of CPU accesses to a memory window defined in
either the 82551IT Flash Base Address Register (PCI Configuration space at offset 18h) or the
Expansion ROM Base Address Register (PCI Configuration space at offset 30h). The 82551IT
asserts control to the Flash when it decodes a valid access.
The 82551IT supports an external Flash memory (or boot PROM) of up to 128 KB. The Expansion
ROM address can be separately disabled by setting the corresponding bit in the EEPROM, word
Ah.
Note: Flash accesses must always be assembled or disassembled by the 82551IT whenever the access is
greater than a byte-wide access. Due to slow access times to a typical Flash and to avoid violating
PCI bus holding specifications (no more th an 16 wait states inserted for any cycles that are not
system initiation cycles), the maximum data size is either one word or one byte for a read operation
and one byte only for a write operation.
5.5 Serial EEPROM Interface
The serial EEPROM stores configuration data for the 82551IT and is a serial in/serial out device.
The 82551IT supports either a 64-register or 256-register size EEPROM and automatically detects
the EEPROM’s size. The EEPROM should also operate at a frequency of at least 1 MHz.
Networking Silicon — 82551IT
Datasheet 31
All accesses, either read or write, are preceded by a command instruction to the device. The
address field is six bits for a 64-register EEPR OM or eight bits for a 256-register EEPROM. The
end of the address field is indicated by a dummy zero bit from the EEPROM, which indicates the
entire address field has been transferred to the device. An EEPROM read instruction waveform is
shown in the figure below.
The 82551IT performs an automatic read of four words (0h, 1h, 2h, and Ah) of the EEPROM after
the de-assertion of Reset. Refer to the 82551QM/ER/IT EEPROM Map and Programming
Information for more details.
Figure 10. 64-Word EEPROM Read Instruction Waveform
A
1
A
0
EECS
EESK
EEDI
EEDO
A
5
A
4
A
2
D
15
D
0
READ OP code
A
3
A
1
A
0
82551IT — Networking Silicon
32 Datasheet
5.5.1 EEPROM Address Map
Table 12 lists the EEPROM address map for the 82551IT Fast Ethernet Controller.
Note: Refer to the 82551QM/ER/IT EEPROM Map and Programming Information for more details.
5.6 10/100 Mbps CSMA/CD Unit
The 82551IT CSMA/CD unit implements both the IEEE 802.3 Ethernet 10 Mbps and IEEE 802.3u
Fast Ethernet 100 Mbps standards. It perfo rm s all the CSMA/CD protocol functions such as
transmission, reception, collision handling, etc. The 82551IT CSMA/CD unit communicates with
the internal PHY unit through a standard Media Independent Interface (MII), as specified by IEEE
802.3, Chapter 22. This is a 10/100 Mbps mode in which the data stream is nibble-wide and the
serial clocks run at either 25 or 2.5 MHz.
Table 12. 82551IT EEPROM Address Map
Word High Byte (Bits 15:8) Low Byte (Bits 7:0)
00h Ethernet Individual Address Byte 2 Ethernet Individual Address Byte 1
01h Ethernet Individual Address Byte 4 Ethernet Individual Address Byte 3
02h Ethernet Individual Address Byte 6 Ethernet Individual Address Byte 5
03h Compatibility Byte 1 Compatibility Byte 0
04h Reserved
05h Controller Type Connectors
06h Primary PHY Record, high byte Primary PHY Record, low byte
07h Secondary PHY Record, high byte Secondary PHY Record, low byte
08h PWA Byte 1 PWA Byte 2
09h PWA Byte 3 PWA Byte 4
0Ah EEPROM_ID, high byte EEPROM_ID, low byte
0Bh Subsystem_ID, high byte Subsystem_ID, low byte
0Ch Subsystem_Vendor, high byte Subsystem_Vendor, low byte
0Dh:0Fh Reserved
10h:22h Reserved
23h Device ID, high byte Device ID, low byte
24h:2Fh Reserved
30h:33h Reserved
34h:3Eh Reserved
3Fh 64-word EEPROM Checksum, high byte 64-word EEPROM Checksum, low byte
40h:FEh Reserved
FFh 256-word EEPROM Checksum, high byte 256-word EEPROM Checksum, low byte
Networking Silicon — 82551IT
Datasheet 33
5.6.1 Full Duplex
When operating in full duplex mode the 82551IT can transmit and receive frames simultaneously.
Transmission starts regardless of the state of the internal receive path. Reception starts when the
internal PHY detects a valid frame on the receive differential pair of the PHY.
The 82551IT operates in either half duplex mode or full duplex mode. For proper operat ion, both
the 82551IT CSMA/CD module and the PHY unit m ust be set to the same dup lex mode. The
CSMA duplex mode is set by the 82551IT Configure command or forced by the settings in the
PHY unit’s registers.
The PHY duplex mode is set either by Auto-Negoti a tion or, if Auto-Negotiation is disabled, by
setting the full duplex bit in the Management Data Interface (MDI) Register 0, bit 8. By default, the
internal PHY unit advertises full duplex ability in the Auto-Negotiation process regardless of the
duplex setting of the CSMA unit. The CSMA configu rati on shou ld match the result of the Auto-
Negotiation.
The selection of duplex operation (full or half) and flow control is done in two levels: MAC and
PHY. The MAC duplex selection is done only through the CSMA configuration mechanism (in
other words, the Configure command in software).
5.6.2 Flow Control
The 82551IT supports IEEE 802.3x frame-based flow control frames in both full duplex and half
duplex switched environment s. Th e 82551 IT flow control feature is not intended to be used in
shared media environments.
The PHY unit’ s duplex and flow control enable can be selected using the NWay* Auto-Negotiation
algorithm or through the Management Data Interface.
5.6.3 Address Filtering Modifications
The 82551IT can be configured to ignore one bit when checking for its Individual Address (IA) on
incoming receive frames. The address bit, known as the Upper/Lower (U/L) bit, is the second least
significant bit of the first byte of the IA. This bit may be used, in some cases, as a pri ori ty
indication bit. When configured to do so, the 8 2551IT passes any frame that matches all other 47
address bits of its IA, regardless of the U/L bit value.
This configuration only affects the 82551IT specific IA and not multicast, multi-IA or broadcast
address filtering. The 82551IT does not attribute any priority to frames with this bit set, it simply
passes them to memory regardless of this bit.
5.6.4 VLAN Support
The 82551IT controller supports th e VLA N standard as currently defined by the IEEE 802.1
committee. All VLAN receive flows will be implemented by software. The 82551IT su pports the
reception of long frames, specifically frames longer than 1518 bytes, including CRC, if software
sets the Long Receive OK bit in the Configuration command. Otherwise, “long” frames are
discarded.
82551IT — Networking Silicon
34 Datasheet
5.7 Media Independent Interface (MII) Management Interface
The MII management interface allows the CPU to control the PHY unit through a control register
in the 82551IT. This allows the software driver to place the PHY in specific modes such as full
duplex, loopback, power down, etc., without the need for specific hardware pins to select the
desired mode. This structure allows the 82551IT to qu ery the PHY unit for status of the link. This
register is the MDI Control Register and resides at offset 10h in the 82551IT CSR. (The MDI
registers are described in detail in Section 9.0, “PHY Unit Registers”.) The CPU writes commands
to this register and the 82551IT reads or writes the control/status parameters to the PHY unit
through the MDI register. Although the 82551IT follows the MII format, the MI bus is not
accessible on external pins.
Networking Silicon — 82551IT
Datasheet 35
6.0 Physical Layer Functional Description
6.1 100BASE-TX PHY Unit
6.1.1 100BASE-TX Transmit Clock Generation
A 25 MHz crystal or a 25 MHz oscillator is used to drive the PHY unit’ s X1 and X2 pins. The PHY
unit derives its internal transmit digital clocks from this crystal or oscillato r inp ut. The internal
Transmit Clock signal is a derivative of the 25 MHz internal clock. The accuracy of the external
crystal or oscillator must be ± 0.005% (30 ppm).
6.1.2 100BASE-TX Transmit Blocks
The transmit subsection of the PHY unit accepts nibble-wide data from the CSMA/CD unit. The
transmit subsection passes data unconditionally to a 4B/5B encoder.
The 4B/5B encoder accepts nibble-wide data (4 bits) from the CSMA unit and compiles it into 5-
bit-wide parallel symbols according to the IEEE 802.3u 100BASE_TX standard. Next, the symbols
are scrambled to reduce electromagnetic emissions during long sequences of high-frequency data
codes.
The MLT-3 (multi-level signal) encoder receives the scrambled Non-Return to Zero (NRZ) data
stream from the scrambler and encodes the stream into MLT-3 for presentation to the driv er. MLT-
3 is similar to NRZ1 coding, but three levels are output instead of two. The three output levels are
positive, negative and zero.
The transmit differential pair line drivers are implemented with digital slope controlled current
buffers that meet the TP-PMD specifications. Curren t is sinked from an isolati on transformer by
the TDP and TDN pins. The 125 Mbps bit stream is typically driven onto Unshielded Twisted Pair
(UTP) cable.
6.1.3 100BASE-TX Receive Blocks
The receive subsection of the PHY unit accepts 100BASE-TX MLT-3 data on the receive
differential pair. Due to the advanced digital signal processi ng design techniques employed, the
PHY unit will accurately receive valid data from Category 5 (CAT5) UTP cables of lengths well in
excess of 100 meters.
The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer
performs adaptation based on the sh ape of the r eceived signal. The clock recovery circuit uses
digital signal processing to compensate for various signal jitter causes. The circuit recovers the 125
MHz clock and data and presents the data to the MLT-3 decoder.
The PHY unit first decodes the MLT-3 data; af terw ards, the descram bler reproduces the 5B
symbols originat ed in the transmitter. The data is decoded at the 4B/5B decoder. Aft er the 4B
symbols are obtained, the PHY unit outputs the receive data to the CSMA unit.
In 100BASE-TX mode, the PHY unit can detect errors in receive data in a number of ways,
including link integrit y failures, undetected start of st ream delimiters, invalid symbo ls, or idles in
the middle of a frame.
82551IT — Networking Silicon
36 Datasheet
6.1.4 100BASE-TX Link Integrity Auto-Negotiation
The 82551IT Auto-Negotiation function automat icall y confi gures the device to th e technol ogy,
media, and speed to operate with its link partner. Auto-Negotiation is described in IEEE
specification 802.3u, clause 28. The PHY unit suppo rts 10BASE-T half duplex, 10BASE-T full
duplex, 100BASE-TX half duplex, and 100BASE-TX full duplex.
Speed and duplex auto-select are functions of Auto-Negotiation. However, these parameters may
be manually configured through the MII management interface (MDI registers). Manual
configurations override the auto-select.
6.2 10BASE-T PHY Functions
6.2.1 10BASE-T Transmit Clock Generation
The 20 MHz and 10 MHz clocks needed for 10BASE-T are synthesized from the external 25 MHz
crystal or oscillator. The PHY unit provides the transmit clock and receive clock to the internal
MAC at 2.5 MHz.
6.2.2 10BASE-T Transmit Blocks
After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock
performs Manchest er encoding.
Since 10BASE-T and 100BASE-TX have different filtration needs, both filters are implemented
inside the chip. The PHY unit supports both technologies through one pair of TD pins and by
externally sharing the same magnetics.
In 10 Mbps mode, the line drivers use a pre-distortion algorithm to improve jitter tolerance. The
line drivers reduce their drive level durin g the seco nd half of “wide” Manchester pulses and
maintain a full drive level during narrow pulses and the first half of the wide pulses. This reduces
jitter caused by overcharging the line.
6.2.3 10BASE-T Receive Blocks
The PHY unit performs Manchester decodin g and timing recovery when in 10 Mbps mode. The
Manchester-encoded data stream is decoded from the RD pair to separate Receive Clock and
Receive Data from the differential signal. This data is transferred to the CSMA unit at 2.5 MHz/
nibble.
In 10 Mbps mode, data is expected to be received on the receive differential pair after passing
through isolation tran sformers. The inpu t differential voltage range capability for the Twisted Pair
Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V. The TPE receive buffer
distinguishes valid receive data, link test pulses, and idles, according to the requirements of the
10BASE-T standard.
In 10 Mbps mode, the PHY unit can detect errors in the receive data, including voltage drops prior
to the end-of-frame bit. Collision detection in 10 Mbps mode is initiated by simul taneou s
transmission and reception. If the PHY unit detects this condition, it asserts a collision indication to
the CSMA/CD unit.
Networking Silicon — 82551IT
Datasheet 37
6.2.4 10BASE-T Link Integrity and Full Duplex
The link integrity in 10 Mbps works with link pulses. The PHY unit senses and dif ferentiates those
link pulses from fast link pulses and from 100BASE-TX idles. Th e link beat pulse is also used to
determine if the receive pair polarity is reversed. If it is, the polarity is corrected internally.
The PHY unit supports 10 Mbps full duplex by disabling the collision function, the squelch test,
and the carrier sense transmit function. This allows the PHY unit to transmit and receive
simultaneously, achieving up to 20 Mbps network bandwidth using Auto-Nego tiati on. Full duplex
can only be used in point-to-point connections (n o shared media).
6.3 Auto-Negotiation
The PHY unit supports Auto-Negotiation, which is an automatic configuration scheme designed to
manage interoperability in multifunctional LAN environments. An Auto-Negotiation capable
device can detect and automatically configure its port to take maximum advan tage of common
modes of operation without user interventi on or prior knowledge by either station. Auto-
Negotiation is described in IEEE Standard 802.3u, clause 28.
6.3.1 Description
A PHY’s capability is encoded by bursts of link pulses called Fast Link Pulses (FLPs). Connection
is established by FLP exchange and handshake during link initialization time. After the lin k is
established by this handshake, the native link pulse scheme resumes. A reset or management re-
negotiate command (through the MDI interface) will restart the process. If the PHY unit cannot
perform Auto-Negotiation, it will set this bit to 0 and determine the speed using Parallel Detection.
The PHY unit supports four technologies: 100BASE-Tx Full and Half Duplex and 10BASE-T Full
and Half Duplex. Since only one technology can be used at a time (after every re-negotiate
command), a prioritization scheme is used to ensure that the abil ity of the highest common
denominator is chosen.
6.3.2 Parallel Detect and Auto-Negotiation
The PHY unit can automatically determ ine the speed of the link by using Parallel Detect as an
alternative to Auto-Negotiation. Upon a reset, a link status fail, or a negotiate/re-negotiate
command, the PHY unit inserts a long delay during which no link pulses are transmitted. Th is
period insures that the PHY unit‘s link partner has gone into a Link Fail state before Auto-
Negotiation or Parallel Detection begins. The PHY unit will look for both FLPs and link integrit y
pulses. The following diagram illustrates this process.
82551IT — Networking Silicon
38 Datasheet
6.4 LED Description
The PHY unit supports three LED pins to indicate link status, network activity and network speed.
Each pin can source 10 mA.
•Link: This LED is off until a valid link has been detected. After a valid link has been detected,
the LED will remain on (active-low).
•Activity: This LED blinks on and off when activity is detected on the wire.
•Speed: This LED will be on if a 100BASE-TX link is detected and off if a 10BASE-T link is
detected. If the link fails while in Auto-Negoti ation, this LED will keep the last valid link
state. If 100BASE-TX link is forced th is LED will be on, regardless of the link status. This
LED will be off if the 10BASE-T link is forced, regardless of the link status.
MDI register 27 in Section 9.3.12, “Register 27: PHY Unit Special Control Register” details the
information for LED function mapp ing and support enhancements.
Figure 12 provides possible schematic diagrams for config urat ions using two and three LEDs.
Figure 11. Auto-Negotiation and Parallel Detect
Force_Fail
A
bility detect either b
y
parallel detect or auto-
negotiation.
10Base-T or
100Base-TX Link
Ready FLP capable
LINK PASS
Parallel Detection
A
uto-Negotiation
Look at Link Pulse;
A
uto-Negotiation capable = 0
A
uto-Negotiation capable = 1
A
bility Match
A
uto-Negotiation Complete bit set
Networking Silicon — 82551IT
Datasheet 39
Figure 12. Two and Three LED Schematic Dia gram
LILED#
ACTLED#
SPDLED#
vcc
RR
R
LILED#
SPDLED#
ACTLED#
R
R
82551IT
82551IT — Networking Silicon
40 Datasheet
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Networking Silicon — 82551IT
Datasheet 41
7.0 Configuration Registers
The 82551IT acts as both a master and a slave on the PCI bus. As a master, the 82551IT interacts
with the system main memory to access data for transmission or deposit received data. As a slave,
some 82551IT control structures are accessed by the host CPU to read or write information to the
on-chip registers. The CPU also provides the 82551IT with the necessary commands and pointers
that allow it to process receive and transmit data.
7.1 Function 0: LAN (Ethernet) PCI Configuration Space
The 82551IT PCI configuration space is configured as 16 Dwords of Type 0 Configuration Space
Header, as defined in the PCI Specification, Revision 2.1. A small section is also configured
according to its device specific configuration space. The configuration space header is depicted
below in Figur e 13.
7.1.1 PCI Vendor ID and Device ID Registers
The Vendor ID and Device ID of the 82551IT are both read only word entities. Their values are:
Vendor ID: 8086h
Device ID: 1209h
Figure 13. PCI Configuration Regis ters
Device ID Vendor ID 00h
Status Command 04h
Class Code Revision ID 08h
BIST Header Type Latency Timer Cache Line Size 0Ch
CSR Memory Mapped Base Address Register 10h
CSR I/O Mapped Base Address Register 14h
Flash Memory Mapped Base Address Register 18h
Reserved Base Address Register 1Ch
Reserved Base Address Register 20h
Reserved Base Address Register 24h
Reserved (PCI mode) 28h
Subsystem ID Subsystem Vendor ID 2Ch
Expansion ROM Base Address Register 30h
Reserved Cap_Ptr 34h
Reserved 38h
Max_Lat Min_Gnt Interrupt Pin Interrupt Line 3Ch
Power Management Capabilities Next Item Ptr Capability ID DCh
Reserved Data Power Management CSR E0h
82551IT — Networking Silicon
42 Datasheet
7.1.2 PCI Command Register
The 82551IT Command register at word address 04h in the PCI configuration space provides
control over the 82551IT’s ability to generate and respond to PCI cycles. If a 0 is written to this
register, the 82551IT is logically disconnected from the PCI bus for all accesses except
configuration accesses. The format of this register is shown in the figure below.
Bits three, five, seven, and nine are set to 0b. Table 13 describes the bits of the PCI Command
register.
Figure 14. PCI Command Register
Reserved
15 10987 654 321 0
SERR# Enable
Parity Error Response
Memory Write and Invalidate Enable
Bus Master Enable
Memory Space
I/O Space
0000
Table 13. PCI Command Register Bits
Bits Name Description
15:10 Reserved These bits are reserved and should be set to 0b.
8 SERR# Enable This bit controls a device’s ability to enable the SERR# driver . A value of 0b
disables the SERR# driver. A value of 1b enables the SERR# driver. This
bit must be set to report address parity errors. In the 82551IT, this bit is
configurable and has a default value of 0b.
6 Parity Error Control
This bit controls a device’s response to parity errors. A value of 0b causes
the device to ignore any parity errors that it detects and continue normal
operation. A value of 1b causes the device to take normal action when a
parity error is detected. This bit must be set to 0b after RST# is asserted. In
the 82551IT, this bit is configurable and has a default value of 0b.
4Memory Write and
Invalidate Enable
This bit controls a device’s ability to use the Memory Write and Invalidate
command. A value of 0b disables the device from using the Memory Write
and Invalidate Enable command. A value of 1b enables the device to use
the Memory Write and Invalidate command. In the 82551IT, this bit is
configurable and has a default value of 0b.
2Bus Master This bit controls a device’s ability to act as a master on the PCI bus. A
value of 0b disables the device from generating PCI accesses. A value of
1b allows the device to behave as a bus master. In the 82551IT, this bit is
configurable and has a default value of 0b.
1 Memory Space This bit controls a device’s response to the memory space accesses. A
value of 0b disables the device response. A value of 1b allows the device
to respond to memory space accesses. In the 82551IT, this bit is
configurable and its default value of 0b.
0 I/O Space This bit controls a device’s response to the I/O space accesses. A value of
0b disables the device response. A value of 1b allows the device to
respond to I/O space accesses. In the 82551IT, this bit is configurable and
the default value of 0b.
Networking Silicon — 82551IT
Datasheet 43
7.1.3 PCI Status Register
The 82551IT Status register is used to record status information for PCI bus related events. The
format of this register is shown in the figure below.
Note: Bits 21, 22, 26, and 27 are set to 0b and bits 20, 23, and 25 are set to 1b. The PCI Status register bits
are described in Table 14.
Figure 15. PCI Status Register
Table 14. PCI Status Register Bits
Bits Name Description
31 Detected Parity Error
This bit indicates whether a parity error is detected. This bit must be set by
the device when it detects a parity error, even if pa rity error handling is
disabled (as controlled by the Parity Error Response bit in the PCI
Command register, bit 6). In the 82551IT, the initial value of the Detected
Parity Error bit is 0b. This bit is set until cleared by writing a 1b.
30 Signaled System Error This bit indicates when the device has asserted SERR#. In the 82551IT,
the initial value of the Signaled System Error bit is 0b. This bit is set until
cleared by writing a 1b.
29 Received Master
Abort
This bit indicates whether or not a master abort has occurred. This bit must
be set by the master device when its transaction is terminated with a
master abort. In the 82551IT, the initial value of the Received Master Abort
bit is 0b. This bit is set until cleared by writing a 1b.
28 Received Target Abort This bit indicates that the master has received the target abort. This bit
must be set by the master device when its transaction is terminated by a
target abort. In the 82551IT, the initial value of the Received Target Abort
bit is 0b. This bit is set until cleared by writing a 1b.
27 Signaled Target Abort This bit indicates whether a transaction was terminated by a target abort.
This bit must be set by the target device when it terminates a transaction
with target abort. In the 82551IT, this bit is always set to 0b.
26:25 DEVSEL# Timing
These two bits indicate the timing of DEVSEL#:
00b - Fast
01b - Medium
10b - Slow
11b - Reserved
In the 82551IT, these bits are always set to 1b, medium.
0
Detected Parity Error
Signaled System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
Devsel Timing
Parity Error Detected
Fast Back To Back (target)
Capabilities List
Reserved011000 10
31 30 29 28 27 26 25 24 23 22 21 20 19 16
82551IT — Networking Silicon
44 Datasheet
24 Parity Error Detected
This bit indicates whether a parity error has been detected. This bit is set to
1b when the following three conditions are met:
1. The bus agent asserted PERR# itself or observed PERR# asserted.
2. The agent setting the bit acted as the bus master for the operation in
which the error occurred.
3. The Parity Error Response bit in the command register (bit 6) is set.
In the 82551IT, the initial value of the Parity Error Detected bit is 0b. This
bit is set until cleared by writing a 1b.
23 Fast Back-to-Back This bit indicates a device’s ability to accept fast back-to-back transactions
when the transactions are not to the same agent. A value of 0b disables
fast back-to-back ability. A value of 1b enables fast back-to-back ability. In
the 82551IT, this bit is read only and is set to 1b.
20 Capabilities List
This bit indicates whether the 82551IT implements a list of new capabilities
such as PCI Power Management. A value of 0b means that this function
does not implement the Capabilities List. If this bit is set to 1b, the Cap_Ptr
register provides an offset into the 82551IT PCI Configuration space
pointing to the location of the first item in the Capabilities List. This bit is set
only if the power management bit in the EEPROM is set.
19:16 Reserved These bits are reserved and should be set to 0b.
Table 14. PCI Stat us Register Bits
Bits Name Description
Networking Silicon — 82551IT
Datasheet 45
7.1.4 PCI Revision ID Register
The Revision ID is an 8-bit read only register . The three least significant bits of the Revision ID can
be overridden by the ID and Revision ID fields in the EEPROM (Section 5.5, “Serial EEPROM
Interface”). The default values of the Revision ID are:
82551IT (A-step): 0Fh
7.1.5 PCI Class Code Register
The Class Code register is read only and is used to identify the generic function of the device and,
in some cases, specific register level programming interface. The register is broken into three byte
size fields. The upper byte is a base class code and specifies the 82551IT as a netw ork controller,
2h. The middle byte is a subclass code and specifies the 82551IT as an Ethernet controller, 0h. The
lower byte identifies a specific register level programming interface and the 82551IT always
returns a 0h in this field.
7.1.6 PCI Cache Line Size Register
In order for the 82551IT to support th e Memo ry Write and Invalidate (MWI) command, the
82551IT must also support the Cache Line Size (CLS) register in PCI Configuration space. The
register supports only cache line sizes of 8 and 16 Dwords. Any value other than 8 or 16 that is
written to the register is ignored and the 82551IT does not use the MWI command. If a value other
than 8 or 16 is written into the CLS register, the 82551IT returns all zeroes when the CLS register
is read. The figure below shows the format of this register.
Note: Bit 3 is set to 1b only if the value 00001000b (8h) is written to this register, and bit 4 is set to 1b
only if the value of 00010000b (16h) is written to this register. All other bits are read only and will
return a value of 0b on read.
The BIOS is expected to write to this register. Therefore, the 82551IT driver should not write to it.
7.1.7 PCI Latency Timer
The Latency Timer register is a byte wide register. When the 82551IT is acting as a bus master, this
register defines the amount of tim e, in PCI clock cycles, that it may ow n the bus.
7.1.8 PCI Header Type
The Header Type register is a byte read only register and is equal to 00h for a single function NIC
or LOM system. The value of the header type is set by the EEPROM (Section 5.5, “Serial
EEPROM Interface”).
Figure 16. Cache Line Size Register
76543210
000RWRW000
82551IT — Networking Silicon
46 Datasheet
7.1.9 PCI Base Address Registers
One of the most important functions for enabli ng superior configurabil ity and ease of use is the
ability to relocate PCI devices in address spaces. The 82551IT contains three types of Base
Address Registers (BARs). Two are used for memory mapped resources, and one is used for I/O
mapping. Each register is 32 bits wide. The least significant bit in the BAR determines whether it
represents a memory or I/O space. The figures below show the layout of a BAR for both memory
and I/O mapping. After determining this information, power-up software can map the memory and
I/O controllers into available locations and proceed with system boot. In order to do this mapping
in a device independent manner, the base registers for this mapping are placed in the predefined
header portion of configuration space. Device drivers can then access this configuration space to
determine the mapping of a particular device.
Note: Bit 0 in all base registers is read only and used to determine whether the register maps into memory
or I/O space. Base registers that map to memory space must return a 0b in bit 0. Base registers that
map to I/O space must return 1b in bit 0.
Base registers that map into I/O space are always 32 bits wide with bit 0 hard-wired to a 1b, bit 1 is
reserved and must return 0b on reads, and the other bits are used to map the device into I/O space.
The number of upper bits that a device actually implements depen ds on how much of the address
space the device will respond to. For example, a device that wants a 1 MB memory address space
would set the most significant 12 bits of the base address register to be configurable, setting the
other bits to 0b.
The 82551IT contains BARs for the Control/Status Register (CSR), Flash, and Expansion ROM.
Figure 17. Base Address Register for Memory Mapping
Base Address 0
0
31 4321
Prefetchable
Type:
00 - locate anywhere in 32-bit address space
01 - locate below 1 MB
10 - locate anywhere in 64-bit address space
11 - reserved
Memory space indicator
Figure 18. Base Address Register for I/O Mapping
Base Address 00
31 21
Reserved
I/O space indicator
1
Networking Silicon — 82551IT
Datasheet 47
7.1.9.1 CSR Memory Mapped Base Address Register
The 82551IT requires one BAR for memory map ping. Software determines which BAR, memory
or I/O, is used to access the 82551IT CSR registers.
The memory space for the 82551IT CSR Memory Mapped BAR is 4 KB. The space is marked as
not prefetchable and is mapped anywhere in the 32-bit memory address space.
7.1.9.2 CSR I/O Mapped Base Address Register
The 82551IT requires one BAR for I/O map ping. Software determines which BAR, I/O or
memory, is used to access the 82551IT CSR registers. The I/O space for the 82551IT CSR I/O
BAR is 64 bytes.
7.1.9.3 Flash Memory Mapped Base Address Register
The Flash Memory BAR is a Dword register. The 82551IT physically supports a 128 KB Flash
device.
7.1.9.4 Expansion ROM Base Address Register
The Expansion ROM has a memory space of 1 MB and its BAR is a Dword register that supports a
128 KB memory via the 8255 1IT local bus. The Expansion ROM BAR can be disabled by setting
the Boot Disable bit located in the EEPROM (word Ah, bit 11). If the Boot Disable bit is set, the
82551IT returns a 0b for all bits in this address register, avoiding request of memory allocation for
this space.
7.1.10 Base Address Registry Summary
The preceding description of the Base Address Registers’ functions are listed in Table 15.
7.1.11 PCI Subsystem Vendor ID and Subsystem ID Registers
The Subsystem Vendor ID field identifies the vendor of an 82551IT based solution. The Subsystem
Vendor ID values are based upon the vendor’s PCI Vendor ID and is controlled by the PCI Special
Interest Group (SIG).
The Subsystem ID field identifies the 82 551IT based specific solution implemented by the vendor
indicated in the Subsystem Vendor ID field.
Table 15. Base Address Register Functions
Register Name PCI Function PCI Window
BAR0 Memory CSR 4 KB
BAR1 I/O CSR 4 KB
BAR2 Flash 128 KB
Expansion BAR BootROM 1 MB
82551IT — Networking Silicon
48 Datasheet
The 82551IT provides support fo r configu rabl e Subsyst em Vendo r ID and Subsystem ID fields.
After hardware reset is de-asserted, the 82551IT automatically reads addresses Ah through Ch of
the EEPROM. The first of these 16-bit values is used for contro lling various 82551IT functions.
The second is the Subsystem ID value, and the third is the Subsystem Vendor ID value. Again, the
default values for the Subsystem ID and Subsystem Vendor ID are 0h and 0h, respectively.
The 82551IT checks bit numbers 15, 14, and 13 in the EEPROM, word Ah and functions are listed
in Table 16.
The above table implies that if the 82551IT detects the presence of an EEPROM (as indicated by a
value of 1b in bits 15 and 14), then bit number 13 determin es whether the values read from the
EEPROM, words Bh and Ch, are loaded int o the Su bsystem ID (word Bh) and Subsystem Vendor
ID (word Ch) fields. If bits 15 and 14 equal 1b and bit 13 equals 1b, the three least significant bits
of the Revision ID field are programmed by bits 10:8 of th e first EEPROM word, Ah.
Between the de-assertion of reset and the completion of the automatic EEPROM read, the 82551IT
does not respond to any PCI configuration cycles. If the 82551IT happens to be accessed during
this time, it will Retry the access. More information on Retry is provided in Section 5.2.1.1.3,
“Retry Premature Accesses”.
7.1.12 Capability Pointer
The Capability Pointer is a hard-coded byte register with a value of DCh. It provides an offset
within the Configuration Space for the location of the Power Management registers.
7.1.13 Interrupt Line Register
The Interrupt Line register identifies which system interrupt request line on the interrupt controller
the device’s PCI int errupt request pin (as defined in the Interrupt Pin register) is routed to.
7.1.14 Interrupt Pin Register
The Interrupt Pin register is read only and defines which of the four PCI interrupt request pins,
INTA# through INTD#, a PCI device is connected to. The 82551IT is connected the INTA# pin.
Table 16. ID Fields Programming
Signature
(Bits 15:14) ID
(Bit 13) AltID
(Bit 7) Device
ID Vendor
ID Revision IDa
(A-0 and A-1) Subsystem
ID Subsystem
Vendor ID
11bb, 10b,
00b X X 1209h 8086h 0Fh 0000h 0000h
01b 1b X 1209h 8086h Word Ah, bits
10:8 Word Bh Word Ch
01b 0b 0b 1209h 8086h 0Fh Word Bh Word Ch
01b 0b 0b 1209h 8086h 08h Word Bh Word Ch
a. The Revision ID is subject to change according to the silicon stepping.
b. If bit 15 equals 1b, the EEPROM is invalid and the default values are used.
Networking Silicon — 82551IT
Datasheet 49
7.1.15 Minimum Grant Register
The Minimum Grant (Min_Gnt) register is an optional read only register for bus masters and is not
applicable to non-master devices. It defines the amount of time the bus master wants to retain PCI
bus ownership when it initiates a transaction. The default value of this register for the 82551IT is
08h.
7.1.16 Maximum Latency Register
The Maximum Latency (Max_Lat) register is an optional read only register for bus masters and is
not applicable to non-master devices. This register defines how often a device needs to access the
PCI bus. The default value of this register for the 82551IT is 18h.
7.1.17 Capability ID Register
The Capability ID is a byte register. It signifies whether the current item in the linked list is the
register defined for PCI Power Management. PCI Power Management has been assigned the value
of 01h. The 82551IT is fully compliant with th e PCI Power Management Sp ecification, Revision
2.2.
7.1.18 Next Item Pointer
The Next Item Pointer is a byte register. It describes the location of the next item in the 82551IT’s
capability list. Since power management is the last item in the list, th is register is set to 0b.
7.1.19 Power Management Capabilities Register
The Power Management Capabilities register is a word read only register. It provides information
on the capabilities of the 82551IT related to power management. The 82551IT reports a value of
FE21h if it is connected to an auxiliary power source and 7E21h otherwise. It indicates that the
82551IT supports wake-up in the D3 state if power is supplied, either Vcc or VAUX.
Table 17. Power Management Capability Register
Bits Default Read/Write Description
31:27
00011b
(no VAUX)
11111b
(VAUX)
Read Only
PME# Support. This five-bit field indicates the power states in which
the 82551IT may assert PME#. The 82551IT supports wake-up in all
power states if it is fed by an auxiliary power supply (VAUX) and D0,
D1, D2, and D3hot if it is fed by PCI power.
26 1b Read Only D2 Support. If this bit is set, the 82551IT supports the D2 power
state.
25 1b Read Only D1 Support. If this bit is set, the 82551IT supports the D1 power
state.
24:22 0b Read Only
Auxiliary Current. This field reports whether the 82551IT
implements the Data registers. The auxiliary power consumption is
the same as the current consumption reported in the D3 state in the
Data register.
21 1b Read Only
Device Specific Initialization (DSI). The DSI bit indicates whether
special initialization of this function is required (beyond the standard
PCI configuration header) before the generic class device driver is
able to use it. DSI is required for the 82551IT after D3-to-D0 reset.
82551IT — Networking Silicon
50 Datasheet
7.1.20 Power Management Control/Status Register (PMCSR)
The Power Management Control/Status is a word register. It is used to determine and change the
current power state of the 82551 IT and cont rol the power management interrupts in a standard
manner.
20 0b (PCI) Read Only Reserved PCI.
19 0b Read Only PME# Cl ock . The 82551IT does not require a clock to generate a
power management event.
18:16 010b Read Only Version. A value of 010b indicates that the 82551IT complies with of
the PCI Power Management Specification, Revision 2.2.
Table 17. Power Management Capability Register
Bits Default Read/Write Description
Table 18. Power Management Control and Status Register
Bits Default Read/Write Description
15 0b Read/Clear
PME# Status. This bit is set upon a wake-up event. It is independent
of the state of the PME# Enable bit. If 1b is written to this bit, the bit will
be cleared. It also de-asserts the PME# signal and clears the PME#
status bit in the Power Management Driver Register. When the PME#
signal is enabled, the PME# signal reflects the state of the PME status
bit.
14:13 0b Read Only Data Scale. This field indicates the data register scaling factor. It
equals 1b for registers zero through eight and 0b for registers 9
through 15.
12:9 0b Read Only Data Select. This field is used to select which data is reported through
the Data register and Data Scale field.
8 0b Read Clear PME Enable. This bit enables the 82551IT to assert PME#.
7:5 0b Read Only Reserved. These bits are reserved and should be set to 0b.
4 0b Read Only Dynamic Data. The 82551IT does not support the ability to monitor
the power consumption dynamically.
3:2 0b Read Only Reserved. These bits are reserved and should be set to 0b.
1:0 0b Read/Write
Power State. This 2-bit field is used to determine the current power
state of the 82551IT and to set the 82551IT into a new power state.
The definition of the field values is as follows.
00 - D0
01 - D1
10 - D2
11 - D3
Networking Silicon — 82551IT
Datasheet 51
7.1.21 Data Register
The data register is an 8-bit read only register that provides a mechanism for the 82551IT to report
state dependent maximum power consumption and heat dissipation. The valu e reported in this
register depends on the value written to the Data Select field in the PMCSR register. The power
measurements def ined in thi s r egist er have a dy nami c ra nge o f 0 t o 2 .55 W wi th 0. 01 W r esolu tio n
according to the Data Scale. The value in this register is hard-coded in the silicon. The structure of
the data register is presented below.
Table 19. Ethernet Dat a Register
Data Select Data Scale Data Reported
0 2 D0 Power Consumption = 60 (600 mW)
1 2 D1 Power Consumption = 42 (420 mW)
2 2 D2 Power Consumption = 42 (420 mW)
3 2 D3 Power Consumption = 42 (420 mW)
4 2 D0 Power Dissipated = 60 (60 mW)
5 2 D1 Power Dissipated = 42 (420 mW)
6 2 D2 Power Dissipated = 42 (420 mW)
7 2 D3 Power Dissipated = 42 (420 mW)
8 2 Common Function Power Dissipated = 00
9-15 0 Reserved (00h)
82551IT — Networking Silicon
52 Datasheet
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Networking Silicon — 82551IT
Datasheet 53
8.0 Control/Status Registers
8.1 LAN (Ethernet) Control/Status Registers
The 82551IT’s Control/Status Register (CSR) is shown in the figure Figure 19.
NOTE: In Figure 19 above, SCB is defined as the System Control Block of the 82551IT, and PMDR is defined
as the Power Management Driver Register.
SCB S tatus Word: The 82551IT places the status of its Command and Receive units and interrupt
indications in this register for the CPU to read.
SCB Command Word: The CPU places commands for the Command and Receive units in this
register. Interrupts are also acknowledged in this register.
SCB General Pointer: The SCB General Pointer register points to various data structures in main
memory depending on the current SCB Command word.
PORT Interface: The PORT interface allows the CPU to reset the 82551IT, force the 82551IT to
dump information to main memory, or perform an internal self test.
Flash Control Register: The Flash Control register allows the CPU to enable writes to an external
Flash.
EEPROM Control Register: The EEPROM Control register allows the CPU to read and write to
an external EEPROM.
Figure 19. Control/Status Register
D31 Upper Word D16 D15 Lower Word D0 Offset
SCB Command Word SCB Status Word 00h
System Control Block General Pointer 04h
PORT 08h
EEPROM Control Register Flash Control Register 0Ch
Management Data Interface (MDI) Control Register 10h
Receive Direct Memory Access Byte Count 14h
PMDR Flow Control Register Reserved 18h
Reserved General Status General Control 1Ch
Reserved 20h
Command Block Pointer 24h
Reserved 28h
Reserved 2Ch
Function Event Register 30h
Function Event Mask Register 34h
Function Present State Register 38h
Force Event Register 3Ch
82551IT — Networking Silicon
54 Datasheet
MDI Control Register: The MDI Control register allows the CPU to read and write information
from the PHY unit (or an external PHY component) through the Management Data Interface.
Receive DMA Byte Count: The Receive DMA Byte Count register keeps track of how many
bytes of receive data have been passed into host memory via DMA.
Flow Control Register: This register holds the flow control threshold value and indicates the flow
control commands to the 82551IT.
PMDR: The Power Management Driver Register provides an indication in memory and I/O space
that a wake-up interrupt has occurred.
General Control: The General Control register allows the 82551IT to enter the deep power-down
state and provides the ability to disable the Clockrun functionality.
General Status: The General Status register describes the status of the 82551IT’s duplex mode,
speed, and link.
Function Present State: The Function Present State register reflects the current state of each
condition that may cause a status change or interrup t.
Force Event: The Force Event register simulates the status change events for troubleshooting
purposes.
8.1.1 System Control Block Status Word
The System Control Block (SCB) Status Word contains status information relating to the
82551IT’s Command and Receive units.
Table 20. System Control Block Sta tus Word
Bits Name Description
15 CX Command Unit (CU) Executed. The CX bit indicates that the CU has
completed executing a command with its interrupt bit set.
14 FR Frame Received. The FR bit indicates that the Receive Unit (RU) has
finished receiving a frame.
13 CNA CU Not Active. The CNA bit is set when the CU is no longer active and in
either an idle or suspended state.
12 RNR Receive Not Ready. The RNR bit is set when the RU is not in the ready
state. This may be caused by an RU Abort command, a no resources
situation, or set suspend bit due to a filled Receive Frame Descriptor .
11 MDI
Management Data Interrupt. The MDI bit is set when a Management Data
Interface read or write cycle has completed. The management data interrupt
is enabled through the interrupt enable bit (bit 29 in the Management Data
Interface Control register in the CSR).
10 SWI Software Interrupt. The SWI bit is set when software generates an
interrupt.
9 Reserved This bit is reserved and should be set to 0b.
8FCP Flow Control Pause. The FCP bit is used as the flow control pause bit.
Networking Silicon — 82551IT
Datasheet 55
8.1.2 System Control Block Command Word
Commands for the 82551IT’s Command and Receive units are placed in this register by the CPU.
8.1.3 System Control Block General Pointer
The System Control Block (SCB) General Pointer is a 32-bit field that points to various data
structures depending on the comman d in the CU Command or RU Command field.
8.1.4 PORT
The PORT interface allows software to perform certain control functions on the 82551IT. This
field is 32 bits wide:
•Address and Data (bits 32:4)
•PORT Function Selectio n (bits 3:0)
The 82551IT supports four PORT comm ands: Soft ware Reset, Self-test, Selective Reset, and
Dump.
8.1.5 Flash Control Register
The Flash Control Register is a 32-bit field that allows access to an external Flash device.
7:6 CUS Command Unit Status. The CUS field contains the status of the Command
Unit.
5:2 RUS Receive Unit Status. The RUS field contains the status of the Receive Unit.
1:0 Reserved These bits are reserved and should be set to 0b.
Table 20. System Control Block Status Word
Bits Name Description
Table 21. System Control Block Command Word
Bits Name Description
31:26 Specific
Interrupt Mask
Specific Interrupt Mask. Setting this bit to 1b causes the 82551IT to stop
generating an interrupt (in other words, de-assert the INTA# signal) on the
corresponding event.
25 SI Software Generated Interrupt. Setting this bit to 1b causes the 82551IT to
generate an interrupt. Writing a 0b to this bit has no effect.
24 M Interrupt Mask. If the Interrupt Mask bit is set to 1b, the 82551IT will not
assert its INTA# pin. The M bit has higher precedence that the Specific
Interrupt Mask bits and the SI bit.
23:20 CUC Command Unit Command. This field contains the CU command.
19:16 RUC Receive Unit Command. This field contains the RU command.
82551IT — Networking Silicon
56 Datasheet
8.1.6 EEPROM Control Register
The EEPROM Control Register is a 32-bit field that enables a read from and a write to the external
EEPROM.
8.1.7 Management Data Interface Control Register
The Management Data Interface (MDI) Control register is a 32-bit field and is used to read and
write bits from the MDI.
8.1.8 Receive Direct Memory Access Byte Count
The Receive DMA Byte Count register keeps track of how many bytes of receive data have been
passed into host memory via DMA.
8.1.9 Flow Control Register
The Flow Control Register contains the follow ing fields:
•Flow Control Command
The Flow Control Command fiel d describes the action of the flow control process (for
example, pause, on, or off).
•Flow Control Threshold
The Flow Control Threshold field contains the threshold value (in other words, the number of
free bytes in the Receive FIFO).
Table 22. MDI Control Register
Bits Description
31:30 These bits are reserved and should be set to 0b.
29 Interrupt Enable. When this bit is set to 1b by software, the 82551IT asserts an interrupt to
indicate the end of an MDI cycle.
28 Ready. This bit is set to 1b by the 82551IT at the end of an MDI transaction. Software should
set this bit to 0 at the same time the command is written.
27:26 Opcode. These bits define the opcode: 01 for MDI write and 10 for MDI read. All other values
(00 and 11) are reserved.
25:21 PHY Address. This field of bits contains the PHY address.
20:16 PHY Register Address. This field of bits contains the PHY Register Address.
15:0 Data. In a write command, software places the data bits in this field, and the 82551IT transfers
the data to the PHY unit. During a read command, the 82551IT reads these bits serially from
the PHY unit, and software reads the data from this location.
Networking Silicon — 82551IT
Datasheet 57
8.2 Statistical Counters
The 82551IT provides informat ion for network management statistics by providing on-chip
statistical counters that count a variety of events associated with both transmit and receive. The
counters are updated by the 82551 IT w hen it com pletes the processing of a frame (that is, when it
has completed transmitting a frame on the link or when it has completed receiving a frame). The
Statistical Counters are reported to the software on demand by issuing the Dump Statistical
Counters command or Dump and Reset Statistical Counters command in the SCB Command Unit
Command (CUC) field.
Table 23. Statistical Counters
ID Counter Description
0 Transmit Good Frames
This counter contains the number of frames that were
transmitted properly on the link. It is updated only after the
actual transmission on the link is completed, not when the
frame was read from memory, as is done for the Transmit
Command Block status.
4Transmit Maximum Collisions
(MAXCOL) Errors This counter contains the number of frames that were not
transmitted because they encountered the configured
maximum number of collisions.
8Transmit Late Collisions
(LATECOL) Errors This counter contains the number of frames that were not
transmitted due to an encountered collision after the
configured slot time.
12 Transmit Underrun Errors
A transmit underrun occurs because the system bus cannot
keep up with the transmission. This counter contains the
number of frames that were either not transmitted or
retransmitted due to a transmit DMA underrun. If the 82551IT
is configured to retransmit on underrun, this counter may be
updated multiple times for a single frame.
16 Transmit Lost Carrier Sense (CRS) This counter contains the number of frames that were
transmitted by the 82551IT despite the fact that it detected the
de-assertion of CRS during the transmission.
20 Transmit Deferred This counter contains the number of frames that were
deferred before transmission due to activity on the link.
24 Transmit Single Collisions This counter contains the number of transmitted frames that
encountered one collision.
28 Transmit Multiple Collisions This counter contains the number of transmitted frames that
encountered more than one collision.
32 Transmit Total Collisions This counter contains the total number of collisions that were
encountered while attempting to transmit. This count includes
late collisions and frames that encountered MAXCOL.
36 Receive Good Frames This counter contains the number of frames that were
received properly from the link. It is updated only after the
actual reception from the link is completed and all the data
bytes are stored in memory.
40 Receive CRC Errors
This counter contains the number of aligned frames discarded
because of a CRC error. This counter is updated, if needed,
regardless of the Receive Unit state. The Receive CRC Errors
counter is mutually exclusive of the Receive Alignment Errors
and Receive Short Frame Errors counters.
82551IT — Networking Silicon
58 Datasheet
44 Receive Alignment Errors
This counter contains the number of frames that are both
misaligned (for example, CRS de-asserts on a non-octal
boundary) and contain a CRC error . The counter is updated, if
needed, regardless of the Receive Unit state. The Receive
Alignment Errors counter is mutually exclusive of the Receive
CRC Errors and Receive Short Frame Errors counters.
48 Receive Resource Errors
This counter contains the number of good frames discarded
due to unavailability of resources. Frames intended for a host
whose Receive Unit is in the No Resources state fall into this
category. If the 82551IT is configured to Save Bad Frames
and the status of the received frame indicates that it is a bad
frame, the Receive Resource Errors counter is not updated.
52 Receive Overrun Errors
This counter contains the number of frames known to be lost
because the local system bus was not available. If the traffic
problem persists for more than one frame, the frames that
follow the first are also lost; however, because there is no lost
frame indicator, they are not counted.
56 Receive Collision Detect (CDT) This counter contains the number of frames that encountered
collisions during frame reception.
60 Receive Short Frame Errors
This counter contains the number of received frames that are
shorter than the minimum frame length. The Receive Short
Frame Errors counter is mutually exclusive to the Receive
Alignment Errors and Receive CRC Errors counters. A short
frame will always increment only the Receive Short Frame
Errors counter.
64 Flow Control Transmit Pause This counter contains the number of Flow Control frames
transmitted by the 82551IT. This count includes both the Xoff
frames transmitted and Xon (PAUSE(0)) frames transmitted.
68 Flow Control Receive Pause This counter contains the number of Flow Control frames
received by the 82551IT. This count includes both the Xoff
frames received and Xon (PAUSE(0)) frames received.
72 Flow Control Receive Unsupported
This counter contains the number of MAC Control frames
received by the 82551IT that are not Flow Control Pause
frames. These frames are valid MAC control frames that have
the predefined MAC control Type value and a valid address
but has an unsupported opcode.
Table 23. Statistical Counters
ID Counter Description
Networking Silicon — 82551IT
Datasheet 59
The Statistical Counters are initially set to zero by the 82551IT after reset. They cannot be preset to
anything other than zero. The 82551IT increments the counters by internally reading th em,
incrementing them and writing them back. This process is invisible to the CPU and PCI bus. In
addition, the counters adhere to the following rules:
•The counters are wrap-around counters. After reaching FFFFFFFFh the counters wrap around
to 0.
•The 82551IT updates the required counters for each frame. It is possible for more than one
counter to be updated as multipl e errors can occur in a single frame.
•The counters are 32 bits wide and their behavior is fully compatible with the IEEE 802.1
standard. The 82551IT supports all mandatory and recommend statistics functions through the
status of the receive header and directly through these Statistical Counters.
The CPU can access the counters by issuing a Dump Statistical Counters SCB command. This
provides a “snapshot”, in main memory, of the intern al 82551IT statistical counters. The 82551IT
supports 19 counters. The dump could cons ist of either 16 or 19 counters, depending on the status
of the Extended Statistics Counters configuration bits in the Configuration command.
82551IT — Networking Silicon
60 Datasheet
Note: This page is intentionally left blank.
Networking Silicon — 82551IT
Datasheet 61
9.0 PHY Unit Registers
The 82551IT provides status and accepts management information via the Management Data
Interface (MDI) within the CSR space.
Acronyms mentioned in the registers are defined as follows:
9.1 MDI Registers 0 - 7
9.1.1 Register 0: Control Register
SC - self cleared
RO - read only
E - EEPROM setting affects content
LL - latch low
LH - latch high
Table 24. Register 0: Control
Bit(s) Name Description Default R/W
15 Reset This bit sets the status and control register of the PHY to
their default states and is self-clearing. The PHY returns
a value of one until the reset process has completed and
accepts a read or write transaction.
1 = PHY Reset
0RW
SC
14 Loopback This bit enables loopback of transmit data nibbles from
the TXD[3:0] signals to the receive data path. The PHY
unit’s receive circuitry is isolated from the network.
Note that this may cause the descrambler to lose
synchronization and produce 560 nanoseconds of “dead
time.”
Note also that the loopback configuration bit takes priority
over the Loopback MDI bit.
1 = Loopback enabled
0 = Loopback disabled (Normal operation)
0RW
13 Speed Selection This bit controls speed when Auto-Negotiation is disabled
and is valid on read when Auto-Negotiation is disabled.
1 = 100 Mbps
0 = 10 Mbps
1RW
12 Auto-Negotiation
Enable This bit enables Auto-Negotiation. Bits 13 and 8, Speed
Selection and Duplex Mode, respectively, are ignored
when Auto-Negotiation is enabled.
1 = Auto-Negotiation enabled
0 = Auto-Negotiation disabled
1RW
82551IT — Networking Silicon
62 Datasheet
9.1.2 Register 1: Status Register
11 Power-Down This bit sets the PHY unit into a low power mode. In low
power mode, the PHY unit consumes no more than 30
mA.
1 = Power-Down enabled
0 = Power-Down disabled (Normal operation)
0RW
10 Reserved This bit is reserved and should be set to 0b. 0 RW
9 Restart Auto-
Negotiation This bit restarts the Auto-Negotiation process and is self-
clearing.
1 = Restart Auto-Negotiation process
0RW
SC
8 Duplex Mode This bit controls the duplex mode when Auto-Negotiation
is disabled. If the PHY reports that it is only able to
operate in one duplex mode, the value of this bit shall
correspond to the mode which the PHY can operate.
When the PHY is placed in Loopback mode, the behavior
of the PHY shall not be affected by the status of this bit,
bit 8.
1 = Full Duplex
0 = Half Duplex
0RW
7 Collision Test This bit will force a collision in response to the assertion
of the transmit enable signal.
1 = Force COL
0 = Do not force COL
0RW
6:0 Reserved These bits are reserved and should be set to 0b. 0 RW
Table 25. Register 1: Status
Bit(s) Name Description Default R/W
15 Reserved This bit is reserved and should be set to 0b. 0 RO
E
14 100BASE-TX Full
Duplex 1 = PHY able to perform full duplex 100BASE-TX 1 RO
13 100 Mbps Half
Duplex 1 = PHY able to perform half duplex 100BASE-TX 1 RO
12 10 Mbps Full
Duplex 1 = PHY able to operate at 10Mbps in full duplex
mode 1RO
11 10 Mbps Half
Duplex 1 = PHY able to operate at 10 Mbps in half duplex
mode 1RO
10:7 Reserved These bits are reserved and should be set to 0b. 0 RO
6 Management
Frames Preamble
Suppression
0 = PHY will not accept management frames with
preamble suppressed 0RO
5 Auto-Negotiation
Complete 1 = Auto-Negotiation process completed
0 = Auto-Negotiation process has not completed 0RO
4 Remote Fault 0 = No remote fault condition detected 0 RO
Table 24. Register 0: Control
Bit(s) Name Description Default R/W
Networking Silicon — 82551IT
Datasheet 63
9.1.3 Register 2: PHY Identifier Register
9.1.4 Register 3: PHY Identifier Register
9.1.5 Register 4: Auto-Negotiation Advertisement Register
3 Auto-Negotiation
Ability 1 = PHY is able to perform Auto-Negotiation 1 RO
2 Link Status 1 = Valid link has been established
0 = Invalid link detected 0RO
LL
1 Jabber Detect 1 = Jabber condition detected
0 = No jabber condition detected 0RO
LH
0 Extended
Capability 1 = Extended register capabilities enabled 1 RO
Table 26. Register 2: PHY Identifier
Bit(s) Name Description Default R/W
15:0 PHY ID (high
byte) Value: 02A8h -- RO
Table 27. Register 3 PHY Identifier
Bit(s) Name Description Default R/W
15:0 PHY ID (low byte) Value: 0154h -- RO
Table 28. Register 4: Auto-Negotiation Advertisement
Bit(s) Name Description Default R/W
15 Next Page Constant 0 = Transmitting primary capability data
page 0RO
14 Reserved This bit is reserved and should be set to 0b. 0 RO
13 Remote Fault 1 = Indicate link p a rtner’s remote fault
0 = No remote fault 0RW
12:5 T echnology Ability
Field Technology Ability Field is an 8-bit field containing
information indicating supported technologies specific
to the selector field value.
00101111 RW
4:0 Selector Field The Selector Field is a 5-bit field identifying the type of
message to be sent via Auto-Negotiation. This field is
read only in the 82551IT and contains a value of
00001b, IEEE Standard 802.3.
00001 RO
Table 25. Register 1: Status
Bit(s) Name Description Default R/W
82551IT — Networking Silicon
64 Datasheet
9.1.6 Register 5: Auto-Negotiation Link Partner Ability Register
9.1.7 Register 6: Auto-Negotiation Expansion Register
9.2 MDI Registers 8:15
Registers 8 through 15 are reserved for IEEE.
Table 29. Auto-Negotiation Link Partner Ability
Bit(s) Name Description Default R/W
15 Next Page This bit reflects the PHY’s link partner’s Auto-
Negotiation ability. -- RO
14 Acknowledge This bit is used to indicate that the 82551IT’s PHY unit
has successfully received its link partner’s Auto-
Negotiation advertising ability.
-- RO
13 Remote Fault This bit reflects the PHY’s link partner’s Auto-
Negotiation ability. -- RO
12:5 Technology Ability
Field This bit reflects the PHY’s link partner’s Auto-
Negotiation ability. -- RO
4:0 Selector Field This bit reflects the PHY’s link partner’s Auto-
Negotiation ability. -- RO
Table 30. Register 6: Auto-Negotiation Expansion
Bit(s) Name Description Default R/W
15:5 Reserved These bits are reserved and should be set to 0b. 0 RO
4 Parallel Detection
Fault 1 = Fault detected via parallel detection (multiple link
fault occurred)
0 = No fault detected via parallel detection
This bit will self-clear on read
0RO
SC
LH
3 Link Partner Next
page Able 1 = Link Partner is Next Page able
0 = Link Partner is not Next Page able 0RO
2 Next Page Able 1 = Local drive is Next Page able
0 = Local drive is not Next Page able 0RO
1 Page Received 1 = New Page received
0 = New Page not received
This bit will self-clear on read.
0RO
SC
LH
0 Link Partner Auto-
Negotiation Able 1 = Link Partner is Auto-Negotiation able
0 = Link Partner is not Auto-Negotiation able 0RO
Networking Silicon — 82551IT
Datasheet 65
9.3 MDI Register 16:31
9.3.1 Register 16: PHY Unit Status and Control Register
9.3.2 Register 17: PHY Unit Special Control Register
Table 31. PHY Unit Status and Control
Bit(s) Name Description Default R/W
15:14 Reserved These bits are reserved and should be set to 0b 00 RW
13 Carrier Sense
Disconnect
Control
This bit enables the disconnect function.
1 = Disconnect function enabled
0 = Disconnect function disabled
0RW
12 Transmit Flow
Control Disable This bit enables Transmit Flow Control
1 = Transmit Flow Control enabled
0 = Transmit Flow Control disabled
0RW
11 Receive De-
Serializer In-Sync
Indication
This bit indicates receipt status of the 100BASE-TX
receive de-serializer in-sync. -- RO
10 100BASE-TX
Power-Down This bit indicates the power state of 100BASE-TX
PHY unit.
1 = Power-Down
0 = Normal operation
1RO
9 10BASE-T
Power-Down This bit indicates the power state of 100BASE-TX
PHY unit.
1 = Power-Down
0 = Normal operation
1RO
8 Polarity This bit indicates 10BASE-T polarity.
1 = Reverse polarity
0 = Normal polarity
-- RO
7:2 Reserved These bits are reserved and should be set to 0b. 000000 RO
1 Speed This bit indicates the Auto-Negotiation result.
1 = 100 Mbps
0 = 10 Mbps
-- RO
0 Duplex Mode This bit indicates the Auto-Negotiation result.
1 = Full Duplex
0 = Half Duplex
-- RO
Table 32. Register 17: PHY Unit Special Control
Bit(s) Name Description Default R/W
15 Scrambler By-
pass 1 = By-pass Scrambler
0 = Normal operations 0RW
14 By-pass 4B/5B 1 = 4 bit to 5 bit by-pass
0 = Normal operation 0RW
13 Force Transmit H-
Pattern 1 = Force transmit H-pattern
0 = Normal operation 0RW
82551IT — Networking Silicon
66 Datasheet
9.3.3 Register 18: PHY Address Register
9.3.4 Register 19: 100BASE-TX Receive False Carrier Counter
12 Force 34
Transmit Pattern 1 = Force 34 transmit pattern
0 = Normal operation 0RW
11 Good Link 1 = 100BASE-TX link good
0 = Normal operation 0RW
10 Reserved This bit is reserved and should be set to 0b. 0 RW
9 Transmit Carrier
Sense Disable 1 = Transmit Carrier Sense disabled
0 = Transmit Carrier Sense enabled 0RW
8 Disable Dynamic
Power-Down 1 = Dynamic Power-Down disabled
0 = Dynamic Power-Down enabled (normal) 0RW
7 Auto-Negotiation
Loopback 1 = Auto-Negotiation loopback
0 = Auto-Negotiation normal mode 0RW
6 MDI Tr i-State 1 = MDI Tri-state (transmit driver tri-states)
0 = Normal operation 0RW
5 Filter By-pass 1 = By-p ass filter
0 = Normal filter operation 0RW
4 Auto Polarity
Disable 1 = Auto Polarity disabled
0 = Normal polarity operation 0RW
3 Squelch Disable 1 = 10BASE-T squelch test disable
0 = Normal squelch operation 0RW
2 Extended
Squelch 1 = 10BASE-T Extended Squelch control enabled
0 = 10BASE-T Extended Squelch control disabled 0RW
1 Link Integrity
Disable 1 = Link disabled
0 = Normal Link Integrity operation 0RW
0 Jabber Function
Disable 1 = Jabber disabled
0 = Normal Jabber operation 0RW
Table 33. Register 18: PHY Address
Bit(s) Name Description Default R/W
15:5 Reserved These bits are reserved and should be set to a
constant ‘0’ 0RO
4:0 PHY Address These bits are set to the PHY’s address, 00001b. 1 RO
Table 34. Register 19: 100BASE-TX Receive False Carrier Counter
Bit(s) Name Description Default R/W
15:0 Receive False
Carrier These bits are used for the false carrier counter. -- RO
SC
Table 32. Register 17: PHY Unit Special Control
Bit(s) Name Description Default R/W
Networking Silicon — 82551IT
Datasheet 67
9.3.5 Register 20: 100BASE-TX Receive Disconnect Counter
9.3.6 Register 21: 100BASE-TX Receive Error Frame Counter
9.3.7 Register 22: Receive Symbol Error Counter
9.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error
Counter
9.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter
Table 35. Register 20: 100BASE-TX Receive Disconnect Counter
Bit(s) Name Description Default R/W
15:0 Disconnect Event This field contains a 16-bit counter that increments for
each disconnect event. The counter freezes when full
and self-clears on read
-- RO
SC
Table 36. Register 21: 100BASE-TX Receive Error Frame Counter
Bit(s) Name Description Default R/W
15:0 Receive Error
Frame This field contains a 16-bit counter that increments
once per frame for any receive error condition (such
as a symbol error or premature end of frame) in that
frame. The counter freezes when full and self-clears
on read.
-- RO
SC
Table 37. Register 22: Receive Symbol Error Counter
Bit(s) Name Description Default R/W
15:0 Symbol Error
Counter This field contains a 16-bit counter that increments for
each symbol error. The counter freezes when full and
self-clears on read.
In a frame with a bad symbol, each sequential six bad
symbols count as one.
-- RO
SC
Table 38. Register 23: 100BASE-TX Receive Premature End of Frame Error Counter
Bit(s) Name Description Default R/W
15:0 Premature End of
Frame This field contains a 16-bit counter that increments for
each premature end of frame event. The counter
freezes when full and self-clears on read.
-- RO
SC
Table 39. Register 24: 10BASE-T Receive End of Frame Error Counter
Bit(s) Name Description Default R/W
15:0 End of Frame
Counter This is a 16-bit counter that increments for each end
of frame error event. The counter freezes when full
and self-clears on read.
-- RO
SC
82551IT — Networking Silicon
68 Datasheet
9.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter
9.3.11 Register 26: Equalizer Control and Status Register
9.3.12 Register 27: PHY Unit Special Control Register
Table 40. Register 25: 10BASE-T Transmit Jabber Detect Counter
Bit(s) Name Description Default R/W
15:0 Jabber Detect
Counter This is a 16-bit counter that increments for each
jabber detection event. The counter freezes when full
and self-clears on read.
-- RO
SC
Table 41. Register 26: Equalizer Control and Status
Bit(s) Name Description Default R/W
15:0 Reserved Reserved for future use -- RW
Table 42. Register 27: PHY Unit Special Control
Bit(s) Name Description Default R/W
15:3 Reserved These bits are reserved and should be set to 0b. 0 RW
2:0 LED Switch
Control Value
000
001
010
011
100
101
110
111
ACTLED#
Activity
Speed
Speed
Activity
Off
Off
On
On
LILED#
Link
Collision
Link
Collision
Off
On
Off
On
000 RW
Networking Silicon — 82551IT
Datasheet 69
9.3.13 Register 28: MDI/MDI-X Control Register
9.3.14 Register 29: Hardware Integrity Control Register
Table 43. Register 28: MDI/MDI-X Control
Bit(s) Name Definition Default R/W
15:8 Reserved Reserved for future use. Set these bits to 0. 0 R/W
7Auto Switch
Enable
Enables the MDI/MDI-X feature (writing to this bit
overwrites the default value).
1 = Enabled.
0 = Disabled.
0R/W
6Switch Manual switch (valid only if bit 7 is set to 0).
1 = Forces the port to be MDI-X (cross-over).
0 = Forces the port to be MDI (straight-through) 0R/W
5Status Indicates the state of the MDI pair.
1 = MDI-X (cross-over).
0 = MDI (straight-through). 0RO
4Auto Switch
Complete
Indicates when the correct configuration is achieved.
1 = Resolution algorithm has completed.
0 = Resolution algorithm has not completed. 1RO
3:0 Resolution Timer
Defines the minimum slot time the algorithm uses in
order to switch between one configuration or another .
0000 = 80ms.
1111 = 105ms.
0000 R/W
Table 44. Register 29: Hardware Integrity Control
Bit(s) Name Description Default R/W
15 HWI Enable This bit enables the HWI feature causing the PHY unit
to enter HWI test mode.
1 = HWI enabled
0 = HWI disabled
0RW
14 Ability Check This bit reports the results of the HWI ability check
and is valid 100 µs after the HWI Enabled bit (bit 15 of
this register) is set (1b).
1 = Test passed
0 = Test failed (HWI ability not detected)
RO
13 Test Execute When this bit is set, the PHY unit launches test pulses
on the wire to determine the distance to the cable’s
high or low impedance point.
1 = Execute test
0 = Do not execute test
WO
82551IT — Networking Silicon
70 Datasheet
12:11 Reserved These bits are reserved and should be set to 0b. 00 RO
10:9 LowZ/HighZ This field of bits indicates either a short (Low Z) or
open (high Z) on the line. It is valid 100 µs after the
Test Execute bit (bit 13 of this register) is set.
1 = Short (low Z)
0 = Open (high Z)
RO
8:0 Distance These bits define the distance to the short or open in
the cable and are valid 100 µs after the Test Execute
bit (bit 13 of this register) is set. The distance is
defined in granularities of 80 cm (35 inches).
RO
Table 44. Register 29: Hardware Integrity Control
Bit(s) Name Description Default R/W
Networking Silicon — 82551IT
Datasheet 71
10.0 82551IT Test Port Functionality
10.1 Introduction
The 82551IT’s XOR Tree Test Access Port (TAP) is the access point for test data to and from the
device. The port provides the ability to perform basic production level testing.
10.2 Test Function Description
The 82551IT TAP mode supports two tests that can be used in board level design. These tests help
verify basic functionality as well as te st the integrity of solder connection on the board. The tests
are described in the following subsections.
10.2.1 Tristate
The tristate command sets all 82551IT input and output pins into a tri state (high-Z) mode (all
internal pull-ups and pull-downs are disabled). This mode is entered by setting the follo wing test
pin combination and resetting the de vice:
TEST = 1 TEXEC = 0
TCK = 0 TI = 1
82551IT — Networking Silicon
72 Datasheet
10.2.2 XOR Tree
The XOR Tree test mode is the most useful of the asynchronous test modes. It enables the
placement of the 82551IT to be validated at board test. The XOR Tree was chosen for its speed
advantages. Modern automated test equipment can perform a complete peripheral scan without
support at the board level. This command connects all outputs of the input buffers in the device
periphery into a XOR T ree scheme. All the output drivers of the output buf fers, except the Test Port
Data Output (TO) pin, are put into high-Z mode. These pins are driven to affect the output of the
tree. There are two separate chains and associated outputs for speed. Any hard strapped pins will
prevent the tester from scanning correctly. This mode is entered by placing the test pins in the
following combination :
TEST = 1 TEXEC = 1
TCK = 0 TI = 1
ISOLATE# = 1
Note: ISOLATE# must be driven high in order to enter test mode and must be kept high throughout the
entire test.
There are two XOR Tree chains with two separate outputs assigned to FLOE# (Chain 1) and
FLWE# (Chain 2).
Table 45. XOR Tree Chains
Chain Order
(XOR Tree Output) Chain 1
(FLOE#) Chain 2
(FLWE#)
1RST#LILED#
2 IDSEL ACTLED#
3 REQ# SPDLED#
4 AD[23]
5 SERR#
6 AD[22]
7 AD[21]
8 AD[20] ALTRST#
9 AD[19] CLK_RUN#
10 AD[18] AD[31]
11 AD[17] AD[30]
12 C/BE#[2] AD[29]
13 FRAME# AD[28]
14 IRDY# AD[27]
15 TRDY# PME#
16 CLK
17 DEVSEL# AD[26]
18 INTA# AD[25]
19 STOP# C/BE#[3]
20 GNT# AD[24]
21 PERR# FLD0
Networking Silicon — 82551IT
Datasheet 73
22 PAR FLD1
23 AD[16] FLD2
24 C/BE#[1] FLD3
25 AD[15] FLD4
26 AD[14] FLD5
27 AD[13] FLD6
28 AD[12] FLD7
29 AD[11] FLA0
30 AD[10] FLA1
31 AD[9] FLA2
32 AD[8] FLA3
33 C/BE#[0] FLA4
34 AD[7] FLA5
35 AD[6] FLA6
36 AD[5] FLA7
37 AD[4] FLA8
37 AD[3] FLA9
39 AD[2] FLA10
40 AD[1] FLA11
41 AD[0] FLA12
42 EECS FLA13/EEDI
43 FLA14/EEDO
44 FLA15/EESK
45 FLA16
46 FLCS#
Table 45. XOR Tree Chains
Chain Order
(XOR Tree Output) Chain 1
(FLOE#) Chain 2
(FLWE#)
82551IT — Networking Silicon
74 Datasheet
Note: This page is intentionally left blank.
Networking Silicon — 82551IT
Datasheet 75
11.0 Electrical and Timing Specifications
Note: This section contains information on prod ucts in sampling and early production phase of
development. Do not finalize a design with this information. Revised information will be published
when the product becomes available.
11.1 Absolute Maximum Ratings
Maximum ratings are list ed below:
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40° C to 85° C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65° C to 140° C
Outputs and Supply Voltages (except PCI and SMB). . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.0 V
PCI and SMB Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50 V to 5.25 V
Transmit Data Output Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 8.0 V
Input Voltages (except PCI and SMB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 V to 5.0 V
PCI and SMB Input Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V 6.0 V
Stresses above the listed absolute maximum ratings may cause permanent damage to the 82551IT
device.
Note: The 82551QM/82551ER maximum rating for the Ambient Temperature is 0° C to 85 ° C.
82551IT — Networking Silicon
76 Datasheet
11.2 DC Specifications
NOTES:
1. Preferably, VIO should be 5 V ± 5% in any PCI environment (either 5 V or 3.3 V signaling). If 5 V is not
available in a 3.3 V signaling environment, 3.3 V ± 5% may be used instead.
2. Typical current consumption is in nominal operating conditions (VCC = 3.3 V) and average link activity.
Maximum current consumption is in maximum VCC and maximum link activity.
Table 46. General DC Specifications
Symbol Parameter Condition Min Typical Max Units Notes
VCC Supply Voltage 3.0 3.3 3.6 V
VIO Periphery Clamp
Voltage PCI 4.75 5.0 5.25 V 1
ICC
Power Supply
(10BASE-T)
D0a 10BASE-T full
function 85 100 mA 2
D1, D2, D3hot 10BASE-T
wake-up enabled 65 75 mA
D3cold 10BASE-T wake-
up enabled 40 50 mA
D3cold 10BASE-T wake-
up disabled 1.5 2.0 mA
Power Supply
(100BASE-TX)
D0a 100BASE-TX full
function 135 155 mA 2
D1, D2, D3hot 100BASE-
TX wake-up enabled 110 125 mA
D3cold 100BASE-TX
wake-up enabled 95 110 mA
D3cold 100BASE-TX
wake-up disabled 1.5 2.0 mA
Networking Silicon — 82551IT
Datasheet 77
The 82551IT supports PCI interface standards. In the PCI mode, it is five volts tolerant and
supports both 5 V and 3.3 V signaling environments.
NOTES:
1. These values are only applicable in 3.3 V signaling environments. Outside of this limit the input buffer must
consume its minimum current.
2. Input leakage currents include high-Z output leakage for all bidirectional buffers with tristate outputs.
3. Signals without pull-up resistors have 3 mA low output current; and signals requiring pull-up resistors, 6 mA.
The signals requiring pull-up resistors include: FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR# and
PERR#.
4. This value is characterized but not tested.
5. This input leakage current is the maximum allowable leakage into the PME# open drain driver when power is
removed from VCC of the component. This assumes that no event has occurred to cause the device to
assertion of PME#.
1. This value is characterized but not tested.
Table 47. PCI Interface DC Specifications
Symbol Parameter Condition Min Max Units Notes
VIHP Input High Voltage 0.475VCC VIO + 0.5 V
VILP Input Low Voltage -0.5 0.325VCC V
VIPUP Input Pull-up Voltage 0.7VCC V1
VIPDP Input Pull-down Voltage 0.2VCC V1
IILP Input Leakage Current 0 < VIN < VCC ±10 µA 2
VOHP Output High Voltage Iout = -2 mA
Iout = -500 µA 2.4
0.9VCC
V
VPCI
VOLP Output Low Voltage Iout = 3 mA, 6 mA
Iout = 1500 µA 0.55
0.1VCC
V
V3, PCI
CINP Input Pin Capacitance 10 pF 4
CCLKP CLK Pin Capacitance 5 12 pF 4
CIDSEL IDSEL Pin Capacitance 8 pF 4
LPINP Pin Inductance 20 nH 4
IOFFPME PME# Input Leakage
Current VO < VIO 1mA5
Table 48. Flash/EEPROM Interface DC Specifications
Symbol Parameter Condition Min Max Units Notes
VIHL Input High Voltage 2.0 VCC + 0.5 V
VILL Input Low Voltage -0.5 0.8 V
IILL Input Low Leakage
Current 0 < VIN < VCC ±20 µA
VOHL Output High Voltage Iout = -1 mA 2.4 V
VOLL Output Low Voltage Iout = 2 mA 0.4 V
CINL Input Pin Capacitance 10 pF 1
82551IT — Networking Silicon
78 Datasheet
NOTES:
1. Current is measured on all VCC pins (VCC = 3.3 V).
2. Transmitter peak current is attained by dividing the measured maximum differential output peak voltage by
the load resistance value.
3. Recommended starting value for RBIAS100.
Table 49. LED Voltage/Current Characteristics
Symbol Parameter Condition Min Typical Max Units Notes
VOHLED Output High Voltage Iout = -10 mA 2.4 V
VOLLED Output Low Voltage Iout = 10 mA 0.7 V
Table 50. 100BASE-TX Voltage/ Current Characteristics
Symbol Parameter Condition Min Typical Max Units Notes
RID100 Input Differential
Impedance DC 10 K
VIDA100 Input Differential
Accept Peak Voltage ±500 mV
VIDR100 Input Differential
Reject Peak Voltage ±100 mV
VICM100 Input Common Mode
Voltage VCC/2 V
VOD100 Output Differential
Peak Voltage 0.95 1.00 1.05 V
ICCT100 Line Driver Supply
Peak Current RBIAS100 = 649 20 mA 1, 2, 3
Networking Silicon — 82551IT
Datasheet 79
NOTES:
1. Current is measured on all VCC pins (VCC = 3.3 V).
2. Transmitter peak current is attained by dividing the measured maximum differential output peak voltage by
the load resistance value.
3. Recommended starting value for RBIAS10.
Table 51. 10BASE-T Voltage/Current Characteristics
Symbol Parameter Condition Min Typical Max Units Notes
RID10 Input Differential
Impedance 10 MHz 10 K
VIDA10 Input Differential
Accept Peak Voltage 5 MHz f 10 MHz ±585 ±440 ±3100 mV
VIDR10 Input Differential
Reject Peak Voltage 5 MHz f 10 MHz 0 ±440 ±300 mV
VICM10 Input Common Mode
Voltage VCC/2 V
VOD10 Output Differential
Peak Voltage RL = 100 2.2 2.8 V
ICCT10 Line Driver Supply
Peak Current RBIAS10 = 619 20 mA 1, 2, 3
Table 52. Digita l I/O Characteristics
Symbol Parameter Min Typical Max Units Notes
VIH Output High Voltage 2.0 Vcc+0.5 V
VIL Output Low Voltage -0.5 0.8 V
Table 53. Crystal Input One (X1) Characteristics
Symbol Parameter Min Typical Max Units Notes
VIH Input High Voltage 2.0 Vcc+0.5 V
VIL Input Low Voltage -0.5 0.8 V
82551IT — Networking Silicon
80 Datasheet
11.3 AC Specifications
NOTES:
1. Switching Current High specifications are not relevant to PME#, SERR#, or INTA#, which are open drain
outputs.
2. Maximum current requirements will be met as drivers pull beyond the first step voltage (AC drive point).
Equations defining these maximums (A and B) are provided. To facilitate component testing, a maximum
current test point is defined for each side of the output driver.
3. Do not test. Guaranteed by design.
Table 54. AC Specifications for PCI Signaling
Symbol Parameter Condition Min Max Units Notes
IOH(AC)
Switching
Current High
0 < VOUT 1.4 -44 mA 1
1.4 < VOUT < 0.9VCC -17.1(VCC - VOUT)mA1
0.7VCC < VOUT < VCC Eqn A mA 2
(Test Point) VOUT = 0.7VCC -32VCC mA 2
IOL(AC)
Switching
Current Low
VOUT 2.2 95 mA 1
2.2 > VOUT > 0.1VCC VOUT/0.023 mA 1
0.18VCC > VOUT > 0 Eqn B mA 2
(Test Point) VOUT = 0.18VCC 38VCC mA 2
ICL Low Clamp
Current -3 < VIN -1 -25 + (VIN + 1)/0.015 mA 3
ICH High Clamp
Current VCC + 4 > VIN VCC + 1 25 + (VIN - VCC -1)/
0.015 mA
slewRP PCI Output Rise
Slew Rate 0.4 V to 2.4 V 1 4 V/ns
slewFP PCI Output Fall
Slew Rate 2.4 V to 0.4 V 1 4 V/ns
Equation A. IOH = (98/VCC)*(Vout - VCC)*(Vout + 0.4VCC), for VCC > Vout > 0.7VCC
Equation B. IOL = (256/VCC)*(Vout)*(VCC - Vout), for 0 < Vout < 0.18VCC
Networking Silicon — 82551IT
Datasheet 81
11.4 Timing Specifications
11.4.1 Clocks Specifications
11.4.1.1 PCI Clock Specifications
The 82551IT uses the PCI Clock signal directly. Figure 20 shows the clock waveform and required
measurement points for the PCI Clock signal. Table 55 summarizes the PCI Clock specifications.
NOTES:
1. The 82551IT will work with any PCI clock frequency up to 33 MHz.
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate is met across the
minimum peak-to-peak portion of the clock waveform as shown in Figure 20.
11.4.1.2 X1 Specifications
X1 serves as a signal input from an external crystal or oscillator. Table 56 defines the 82551IT
requirements from this signal.
Figure 20. PCI Clock Waveform
0.6VCC
0.475VCC
0.4VCC
0.325VCC
0.2VCC
0.4VCC p-to-p
(minimum)
T_high T_low
T_cyc
Table 55. PCI Clock Specifications
Symbol Parameter Min Max Units Notes
T1 Tcyc CLK Cycle Time 30 ns 1
T2 Thigh CLK High Time 11 ns
T3 Tlow CLK Low Time 11 ns
T4 Tslew CLK Slew Rate 1 4 V/ns 2
Table 56. X1 Clock Specific ations
Symbol Parameter Min Typical Max Units Notes
T8 Tx1_dc X1 Duty Cycle 40% 60%
T9 Tx1_pr X1 Period 40 ns ±30 ppm
82551IT — Networking Silicon
82 Datasheet
11.4.2 Timing Parameters
11.4.2.1 Measurement and Test Conditions
Figure 21, Figure 22, and Table 57 define the cond iti ons under which timing measurements are
done. The component test guarantees that all timing s are met with minimum clock slew rate
(slowest edge) and voltage swing. The design must guarantee that minimum timings are also met
with maximum clock slew rate (fastest edge) and voltage swing. In addit ion, the desig n must
guarantee proper input operation for input voltage swings and slew rates that exceed the specified
test conditions.
Figure 21. Output Timing Measurement Conditions
T_off
T_on
T_val
V_step
V_test V_test
V_test
V_th
V_tl
CLK
OUTPUT
DELAY
Tri-State
OUTPUT
Figure 22. Input Timing Measurement Conditions
CLK
INPUT
V_test V_test
V_test
V_th
V_tl
V_th
V_tl
T_h
T_su
inputs
valid V_max
Table 57. Measure and Test Condition Parameters
Symbol PCI Level Units Notes
Vth 0.6VCC V
Vtl 0.2VCC V
Networking Silicon — 82551IT
Datasheet 83
NOTE: Input test is done with 0.1VCC overdrive. Vmax specifies the maximum peak-to-peak waveform allowed
for testing input timing.
11.4.2.2 PCI Timings
NOTES:
1. Timing measurement conditions are illustrated in Figure 21.
2. PCI minimum times are specified with loads as detailed in the PCI Bus Specification, Revision 2.1, Section
4.2.3.2.
3. n a PCI environment, REQ# and GNT# are point-to-point signals and have different output valid delay times
and input setup times than bussed signals. All other signals are bussed.
4. Timing measurement conditions are illustrated in Figure 22.
5. RST# is asserted and de-asserted asynchronously with respect to the CLK signal.
6. All PCI interface output drivers are floated when RST# is active.
11.4.2.3 Flash Interface Timings
The 82551IT is designed to support up to 150 ns of Flash access time. The VPP signal in the Flash
implementation should be conn ected permanently to 12 V. Thus, writing to the Flash is controlled
only by the FLWE# pin.
Table 59 provides the timing parameters for the Flash interface signals. The timing parameters are
illustrated in Figure 23 and Figure 24.
Vtest 0.4VCC V
Vstep (rising edge) 0.285VCC V Min Delay
VMax Delay
Vstep (falling edge) 0.615VCC V Min Delay
VMax Delay
Vmax 0.4VCC V
Input Signal Edge
Rate 1V/ns
Table 57. Measure and Test Condition Parameters
Table 58. PCI Timing Parameters
Symbol Parameter Min Max Units Notes
T14 tval PCI CLK to Signal Valid Delay 2 11 ns 1, 2, 3
T15 tval(ptp) PCI CLK to Signal Valid Delay (point-
to-point) 2 12 ns 1, 2, 3
T16 ton Float to Active Delay 2 ns 1
T17 toff Active to Float Delay 28 ns 1
T18 tsu Input Setup Time to CLK 7 ns 3, 4
T19 tsu(ptp) PCI Input Setup Time to CLK (point-to-
point) 10 ns 3, 4
T20 thInput Hold Time from CLK 0 ns 5
T21 trst Reset Active Time After Power Stable 1 ms 5
T22 Trst-clk PCI Reset Active Time After CLK
Stable 100 clocks 5
T23 Trst-off Reset Active to Output Float Delay 40 ns 5, 6
82551IT — Networking Silicon
84 Datasheet
NOTES:
1. These timing specifications apply to Flash read cycles. The Flash timings referenced are 28F020-150
timings.
2. These timing specifications apply to Flash write cycles. The Flash timings referenced are 28F020-150
timings.
Table 59. Flash Timing Parameters
Symbol Parameter Min Max Units Notes
T35 tflrwc Flash Read/Write Cycle Time 150 ns 1, Flash tAVAV
= 150 ns
T36 tflacc FLA to Read FLD Setup Time 150 ns 1, Flash tAVQV
= 150 ns
T37 tflce FLCS# to Read FLD Setup Time 150 ns 1, Flash tELQV
= 150 ns
T38 tfloe FLOE# Active to Read FLD Setup Time 120 ns 1, Flash tGLQV
= 55 ns
T39 tfldf FLOE# Inactive to FLD Driven Delay
Time 50 ns 1, Flash tGHQZ
= 35 ns
T40 tflas FLA Setup Time before FLWE# 5 ns 2, Flash tAVWL
= 0 ns
T41 tflah FLA Hold Time after FLWE# 200 ns 2, Flash tWLAX
= 60 ns
T42 tflcs FLCS# Hold Time before FLWE# 30 ns 2, Flash tELWL
= 20 ns
T43 tflch FLCS# Hold Time after FLWE# 30 ns 2, Flash tWHEH
= 0 ns
T44 tflds FLD Setup Time 150 ns 2, Flash tDVWH
= 50 ns
T45 tfldh FLD Hold Time 10 ns 2, Flash tWHDX
= 10 ns
T46 tflwp Write Pulse Width 120 ns 2, Flash tWLWH
= 60 ns
T47 tflwph Write Pulse Width High 25 ns 2, Flash tWHWL
= 20 ns
T48 tMioha IOCHRDY Hold Time after FLWE# or
FLOE# Active 25 ns
T49 tMiohi IOCHRDY Hold Time after FLWE# or
FLOE# Inactive 0ns
Networking Silicon — 82551IT
Datasheet 85
Figure 23. Flash Timings for a Read Cycle
FLADDR
FLCS#
FLOE#
FLDATA-R
IOCHRDY
Address Stable
Data In
T35
T37
T38 T39
T48T49
T36
Figure 24. Flash Timings for a Write Cycle
FLADDR
FLCS#
FLWE#
FLDATA-W
IOCHRDY
Address Stable
Data Out
T35
T40 T41
T42 T46 T43
T47 T44 T45
T48T49
82551IT — Networking Silicon
86 Datasheet
11.4.2.4 EEPROM Interface Timings
The 82551IT is designed to support a standard64x16 or 256x16 serial EEPROM. T able 60 provides
the timing parameters for the EEPROM interface signals. The timing parameters are shown in
Figure 25.
Table 60. EEPROM Timing Parameters
Symbol Parameter Min Max Units Notes
T51 tECSS Delay from EECS High to EESK High 300 ns EEPROM tcss
= 50 ns
T52 tECSH Delay from EESK Low to EECS Low 30 ns EEPROM tcsh
= 0 ns
T53 tEDIS Setup Time of EEDI to EESK 300 ns EEPROM tdis
= 150 ns
T54 tEDIH Hold Time of EEDI after EESK 300 ns EEPROM tdih
= 150 ms
T55 tECS EECS Low Time 750 ns EEPROM tcs =
250 ns
Figure 25. EEPROM Timings
EECS
FLA15EESK
FLA13EEDI
T51 T52
T54T53
Networking Silicon — 82551IT
Datasheet 87
11.4.2.5 PHY Timings
Table 61. 10BASE-T Normal Link Pulse (NLP) Timing Parameters
Symbol Parameter Condition Min Typ Max Units
T56 Tnlp_wid NLP Width 10 Mbps 100 ns
T57 Tnlp_per NLP Period 10 Mbps 8 24 ms
Figure 26. 10BASE-T Normal Link Pulse (NLP) Timings
Normal Link Pulse
T57
T56
Table 62. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
Symbol Parameter Min Typ Max Units
T58 Tflp_wid FLP Width (clock/data) 100 ns
T59 Tflp_clk_clk Clock Pulse to Clock Pulse Period 111 125 139 µs
T60 Tflp_clk_dat Clock Pulse to Data Pulse Period 55.5 62.5 69.5 µs
T61 Tflp_bur_num Number of Pulses in one burst 17 33
T62 Tflp_bur_wid FLP Burst Width 2 ms
T63 Tflp_bur_per FLP Burst Period 8 24 ms
Figure 27. Auto-Negotiat ion Fast Link Pulse (FLP) Timings
Fast Link Pulse
T60
T58
T59
Clock Pulse Data Pulse Clock Pulse
FLP Bursts T62 T63
82551IT — Networking Silicon
88 Datasheet
Table 63. 100Base-TX Transmitter AC Specification
Symbol Parameter Condition Min Typ Max Units
T64 Tjit TDP/TDN Differential
Output Peak Jitter HLS Data 1400 ps
Networking Silicon — 82551IT
Datasheet 89
12.0 Package and Pinout Information
12.1 Package Information
The 82551IT is a 196-pin Ball Grid Array (BGA) package. Package dimensions are shown in
Figure 28. More information on In tel® device packaging is available in the Intel Packaging
Handbook.
Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change.
Figure 28. Dimension Diagram for the 196-pin BGA
Substrate change from
0.36 mm to 0.32 mm
0.32 +/-0.04
Note: All dimensions are in millimeters.
0.40 +/-0.10 Seating Plate
0.85
1.56 +/-0.19
30
o
82551IT — Networking Silicon
90 Datasheet
Figure 29. 196 PBGA Package Pad Detail
As illustrated in Figure 29, the 82551IT package uses solder mask defined pads. The copper area is
0.60 mm and the opening in the solder mask is 0.45 mm. The nominal ball sphere diameter is 0.50
mm.
0.45
Solder Resist Opening
0.60
Metal Diameter
Detail Area
Networking Silicon — 82551IT
Datasheet 91
12.2 Pinout Information
12.2.1 Pin Assignments
Table 62. Pin Assignments
Pin Name Pin Name Pin Name
A1 NC A2 SERR# A3 VCC
A4 IDSEL A5 AD[25] A6 PME#
A7 VCC A8 AD[30] A9 ALTRST#
A10 NC A11 VCC A12 LILED#
A13 TEST A14 NC
B1 AD[22] B2 AD[23] B3 VSSPP
B4 AD[24] B5 AD[26] B6 AD[27]
B7 VSSPP B8 AD[31] B9 ISOLATE#
B10 NC B11 SPDLED# B12 TO
B13 RBIAS100 B14 RBIAS10
C1 AD[21] C2 RST# C3 REQ#
C4 C/BE#[3] C5 NC C6 AD[28]
C7 AD[29] C8 CLK_RUN# C9 NC
C10 VSSPT C11 ACTLED# C12 VREF
C13 TDP C14 TDN
D1 AD[18] D2 AD[19] D3 AD[20]
D4 VSS D5 VSS D6 VSS
D7 VSS D8 VSS D9 NC
D10 NC D11 NC D12 TI
D13 TEXEC D14 TCK
E1 VCC E2 VSSPP E3 AD[17]
E4 VSS E5 VSS E6 VSS
E7 VSS E8 VSS E9 VSS
E10 VSS E11 NC E12 VCC
E13 RDP E14 RDN
F1 IRDY# F2 FRAME# F3 C/BE#[2]
F4 VSS F5 VSS F6 VSS
F7 VSS F8 VSS F9 VSS
F10 VSS F11 VSS F12 FLD2
F13 FLD1 F14 FLD0
G1 CLK G2 VIO G3 TRDY#
G4 NC G5 VCC G6 VCC
G7 VSS G8 VSS G9 VSS
G10 VSS G11 VSS G12 FLD3
82551IT — Networking Silicon
92 Datasheet
G13 VCC G14 VSSPL
H1 STOP# H2 INTA# H3 DEVSEL#
H4 NC H5 VCC H6 VCC
H7 VCC H8 VCC H9 VSS
H10 VSS H11 NC H12 FLD6
H13FLD5H14FLD4
J1 PAR J2 PERR# J3 GNT#
J4 NC J5 VCC J6 VCC
J7 VCC J8 VCC J9 VCC
J10 VCCR J11 VCCR J12 FLA1
J13FLA0J14FLD7
K1 AD[16] K2 VSSPP K3 VCC
K4 VCC K5 VCC K6 VCC
K7 VCC K8 VCC K9 VCC
K10 VCC K11 VCC K12 VSSPL
K13 VCC K14 FLA2
L1 AD[14] L2 AD[15] L3 C/BE#[1]
L4 VCC L5 VCC L6 VSS
L7 NC L8 NC L9 VCC
L10 VCC L11 VSS L12 FLA5
L13 FLA4 L14 FLA3
M1 AD[11] M2 AD[12] M3 AD[13]
M4 C/BE#[0] M5 AD[5] M6 VSSPP
M7 AD[1] M8 FLOE# M9 FLWE#
M10 FLA15/EESK M11 FLA12 M12 FLA11
M13FLA7M14FLA6
N1 VSSPP N2 AD[10] N3 AD[9]
N4 AD[7] N5 AD[4] N6 VCC
N7 AD[0] N8 VCC N9 FLCS#
N10 FLA14/EEDO N11 X1 N12 VSSPL
N13 FLA10 N14 FLA8/IOCHRDY
P1 NC P2 VCC P3 AD[8]
P4 AD[6] P5 AD[3] P6 AD[2]
P7 EECS P8 VSSPL P9 FLA16
P10 FLA13/EEDI P11 X2 P12 VCC
P13FLA9P14 NC
Table 62. Pin Assignments
Pin Name Pin Name Pin Name
Networking Silicon — 82551IT
Datasheet 93
12.2.2 Ball Grid Array Diagram
Figure 30. Ball Grid Array Diagram
AD[22] AD[21] AD[18] VCC IRDY# CLK STOP# PAR NCVSSPPAD[11]AD[14]AD[16]NC
AD[23] RST# AD[19] VSSPP FRAME# VIO INTA# PERR# VCCAD[10]AD[12]AD[15]VSSPPSERR#
VSSPP REQ# AD[20] AD[17] C/BE#[2] TRDY# DVSEL# GNT# AD[8]AD[9]AD[13]C/B3#[1]VCCVCC
AD[24] C/BE#[3] VSS VSS VSS NC NC NC AD[6]AD[7]
C/BE#[0]
VCCVCCIDSEL
AD[26] NC VSS VSS VSS VCC VCC VCC AD[3]AD[4]AD[5]VCCVCCAD[25]
AD[27] AD[28] VSS VSS VSS VCC VCC VCC AD[2]VCCVSSPPVSSVCCPME#
VSSPP AD[29] VSS VSS VSS VSS VCC VCC EECSAD[0]AD[1]
NC
VCCVCC
AD[31] CLK_
RUN# VSS VSS VSS VSS VCC VCC VSSPLVCCFLOE#NCVCCAD[30]
ISOLATE#
NC VSS VSS VSS VSS VCC FLA16FLCS#FLWE#VCCVCC
ALTRST#
VSSPT NC VSS VSS VSS VSS VCCR FLA13/
EEDI
FLA14/
EEDO
FLA15/
EESK
VCCVCC
SPDLED# ACTLED# NC NC VSS VSS NC VCCR X2X1FLA12VSSVCCVCC
TO VREF TI VCC FLD2 FLD3 FLD6 FLA1 VCCVSSPLFLA11FLA5VSSPLLILED#
RBIAS
100 TDP TEXEC RDP FLD1 VCC FLD5 FLA0 FLA9FLA10FLA7FLA4VCCTEST
RBIAS
10 TDN TCK RDN FLD0 VSSPL FLD4 FLD7 NC
FLA8
FLA6FLA3FLA2NC
ABCDE FGHJ K LMNP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC NC
NC
82551IT — Networking Silicon
94 Datasheet
13.0 Reference Schematics
This section shows a 10/100 Mbps design using the 82551 IT Fast Ethernet PCI Controller.
Networking Silicon — 82551IT
Datasheet 95
Figure 31. Reference Schematic Layout (Sheet 1 of 2)
82551IT
B
SV3
0
33
12
DEL
1
2
0
3
3
12
DEL
12
DELIL
D
ELT
CA
DE
LDEEPS
The 82551IT can drive three
LEDs with the cathode of
each device connected to
the 82551IT as shown with
the SPEEDLED or a two LED
configuration can be used,
as shown. In the two LED
configuration the link and the
activity functions share an
indicator. In this scheme the
LINK LED would flash LOW
each time activity is detected.
RDP
TDP
TDN
RDN
E13
A12
C11
B11
C13
C14
E14
8-22 pF
pF
uF
0.1 uF 0.1 uF
0.1 uF
Termplane
Use plane for
this signal to
make a board
capacitor.
Termplane
CGND = Chassis ground
Use plane for this signal
BSV3
Fu1.0
12
F
u1.0
12
Fu1.0
12
Fu1.0
12
Fu1.
0
12
F
u1
.
0
12
Fu1.0
12
Fu1.0
12
Fu1.0
12
12
Fu
7
.
4
12
Fu7.4
12
Fu1.0
Place decoupling capacitors as close to the 82551 as possible. If component placements
are used on the bottom side of the board, then place decoupling under the 82551IT.
Create termination plane in PCB. This plane
acts as a path for low-frequency noise that
might be coupled to unused pins. The plane
should not have any direct connection.
Optional capacitor
to help with EFT
conformance.
Keep trace length from magnetics to RJ-45 connector under one inch.
Keep all termination resistors as
close to the 82551 as possible.
This capacitor is normally not installed; however a placement can be provided.
It might need to be placed based on the results of FCC conformance testing. If it
is required, values in the pico fared range can be used. Large capacitance values
installed in this location can have a negative effect on long cable performance. So care
must be taken in selecting the values used.
RECEIVE
RECEIVE
TRANSMIT
TRANSMIT
MDI Mode Only
MDI-X Mode Only
RD+ 1
RD- 2
RDC
RX+
RX-
CT
3
7
6
11
10
15
16
5
TDC 14
TD+ 16
TD- 15
10 TX+
TXCT
1:1
75 Ohms
1500pF
2kV
11 TX- TD-
TD+
TX-
1:1 TX+
7
6
1
2
RD+
RD-
RX+
1:1 RX-
82551IT — Networking Silicon
96 Datasheet
Figure 32. Reference Schematic Layout (Sheet 2 of 2)
82551IT
SCE
E
KSEE
IDEE
O
D
EE
B
SV3
BS
V
3
K3
.3
12
64C3
9
1
2
3
4
8
S
C
K
S
I
D
OD
VCC
9P
0
1M
01N
01P
11M
2
1
M
31N
31
P
41N
31M
4
1
M
2
1
L
3
1L
4
1L
41K
21J
31J
41J
2
1H
31H
4
1
F
31F
2
1
F
21G
4
1H
7P
9
N
61A
L
F
K
SEE/5
1
ALF
O
D
E
E
/
41
A
LF
ID
EE
/
3
1ALF
21A
1
1
ALF
0
1ALF
9A
L
F
YDRHCOI/8
A
L
7
AL
F
6
A
LF
5ALF
4ALF
3A
LF
2AL
F
R
WP
X
U
A/1
A
L
F
0
7DL
F
6
DLF
5
D
LF
0DLF
1D
L
F
2DLF
3
D
L
F
4DL
F
S
C
EE
#SCLF
L
F
F
A
L
F
zHM52
12
1
12
12
12
Fp
12
Fp
12
11
N
11P
9N
8
M
9M
31A
31D
4
1D
21D
4
1
B
3
1B
21C
21B
1X
2X
#SCLF
#EOLF
#EWLF
TSE
T
CEXET
KCT
IT
01SAIBR
0
0
1S
AI
B
R
FERV
OT
VREF: External VREF can be applied here if the internal reference
is not used. The internal reference is recommended, but if an
external reference is implemented, then this will cause the RBIAS
values to change.
91
6
649
2222
RBIAS10 and RBIAS100
should be tuned for your
specific application. The
values shown are a
good starting value.
K ohm
Pulldown resistors are used
on strapped pins to enable
the NAND tree test mode to
work. The value of 1 K ohm
was chosen strictly on the basis
of Intel’s test fixturing requirements
Other values can be used, but it is
recommended that resistors be used
other than hard strapping the pins.
All Vss pins are connected together on the PCB
level. The power on the symbol is broken down
between core power (Vss), local bus power (Vsspl),
transmit power (Vsst), and PCI power (Vsspp) just
for clarity.
TO PCI BUS
#
R
RE
S
1
E
B
/
C
#
E
TA
L
O
SI
L
ES
D
I
2
E
B
/
C
#
N
U
R
K
L
C
#
E
M
P
D
O
OG
_
X
UA
A
T
N
I
#
T
S
R
K
L
C
#
T
NG
#
R
R
EP
3
E
B
/C
0
E
B
/
C
#QE
R
]
0
:
3
[
E
B
/
C
26
12
4
M
3
L
3F
4
C
2
F
1
F
3
G
3
H
1
H
1
J
2
H
2
J
2A
4
A
3C
3
J
2C
1
G
9B
9
A
0
1
A
9
C
01B
5
C
6A
8
C
#0
E
B
/
C
#1
E
B
/
C
#
2
EB/
C
#
3
E
B/C
#EMARF
#
Y
D
RI
#YDR
T
#
LES
V
E
D
#POT
S
R
A
P
#
ATNI
#
RR
EP
#R
RE
S
L
E
SD
I
#
QE
R
#
T
NG
#TSR
K
L
C
#
E
TAL
OSI
#S
R
T
L
A
#
EM
P
#
N
U
R
K
LC
#
E
M
ARF
#Y
D
RI
#
Y
D
RT
#L
E
SV
E
D
#P
O
T
S
R
A
P
K ohm
#
E
M
P
To PIIX4
T
The ISOLATE signal should be a signal that
is driven low just prior to the PCI bus shutting
down and it should be driven high immediately
following the PCI bus re-activation.
7
2D
A
81D
A
6
2D
A
3
2D
A
22D
A
12
D
A
01DA
4DA
21DA
0
DA
92DA
91
DA
7
1
DA
1
3DA
7
D
A
3
1DA
6DA
1DA
8
2DA
52
D
A
42DA
3DA
0
3DA
0
2D
A
6
1
DA
5
1
DA
41D
A
5DA
2DA
1
1
DA
9
DA
8
DA
]0:13[
D
A
7
N
7M
6
P
5
P
5N
5M
4
P
4N
3P
3
N
2N
1
M
2M
3
M
1L
2L
1
K
3
E
1
D
2
D
3
D
1C
1
B
2
B
4
B
5A
5B
6B
6C
7C
8A
8B
0DA
1
D
A
2
D
A
3DA
4
D
A
5D
A
6DA
7D
A
8
DA
9D
A
01D
A
11DA
21D
A
31
DA
41
DA
5
1
DA
6
1
DA
71
DA
8
1
DA
9
1D
A
02DA
1
2D
A
2
2
DA
32
D
A
42DA
52D
A
62
D
A
72
D
A
82
D
A
92D
A
03DA
13DA
V
5_ICP
F
u
1
.0
12
100
12
2
GOIV
K ohm
1) The decoupling
capacitor should be
added to the VIO pin.
2) The voltage on VIO determines the slope of the signals on the bus. Although the device
communicates if VIO is connected to 3.3V in 3.3V PCI systems, optimal performance is
acheived if this signal is connected to +5V in PCI bus systems regardless of bus voltage.
All Vcc pins are connected together on the PCB
level. The power on the symbol is broken down
between core power (Vcc), local bus power (Vccpl),
transmit power (Vcct), and PCI power (Vccpp) just
for clarity.
