DATASHEET
Low Voltage 1:5 Differential LVDS
Clock Fanout Buffer
MC100ES8014
MC100ES8014 REVISION A FEBRUARY 6, 2013 769 ©2013 Integrated Device Technology, Inc.
Product Discontinuance Notice – Last Time Buy Expires on (1/31/2014)
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The MC100ES8014 is a HSTL differential clock fanout buffer. Designed for
the most demanding clock distribution systems, the MC100ES8014 supports
various applications that require the distribution of precisely aligned differential
clock signals. Using SiGe technology and a fully differential architecture, the
device offers very low skew outputs and superior digital signal characteristics.
Target applications for this clock driver are in high performance clock
distribution in computing, networking and telecommunication systems.
The MC100ES8014 is designed for low skew clock distribution systems and
supports clock frequencies up to 400MHz. The device accepts two clock
sources. The CLK0 input accepts HSTL compatible signals and CLK1 accepts
PECL compatible signals. The selected input signal is distributed to 5 identical,
differential HSTL compatible outputs.
Features
• 1:5 differential clock fanout buffer
• 50 ps maximum device skew
• SiGe Technology
• Supports DC to 400 MHz operation
• 1.5V HSTL compatible differential clock outputs
• PECL and HSTL compatible differential clock inputs
• 3.3V power supply for device core, 1.5V or 1.8V HSTL output supply
• Supports industrial temperature range
• Standard 20 lead TSSOP package
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
MC100ES8014
1:5 DIFFERENTIAL HSTL
CLOCK FANOUT DRIVER
ORDERING INFORMATION
Device Package
MC100ES8014DT TSSOP-20
MC100ES8014DTR2 TSSOP-20
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-02
VCCO NC VEE CLK1 CLK1 EN CLK0 CLK0 CLK_SEL VCC
20 19 18 17 16 15 14 13 12 11
10
1 2 345678 910
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4
D
Q
MC100ES8014 REVISION A FEBRUARY 6, 2013 770 ©2013 Integrated Device Technology, Inc.
MC100ES8014 Data Sheet LOW VOLTAGE 1:5 DIFFERENTIAL LVDS CLOCK FANOUT BUFFER
Table 1. Pin Description
Pin Function
CLK0, CLK0 HSTL Data Inputs
CLK1, CLK1 PECL Data Inputs
Q[0:4], Q[0:4] HSTL Data Outputs
CLK_SEL LVCMOS Active Clock Select Input
EN LVCMOS Sync Enable
VCC Positive Supply of device core (3.3V)
VCCO Positive power supply of the HSTL outputs. All VCCO pins must be connected to the positive
power supply (1.5V or 1.8V) for correct DC and AC operation.
VEE Negative Supply
nc no connect
Table 2. Function Table
Control Default 0 1
CLK_SEL 0 CLK0, CLK0 (HSTL) is the active differential clock
input
CLK1, CLK1 (PECL) is the active differential clock
input
EN 0 Q[0:4], Q[0:4] are active. Deassertion of EN can be
asynchronous to the reference clock without
generation of output runt pulses.
Q[0:4] = L, Q[0:4] = H (outputs disabled). Assertion of
EN can be asynchronous to the reference clock
without generation of output runt pulses.
Table 3. General Specifications
Characteristics Value
Internal Input Pulldown Resistor TBD
Internal Input Pullup Resistor TBD
ESD Protection Human Body Model
Machine Model
TBD
JA Thermal Resistance (Junction to Ambient) 0 LFPM, 8 SOIC
500 LFPM, 8 SOIC
TBD
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Table 4. Absolute Maximum Ratings1
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Symbol Parameter Conditions Rating Unit
VSUPPLY Power Supply Voltage Difference between VCC & VEE 3.9 V
VIN Input Voltage VCC – VEE 3.6V VCC + 0.3
VEE – 0.3
V
V
IOUT Output Current Continuous
Surge
50
100
mA
mA
TAOperating Temperature Range –40 to +85 °C
TSTG Storage Temperature Range –65 to +150 °C
MC100ES8014 REVISION A FEBRUARY 6, 2013 771 ©2013 Integrated Device Technology, Inc.
MC100ES8014 Data Sheet LOW VOLTAGE 1:5 DIFFERENTIAL LVDS CLOCK FANOUT BUFFER
Table 5. DC Characteristics (VCC = 3.3 V ± 5%; TJ = 0°C to 110°C)1
1. DC characteristics are design targets and pending characterization.
Symbol Characteristic Min Typ Max Unit Condition
HSTL differential input signals (CLK0, CLK0)
VDIF Differential Input Voltage2
2. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality.
0.2 V
VX, IN Differential Cross Point Voltage3
3. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range
and the input swing lies within the VPP (DC) specification.
0.25 0.68 – 0.9 VCC – 1.3 V
VIH Input High Voltage VX + 0.1 V
VIL Input Low Voltage VX – 0.1 V
IIN Input Current ±150 mA VIN = VX ± 0.1V
PECL differential input signals (CLK1, CLK1)
VPP Differential Input Voltage4
4. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
0.15 1.0 V Differential Operation
VCMR Differential Cross Point Voltage5
5. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range
and the input swing lies within the VPP (DC) specification.
1.0 VCC – 0.6 V Differential Operation
VIH Input High Voltage VCC – 1.165 VCC – 0.880 V
VIL Input Low Voltage VCC – 1.810 VCC – 1.475 V
IIN Input Current ±150 mA VIN = VIH or VIN
LVCMOS control inputs EN, CLK_SEL
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
IIN Input Current ±150 mA VIN = VIH or VIN
HSTL clock outputs (Q[0:4], Q[0:4])
VX, OUT Output Differential Crosspoint 0.68 0.75 0.9 V
VOH Output High Voltage 1 V
VOL Ouput Low Voltage 0.4 V
Supply Current
ICC Maximum Quiescent Supply Current without
output termination current
TBD TBD mA VCC pin (core)
ICCO Maximum Quiescent Supply Current, outputs
terminated 50 to VTT
TBD TBD mA VCCO pin (outputs)
MC100ES8014 REVISION A FEBRUARY 6, 2013 772 ©2013 Integrated Device Technology, Inc.
MC100ES8014 Data Sheet LOW VOLTAGE 1:5 DIFFERENTIAL LVDS CLOCK FANOUT BUFFER
Table 6. AC Characteristics (VCC = 3.3 V ± 5%; TJ = 0°C to 110°C)1 2
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50to VTT.
Symbol Characteristic Min Typ Max Unit Condition
HSTL/LVDS differential input signals (CLK0, CLK0)
VDIF Differential Input Voltage (peak-to-peak)3
3. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.
0.4 V
VX, IN Differential Cross Point Voltage4
4. VX (AC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (AC) range
and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF(AC) impacts the device propagation delay, device and
part-to-part skew.
0.68 0.9 V
fCLK Input Frequency 0 – 400 TBD MHz Differential
tPD Propagation Delay TBD ps Differential
PECL differential input signals (CLK1, CLK1)
VPP Differential Input Voltage (peak-to-peak)5
5. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.
0.2 1.0 V
VCMR Differential Cross Point Voltage6
6. VCMR (AC) is the crosspoint of the differential PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC)
range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP(AC) impacts the device propagation delay, device
and part-to-part skew.
1V
CC – 0.6 V
fCLK Input Frequency 0 – 400 MHz Differential
tPD Propagation Delay TBD ps Differential
HSTL clock outputs (Q[0:4], Q[0:4])
VX, OUT Output Differential Crosspoint 0.68 0.75 0.9 V
VOH Output High Voltage 1 V
VOL Ouput Low Voltage 0.5 V
VO(P-P) Differential Output Voltage (peak-to-peak) 0.5 V
tSK(O) Output-to-Output Skew 50 ps Differential
tSK(PP) Output-to-Output Skew (part-to-part) TBD ps Differential
tJIT(CC) Output Cycle-to-Cycle Jitter TBD
DCOOutput Duty Cycle TBD 50 TBD % DCfref = 50%
tr / tfOutput Rise/Fall Times 0.05 TBD ns 20% to 80%
tPDL Output Disable Time7
7. Propagation delay EN deassertion to differential output disabled (differential low: true output low, complementary output high).
2.5*T +tPD 3.5*T +tPD ns T = CLK period
tPLD Output Enable Time8
8. Propagation delay EN assertion to output enabled (active).
3*T +tPD 4*T +tPD ns T = CLK period
MC100ES8014 REVISION A FEBRUARY 6, 2013 773 ©2013 Integrated Device Technology, Inc.
MC100ES8014 Data Sheet LOW VOLTAGE 1:5 DIFFERENTIAL LVDS CLOCK FANOUT BUFFER
Figure 2. MC100ES8014 AC Test Reference
CLKx
tPDL (EN to Qx[])
50%
tPLD (EN to Qx[])
CLKx
EN
Qx[]
Qx[] Outputs disabled
Figure 3. MC100ES8014 AC Test Reference
Differential Pulse
Generator
Z = 50
RT = 50
ZO = 50
DUT
MC100ES8014
VTT=GND
RT = 50
ZO = 50
VTT=GND
Figure 4. MC100ES8014 AC Reference
Measurement Waveform (HSTL Input)
CLK0,1
tPD (CLK0,1 to Q[0–4])
VX=0.75V
VDIF=1.0V
CLK0,1
Q[0–4]
Q[0–4]
tPD (CLK0,1 to Q[0–4])
VCMR=VCC–1.3V
VPP=0.8V
CLK0,1
CLK0,1
Q[0–4]
Q[0–4]
Figure 5. MC100ES8014 AC Reference
Measurement Waveform (PECL Input)
MC100ES8014 REVISION A FEBRUARY 6, 2013 774 ©2013 Integrated Device Technology, Inc.
MC100ES8014 Data Sheet LOW VOLTAGE 1:5 DIFFERENTIAL LVDS CLOCK FANOUT BUFFER
Revision History Sheet
Rev Table Page Description of Change Date
5 1 Product Discontinuance Notice – Last Time Buy Expires on (12/19/2013) 2/5/2013
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MC100ES8014 Data Sheet LOW VOLTAGE 1:5 DIFFERENTIAL LVDS CLOCK FANOUT BUFFER