FAN4822IM - Fairchild Semiconductor

www.fairchildsemi.com

REV. 1.0.1 8/10/01

Features

• Average current sensing, continuous boost, leading edge

PFC for low total harmonic distortion and near unity

power factor

• Built-in ZVS switch control with fast response for high

efﬁciency at high power levels

• Average line v oltage compensation with bro wnout control

• Current fed gain modulator improv es noise immunity and

provides universal input operation

• Overv oltage comparator eliminates output “runaw ay” due

to load removal

• UVLO, current limit, and soft-start

• Precision 1.3% reference

General Description

The FAN4822 is a PFC controller designed speciﬁcally for

high power applications. The controller contains all of the

functions necessary to implement an average current boost

PFC converter, along with a Zero Voltage Switch (ZVS) con-

troller to reduce diode recovery and MOSFET turn-on

losses.

The average current boost PFC circuit provides high power

factor (>98%) and low Total Harmonic Distortion (THD).

Built-in safety features include undervoltage lockout, over-

voltage protection, peak current limiting, and input voltage

brownout protection.

The ZVS control section drives an external ZVS MOSFET

which, combined with a diode and inductor , soft switches the

boost regulator. This technique reduces diode reverse recov-

ery and MOSFET switching losses to reduce EMI and maxi-

mize efﬁciency.

Block Diagram

–

VEAO

VEA

2.5V

4IAC

5VRMS

–

3ISENSE

8GND 2IEAO

–

IEA

R+

R–+

–

––

6RTCTOSC

GAIN

MODULATOR S

–

2.7V

–1V

VCC

VCCZ

13.5V

ZVS OUT

PFC OUT

PWR GND

OVP

I LIMIT

REF

ZV SENSE

VCCZ

REF

FAN4822

ZVS A verage Current PFC Contr oller

FAN4822 PRODUCT SPECIFICATION

REV. 1.0.1 8/10/01

Pin Conﬁguration

Pin Description

(Pin numbers is parentheses are for 16-pin package)

Pin Name Function

1 (1) VEAO Transconductance voltage error amplifier output.

2 (2) IEAO Transconductance current error amplifier output.

3 (3) I

SENSE

Current sense input to the PFC current limit comparator.

4 (4) I

PFC gain modulator reference input.

5 (5) V

RMS

Input for RMS line voltage compensation.

6 (6) R

Connection for oscillator frequency setting components.

7 (7) ZV SENSE Input to the high speed zero voltage crossing comparator.

8 (10) GND Analog signal ground.

9 (11) PWR GND Return for the PFC and ZVS driver outputs.

10 (12) ZVS OUT ZVS MOSFET driver output.

11 (13) PFC OUT PFC MOSFET driver output.

12 (14) V

Shunt-regulated supply voltage.

13 (15) REF Buffered output for the internal 7.5V reference.

14 (16) FB Transconductance voltage error amplifier input.

VEAO

IEAO

ISENSE

IAC

VRMS

RTCT

ZV SENSE

N/C

FAN4822

16-Pin SOIC (S16W)

FAN4822

14-Pin DIP (P14)

REF

VCC

PFC OUT

ZVS OUT

PWR GND

GND

N/C

TOP VIEW

VEAO

IEAO

ISENSE

IAC

VRMS

RTCT

ZV SENSE

REF

VCC

PFC OUT

ZVS OUT

PWR GND

GND

TOP VIEW

Absolute Maximum Ratings

Absolute maximum ratings are those values be yond which the device could be permanently damaged. Absolute maximum rat-

ings are stress ratings only and functional device operation is not implied.

Parameter Min Max Unit

Shunt Regulator Current (I

)55mA

Peak Driver Output Current ±500 mA

Analog Inputs –0.3 7 V

Junction Temperature 150 °C

Storage Temperature Range –65 150 °C

Lead Temperature (Soldering, 10 sec) 150 °C

Thermal Resistance (

)

Plastic DIP

Plastic SOIC 80

110 °C/W

°C/W

PRODUCT SPECIFICATION FAN4822

REV. 1.0.1 8/10/01

Operating Conditions

Electrical Characteristics

Unless otherwise speciﬁed, R

= 52.3k

Ω

, C

= 470pF, T

= Operating Temperature Range (Note 1)

Temperature Range Min. Max. Units

FAN4822IX –40 85 °C

Parameter Conditions Min. Typ. Max. Units

Voltage Error Amplifier

Input Voltage Range 0 7 V

Transconductance V

NON-INV

= V

INV

, VEAO = 3.75V 50 70 120

Feedback Reference Voltage V

EAO

= V

2.4 2.5 2.6 V

Open Loop Gain 60 75 dB

PSRR V

CCZ

– 3V < V

< V

CCZ

– 0.5V 60 75 dB

Output Low 0.65 1 V

Output High 6.0 6.7 V

Source Current

∆

= ±0.5V, V

OUT

= 6V –40 –80 µA

Sink Current

∆

= ±0.5V, V

OUT

= 1.5V 40 80 mA

Current Error Amplifier

Input Voltage Range –1.5 2 V

Transconductance V

NON-INV

= V

INV

, IEAO = 3.75V 130 195 310

Input Offset Voltage ±3 ±15 mV

Open Loop Gain 60 75 dB

PSRR V

CCZ

– 3V < V

< V

CCZ

– 0.5V 60 75 dB

Output Low 0.65 1 V

Output High 6.0 6.7 V

Source Current

∆

= ±0.5V, V

OUT

= 6V –30 –80

Sink Current

∆

= ±0.5V, V

OUT

= 1.5V 40 80

OVP Comparator

Threshold Voltage 2.6 2.7 2.8 V

Hysteresis 80 120 150 mV

SENSE

Comparator

Threshold Voltage –0.8 –1.0 –1.15 V

Delay to Output 150 300 ns

ZV Sense Comparator

Propagation Delay 100mV Overdrive 50 ns

Threshold Voltage 7.35 7.5 7.65 V

Input Capacitance 6 pF

Ω

FAN4822 PRODUCT SPECIFICATION

REV. 1.0.1 8/10/01

Gain Modulator

Gain (Note 2) I

IAC

= 100mA, V

VRMS

= 0V,

= 0V 0.36 0.51 0.66

IAC

= 50mA, V

VRMS

= 1.2V,

= 0V 1.20 1.72 2.24

IAC

= 100

A, V

VRMS

= 1.8V,

= 0V 0.55 0.78 1.01

IAC

= 100

A, V

VRMS

= 3.3V,

= 0V 0.14 0.20 0.26

Bandwidth I

IAC

= 250

A 10 MHz

Output Voltage V

= 0V, V

VRMS

= 1.15V, I

IAC

250

A0.72 0.8 0.9 V

Oscillator

Initial Accuracy T

= 25°C 74 80 87 kHz

Voltage Stability V

CCZ

– 3V < V

< V

CCZ

– 0.5V 1 %

Temperature Stability 2 %

Total Variation Line, temperature 72 89 kHz

Ramp Valley to Peak Voltage 2.5 V

Dead Time 100 300 450 ns

Discharge Current 4.5 7.5 9.5 mA

Reference

Output Voltage T

= 25°C, I

REF

= 1mA 7.4 7.5 7.6 V

Line Regulation V

CCZ

– 3V < V

< V

CCZ

– 0.5V 2 10 mV

Load Regulation 1mA < I

REF

, < 20mA 2 15 mV

Temperature Stability 0.4 %

Total Variation Line, load, and temperature 7.35 7.65 V

Long Term Stability T

= 125°C, 1000 hours 5 25 mV

Short Circuit Current V

< V

CCZ

– 0.5V, V

REF

= 0V –15 –40 –100 mA

PFC Comparator

Minimum Duty Cycle V

IEAO

> 6.7V 0 %

Maximum Duty Cycle V

IEAO

< 1.2V 90 95 %

MOSFET Driver Outputs

Output Low Voltage I

OUT

= –20mA 0.4 1.0 V

OUT

= –100mA 1.5 3.5 V

OUT

= –10mA, V

= 8V 0.8 1.5 V

Output High Voltage I

OUT

= 20mA 9.5 10.3 V

OUT

= 100mA 9 10.3 V

Output Rise/Fall Time C

= 1000pF 40 ns

Undervoltage Lockout

Threshold Voltage VCCZ –

0.9 VCCZ –

0.6 VCCZ –

0.2 V

Hysteresis 2.4 2.9 3.45 V

Parameter Conditions Min. Typ. Max. Units

Electrical Characteristics (Continued)

Unless otherwise speciﬁed, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1)

PRODUCT SPECIFICATION FAN4822

REV. 1.0.1 8/10/01 5

Notes

1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

2. Gain = K x 5.3 V; K = (IGAINMOD – IOFFSET) x IAC x (VEAO – 1.5)–1.

Supply

Shunt Voltage (VCCZ)I

CC =25mA 12.8 13.5 14.2 V

Load Regulation 25mA < ICC < 55mA ±150 ±300 mV

Total Variation Load and temperature 12.4 14.6 V

Start-up Current VCC < 12.3V 0.7 1.1 mA

Operating Current VCC = VCCZ – 0.5V 22 28 mA

Parameter Conditions Min. Typ. Max. Units

Electrical Characteristics (Continued)

Unless otherwise speciﬁed, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1)

FAN4822 PRODUCT SPECIFICATION

6REV. 1.0.1 8/10/01

Functional Description

Switching losses of wide input voltage range PFC boost con-

verters increase dramatically as power levels increase above

200 watts. The use of zero-voltage switching (ZVS) tech-

niques improves the efﬁciency of high power PFCs by sig-

niﬁcantly reducing the turn-on losses of the boost MOSFET.

ZVS is accomplished by using a second, smaller MOSFET,

together with a storage element (inductor) to convert the

turn-on losses of the boost MOSFET into useful output

power.

The basic function of the FAN4822 is to provide a power

factor corrected, regulated DC b us v oltage using continuous,

av erage current-mode control. Like Micro Linear’s family of

PFC/PWM controllers, the FAN4822 employs leading-edge

pulse width modulation to reduce system noise and permit

frequency synchronization to a trailing edge PWM stage for

the highest possible DC bus voltage bandwidth. For minimi-

zation of switching losses, circuitry has been incorporated to

control the switching of the ZVS FET.

Theory of Operation

Figure 1 shows a simpliﬁed schematic of the output and con-

trol sections of a high power PFC circuit. Figure 2 shows the

relationship of various waveforms in the circuit. Q1 func-

tions as the main switching FET and Q2 provides the ZVS

action. During each cycle, Q2 turns on before Q1, diverting

the current in L1 away from D1 into L2. The current in L2

increases linearly until at t2 it equals the current through L1.

When these currents are equal, L1 ceases discharging current

and is now charged through L2 and Q2. At time t2, the drain

voltage of Q1 begins to fall. The shape of the voltage wave-

form is sinusoidal due to the interaction of L2 and the com-

bined parasitic capacitance of D1 and Q1 (or optional ZVS

capacitor CZVS). At t3, the voltage across Q1 is sufﬁciently

low that the controller turns Q2 off and Q1 on. Q1 then

behaves as an ordinary PFC switch, storing energy in the

boost inductor L1. The ener gy stored in L2 is completely dis-

charged into the boost capacitor via D2 during the Q1 off-

time and the value of L2 must be selected for discontinuous-

mode operation.

Component Selection

Q1 Turn-Off

Because the FAN4822 uses leading edge modulation, the

PFC MOSFET (Q1) is always turned off at the end of each

oscillator ramp cycle. F or proper operation, the internal ZVS

ﬂip-ﬂop must be reset every cycle during the oscillator dis-

charge time. This is done by automatically resetting the ZVS

comparator a short time after the drain voltage of the main Q

has reached zero (refer to Figure 1 sense circuit). This sense

circuit terminates the ZVS on time by sensing the main Q

drain voltage reaching zero. It is then reset by w ay of a resis-

tor pull-up to VCC (R6). The advantage of this circuit is that

the ZVS comparator is not reset at the main Q turn off which

occurs at the end of the clock cycle. This a voids the potential

for improper reset of the internal ZVS ﬂip-ﬂop.

Another concern is the proper operation of the ZVS compar-

ator during discontinuous mode operation (DCM), which

will occur at the cusps of the rectiﬁed AC waveform and at

light loads. Due to the nature of the voltage seen at the drain

of the main boost Q during DCM operation, the ZVS com-

parator can be fooled into forcing the ZVS Q on for the

entire period. By adding a circuit which limits the maximum

on time of the ZVS Q, this problem can be avoided. Q3 in

Figure 1 provides this function.

Figure 1. Simplified PFC/ZVS Schematic.

33pF

330pF

CZVS(OPT)

PFC OUT

ZVS OUT

PWR GND

VCC

13 VREF

VREF

ZV SENSE

GND

FAN4822

MAX ZVS

ON TIME LIMIT

22k

51k

220

PRODUCT SPECIFICATION FAN4822

REV. 1.0.1 8/10/01 7

Q1 Turn-On

The turn-on event consists of the time it takes for the current

through L2 to ramp to the L1 current plus the resonant event

of L2 and the ZVS capacitor. The total ev ent should occur in

a minimum of 350–450ns, but can be longer at the risk of

increasing the total harmonic distortion. Setting these times

equal should minimize conducted and radiated emissions.

Where IL2 is equal to IL1.

The value of L2 is calculated to remain in discontinuous-

mode:

The resonant event occurs in 1/4 of a full sinusoidal cycle.

For example, when a 1/4 cycle occurs in 200ns, the fre-

quency is 1.25MHz.

Rearranging and solving for L2:

The resonant capacitor (CZVS) value is found by setting

equations 2 and 4 equal to each other and solving for CZVS.

Application

Figure 3 displays a typical application circuit for a 500W

ZVS PFC supply. Full design details are covered in applica-

tion note 33, FAN4822 Power Factor Correction With Zero

Voltage Resonant Switching.

Figure 2. Timing Diagrams

tQ1 OFF()

tIL2

=tRES

+400ns=(1)

L2 VBUS VRMS MIN()

tIL2

××

OUT

-----------------------------------------------------------------= (2)

fRES 1

L2 CZVS

2π

----------------------------------- 1

RES

---------------------== (3)

L2 4t

RES2

π2CZVS

--------------------------=(4)

CZVS 4t

RES2

×2P

OUT

××

π2VBUS VRMS MIN()

tIL2

×××

-----------------------------------------------------------------------------= (5)

A. SYSTEM

CLOCK

(INTERNAL)

B. R

C. ZVS GATE (Q2)

D. VDS (Q2)

E. PFC GATE (Q1)

F. VDS (Q1)

G. I

FAN4822 PRODUCT SPECIFICATION

8REV. 1.0.1 8/10/01

Figure 3. FAN4822 Schematic.

VEAO

IEAO

ISENSE

IAC

VRMS

RTCT

ZV SENSE

REF

VCC

PFC OUT

ZVS OUT

PWR GND

GND

FAN4822

LINE

8AMP

250VAC

C14

0.47µF

250VAC

GBU6G R13

402kΩ

R23

402kΩ

R12

453kΩ 1%

R22

453kΩ 1%

R14

100kΩ 1%

0.47µF

16V

470pF

1600V

0.1µF

50V

420uH @ 10A

n = 57

R15

16.2kΩ

10kΩ

R10

102kΩ 1%

93.1kΩ 1%

39kΩ

R29

10kΩ

R26

22kΩ

R16

8.25kΩ

R27

220

R19

10kΩ

R17

220kΩ

D10

UF4005

R24

22kΩ

R25

51kΩ

C22

100pF

C20

2.2nF

50V

C19

330pF

50V

C18

33pF

50V Q3

2N7000

n = 2.5

D11

EGP20A

C16

1µF

50V

1µF

50V

C11

68nF

50V

C12

2.2nF

50V

C13

100pF

50V

2.2µF

50V

0.68µF 50V

C15

1500µF

25V

C17

1µF

50V

D12

EGP20A

1N5819

1N4148

R21

39kΩ

R20

93.1kΩ 1%

R11

2.37kΩ

10Ω

1000pF

50V

400VDC RTN

400VDC

1N4747A

UF4005

1N4747A

8.5m @ 14A

FESI6JT D2

MUR860

FQA24N50 Q2

FQP6N50

MUR460

3.3kΩ

C21

0.1µF

200V

C10

1µF

50V

330µF

450V

1µF

50V

R18

0.0732 5W 1%

D13

1N5401 D7

1N5401

NEUTRAL

IN A

VS RTN

IN B

OUT A

OUT B

TC4427

PRODUCT SPECIFICATION FAN4822

REV. 1.0.1 8/10/01 9

Mechanical Dimensions inches (millimeters)

SEATING PLANE

0.240 - 0.260

(6.09 - 6.61)

PIN 1 ID 0.295 - 0.325

(7.49 - 8.25)

0.740 - 0.760

(18.79 - 19.31)

0.016 - 0.022

(0.40 - 0.56)

0.100 BSC

(2.54 BSC)

0.008 - 0.012

(0.20 - 0.31)

0.015 MIN

(0.38 MIN)

0º - 15º

0.050 - 0.065

(1.27 - 1.65)

0.170 MAX

(4.32 MAX)

0.125 MIN

(3.18 MIN)

0.070 MIN

(1.77 MIN)

(4 PLACES)

Package: P14

14-Pin PDIP

SEATING PLANE

0.291 - 0.301

(7.39 - 7.65)

PIN 1 ID

0.398 - 0.412

(10.11 - 10.47)

0.400 - 0.414

(10.16 - 10.52)

0.012 - 0.020

(0.30 - 0.51)

0.050 BSC

(1.27 BSC)

0.022 - 0.042

(0.56 - 1.07)

0.095 - 0.107

(2.41 - 2.72)

0.005 - 0.013

(0.13 - 0.33)

0.090 - 0.094

(2.28 - 2.39)

0.009 - 0.01

(0.22 - 0.33)

0º - 8º

0.024 - 0.034

(0.61 - 0.86)

(4 PLACES)

Package: S16W

16-Pin Wide SOIC

FAN4822 PRODUCT SPECIFICATION

8/10/01 0.0m 003

Stock#DS30004803

2001 Fairchild Semiconductor Corporation

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CORPORATION. As used herein:

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which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, and (c) whose failure to

perform when properly used in accordance with

instructions for use provided in the labeling, can be

reasonably expected to result in a significant injury of the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

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ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME

ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

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Ordering Information

Part Number PFC/PWM Frequency Package

FAN4822IN

FAN4822IM -40°C to 85°C

-40°C to 85°C14-Pin PDIP (P14)

16-Pin Wide SOIC (S16W)