Low Noise, Low Drift, Low Power,
3-Axis MEMS Accelerometers
Data Sheet ADXL354/ADXL355
Rev. A Document Feedback
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Technical Support www.analog.com
FEATURES
Hermetic package offers excellent long-term stability
0 g offset vs. temperature (all axes): 0.15 mg/°C maximum
Ultralow noise density (all axes): 20 μg/√Hz (ADXL354)
Low power, VSUPPLY (LDO enabled)
ADXL354 in measurement mode: 150 μA
ADXL355 in measurement mode: 200 μA
ADXL354/ADXL355 in standby mode: 21 μA
ADXL354 has user adjustable analog output bandwidth
ADXL355 digital output features
Digital serial peripheral interface (SPI)/I2C interfaces
20-bit analog-to-digital converter (ADC)
Data interpolation routine for synchronous sampling
Programmable high- and low-pass digital filters
Electromechanical self test
Integrated temperature sensor
Voltage range options
VSUPPLY with internal regulators: 2.25 V to 3.6 V
V1P8ANA, V1P8DIG with internal low dropout regulator (LDO)
bypassed: 1.8 V typical ± 10%
Operating temperature range: −40°C to +125°C
14-terminal, 6 mm × 6 mm × 2.1 mm, LCC package,
0.26 grams
APPLICATIONS
Inertial measurement units (IMUs)/altitude and heading
reference systems (AHRSs)
Platform stabilization systems
Structural health monitoring
Seismic imaging
Tilt sensing
Robotics
Condition monitoring
FUNCTIONAL BLOCK DIAGRAMS
TEMP
OUT
Y
OUT
X
OUT
V
SUPPLY
V
SSIO
V
SS
ST1
ST2
ADXL354
STBY
V
DDIO
CONTROL
LOGIC
RANGE
TEMP
SENSOR
POWER
MANAGEMENT
ANALOG
FILTER
3-AXIS
SENSOR
V
1P8ANA
LDO
V
1P8DIG
LDO
14205-002
Figure 1. ADXL354 Functional Block Diagram
ADC
ADC
ADC
ADC
TEMP
SENSOR
V
1P8ANA
DIGITAL
FILTER
FIFO
POWER
MANAGEMENT
V
SUPPLY
V
DDIO
LDO
V
1P8DIG
LDO
ANALOG
FILTER
3-AXIS
SENSOR SCLK/VSSIO
MOSI/SDA
MISO/ASEL
VSSIO VSS
INT1
INT2
CS/SCL
ADXL355
DRDY
SERIAL
I/O
CONTROL
LOGIC
14205-001
Figure 2. ADXL355 Functional Block Diagram
GENERAL DESCRIPTION
The analog output ADXL354 and the digital output ADXL355
are low noise density, low 0 g offset drift, low power, 3-axis
accelerometers with selectable measurement ranges. The
ADXL354B supports the ±2 g and ±4 g ranges, the ADXL354C
supports the ±2 g and ±8 g ranges, and the ADXL355 supports
the ±2.048 g, ±4.096 g, and ±8.192 g ranges. The ADXL354/
ADXL355 offer industry leading noise, minimal offset drift over
temperature, and long term stability enabling precision
applications with minimal calibration.
Highly integrated in a compact form factor, the low power
ADXL355 is ideal in an Internet of Things (IoT) sensor node
and other wireless product designs.
The ADXL355 multifunction pin names may be referenced by
their relevant function only for either the SPI or I2C interfaces.
1 Protected by U.S. Patents 8,472,270; 9,041,462; 8,665,627; 8,917,099; 6,892,576; 9,297,825; and 7,956,621.
ADXL354/ADXL355 Data Sheet
Rev. A | Page 2 of 42
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Analog Output for the ADXL354 ............................................... 3
Digital Output for the ADXL355 ............................................... 4
SPI Digital Interface Characteristics for the ADXL355 .......... 5
I2C Digital Interface Characteristics for the ADXL355 ........... 6
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Root Allan Variance (RAV) ADXL355 Characteristics ......... 19
Theory of Operation ...................................................................... 20
Analog Output ............................................................................ 20
Digital Output ............................................................................. 21
Axes of Acceleration Sensitivity ............................................... 21
Power Sequencing ...................................................................... 22
Power Supply Description ......................................................... 22
Overrange Protection ................................................................. 22
Self Test ........................................................................................ 22
Filter ............................................................................................. 23
Serial Communications ................................................................. 25
SPI Protocol ................................................................................. 25
I2C Protocol ................................................................................. 26
Reading Acceleration or Temperature Data from the Interface
....................................................................................................... 26
FIFO ................................................................................................. 27
Interrupts ......................................................................................... 28
DATA_ RDY ................................................................................. 28
DRDY Pin .................................................................................... 28
FIFO_FULL ................................................................................. 28
FIFO_OVR .................................................................................. 28
Activity ......................................................................................... 28
NVM_BUSY ............................................................................... 28
External Synchronization and Interpolation .......................... 29
ADXL355 Register Map ................................................................. 31
Register Definitions........................................................................ 32
Analog Devices ID Register ...................................................... 32
Analog Devices MEMS ID Register ......................................... 32
Device ID Register ..................................................................... 32
Product Revision ID Register ................................................... 32
Status Register ............................................................................. 32
FIFO Entries Register ................................................................ 33
Temperature Data Registers ...................................................... 33
X-Axis Data Registers ................................................................ 33
Y-Axis Data Registers ................................................................ 34
Z-Axis Data Registers ................................................................ 34
FIFO Access Register ................................................................. 35
X-Axis Offset Trim Registers .................................................... 35
Y-Axis Offset Trim Registers .................................................... 35
Z-Axis Offset Trim Registers .................................................... 36
Activity Enable Register ............................................................ 36
Activity Threshold Registers ..................................................... 36
Activity Count Register ............................................................. 36
Filter Settings Register ............................................................... 37
FIFO Samples Register .............................................................. 37
Interrupt Pin (INTx) Function Map Register......................... 37
Data Synchronization ................................................................ 38
I2C Speed, Interrupt Polarity, and Range Register ................. 38
Power Control Register ............................................................. 38
Self Test Register ......................................................................... 39
Reset Register .............................................................................. 39
Recommended Soldering Profile ................................................. 40
PCB Footprint Pattern ............................................................... 41
Packaging and Ordering Information ......................................... 42
Outline Dimensions ................................................................... 42
Branding Information ................................................................ 42
Ordering Guide .......................................................................... 42
REVISION HISTORY
4/2018—Rev. 0 to Rev.
Added Vibration Parameter, Table 5 .............................................. 8
Changes to Overrange Protection Section .................................. 22
8/2016—Revision 0: Initial Version
Data Sheet ADXL354/ADXL355
Rev. A | Page 3 of 42
SPECIFICATIONS
ANALOG OUTPUT FOR THE ADXL354
TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 g, and z-axis acceleration = 1 g, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
SENSOR INPUT Each axis
Output Full-Scale Range (FSR) ADXL354B, supports two ranges ±2/±4 g
ADXL354C, supports two ranges ±2/±8 g
Resonant Frequency1 2.4 kHz
Nonlinearity ±2 g 0.1 %
Cross Axis Sensitivity 1 %
SENSITIVITY Ratiometric to V1P8ANA
Sensitivity at XOUT, YOUT, ZOUT ±2 g 368 400 432 mV/g
±4 g 184 200 216 mV/g
±8 g 92 100 108 mV/g
Sensitivity Change due to Temperature −40°C to +125°C ±0.01 %/°C
0 g OFFSET Each axis, ±2 g
0 g Output for XOUT, YOUT, ZOUT Referred to V1P8ANA/2 −75 ±25 +75 mg
0 g Offset vs. Temperature (X-Axis, Y-Axis, and Z-Axis)2 −40°C to +125°C −0.15 ±0.1 +0.15 mg/°C
Repeatability3 X-axis and y-axis ±3.5 mg
Z-axis ±9 mg
Vibration Rectification Error (VRE)4 ±2 g range, in a 1 g orientation,
offset due to 2.5 g rms vibration
<0.4 g
NOISE DENSITY ±2 g
X-Axis, Y-Axis, and Z-Axis 20 μg/√Hz
Velocity Random Walk X-axis and y-axis 9 μm/sec/Hr
Z-axis 13
μm/sec/Hr
BANDWIDTH
Internal Low-Pass Filter Frequency Fixed frequency, 50% response
attenuation
1500 Hz
SELF TEST
Output Change
X-Axis 0.3
g
Y-Axis 0.3
g
Z-Axis 1.5
g
POWER SUPPLY
Voltage Range
VSUPPLY5 2.25 2.5 3.6 V
VDDIO V1P8DIG 2.5 3.6 V
V1P8ANA, V1P8DIG with Internal Low Dropout
Regulator (LDO) Bypassed
VSUPPLY = 0 V 1.62 1.8 1.98 V
Current
Measurement Mode
VSUPPLY (LDO Enabled) 150 μA
V1P8ANA (LDO Disabled) 138 μA
V1P8DIG (LDO Disabled) 12 μA
Standby Mode
VSUPPLY (LDO Enabled) 21 μA
V1P8ANA (LDO Disabled) 7 μA
V1P8DIG (LDO Disabled) 10 μA
Turn On Time6 2 g range <10 ms
Power-off to standby <10 ms
ADXL354/ADXL355 Data Sheet
Rev. A | Page 4 of 42
Parameter Test Conditions/Comments Min Typ Max Unit
OUTPUT AMPLIFIER
Swing No load 0.03 V1P8ANA − 0.03 V
Output Series Resistance 32 kΩ
TEMPERATURE SENSOR
Output at 25°C 892.2 mV
Scale Factor 3.0 mV/°C
TEMPERATURE
Operating Temperature Range −40 +125 °C
1 The resonant frequency is a sensor characteristic. An integrated analog 1.5 kHz (−6 dB) sinc low-pass filter that cannot be bypassed limits the actual output response.
2 The temperature change is −40°C to +25°C or +25°C to +125°C.
3 Repeatability is predicted for a 10 year life and includes shifts due to the high temperature operating life test (HTOL) (TA = 150°C, VSUPPLY = 3.6 V, and 1000 hours),
temperature cycling (−55°C to +125°C and 1000 cycles), velocity random walk, broadband noise, and temperature hysteresis.
4 The VRE measurement is the shift in dc offset while the device is subject to 2.5 g rms of random vibration from 50 Hz to 2 kHz. The device under test (DUT) is
configured for the ±2 g range and an output data rate of 4 kHz. The VRE scales with the range setting.
5 When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS.
6 Standby to measurement mode; valid when the output is within 1 mg of the final value.
DIGITAL OUTPUT FOR THE ADXL355
TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 g, and z-axis acceleration = 1 g, and output data rate (ODR) =
500 Hz, unless otherwise noted. Note that multifunction pin names may be referenced by their relevant function only.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
SENSOR INPUT Each axis
Output Full Scale Range (FSR) User selectable ±2.048 g
±4.096
g
±8.192
g
Nonlinearity ±2 g 0.1 % FS
Cross Axis Sensitivity 1 %
SENSITIVITY Each axis
X-Axis, Y-Axis, and Z-Axis Sensitivity ±2 g 235,520 256,000 276,480 LSB/g
±4 g 117,760 128,000 138,240 LSB/g
±8 g 58,880 64,000 69,120 LSB/g
X-Axis, Y-Axis, and Z-Axis Scale Factor ±2 g 3.9 μg/LSB
±4 g 7.8 μg/LSB
±8 g 15.6 μg/LSB
Sensitivity Change due to Temperature −40°C to +125°C ±0.01 %/°C
0 g OFFSET Each axis, ±2 g
X-Axis, Y-Axis, and Z-Axis 0 g Output −75 ±25 +75 mg
0 g Offset vs. Temperature (X-Axis, Y-Axis, and Z-Axis)1 −40°C to +125°C −0.15 ±0.02 +0.15 mg/°C
Repeatability2 X-axis and y-axis ±3.5 mg
Z-axis ±9 mg
Vibration Rectification3 ±2 g range, in a 1 g orientation,
offset due to 2.5 g rms vibration
<0.4 g
NOISE DENSITY ±2 g
X-Axis, Y-Axis, and Z-Axis 25 μg/√Hz
Velocity Random Walk X-axis and y-axis 9 μm/sec/Hr
Z-axis 13
μm/sec/Hr
OUTPUT DATA RATE AND BANDWIDTH
Low-Pass Filter Passband Frequency User programmable, Register 0x28 1 1000 Hz
High-Pass Filter Passband Frequency When Enabled
(Disabled by Default)
User programmable, Register 0x28
for 4 kHz ODR
0.0095 10 Hz
Data Sheet ADXL354/ADXL355
Rev. A | Page 5 of 42
Parameter Test Conditions/Comments Min Typ Max Unit
SELF TEST
Output Change
X-Axis 0.3
g
Y-Axis 0.3
g
Z-Axis 1.5
g
POWER SUPPLY
Voltage Range
VSUPPLY Operating4 2.25 2.5 3.6 V
VDDIO V
1P8DIG 2.5 3.6 V
V1P8ANA and V1P8DIG with Internal LDO Bypassed VSUPPLY = 0 V 1.62 1.8 1.98 V
Current
Measurement Mode
VSUPPLY (LDO Enabled) 200 μA
V1P8ANA (LDO Disabled) 160 μA
V1P8DIG (LDO Disabled) 35.5 μA
Standby Mode
VSUPPLY (LDO Enabled) 21 μA
V1P8ANA (LDO Disabled) 7 μA
V1P8DIG (LDO Disabled) 10 μA
Turn On Time5 2 g range <10 ms
Power-off to standby <10 ms
TEMPERATURE SENSOR
Output at 25°C 1852 LSB
Scale Factor −9.05 LSB/°C
TEMPERATURE
Operating Temperature Range −40 +125 °C
1 The temperature change is −40°C to +25°C or +25°C to +125°C.
2 Repeatability is predicted for a 10 year life and includes shifts due to the HTOL (TA = 150°C, VSUPPLY = 3.6 V, and 1000 hours), temperature cycling (−55°C to +125°C and
1000 cycles), velocity random walk, broadband noise, and temperature hysteresis.
3 The VRE measurement is the shift in dc offset while the device is subject to 2.5 g rms random vibration from 50 Hz to 2 kHz. The DUT is configured for the ±2 g range
and an output data rate of 4 kHz. The VRE scales with the range setting.
4 When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS.
5 Standby to measurement mode; valid when the output is within 1 mg of final value.
SPI DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL355
Note that multifunction pin names may be referenced by their relevant function only.
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DC INPUT LEVELS
Input Voltage
Low Level VIL 0.3 × VDDIO V
High Level VIH 0.7 × VDDIO V
Input Current
Low Level IIL V
IN = 0 V −0.1 μA
High Level IIH V
IN = VDDIO 0.1 μA
DC OUTPUT LEVELS
Output Voltage
Low Level VOL I
OL = IOL, MIN 0.2 × VDDIO V
High Level VOH I
OH = IOH, MAX 0.8 × VDDIO V
Output Current
Low Level IOL V
OL = VOL, MAX −10 mA
High Level IOH V
OH = VOH, MIN 4 mA
ADXL354/ADXL355 Data Sheet
Rev. A | Page 6 of 42
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
AC INPUT LEVELS
SCLK Frequency 0.1 10 MHz
SCLK High Time tHIGH 40 ns
SCLK Low Time tLOW 40 ns
CS Setup Time tCSS 20 ns
CS Hold Time tCSH 20 ns
CS Disable Time tCSD 40 ns
Rising SCLK Setup Time tSCLKS 20 ns
MOSI Setup Time tSU 20 ns
MOSI Hold Time tHD 20 ns
AC OUTPUT LEVELS
Propagation Delay tP CLOAD = 30 pF 30 ns
Enable MISO Time tEN 30 ns
Disable MISO Time tDIS 20 ns
tSU
tCSS tLOW
tHIGH
tCSD
tCSH tSCLKS
tEN tPtDIS
CS
SCLK
MISO
MOSI
tHD
14205-003
Figure 3. SPI Interface Timing Diagram
I2C DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL355
Note that multifunction pin names may be referenced by their relevant function only.
Table 4.
Test Conditions/ I2C_HS = 0 (Fast Mode) I2C_HS = 1 (High Speed Mode)
Parameter Symbol Comments Min Typ Max Min Typ Max Unit
DC INPUT LEVELS
Input Voltage
Low Level VIL 0.3 × VDDIO 0.3 × VDDIO V
High Level VIH 0.7 × VDDIO 0.7 × VDDIO V
Hysteresis of Schmitt
Trigger Inputs
VHYS 0.05 × VDDIO 0.1 × VDDIO μA
Input Current IIL 0.1 × VDDIO < VIN <
0.9 × VDDIO
−10 +10 μA
DC OUTPUT LEVELS
Output Voltage IOL = 3 mA
Low Level VOL1 V
DD > 2 V 0.4 V
V
OL2 V
DD ≤ 2 V 0.2 × VDDIO V
Output Current
Low Level IOL V
OL = 0.4 V 20 mA
V
OL = 0.6 V 6 mA
Data Sheet ADXL354/ADXL355
Rev. A | Page 7 of 42
Test Conditions/ I2C_HS = 0 (Fast Mode) I2C_HS = 1 (High Speed Mode)
Parameter Symbol Comments Min Typ Max Min Typ Max Unit
AC INPUT LEVELS
SCLK Frequency 0 1 0 3.4 MHz
SCL High Time tHIGH 260 60 ns
SCL Low Time tLOW 500 160 ns
Start Setup Time tSUSTA 260 160 ns
Start Hold Time tHDSTA 260 160 ns
SDA Setup Time tSUDAT 50 10 ns
SDA Hold Time tHDDAT 0 0 ns
Stop Setup Time tSUSTO 260 160 ns
Bus Free Time tBUF 500 ns
SCL Input Rise Time tRCL 120 80 ns
SCL Input Fall Time tFCL 120 80 ns
SDA Input Rise Time tRDA 120 160 ns
SDA Input Fall Time tFDA 120 160 ns
Width of Spikes to
Suppress
tSP Not shown in Figure 4 50 10 ns
AC OUTPUT LEVELS
Propagation Delay CLOAD = 500 pF
Data tVDDAT 97 450 27 135 ns
Acknowledge tVDACK 450 ns
Output Fall Time tF Not shown in Figure 4 20 × (VDD/5.5) 120 ns
tSUDAT tHDDAT
tHDSTA tLOW tHIGH
tBUF
tSUSTO tSUSTA
tVDACK
S
DA
SCL
tRCL
tFCL
tFDA tRDA
tSUSTA
tVDDAT
tVDDAT
14205-004
Figure 4. I2C Interface Timing Diagram
ADXL354/ADXL355 Data Sheet
Rev. A | Page 8 of 42
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Acceleration (Any Axis, 0.1 ms)
Unpowered 5,000 g
Vibration Per MIL-STD-883
Method 2007, Test
Condition A
VSUPPLY, VDDIO 5.4 V
V1P8ANA, V1P8DIG Configured as Inputs 1.98 V
ADXL354
Digital Inputs (RANGE, ST1, ST2, STBY) −0.3 V to VDDIO + 0.3 V
Analog Outputs (XOUT, YOUT, ZOUT, TEMP) −0.3 V to V1P8ANA + 0.3 V
ADXL355
Digital Pins (CS, SCLK, MOSI, MISO,
INT1, INT2, DRDY)
−0.3 V to VDDIO + 0.3 V
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −55°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 6. Thermal Resistance
Package Type θJA Unit
E-14-11 42 °C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with four thermal vias. See JEDEC JESD51.
ESD CAUTION
Data Sheet ADXL354/ADXL355
Rev. A | Page 9 of 42
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADXL354
TOP VIEW
(Not to Scale)
V
SUPPLY
V
1P8ANA
V
SS
V
1P8DIG
RANGE
ST1
ST2
TEMP
11
10
9
Z
OUT
Y
OU
T
X
OU
T
14
13
12
8
1
2
3
V
DDIO
V
SSIO
STBY
5
6
7
4
X
Z
Y
14205-007
Figure 5. ADXL354 Pin Configuration
Table 7. ADXL354 Pin Function Descriptions
Pin No. Mnemonic Description
1 RANGE
Range Selection Pin. Set this pin to ground to select the ±2 g range, or set this pin to VDDIO to select the ±4 g
or ±8 g range. This pin is model dependent (see the Ordering Guide section).
2 ST1 Self Test Pin 1. This pin enables self test mode.
3 ST2 Self Test Pin 2. This pin activates the electromechanical self test actuation.
4 TEMP Temperature Sensor Output.
5 VDDIO Digital Interface Supply Voltage.
6 VSSIO Digital Ground.
7 STBY Standby or Measurement Mode Selection Pin. Set this pin to ground to enter standby mode, or set this pin
to VDDIO to enter measurement mode.
8 V1P8DIG Digital Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this
pin externally.
9 VSS Analog Ground.
10 V1P8ANA Analog Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this
pin externally.
11 VSUPPLY Supply Voltage. When VSUPPLY equals 2.25 V to 3.6 V, VSUPPLY enables the internal LDOs to generate V1P8DIG and
V1P8ANA. For VSUPPLY = VSS, V1P8DIG and V1P8ANA are externally supplied.
12 XOUT X-Axis Output.
13 YOUT Y-Axis Output.
14 ZOUT Z-Axis Output.
ADXL354/ADXL355 Data Sheet
Rev. A | Page 10 of 42
ADXL355
TOP VIEW
(Not to Scale)
V
SUPPLY
X
Z
Y
V
1P8ANA
V
SS
V
1P8DIG
CS/SCL
S
CLK/V
SSIO
MOSI/SDA
MISO/ASEL
11
10
9
DRD
Y
INT2
INT1
14
13
12
8
1
2
3
V
DDIO
V
SSIO
RESERVED
5
6
7
4
14205-006
Figure 6. ADXL355 Pin Configuration
Table 8. ADXL355 Pin Function Descriptions
Pin No. Mnemonic Description
1 CS/SCL Chip Select for SPI (CS).
Serial Communications Clock for I2C (SCL).
2 SCLK/VSSIO Serial Communications Clock for SPI (SCLK).
Connect to VSSIO for I2C (VSSIO).
3 MOSI/SDA Master Output, Slave Input for SPI (MOSI).
Serial Data for I2C (SDA).
4 MISO/ASEL Master Input, Slave Output for SPI (MISO).
Alternate I2C Address Select for I2C (ASEL).
5 VDDIO Digital Interface Supply Voltage.
6 VSSIO Digital Ground.
7 RESERVED Reserved. This pin can be connected to ground or left open.
8 V1P8DIG Digital Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this
pin externally.
9 VSS Analog Ground.
10 V1P8ANA Analog Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to this
pin externally.
11 VSUPPLY Supply Voltage. When VSUPPLY equals 2.25 V to 3.6 V, VSUPPLY enables the internal LDOs to generate V1P8DIG and
V1P8ANA. For VSUPPLY = VSS, V1P8DIG and V1P8ANA are externally supplied.
12 INT1 Interrupt Pin 1.
13 INT2 Interrupt Pin 2.
14 DRDY Data Ready Pin.
Data Sheet ADXL354/ADXL355
Rev. A | Page 11 of 42
TYPICAL PERFORMANCE CHARACTERISTICS
All figures include data for multiple devices and multiple lots, and they were taken in the ±2 g range, unless otherwise noted.
0.01
0.1
1
10
10 100 1000
X
OUT
(
g)
FREQUENCY (Hz)
14205-207
Figure 7. ADXL354 Frequency Response for X-Axis
0.01
0.1
1
10
10 100 1000
Y
OUT
(g)
FRE QUE NCY ( Hz)
14205-208
Figure 8. ADXL354 Frequency Response for Y-Axis
0.1
1
10
10 100 1000
Z
OUT
(
g)
FRE QUENCY (Hz)
14205-209
Figure 9. ADXL354 Frequency Response for Z-Axis
FRE QUENCY (Hz)
0.01
0.1
1
10 100 1000
14205-210
Figure 10. ADXL355 Normalized Frequency Response for X-Axis at 4 kHz ODR
Y-AXIS (g)
FREQUENCY (Hz)
0.01
0.1
1
10 100 1000
14205-211
Figure 11. ADXL355 Normalized Frequency Response for Y-Axis at 4 kHz ODR
Z-AXIS (g)
FRE Q UE NCY ( Hz)
0.01
0.1
1
10 100 1000
14205-212
Figure 12. ADXL355 Normalized Frequency Response for Z-Axis at 4 kHz ODR
ADXL354/ADXL355 Data Sheet
Rev. A | Page 12 of 42
–9.75
–5.00
5.00
0
10.00
15.00
–45 5 55 105
RELATIVE OFFSET (
m
g)
TE M P E RATURE ( °C)
MAXIMUM CHAN GE = 1.69mg
AVERAGE CHANGE = 1.18mg
14205-213
Figure 13. ADXL354 X-Axis Zero g Offset Relative to 25°C vs. Temperature
–45 5 55 105
RELATIVE OFFSET (
m
g)
TE M P E RATURE ( °C)
MAXIMUM CHANGE = 3 .12mg
AVERAGE CHANGE = 1 .85mg
14205-214
–9.75
–5.00
5.00
0
10.00
15.00
Figure 14. ADXL354 Y-Axis Zero g Offset Relative to 25°C vs. Temperature
–45 5 55 105
RELATIVE OFFSET (
m
g)
TE MP E RAT URE (°C)
MAXIMUM CHANG E = 3. 1 2mg
AVERAGE CHANGE = 1.8 5mg
14205-215
–9.75
–5.00
5.00
0
10.00
15.00
Figure 15. ADXL354 Z-Axis Zero g Offset Relative to 25°C vs. Temperature
–0.65
–0.50
0
0.50
1.00
–45 5 55 105
REL
A
TIVE SENSIT I VI TY (%)
TE MP E RATURE (° C)
MAXIMUM CHANGE = 0. 60%
AVERAGE CHANG E = 0.34%
14205-216
Figure 16. ADXL354 X-Axis Sensitivity Relative to 25°C vs. Temperature
–0.65
–0.50
0
0.50
1.00
–45 5 55 105
RELATIVE SENSITIVI TY ( %)
TEMPERATURE ( °C)
MAXIMUM CHANGE = 0.54%
AVERAG E CHANG E = 0.28%
14205-217
Figure 17. ADXL354 Y-Axis Sensitivity Relative to 25°C vs. Temperature
–0.65
–0.50
0
0.50
1.00
–4010 60110
REL
A
TIVE SENSIT I VI TY (%)
TE MPERATURE ( °C)
14205-218
MAXIMUM CHANGE = 0 .99%
AVERAGE CHANGE = 0 .51%
Figure 18. ADXL354 Z-Axis Sensitivity Relative to 25°C vs. Temperature
Data Sheet ADXL354/ADXL355
Rev. A | Page 13 of 42
0
10
20
30
40
50
60
70
–0.040
–0.035
–0.030
–0.025
–0.020
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
0.020
0.025
0.030
0.035
0.045
0.050
0.055
0.060
0.065
0.070
0.075
0.045
0.050
0.055
0.060
0.065
0.070
0.075
0.040
ADXL 354 2g O F FSET X-AXIS (g)
HITS PER BIN ( Cou nt)
14205-219
Figure 19. ADXL354 Zero g Offset Histogram at 25°C, X-Axis
0
10
20
30
40
50
60
70
80
–0.040
–0.035
–0.030
–0.025
–0.020
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
0.020
0.025
0.030
0.035
0.045
0.050
0.055
0.060
0.065
0.070
0.075
0.045
0.050
0.055
0.060
0.065
0.070
0.075
0.040
ADXL 354 2g OFFSET Y-AXIS (g)
HIT S PE R BI N ( Co u nt)
14205-220
Figure 20. ADXL354 Zero g Offset Histogram at 25°C, Y-Axis
0
5
10
15
20
25
30
35
40
45
ADXL 354 2g OFFSET Z-AXIS (g)
HITS PER BIN (Count)
14205-221
Figure 21. ADXL354 Zero g Offset Histogram at 25°C, Z-Axis
0
10
20
30
40
50
60
70
80
0.380
0.382
0.384
0.386
0.388
0.390
0.392
0.394
0.396
0.398
0.400
0.368
0.370
0.372
0.374
0.376
0.378
0.402
0.404
0.406
0.408
0.410
0.412
0.414
0.416
0.418
0.420
0.422
0.424
0.426
0.428
0.430
0.432
ADXL 354 2g SENSITIVITY X-AXIS (V/g)
HITS PER BIN (Count )
14205-222
Figure 22. ADXL354 Sensitivity Histogram at 25°C, X-Axis
ADXL 354 2g SENSITIVITY Y-AXIS (V/g)
0
10
20
30
40
50
60
70
80
0.380
0.382
0.384
0.386
0.388
0.390
0.392
0.394
0.396
0.398
0.400
0.402
0.404
0.406
0.408
0.410
0.412
0.414
HITS PE R BIN (Count)
14205-223
0.368
0.370
0.372
0.374
0.376
0.378
0.416
0.418
0.420
0.422
0.424
0.426
0.428
0.430
0.432
Figure 23. ADXL354 Sensitivity Histogram at 25°C, Y-Axis
0
10
20
30
40
50
60
70
0.375
0.377
0.379
0.381
0.383
0.385
0.387
0.389
0.391
0.393
0.395
0.397
0.399
0.401
0.403
0.405
0.407
0.409
ADXL3 54 2g SENSIT I VI TY Z-AXIS (V/g)
HITS PER BI N ( Cou nt)
14205-224
0.368
0.370
0.372
0.374
0.376
0.378
0.416
0.418
0.420
0.422
0.424
0.426
0.428
0.430
0.432
Figure 24. ADXL354 Sensitivity Histogram at 25°C, Z-Axis
ADXL354/ADXL355 Data Sheet
Rev. A | Page 14 of 42
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
01234
OFFSET SHIFT (g)
INPUT VIBRATION (g rms)
14205-225
Figure 25. ADXL354 Vibration Rectification Error (VRE),
X-Axis Offset from +1 g, ±2 g Range, X-Axis Orientation = −1 g
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
01234
OFFSET SHIFT (g)
INPUT VIBRATI ON (g rms)
14205-226
Figure 26. ADXL354 Vibration Rectification Error (VRE),
Y-Axis Offset from +1 g, ±2 g Range, Y-Axis Orientation = +1 g
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
01234
OFFSET SHIFT (g)
INPUT VIBRATION (g rm s)
14205-227
Figure 27. ADXL354 Vibration Rectification Error (VRE),
Z-Axis Offset from +1 g, ±2 g Range, Z-Axis Orientation = +1 g
–0.02
0.08
0.18
0.28
0.38
0.48
0.58
0.68
0246810
OFFSET SHIFT (g)
INPUT VIBRATION (g rms)
14205-228
Figure 28. ADXL354 Vibration Rectification Error (VRE),
X-Axis Offset from +1 g, ±8 g Range, X-Axis Orientation = −1 g
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0246810
OFFSET SHIFT (g)
INPUT VI BRATIO N (g rms)
14205-229
Figure 29. ADXL354 Vibration Rectification Error (VRE),
Y-Axis Offset from +1 g, ±8 g Range, Y-Axis Orientation = +1 g
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0246810
OFF SET SHIF T (g)
INPUT VIBRAT I O N (g rms)
14205-230
Figure 30. ADXL354 Vibration Rectification Error (VRE),
Z-Axis Offset from +1 g, ±8 g Range, Z-Axis Orientation = +1 g
Data Sheet ADXL354/ADXL355
Rev. A | Page 15 of 42
–45 5 55 105
RELATIVE O F FSET (
m
g)
TEMPERATURE (°C)
14205-231
MAXIMUM DELTA = 6.5mg
AVE RAG E DE LT A = 1.7mg
–9.75
–5.00
5.00
0
10.00
15.00
Figure 31. ADXL355 X-Axis Zero g Offset Relative to 25°C vs. Temperature
–45 5 55 105
REL
A
TIVE OF FSET (mg)
TE MPERATURE (°C)
14205-232
MAXIMUM DEL TA = 3.2mg
AVERAG E DE L T A = 1. 4mg
–9.75
–5.00
5.00
0
10.00
15.00
Figure 32. ADXL355 Y-Axis Zero g Offset Relative to 25°C vs. Temperature
–45 5 55 105
REL
A
TIVE O FFSET (mg)
TEMPERATURE (°C)
14205-233
MAXIMUM DELTA = 10.6mg
AVERAGE DE LTA = 5.3mg
–9.75
–5.00
5.00
0
10.00
15.00
Figure 33. ADXL355 Z-Axis Zero g Offset Relative to 25°C vs. Temperature
TEMPERATURE (°C)
–0.50
–0.65
0
0.50
1.00
–45 5 55 105
RELATIVE SENSITIVITY (%)
MAXIMUM CHANGE = 0.78%
AVERA GE C HANGE = 0.72%
14205-234
Figure 34. ADXL355 X-Axis Sensitivity Relative to 25°C vs. Temperature
TE MPERATURE (°C)
–0.65
–0.50
0
0.50
1.00
–45 5 55 105
REL
A
TIVE SENSTIVITY (%)
14205-235
MAXIMUM CHANGE = 0.78%
AVERAGE CHANG E = 0. 72%
Figure 35. ADXL355 Y-Axis Sensitivity Relative to 25°C vs. Temperature
TEMPERATURE (°C)
–0.65
–0.50
0
0.50
1.00
–45 5 55 105
REL
A
TIVE SENSTI VI TY (%)
14205-236
MAXIMUM CHANGE = 0.47%
AVERAGE CHA NGE = 0.3 %
Figure 36. ADXL355 Z-Axis Sensitivity Relative to 25°C vs. Temperature
ADXL354/ADXL355 Data Sheet
Rev. A | Page 16 of 42
14205-237
0
10
20
30
40
50
60
70
80
–75
75
–69
–63
–57
–51
–45
–39
–33
–27
–21
–15
–9
–3
3
9
15
21
27
33
39
45
51
57
63
69
HITS PER BI N ( Cou nt)
OFF SET (mg)
Figure 37. ADXL355 Zero g Offset Histogram at 25°C, X-Axis
HITS PER BI N ( Cou nt)
14205-238
0
10
20
30
40
50
60
70
80
–75
75
–69
–63
–57
–51
–45
–39
–33
–27
–21
–15
–9
–3
3
9
15
21
27
33
39
45
51
57
63
69
OFFSET (mg)
Figure 38. ADXL355 Zero g Offset Histogram at 25°C, Y-Axis
14205-239
0
5
10
15
20
25
30
35
40
45
HITS PER BIN (Count)
–75
75
–69
–63
–57
–51
–45
–39
–33
–27
–21
–15
–9
–3
3
9
15
21
27
33
39
45
51
57
63
69
OFFSET (mg)
Figure 39. ADXL355 Zero g Offset Histogram at 25°C, Z-Axis
14205-240
0
10
20
30
40
50
60
235520
237158
238797
240435
242074
243712
245350
246989
248627
250266
251904
253542
255181
256819
258458
260096
261734
263373
265011
266650
268288
269926
271565
273203
274842
276480
HITS P ER BI N (Coun t)
SENSITIVI T Y (lsb/ g )
Figure 40. ADXL355 Sensitivity Histogram at 25°C, X-Axis
14205-241
HITS PER BIN (Cou nt)
SENSITIVITY (LSB/g)
0
10
20
30
40
50
60
235520
237158
238797
240435
242074
243712
245350
246989
248627
250266
251904
253542
255181
256819
258458
260096
261734
263373
265011
266650
268288
269926
271565
273203
274842
276480
Figure 41. ADXL355 Sensitivity Histogram at 25°C, Y-Axis
14205-242
HITS PER BIN (Count)
SENSITIVITY (LSB/g)
235520
237158
238797
240435
242074
243712
245350
246989
248627
250266
251904
253542
255181
256819
258458
260096
261734
263373
265011
266650
268288
269926
271565
273203
274842
276480
0
10
20
30
40
50
60
Figure 42. ADXL355 Sensitivity Histogram at 25°C, Z-Axis
Data Sheet ADXL354/ADXL355
Rev. A | Page 17 of 42
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
01234
OF FSET CHANGE (g)
INPUT VI BRATIO N (g rms)
14205-243
Figure 43. ADXL355 Vibration Rectification Error (VRE),
X-Axis Offset from +1 g, ±2 g Range, X-Axis Orientation = −1 g
OF F S E T CHANGE (g)
INPUT VIBRAT ION (g rms)
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
01234
14205-244
Figure 44. ADXL355 Vibration Rectification Error (VRE),
Y-Axis Offset from +1 g, ±2 g Range, Y-Axis Orientation = +1 g
OF F S ET CHANGE (g)
INPUT VIBRAT I ON (g rms)
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
01234
14205-245
Figure 45. ADXL355 Vibration Rectification Error (VRE),
Z-Axis Offset from +1 g, ±2 g Range, Z-Axis Orientation = +1 g
–0.02
0.08
0.18
0.28
0.38
0.48
0.58
0.68
0246810
OFFSET SHIFT (g)
INPUT VIBRATION (g rms)
14205-246
Figure 46. ADXL355 Vibration Rectification Error (VRE),
X-Axis Offset from +1 g, ±8 g Range, X-Axis Orientation = −1 g
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0246810
OFF SET SHI F T (g)
INPUT VIBRATION (g rms)
14205-247
Figure 47. ADXL355 Vibration Rectification Error (VRE),
Y-Axis Offset from +1 g, ±8 g Range, Y-Axis Orientation = +1 g
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0246810
OFFSET SHIFT (g)
INPUT VI BRATION (g rms)
14205-248
Figure 48. ADXL355 Vibration Rectification Error (VRE),
Z-Axis Offset from +1 g, ±8 g Range, Z-Axis Orientation = +1 g
ADXL354/ADXL355 Data Sheet
Rev. A | Page 18 of 42
–0.006
–0.004
–0.002
0
0.002
0.004
0.006
0.75
0.85
0.95
1.05
1.15
1.25
1.35
–40 10 60 110
ADXL354 TEMP ERATURE SENSOR
LINEAR OFFSET (V)
ADXL354 T E M PE R
A
TURE SE NS O R O UT P UT (V )
TEMPERATURE (°C)
TEM P E RATURE S E NSOR O UT P UT
LINEARITY
14205-249
Figure 49. ADXL354 Temperature Sensor Output and Linearity Offset vs.
Temperature
125 129 133 137 141 145 149 153 157 161 165 169 173
0
10
20
30
40
50
60
70
80
TOTAL S UPPLY CURRE NT (µA)
HITS PER BIN (Count)
14205-251
Figure 50. ADXL354 Total Supply Current, 3.3 V
0
5
10
15
20
25
30
35
3800 3840 3880 3920 3960 4000 4040 4080 4120 4160 4200
ADXL 355 CLO CK FREQUENCY (Hz)
HITS PER BIN (Count)
14205-252
Figure 51. ADXL355 Internal Clock Frequency Histogram
–4010 60110
ADXL355 TEMPER ATURE SENSOR
LINEAR OFFSET (LSB)
ADXL 3 55 TEM P ERATUR E SE NS OR OUT P UT (LSB)
–8
–6
–4
–2
0
2
4
6
700
900
1100
1300
1500
1700
1900
2100
2300
TE MPE RA TURE SENS OR OUT PUT
LINEARITY
14205-250
TEMPERATURE (°C)
Figure 52. ADXL355 Temperature Sensor Output and Linearity Offset vs.
Temperature
0
10
20
30
40
50
60
70
80
90
100
180 184 188 192 196 200 204 208 212 216 220 224 228
TOTAL SUPP LY CURRE NT (µ A)
HITS PER BIN (Count)
14205-253
Figure 53. ADXL355 Total Supply Current, 3.3 V
Data Sheet ADXL354/ADXL355
Rev. A | Page 19 of 42
ROOT ALLAN VARIANCE (RAV) ADXL355 CHARACTERISTICS
All figures include data for multiple devices and multiple lots, and they were taken in the ±2 g range, unless otherwise noted.
1
10
100
1000
0.01 0.1 1 10 100 1000
R
A
V (µg)
INTEGRATION TIME (Seconds)
14205-254
Figure 54. ADXL355 Root Allan Variance (RAV), X-Axis
1
10
100
1000
0.01 0.1 1 10 100 1000
R
A
V (µg)
INTEGRATION TIME (Seconds)
14205-255
Figure 55. ADXL355 Root Allan Variance (RAV), Y-Axis
1
10
100
1000
0.01 0.1 1 10 100 1000
R
A
V (µg)
INTEGRATION TIME (Seconds)
14205-256
Figure 56. ADXL355 Root Allan Variance (RAV), Z-Axis
ADXL354/ADXL355 Data Sheet
Rev. A | Page 20 of 42
THEORY OF OPERATION
The ADXL354 is a complete 3-axis, ultralow noise and ultrastable
offset MEMS accelerometer with outputs ratiometric to the analog
1.8 V supply, V1P8ANA. The ADXL355 adds three high resolution
ADCs that use the analog 1.8 V supply as a reference to provide
digital outputs insensitive to the supply voltage. The ADXL354B
is pin selectable for ±2 g or ±4 g full scale, the ADXL354C is pin
selectable for ±2 g or ±8 g full scale, and the ADXL355 is
programmable for ±2.048 g, ±4.096 g, and ±8.192 g full scale.
The ADXL355 offers both SPI and I2C communications ports.
The micromachined, sensing elements are fully differential,
comprising the lateral x-axis and y-axis sensors and the vertical,
teeter totter z-axis sensors. The x-axis and y-axis sensors and
the z-axis sensors go through separate signal paths that minimize
offset drift and noise. The signal path is fully differential, except
for a differential to single-ended conversion at the analog
outputs of the ADXL354.
The analog accelerometer outputs of the ADXL354 are ratiometric
to V1P8ANA; therefore, carefully digitize them correctly. The
temperature sensor output is not ratiometric. The XOUT, YOUT,
and ZOUT analog outputs are filtered internally with an anti-
aliasing filter. These analog outputs also have an internal 32 kΩ
series resistor that can be used with an external capacitor to set
the bandwidth of the output.
The ADXL355 includes antialias filters before and after the high
resolution Σ-Δ ADC. User-selectable output data rates and filter
corners are provided. The temperature sensor is digitized with a
12-bit successive approximation register (SAR) ADC.
ANALOG OUTPUT
Figure 57 shows the ADXL354 application circuit. The analog
outputs (XOUT, YOUT, and ZOUT) are ratiometric to the 1.8 V
analog voltage from the V1P8ANA pin. V1P8ANA can be powered
with an on-chip LDO that is powered from VSUPPLY. V1P8ANA can
also be supplied externally by forcing VSUPPLY to VSS, which
disables the LDO. Due to the ratiometric response, the analog
output requires referencing to the V1P8ANA supply when
digitizing to achieve the inherent noise and offset performance
of the ADXL354. The 0 g bias output is nominally equal to
V1P8ANA/2. The recommended option is to use the ADXL354
with a ratiometric ADC (for example, the Analog Devices, Inc.,
AD7682) with V1P8ANA providing the voltage reference. This
configuration results in self cancellation of errors due to minor
supply variations.
The ADXL354 outputs two forms of filtering: internal anti-
aliasing filtering with a cutoff frequency of approximately 1.5 kHz,
and external filtering. The external filter uses a fixed, on-chip,
32 kΩ resistance in series with each output in conjunction with
the external capacitors to implement the low-pass filter antialiasing
and noise reduction prior to the external ADC. The antialias
filter cutoff frequency must be significantly higher than the
desired signal bandwidth. If the antialias filter corner is too low,
ratiometricity can be degraded where the signal attenuation is
different than the reference attenuation.
ADXL354
V
SUPPLY
V
DDIO
(±4g, ±8g)
GND ( ± 2g)
V
DDIO
(MEASUREMENT)
GND ( S TANDBY)
V
1P8ANA
V
SS
V
1P8DIG
ADC V
REF
RANGE
ST1
ST2
TEMP
11
10
9
Z
OUT
Y
OUT
X
OUT
14
13
12
8
1
2
3
V
DDIO
V
SSIO
STBY
5
6
7
4
2.25
V
TO 3. 6V
1µF0.1µF
1µF0.1µF
1µF
0.1µF
1µF
0.1µF
2
.25
V
TO 3. 6V
14205-022
Figure 57. ADXL354 Application Circuit
Data Sheet ADXL354/ADXL355
Rev. A | Page 21 of 42
DIGITAL OUTPUT
Figure 59 shows the ADXL355 application circuit with the
recommended bypass capacitors. The communications interface
is either SPI or I2C (see the Serial Communications section for
additional information).
The ADXL355 includes an internal configurable digital band-
pass filter. Both the high-pass and low-pass poles of the filter
are adjustable, as detailed in the Filter Settings Register section
and Table 43. At power-up, the default conditions for the filters
are as follows:
High-pass filter (HPF) = dc (off)
Low-pass filter (LPF) = 1000 Hz
Output data rate = 4000 Hz
AXES OF ACCELERATION SENSITIVITY
Figure 58 shows the axes of acceleration sensitivity. Note that
the output voltage increases when accelerated along the
sensitive axis.
Y
Z
X
14205-005
Figure 58. Axes of Acceleration Sensitivity
ADXL355
TOP VIEW
(No t to S cal e)
VSUPPLY
V1P8ANA
VSS
V1P8DIG
11
10
9
DRD
Y
INT2
INT1
14
13
12
8
1
2
3
VDDIO
VSSIO
RESERVED
5
6
7
4
2.25V TO 3.6V
1µF0.1µF
1µF0.1µF
1µF
0.1µF
1µF
0.1µF
2.25V TO 3.6V
SPI/I2C
INTERFACE
14205-021
CS/SCL
SCLK/VSSIO
MOSI/SDA
MISO/ASEL
Figure 59. ADXL355 Application Circuit
ADXL354/ADXL355 Data Sheet
Rev. A | Page 22 of 42
POWER SEQUENCING
There are two methods for applying power to the device.
Typically, internal LDO regulators generate the 1.8 V power for
the analog and digital supplies, V1P8ANA and V1P8DIG, respectively.
Optionally, connecting VSUPPLY to VSS and driving V1P8ANA and
V1P8DIG with an external supply can supply V1P8ANA and V1P8DIG.
When using the internal LDO regulators, connect VSUPPLY to a
voltage source between 2.25 V to 3.6 V. In this case, VDDIO and
VSUPPLY can be powered in parallel. VSUPPLY must not exceed the
VDDIO voltage by greater than 0.5 V. If necessary, VDDIO can be
powered before VSUPPLY.
When disabling the internal LDO regulators and using an external
1.8 V supply to power V1P8ANA and V1P8DIG, tie VSUPPLY to ground,
and set V1P8ANA and V1P8DIG to the same final voltage level. In the
case of bypassing the LDOs, the recommended power sequence is
to apply power to VDDIO, followed by applying power to V1P8DIG
approximately 10 μs later, and then applying power to V1P8ANA
approximately 10 μs later. If necessary, V1P8DIG and VDDIO can be
powered from the same 1.8 V supply, which can also be tied to
V1P8ANA with proper isolation. In this case, proper decoupling
and low frequency isolation is important to maintain the noise
performance of the sensor.
POWER SUPPLY DESCRIPTION
The ADXL354/ADXL355 have four different power supply
domains: VSUPPLY, V1P8ANA, V1P8DIG, and VDDIO. The internal
analog and digital circuitry operates at 1.8 V nominal.
VSUPPLY
VSUPPLY is 2.25 V to 3.6 V, which is the input range to the two
LDO regulators that generate the nominal 1.8 V outputs for
V1P8ANA and V1P8DIG. Connect VSUPPLY to VSS to disable the LDO
regulators, which allows driving V1P8ANA and V1P8DIG from an
external source.
V1P8ANA
All sensor and analog signal processing circuitry operates in
this domain. Offset and sensitivity of the analog output
ADXL354 are ratiometric to this supply voltage. When using
external ADCs, use V1P8ANA as the reference voltage. The digital
output ADXL355 includes ADCs that are ratiometric to V1P8ANA,
thereby rendering offset and sensitivity insensitive to the value
of V1P8ANA. V1P8ANA can be an input or an output as defined by the
state of the VSUPPLY voltage.
V1P8DIG
V1P8DIG is the supply voltage for the internal logic circuitry. A
separate LDO regulator decouples the digital supply noise from
the analog signal path. V1P8ANA can be an input or an output as
defined by the state of the VSUPPLY voltage. If driven externally,
V1P8DIG must be the same voltage as the V1P8ANA voltage.
VDDIO
The VDDIO value determines the logic high levels. On the analog
output ADXL354, VDDIO sets the logic high level for the self test
pins, ST1 and ST2, as well as the STBY pin. On the digital output
ADXL355, VDDIO sets the logic high level for communications
interface ports, as well as the interrupt and DRDY outputs.
The LDO regulators are operational when VSUPPLY is between
2.25 V and 3.6 V. V1P8ANA and V1P8DIG are the regulator outputs in
this mode. Alternatively, when tying VSUPPLY to VSS, V1P8ANA and
V1P8DIG are supply voltage inputs with a 1.62 V to 1.98 V range.
OVERRANGE PROTECTION
The maximum nominal measurement range for the ADXL354/
ADXL355 is ±8 g. Do not subject the device to (or use the device
in) applications or assembly processes that reasonably expect to
exceed this level of acceleration, particularly for long durations
or on an ongoing basis. In such applications, the ADXL356/
ADXL357 offer higher g ranges that may be better suited for
such applications.
If an overrange event does occur, all sensor drive clocks turn off
for 0.5 ms to avoid electrostatic capture of the proof mass when
the accelerometer is subject to input acceleration beyond the
full-scale range. In the ±2 g/±2.048 g range setting, the overrange
protection activates for input signals beyond approximately ±8 g/
±8.192 g (±25%), and for the ±4 g/±4.096 g and ±8 g/±8.192 g
range settings, the threshold corresponds to about ±16 g (±25%).
When overrange protection occurs, the XOUT, YOUT, and ZOUT pins
on the ADXL354 begin to drive to midscale. The ADXL355 floats
toward zero, and the first in, first out (FIFO) begins filling with
this data.
SELF TEST
The ADXL354 and ADXL355 incorporate a self test feature
that effectively tests their mechanical and electronic systems
simultaneously. In ADXL354, drive the ST1 pin to VDDIO to
invoke self test mode. Then, by driving the ST2 pin to VDDIO,
the ADXL354 applies an electrostatic force to the mechanical
sensor and induces a change in output in response to the force.
The self test delta (or response) is the difference in output
voltages between when ST2 is high and ST2 is low, both when
ST1 is asserted. After the self test measurement is complete,
bring both pins low to resume normal operation.
The self test operation is similar in the ADXL355, except ST1
and ST2 can be accessed through the SELF_TEST register
(Register 0x2E).
The self test feature rejects externally applied acceleration and
only responds to the self test force, which allows an accurate
measurement of the self test, even in the presence of external
mechanical noise.
Data Sheet ADXL354/ADXL355
Rev. A | Page 23 of 42
FILTER
The ADXL354/ADXL355 use an analog, low-pass, antialiasing
filter to reduce out of band noise and to limit bandwidth. The
ADXL355 provides further digital filtering options to maintain
excellent noise performance at various ODRs.
The analog, low-pass antialiasing filter in the ADXL354/
ADXL355 provides a fixed bandwidth of approximately
1.5 kHz, which is where the output response is attenuated by
approximately 50%. The shape of the filter response in the
frequency domain is that of a sinc3 filter.
The ADXL354 x-axis, y-axis, and z-axis analog outputs include
an amplifier followed by a series 32 kΩ resistor and output to
the XOUT, the YOUT, and the ZOUT pins, respectively.
The ADXL355 provides an internal 20-bit, Σ-Δ ADC to digitize
the filtered analog signal. Additional digital filtering (beyond the
analog, low-pass, antialiasing filter) consists of a low-pass digital
decimation filter and a bypassable high-pass filter that supports
output data rates between 4 kHz and 3.9 Hz. The decimation
filter consists of two stages. The first stage is fixed decimation
with a 4 kHz ODR with a low-pass filter cutoff (50% reduction
in output response) at about 1 kHz. A variable second stage
decimation filter is used for the 2 kHz output data rate and below
(it is bypassed for 4 kHz ODR). Figure 60 shows the low-pass
filter response with a 1 kHz corner (4 kHz ODR) for the
ADXL355. Note that Figure 60 does not include the fixed
frequency analog, low-pass, antialiasing filter with a fixed
bandwidth of approximately 1.5 kHz.
14205-023
–70
–60
–50
–40
–30
–20
–10
0
1 10 100 10k1k
DIGITAL LP F RESPO NSE (dB)
INPUT FREQUENCY (Hz)
Figure 60. ADXL355 Digital Low-Pass Filter (LPF) Response for 4 kHz ODR
The ADXL355 pass band of the signal path relates to the
combined filter responses, including the analog filter previously
discussed, and the digital decimation filter/ODR setting. Table 9
shows the delay associated with the decimation filter for each
setting and provides the attenuation at the ODR/4 corner.
Table 9. Digital Filter Group Delay and Profile
Delay Attenuation
Programmed ODR (Hz) ODR (Cycles) Time (ms) Decimator at ODR/4 (dB) Full Path at ODR/4 (dB)
4000 2.52 0.63 −3.44 −3.63
4000/2 = 2000 2.00 1.00 −2.21 −2.26
4000/4 = 1000 1.78 1.78 −1.92 −1.93
4000/8 = 500 1.63 3.26 −1.83 −1.83
4000/16 = 250 1.57 6.27 −1.83 −1.83
4000/32 = 125 1.54 12.34 −1.83 −1.83
4000/64 = 62.5 1.51 24.18 −1.83 −1.83
4000/128 ~ 31 1.49 47.59 −1.83 −1.83
4000/256 ~ 16 1.50 96.25 −1.83 −1.83
4000/512 ~ 8 1.50 189.58 −1.83 −1.83
4000/1024 ~ 4 1.50 384.31 −1.83 −1.83
ADXL354/ADXL355 Data Sheet
Rev. A | Page 24 of 42
The ADXL355 also includes an optional digital high-pass filter
with a programmable corner frequency. By default, the high-
pass filter is disabled. The high pass corner frequency, where
the output is attenuated by 50%, is related to the ODR, and the
HPF_CORNER setting in the filter register (Register 0x28,
Bits[6:4]). Table 10 shows the HPF_CORNER response. Figure 61
and Figure 62 show the simulated high-pass filter response and
delay for a 10 Hz cutoff.
The ADXL355 also includes an interpolation filter after the
decimation filters to produce oversampled/upconverted data
that provides an external synchronization option. See the Data
Synchronization section for more details. Table 11 shows the
delay and attenuation relative to the programmed ODR.
AMPLITUDE REL
A
TIVE TO FULL SCALE (dB)
0
–3
–10
–20
–30
–40
–500 9.8801 100
FRE QUENCY (kHz)
14205-024
Figure 61. High-Pass Filter Pass-Band Response for a 4 kHz ODR and an
HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])
Group delay is the digital filter delay from the input to the ADC
until data is available at the interface (see the Filter section).
This delay is the largest component of the total delay from
sensor to serial interface.
DEL
A
Y (ODR CY CLES )
40
32.2122
30
20
10
1
00 9.8801 F RE QUENCY (k Hz )
14205-025
Figure 62. High-Pass Filter Delay Response for a 4 kHz ODR and an
HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])
Table 10. Digital High-Pass Filter Response
HPF_CORNER Register Setting
(Register 0x28, Bits[6:4]) HPF_CORNER Frequency, −3 dB Point Relative to ODR Setting −3 dB at 4 kHz ODR (Hz)
000 Not applicable, no high-pass filter enabled Off
001 24.7 × 10−4 × ODR 9.88
010 6.2084 × 10−4 × ODR 2.48
011 1.5545 × 10−4 × ODR 0.62
100 0.3862 × 10−4 × ODR 0.1545
101 0.0954 × 10−4 × ODR 0.03816
110 0.0238 × 10−4 × ODR 0.00952
Table 11. Combined Digital Interpolation Filter and Decimation Filter Response
Interpolator Data Rate Resolution
Relative to 64 × ODR (Hz)
Combined Interpolator/
Decimator Delay (ODR Cycles)
Combined Interpolator/
Decimator Delay (ms)
Combined Interpolator/Decimator
Output Attenuation at ODR/4 (dB)
64 × 4000 = 256000 3.51661 0.88 −6.18
64 × 2000 = 128000 3.0126 1.51 −4.93
64 × 1000 = 64000 2.752 2.75 −4.66
64 × 500 = 32000 2.6346 5.27 −4.58
64 × 250 = 16000 2.5773 10.31 −4.55
64 × 125 = 8000 2.5473 20.38 −4.55
64 × 62.5 = 4000 2.53257 40.52 −4.55
64 × 31.25 = 2000 2.52452 80.78 −4.55
64 × 15.625 = 1000 2.52045 161.31 −4.55
64 × 7.8125 = 500 2.5194 322.48 −4.55
64 × 3.90625 = 250 2.51714 644.39 −4.55
Data Sheet ADXL354/ADXL355
Rev. A | Page 25 of 42
SERIAL COMMUNICATIONS
The 4-wire serial interface communicates in either the SPI or
I2C protocol. It affectively autodetects the format being used,
requiring no configuration control to select the format.
SPI PROTOCOL
Wire the ADXL355 for SPI communication as shown in the
connection diagram in Figure 63. The SPI protocol timing is
shown in Figure 64 to Figure 67. The timing scheme follows the
clock polarity (CPOL) = 0 and clock phase (CPHA) = 0. The
SPI clock speed ranges from 100 kHz to 10 MHz.
PROCESSOR
CS
MOSI
MISO
SCLK
DOUT
DOUT
DIN
DOUT
ADXL355
14205-026
Figure 63. 4-Wire SPI Connection
RWA6 A5 A4 A3 A2 A1 A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CS
SCLK
MOSI
MISO D7 D6 D5 D4 D3 D2 D1 D0
14205-027
Figure 64. SPI Timing Diagram—Single-Byte Read
D7 D6 D5 D4 D3 D2 D1 D0
12345678910 11 12 13 14 15 16
SCLK
MOSI
MISO
RWA6 A5 A4 A3 A2 A1 A0
CS
14205-028
Figure 65. SPI Timing Diagram—Single-Byte Write
10 11 12 13 14 15 16 17123456789
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0D0 D7
BYTE 1 BYTE n
RWA6 A5 A4 A3 A2 A1 A0
SCLK
MOSI
MISO
CS
14205-029
Figure 66. SPI Timing Diagram—Multibyte Read
10 11 12 13 14 15 16 17
BYTE 1 BYTE n
123456789
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0D0 D7RWA6 A5 A4 A3 A2 A1 A0
SCLK
MOSI
MISO
CS
14205-030
Figure 67. SPI Timing Diagram—Multibyte Write
ADXL354/ADXL355 Data Sheet
Rev. A | Page 26 of 42
I2C PROTOCOL
Figure 68 to Figure 70 detail the I2C protocol timing. The I2C
interface can be used on most buses operating in I2C standard
mode (100 kHz), fast mode (400 kHz), fast mode plus (1 MHz),
and high speed mode (3.4 MHz). The ADXL355 I2C device ID
is as follows:
ASEL (pin) = 0, device address = 0x1D
ASEL (pin) = 1, device address = 0x53
READING ACCELERATION OR TEMPERATURE
DATA FROM THE INTERFACE
Acceleration data is left justified and has a register address
order of most significant data to least significant data, which
allows the user to use multibyte transfers and to take only as
much data as required—either 8 bits, 16 bits, or 20 bits plus the
marker. Temperature data is 12 bits unsigned, right justified.
The data in XDATA, YDATA, and ZDATA is always the most
recent available. It is not guaranteed that XDATA, YDATA, and
ZDATA form a set corresponding to one sample point in time.
The routine used to retrieve the data from the device controls
this data set continuity. If data transfers are initiated when the
DATA_RDY bit goes high and completes in a time
approximately equal to 1/ODR, XDATA, YDATA, and ZDATA
apply to the same data set.
For multibyte read or write transactions through either serial
interface, the internal register address autoincrements. When
the top of the register address range, 0x3FF, is reached the auto-
increment stops and does not wrap back to Hex Address 0x00.
The address autoincrement function disables when the FIFO
address is used, so that data can be read continuously from the
FIFO as a multibyte transaction. In cases where the starting
address of a multibyte transaction is less than the FIFO address,
the address autoincrements until reaching the FIFO address,
and then stops at the FIFO address.
10 11 12 13 14 15 16 17 18 19 28 2920 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37123456789
A60 A5A4A3A2A1A0 D60 D5D4D3D2D1D0AKAKAK A6 A5 A4 A3 A2 A1 A0
A6 A5 A4 A3 A2 A1 A0 RW
RW
SCL
START REPEAT
START
DEVICE ADDRESS
SINGL E BYTE READ
REG IST ER ADDRESS DEVICE ADDRE S S DATA BYTE
STOP
SDA
AK
INDICATE SDA IS
CONTRO LLED BY ADXL355
14205-031
Figure 68. I2C Timing Diagram—Single-Byte Read
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27123456789
START DEVI CE ADDRE SS REGI S TER ADDRES S DATA BYT E STOP
SCL
SDA A60 A5A4A3A2A1A0AK D6D7 D5 D4 D3 D2 D1 D0 AK
A6 A5 A4 A3 A2 A1 A0 RW AK
14205-032
Figure 69. I2C Timing Diagram—Single-Byte Write
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 19123456789
SCL
START
DEVI CE ADDRE SS REG IST ER ADDRESS DATA BY TE 1 DATA BYTE n
S
D
A
A60 A5A4A3A2A1A0AK D6D7 D5 D4 D3 D2 D1 D0 D7AK D0 AK D6D7 D5 D4 D3 D2 D1 D0 AK
A6 A5 A4 A3 A2 A1 A0 RW AK
14205-033
Figure 70. I2C Timing Diagram—Multibyte Write
Data Sheet ADXL354/ADXL355
Rev. A | Page 27 of 42
FIFO
FIFO operates in a stream mode, that is, when the FIFO
overruns new data overwrites the oldest data in the FIFO. A
read from the FIFO address guarantees that the three bytes
associated with the acceleration measurement on an axis all
pertain to the same measurement. The FIFO never overruns,
and data is always taken out in sets (multiples of three data
points).
There are 96 21-bit locations in the FIFO. Each location
contains 20 bits of data and a marker bit for the x-axis data. A
single-byte read from the FIFO address pops one location from
the FIFO. A multibyte read to the FIFO location pops the FIFO
on the read of the first byte and every third byte read thereafter.
Figure 71 shows the organization of the data in the FIFO. The
acceleration data is twos complement, 20-bit data. The FIFO
control logic inserts the two LSB reads on the interface. Bit 1
indicates that an attempt was made to read an empty FIFO, and
that the data is not valid acceleration data. Bit 0 is a marker bit
to identify the x-axis, which allows a user to verify that the
FIFO data was correctly read. An acceleration data point for a
given axis occupies one FIFO location. The read pointer, RD_PTR,
points to the oldest stored data that was not read already from
the interface (see Figure 71). There are no physical x-acceleration,
y-acceleration, or z-acceleration data registers. This data also comes
directly from the most recent data set in the FIFO, which points
to by the z pointer, Z_PTR, (see Figure 71).
0
Z17 Z16 Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0
Y3 Y2 Y1 Y0
0
DATA SET. SAMPLE POINT
IS THE S AME ACROSS
A SINGLE X-AXIS, Y-AXIS,
AND Z-AXIS DATA SET.
RD_PTR
Z_PTR
Z_PTR – 1
Z_PTR – 2
X-AX IS MARKER
VI RTUAL BI TS
(NOT ALLOCATED IN THE FIFO)
ACCEL E RATION DATA
ASCENDING SPI ADDRESSES
Z19 Z18
Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4Y19 Y18
1Z_PTR + 1 00000000 00000000 0000001
0
0
EMPTY INDICATOR
ASCENDING FIFO ADDRESSES
ASCENDING
SPI ADDRESSES
14205-035
Figure 71. FIFO Data Organization
ADXL354/ADXL355 Data Sheet
Rev. A | Page 28 of 42
INTERRUPTS
The status register (Register 0x04) contains five individual bits,
four of which can be mapped to either the INT1 pin, the INT2 pin,
or both. The polarity of the interrupt, active high or active low,
is also selectable via the INT_POL bit in the range (Register 0x2C)
register. In general, the status register clears when read, but this
is not the case if the condition that caused the interrupt persists
after the read of the register. The definition of persist varies
slightly in each case, but it is described in the following sections.
The DRDY pin is similar to an interrupt pins (INTx) but clears
very differently. This case is also described.
DATA_RDY
The DATA_RDY bit is set when new acceleration data is
available to the interface. It clears on a read of the status register.
It is not set again until acceleration data that is newer than the
status register read is available.
Special logic on the clear of the DATA_RDY bit covers the
corner case where new data arrives during the read of the status
register. In this case, the data ready condition may be missed
completely. This logic results in a delay of the clearing of
DATA_RDY of up to four 512 kHz cycles.
DRDY PIN
DATA is not a status register bit; it instead behaves similar to an
unmaskable interrupt. DRDY is set when new acceleration data
is available to the interface. It clears on a read of the FIFO, on a
read of XDATA, YDATA, or ZDATA, or by an autoclear
function that occurs approximately halfway between output
acceleration data sets.
DRDY is always active high. The INT_POL bit does not affect
DRDY. In EXT_SYNC modes, the first few DRDY pulses after
initial synchronization can be lost or corrupted. The length of
this potential corruption is less than the group delay.
FIFO_FULL
The FIFO_FULL bit is set when the entries in the FIFO are
equal to the setting of the FIFO_SAMPLES bits. It clears as
follows:
If the entries in the FIFO fall below the FIFO_SAMPLES,
which is only the case if sufficient data is read from the
FIFO.
On a read of the status register, but only if the entries in the
FIFO are less than the FIFO_SAMPLES bits.
FIFO_OVR
The FIFO_OVR bit is set when the FIFO is so far overrange that
data is lost. The specified size of the FIFO is 96 locations. There
is an additional three location buffer to compensate for delays
in the synchronization of the clock domains. It is only when
there is an attempt to write past this 99 location limit that
FIFO_OVR is set.
A read of the status register clears FIFO_OVR. It is not set again
until data is lost subsequent to this data register read.
ACTIVITY
The activity bit (Register 0x04, Bit 3) is set when the measured
acceleration on any axis is above the ACT_THRESH bits for
ACT_COUNT consecutive measurements. An over threshold
condition can shift from one axis to another on successive
measurements and is still counted toward the consecutive
ACT_COUNT count.
A read of the status register clears the activity bit (Register 0x04,
Bit 3), but it sets again at the end of the next measurement if the
activity bit (Register 0x04, Bit 3) conditions are still satisfied.
NVM_BUSY
The NVM_BUSY bit indicates that the nonvolatile memory
(NVM) controller is busy, and it cannot be accessed to read,
write, or generate an interrupt.
A status register read that occurs after the NVM controller is no
longer busy clears NVM_BUSY.
Data Sheet ADXL354/ADXL355
Rev. A | Page 29 of 42
EXTERNAL SYNCHRONIZATION AND
INTERPOLATION
There are three possible synchronization options for the ADXL355,
shown in Figure 72 to Figure 74. For clarity, the clock frequencies
and delays are drawn to scale. The labels in Figure 72 to Figure 74
are defined as follows:
Internal ODR is the alignment of the decimated output
data based on the internal clock.
ADC clock shows the internal master clock rate
DRDY is an output indicator signaling a sample is ready.
The three modes are include as follows:
No external synchronization (internal clocks used)
Synchronization with interpolation filter enabled
Sync with an external sync and clock signals, no
interpolation filter
EXT_SYNC = 00—No External Sync or Interpolation
For this case, an internal clock that serves as the synchronization
master generates the data. No external signals are required, and
this is used commonly when the external processor retrieves
data from the device asynchronously and absolute synchronization
to an external source is not required. Use Register 0x28 to program
the ODR.
The device outputs a DRDY (active high) to signal that a new
sample is available, and data is retrieved from the real-time
registers or the FIFO. The group delay is based on the
decimation setting as shown in Table 9.
EXT_SYNC = 10—External Sync with Interpolation
In this case, the internal clock generates data; however, an
interpolation filter provides additional time resolution of 64
times the programmed ODR. Synchronization using interpolation
filters and an external ODR clock is commonly used when the
external processor can provide a synchronization signal (which
is asynchronous to the internal clock) at the desired ODR.
Synchronization with the interpolation filter enabled
(EXT_SYNC = 10) allows the nonsynchronous external clock to
output data most closely associated with the external clock
rising edge. The interpolation filter provides a frequency
resolution related to ODR (see Table 11).
The advantage of this mode is that data is available at a user
defined sample rate and is asynchronous to the internal oscillator.
The disadvantage of this mode is that the group delay is increased,
and there is increased attenuation at the band edge. Additionally,
because there is a limit to the time resolution, there is some
distortion related to the mismatch of the external sync relative
to the internal oscillator. This mismatch degrades spectral
performance. The group delay is based on the decimation setting
and interpolation setting (see Table 11). Table 13 shows the delay
between the SYNC signal (input) to DRDY (output).
EXT_SYNC = 01—External Sync and External Clock
In this case, an external source provides an external clock at a
frequency of 4 × 64 × ODR. The external clock becomes the
master clock source for the device. In addition, an external
synchronization signal is needed to align the decimation filter
output to a specific clock edge, which provides full external
synchronization and is commonly used when a fixed external
clock captures and processes data, and asynchronous clock(s) are
not allowed. When using multiple sensors, synchronization with an
external master clock is beneficial and requires time alignment.
When configured for EXT_SYNC = 01 with an ODR of 4 kHz,
the user must supply an external clock at 1.024 MHz (64 × 4 ×
4 kHz) on the INT2 pin (Pin 13), and an external synchronization
on DRDY pin (Pin 14), as shown in Table 12.
Special restrictions when using this mode include the following:
An external clock (EXT_CLK) must be provided as well as
an external sync.
The frequency of EXT_CLK must be exactly 4 × 64 × ODR.
The width of sync must be a minimum of four EXT_CLK
periods.
The phase of sync must meet an approximate 25 ns setup
time to the EXT_CLK rising edge.
When using the EXT_SYNC mode and without providing sync,
the device runs on its own synchronization. Similarly, after
synchronization, the device continues to run synchronized to
the last sync pulse it received, which means that EXT_SYNC = 01
mode can be used with only a single synchronization pulse.
The interpolation filter provides a frequency resolution related to
the ODR (see Table 11). In this case, the data provided corresponds
to the external signal, which can be greater than the set ODR,
but the output pass band remains the same it was prior to the
interpolation filter.
Table 12. Multiplexing of INT2 and DRDY
Register or Bit Fields Pins
EXT_CLK EXT_SYNC[1:0] INT_MAP[7:4] INT2 (Pin 13) DRDY (Pin 14) Comments
0 00 0000 Low DRDY Synchronization is to the internal clocks, and there is
no external clock synchronization.
0 00 Not 0000 INT2 DRDY
1 00 0000 EXT_CLK DRDY
1 00 Not 00002 EXT_CLK DRDY
0 01 0000 DRDY SYNC These options reset the digital filters on every
synchronization pulse and are not recommended.
0 011 Not 0000 INT2 SYNC
ADXL354/ADXL355 Data Sheet
Rev. A | Page 30 of 42
Register or Bit Fields Pins
EXT_CLK EXT_SYNC[1:0] INT_MAP[7:4] INT2 (Pin 13) DRDY (Pin 14) Comments
1 011 0000 EXT_CLK SYNC
External synchronization, no interpolation filter, and
DRDY (active high) signals that data is ready. Data
represents a sample point group delay earlier in time.
1 011 Not 00002 EXT_CLK SYNC
0 10 0000 DRDY SYNC External synchronization, interpolation filter, and
DRDY (active high) signals that data is ready. Data
sample group delay earlier in time.
0 101 Not 0000 INT2 SYNC
1 101 0000 EXT_CLK SYNC
1 101 Not 0000 EXT_CLK SYNC
1 No DRDY.
2 No INT2, even though it is enabled.
INTERNA L ODR
GROUP DEL
A
Y
(FIX ED RELATI VE TO DRDY)
SAMPLE POINT
ADC MOD. CL K.
64× ODR
DRDY
14205-036
Figure 72. External Synchronization Option—EXT_SYNC = 00, Internal Sync
INT E RNAL ODR
INTERPOLATOR
64× ODR
DRDY
GROUP DEL
A
Y
(FIX ED RELATI VE TO SYNC) INTE RFACE SYNCHRONIZATI O N DELAYSAMPLE POINT
SYNC
110% ODR
14205-037
Figure 73. External Synchronization Option—EXT_SYNC = 10, External Sync, External Clock, Interpolation Filter
INTERNAL ODR
DRDY
GROUP DEL
A
Y
(FI X ED RELAT I VE TO SYNC)
SAMPLE POINT
LOST SAMPL E
SYNCHRONIZE
EXT_CLK
(4 × 64) × SYN C
SYNC
14205-038
Figure 74. External Synchronization Option—EXT_SYNC = 01, External Sync, No Interpolation Filter
Table 13. EXT_SYNC = 10, DRDY Delay
ODR_LPF Delay (OSC Cycles)
0x0 8
0x1 10
0x2 14
0x3 22
0x4 38
0x5 70
0x6 134
0x7 262
0x8 1031
0x9 2054
0x10 4102
Data Sheet ADXL354/ADXL355
Rev. A | Page 31 of 42
ADXL355 REGISTER MAP
Note that while configuring the ADXL355 in an application, all configuration registers must be programmed before enabling measurement
mode in the POWER_CTL register. When the ADXL355 is in measurement mode, only the following configurations can change: the
HPF_CORNER bits in the filter register, the INT_MAP register, the ST1 and ST2 bits in the SELF_TEST register, and the reset register.
Table 14. ADXL355 Register Map
Hex. Addr. Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W
0x00 DEVID_AD DEVID_AD 0xAD R
0x01 DEVID_MST DEVID_MST 0x1D R
0x02 PARTID PARTID 0xED R
0x03 REVID REVID 0x01 R
0x04 Status Reserved NVM_BUSY Activity FIFO_OVR FIFO_FULL DATA_RDY 0x00 R
0x05 FIFO_ENTRIES Reserved FIFO_ENTRIES 0x00 R
0x06 TEMP2 Reserved Temperature, Bits[11:8] 0x00 R
0x07 TEMP1 Temperature, Bits[7:0] 0x00 R
0x08 XDATA3 XDATA, Bits[19:12] 0x00 R
0x09 XDATA2 XDATA, Bits[11:4] 0x00 R
0x0A XDATA1 XDATA, Bits[3:0] Reserved 0x00 R
0x0B YDATA3 YDATA, Bits[19:12] 0x00 R
0x0C YDATA2 YDATA, Bits[11:4] 0x00 R
0x0D YDATA1 YDATA, Bits[3:0] Reserved 0x00 R
0x0E ZDATA3 ZDATA, Bits[19:12] 0x00 R
0x0F ZDATA2 ZDATA, Bits[11:4] 0x00 R
0x10 ZDATA1 ZDATA, Bits[3:0] Reserved 0x00 R
0x11 FIFO_DATA FIFO_DATA 0x00 R
0x1E OFFSET_X_H OFFSET_X, Bits[15:8] 0x00 R/W
0x1F OFFSET_X_L OFFSET_X, Bits[7:0] 0x00 R/W
0x20 OFFSET_Y_H OFFSET_Y, Bits[15:8] 0x00 R/W
0x21 OFFSET_Y_L OFFSET_Y, Bits[7:0] 0x00 R/W
0x22 OFFSET_Z_H OFFSET_Z, Bits[15:8] 0x00 R/W
0x23 OFFSET_Z_L OFFSET_Z, Bits[7:0] 0x00 R/W
0x24 ACT_EN Reserved ACT_Z ACT_Y ACT_X 0x00 R/W
0x25 ACT_THRESH_H ACT_THRESH, Bits[15:8] 0x00 R/W
0x26 ACT_THRESH_L ACT_THRESH, Bits[7:0] 0x00 R/W
0x27 ACT_COUNT ACT_COUNT 0x01 R/W
0x28 Filter Reserved HPF_CORNER ODR_LPF 0x00 R/W
0x29 FIFO_SAMPLES Reserved FIFO_SAMPLES 0x60 R/W
0x2A INT_MAP ACT_EN2 OVR_EN2 FULL_EN2 RDY_EN2 ACT_EN1 OVR_EN1 FULL_EN1 RDY_EN1 0x00 R/W
0x2B Sync Reserved EXT_CLK EXT_SYNC 0x00 R/W
0x2C Range I2C_HS INT_POL Reserved Range 0x81 R/W
0x2D POWER_CTL Reserved DRDY_OFF TEMP_OFF STANDBY 0x01 R/W
0x2E SELF_TEST Reserved ST2 ST1 0x00 R/W
0x2F Reset Reset 0x00 W
ADXL354/ADXL355 Data Sheet
Rev. A | Page 32 of 42
REGISTER DEFINITIONS
This section describes the functions of the ADXL355 registers. The ADXL355 powers up with the default register values, as shown in the
Reset column of Table 14.
ANALOG DEVICES ID REGISTER
This register contains the Analog Devices ID, 0xAD.
Address: 0x00, Reset: 0xAD, Name: DEVID_AD
Table 15. Bit Descriptions for DEVID_AD
Bits Bit Name Settings Description Reset Access
[7:0] DEVID_AD Analog Devices ID 0xAD R
ANALOG DEVICES MEMS ID REGISTER
This register contains the Analog Devices MEMS ID, 0x1D.
Address: 0x01, Reset: 0x1D, Name: DEVID_MST
Table 16. Bit Descriptions for DEVID_MST
Bits Bit Name Settings Description Reset Access
[7:0] DEVID_MST Analog Devices MEMS ID 0x1D R
DEVICE ID REGISTER
This register contains the device ID, 0xED (355 octal).
Address: 0x02, Reset: 0xED, Name: PARTID
Table 17. Bit Descriptions for PARTID
Bits Bit Name Settings Description Reset Access
[7:0] PARTID Device ID (355 octal) 0xED R
PRODUCT REVISION ID REGISTER
This register contains the product revision ID, beginning with 0x00 and incrementing for each subsequent revision.
Address: 0x03, Reset: 0x00, Name: REVID
Table 18. Bit Descriptions for REVID
Bits Bit Name Settings Description Reset Access
[7:0] REVID Mask revision 0x01 R
STATUS REGISTER
This register includes bits that describe the various conditions of the ADXL355.
Address: 0x04, Reset: 0x00, Name: STATUS
Table 19. Bit Descriptions for STATUS
Bits Bit Name Settings Description Reset Access
[7:5] Reserved Reserved. 0x0 R
4 NVM_BUSY NVM controller is busy with either refresh, programming, or built-in, self test (BIST). 0x0 R
3 Activity Activity, as defined in the THRESH_ACT and COUNT_ACT registers, is detected. 0x0 R
2 FIFO_OVR FIFO has overrun, and the oldest data is lost. 0x0 R
1 FIFO_FULL FIFO watermark is reached. 0x0 R
0 DATA_RDY A complete x-axis, y-axis, and z-axis measurement was made and results can be read. 0x0 R
Data Sheet ADXL354/ADXL355
Rev. A | Page 33 of 42
FIFO ENTRIES REGISTER
This register indicates the number of valid data samples present in the FIFO buffer. This number ranges from 0 to 96.
Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES
Table 20. Bit Descriptions for FIFO_ENTRIES
Bits Bit Name Settings Description Reset Access
7 Reserved Reserved 0x0 R
[6:0] FIFO_ENTRIES Number of data samples stored in the FIFO 0x0 R
TEMPERATURE DATA REGISTERS
These two registers contain the uncalibrated temperature data. The nominal intercept is 1852 LSB at 25°C and the nominal slope is
−9.05 LSB/°C. TEMP2 contains the four most significant bits, and TEMP1 contains the eight least significant bits of the 12-bit value.
Address: 0x06, Reset: 0x00, Name: TEMP2
Table 21. Bit Descriptions for TEMP2
Bits Bit Name Settings Description Reset Access
[7:4] Reserved Reserved.
[3:0] Temperature, Bits[11:8] Uncalibrated temperature data 0x0 R
Address: 0x07, Reset: 0x00, Name: TEMP1
Table 22. Bit Descriptions for TEMP1
Bits Bit Name Settings Description Reset Access
[7:0] Temperature, Bits[7:0] Uncalibrated temperature data 0x0 R
X-AXIS DATA REGISTERS
These three registers contain the x-axis acceleration data. Data is left justified and formatted as twos complement.
Address: 0x08, Reset: 0x00, Name: XDATA3
Table 23. Bit Descriptions for XDATA3
Bits Bit Name Settings Description Reset Access
[7:0] XDATA, Bits[19:12] X-axis data 0x0 R
Address: 0x09, Reset: 0x00, Name: XDATA2
Table 24. Bit Descriptions for XDATA2
Bits Bit Name Settings Description Reset Access
[7:0] XDATA, Bits[11:4] X-axis data 0x0 R
Address: 0x0A, Reset: 0x00, Name: XDATA1
Table 25. Bit Descriptions for XDATA1
Bits Bit Name Settings Description Reset Access
[7:4] XDATA, Bits[3:0] X-axis data 0x0 R
[3:0] Reserved Reserved 0x0 R
ADXL354/ADXL355 Data Sheet
Rev. A | Page 34 of 42
Y-AXIS DATA REGISTERS
These three registers contain the y-axis acceleration data. Data is left justified and formatted as twos complement.
Address: 0x0B, Reset: 0x00, Name: YDATA3
Table 26. Bit Descriptions for YDATA3
Bits Bit Name Settings Description Reset Access
[7:0] YDATA, Bits[19:12] Y-axis data 0x0 R
Address: 0x0C, Reset: 0x00, Name: YDATA2
Table 27. Bit Descriptions for YDATA2
Bits Bit Name Settings Description Reset Access
[7:0] YDATA, Bits[11:4] Y-axis data 0x0 R
Address: 0x0D, Reset: 0x00, Name: YDATA1
Table 28. Bit Descriptions for YDATA1
Bits Bit Name Settings Description Reset Access
[7:4] YDATA, Bits[3:0] Y-axis data 0x0 R
[3:0] Reserved Reserved 0x0 R
Z-AXIS DATA REGISTERS
These three registers contain the z-axis acceleration data. Data is left justified and formatted as twos complement.
Address: 0x0E, Reset: 0x00, Name: ZDATA3
Table 29. Bit Descriptions for ZDATA3
Bits Bit Name Settings Description Reset Access
[7:0] ZDATA, Bits[19:12] Z-axis data 0x0 R
Address: 0x0F, Reset: 0x00, Name: ZDATA2
Table 30. Bit Descriptions for ZDATA2
Bits Bit Name Settings Description Reset Access
[7:0] ZDATA, Bits[11:4] Z-axis data 0x0 R
Address: 0x10, Reset: 0x00, Name: ZDATA1
Table 31. Bit Descriptions for ZDATA1
Bits Bit Name Settings Description Reset Access
[7:4] ZDATA, Bits[3:0] Z-axis data 0x0 R
[3:0] Reserved Reserved 0x0 R
Data Sheet ADXL354/ADXL355
Rev. A | Page 35 of 42
FIFO ACCESS REGISTER
Address: 0x11, Reset: 0x00, Name: FIFO_DATA
Read this register to access data stored in the FIFO.
Table 32. Bit Descriptions for FIFO_DATA
Bits Bit Name Settings Description Reset Access
[7:0] FIFO_DATA FIFO data is formatted to 24 bits, 3 bytes, most significant byte first. A read to this
address pops an effective three equal byte words of axis data from the FIFO. Two
subsequent reads or a multibyte read completes the transaction of this data onto the
interface. Continued reading or a sustained multibyte read of this field continues to
pop the FIFO every third byte. Multibyte reads to this address do not increment the
address pointer. If this address is read due to an autoincrement from the previous
address, it does not pop the FIFO. Instead, it returns zeros and increments on to the
next address.
0x0 R
X-AXIS OFFSET TRIM REGISTERS
Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H
Table 33. Bit Descriptions for OFFSET_X_H
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_X,
Bits[15:8]
Offset added to x-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_X[15:0] matches the significance of XDATA[19:4].
0x0 R/W
Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L
Table 34. Bit Descriptions for OFFSET_X_L
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_X,
Bits[7:0]
Offset added to x-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_X[15:0] matches the significance of XDATA[19:4].
0x0 R/W
Y-AXIS OFFSET TRIM REGISTERS
Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H
Table 35. Bit Descriptions for OFFSET_Y_H
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_Y,
Bits[15:8]
Offset added to y-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Y[15:0] matches the significance of YDATA[19:4].
0x0 R/W
Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L
Table 36. Bit Descriptions for OFFSET_Y_L
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_Y,
Bits[7:0]
Offset added to y-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Y[15:0] matches the significance of YDATA[19:4].
0x0 R/W
ADXL354/ADXL355 Data Sheet
Rev. A | Page 36 of 42
Z-AXIS OFFSET TRIM REGISTERS
Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H
Table 37. Bit Descriptions for OFFSET_Z_H
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_Z,
Bits[15:8]
Offset added to z-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Z[15:0] matches the significance of ZDATA[19:4].
0x0 R/W
Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L
Table 38. Bit Descriptions for OFFSET_Z_L
Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_Z,
Bits[7:0]
Offset added to z-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Z[15:0] matches the significance of ZDATA[19:4].
0x0 R/W
ACTIVITY ENABLE REGISTER
Address: 0x24, Reset: 0x00, Name: ACT_EN
Table 39. Bit Descriptions for ACT_EN
Bits Bit Name Settings Description Reset Access
[7:3] Reserved Reserved. 0x0 R
2 ACT_Z Z-axis data is a component of the activity detection algorithm. 0x0 R/W
1 ACT_Y Y-axis data is a component of the activity detection algorithm. 0x0 R/W
0 ACT_X X-axis data is a component of the activity detection algorithm. 0x0 R/W
ACTIVITY THRESHOLD REGISTERS
Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H
Table 40. Bit Descriptions for ACT_THRESH_H
Bits Bit Name Settings Description Reset Access
[7:0] ACT_THRESH[15:8]
Threshold for activity detection. Acceleration magnitude must be above
ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned
magnitude. The significance of ACT_TRESH[15:0] matches the significance of
XDATA, YDATA, and ZDATA[18:3].
0x0 R/W
Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L
Table 41. Bit Descriptions for THRESH_ACT_X_L
Bits Bit Name Settings Description Reset Access
[7:0] ACT_THRESH[7:0]
Threshold for activity detection. Acceleration magnitude must be above
ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned
magnitude. The significance of ACT_TRESH[15:0] matches the significance of
XDATA, YDATA, and ZDATA[18:3].
0x0 R/W
ACTIVITY COUNT REGISTER
Address: 0x27, Reset: 0x01, Name: ACT_COUNT
Table 42. Bit Descriptions for ACT_COUNT
Bits Bit Name Settings Description Reset Access
[7:0] ACT_COUNT Number of consecutive events above threshold required to detect activity 0x1 R/W
Data Sheet ADXL354/ADXL355
Rev. A | Page 37 of 42
FILTER SETTINGS REGISTER
Address: 0x28, Reset: 0x00, Name: Filter
Use this register to specify parameters for the internal high-pass and low-pass filters.
Table 43. Bit Descriptions for Filter
Bits Bit Name Settings Description Reset Access
7 Reserved Reserved 0x0 R
[6:4] HPF_CORNER −3 dB filter corner for the first-order, high-pass filter relative to the ODR 0x0 R/W
000 Not applicable, no high-pass filter enabled
001 247 × 10−3 × ODR
010 62.084 × 10−3 × ODR
011 15.545 × 10−3 × ODR
100 3.862 × 10−3 × ODR
101 0.954 × 10−3 × ODR
110 0.238 × 10−3 × ODR
[3:0] ODR_LPF ODR and low-pass filter corner 0x0 R/W
0000 4000 Hz and 1000 Hz
0001 2000 Hz and 500 Hz
0010 1000 Hz and 250 Hz
0011 500 Hz and 125 Hz
0100 250 Hz and 62.5 Hz
0101 125 Hz and 31.25 Hz
0110 62.5 Hz and 15.625 Hz
0111 31.25 Hz and 7.813 Hz
1000 15.625 Hz and 3.906 Hz
1001 7.813 Hz and 1.953 Hz
1010 3.906 Hz and 0.977 Hz
FIFO SAMPLES REGISTER
Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES
Use the FIFO_SAMPLES value to specify the number of samples to store in the FIFO. The default value of this register is 0x60 to avoid
triggering the FIFO watermark interrupt.
Table 44. Bit Descriptions for FIFO_SAMPLES
Bits Bit Name Settings Description Reset Access
7 Reserved Reserved. 0x0 R
[6:0] FIFO_SAMPLES Watermark number of samples stored in the FIFO that triggers a FIFO_FULL condition.
Values range from 1 to 96.
0x60 R/W
INTERRUPT PIN (INTx) FUNCTION MAP REGISTER
Address: 0x2A, Reset: 0x00, Name: INT_MAP
The INT_MAP register configures the interrupt pins. Bits[7:0] select which function(s) generate an interrupt on the INT1 and INT2 pins.
Multiple events can be configured. If the corresponding bit is set to 1, the function generates an interrupt on the interrupt pins.
Table 45. Bit Descriptions for INT_MAP
Bits Bit Name Settings Description Reset Access
7 ACT_EN2 Activity interrupt enable on INT2 0x0 R/W
6 OVR_EN2 FIFO_OVR interrupt enable on INT2 0x0 R/W
5 FULL_EN2 FIFO_FULL interrupt enable on INT2 0x0 R/W
4 RDY_EN2 DATA_RDY interrupt enable on INT2 0x0 R/W
3 ACT_EN1 Activity interrupt enable on INT1 0x0 R/W
2 OVR_EN1 FIFO_OVR interrupt enable on INT1 0x0 R/W
1 FULL_EN1 FIFO_FULL interrupt enable on INT1 0x0 R/W
0 RDY_EN1 DATA_RDY interrupt enable on INT1 0x0 R/W
ADXL354/ADXL355 Data Sheet
Rev. A | Page 38 of 42
DATA SYNCHRONIZATION
Address: 0x2B, Reset: 0x00, Name: Sync
Use this register to control the external timing triggers.
Table 46. Bit Descriptions for Sync
Bits Bit Name Settings Description Reset Access
[7:3] Reserved Reserved. 0x0 R
2 EXT_CLK Enable external clock. 0x0 R/W
[1:0] EXT_SYNC Enable external sync control. 0x0 R/W
00 Internal sync.
01
External sync, no interpolation filter. After synchronization, and for EXT_SYNC within
specification, DATA_RDY occurs on EXT_SYNC.
10
External sync, interpolation filter, next available data indicated by DATA_RDY 14 to
8204 oscillator cycles later (longer delay for higher ODR_LPF setting), data represents
a sample point group delay earlier in time.
11 Reserved.
I2C SPEED, INTERRUPT POLARITY, AND RANGE REGISTER
Address: 0x2C, Reset: 0x81, Name: Range
Table 47. Bit Descriptions for Range
Bits Bit Name Settings Description Reset Access
7 I2C_HS I2C speed. 0x1 R/W
1 = high speed mode.
0 = fast mode.
6 INT_POL Interrupt polarity. 0x0 R/W
0 INT1 and INT2 are active low.
1 INT1 and INT2 are active high.
[5:2] Reserved Reserved. 0x0 R
[1:0] Range Range. 0x1 R/W
01 ±2 g.
10 ±4 g.
11 ±8 g.
POWER CONTROL REGISTER
Address: 0x2D, Reset: 0x01, Name: POWER_CTL
Table 48. Bit Descriptions for POWER_CTL
Bits Bit Name Settings Description Reset Access
[7:3] Reserved Reserved. 0x0 R
2 DRDY_OFF Set to 1 to force the DRDY output to 0 in modes where it is normally signal data ready. 0x0 R/W
1 TEMP_OFF
Set to 1 to disable temperature processing. Temperature processing is also disabled
when STANDBY = 1.
0x0 R/W
0 STANDBY Standby or measurement mode. 0x1 R/W
1
Standby mode. In standby mode, the device is in a low power state, and the
temperature and acceleration datapaths are not operating. In addition, digital
functions, including FIFO pointers, reset. Changes to the configuration setting of the
device must be made when STANDBY = 1. An exception is a high-pass filter that can
be changed when the device is operating.
0 Measurement mode.
Data Sheet ADXL354/ADXL355
Rev. A | Page 39 of 42
SELF TEST REGISTER
Address: 0x2E, Reset: 0x00, Name: SELF_TEST
Refer to the Self Test section for more information on the operation of the self test feature.
Table 49. Bit Descriptions for SELF_TEST
Bits Bit Name Settings Description Reset Access
[7:2] Reserved Reserved. 0x0 R
1 ST2 Set to 1 to enable self test force 0x0 R/W
0 ST1 Set to 1 to enable self test mode 0x0 R/W
RESET REGISTER
Address: 0x2F, Reset: 0x00, Name: Reset
Table 50. Bit Descriptions for Reset
Bits Bit Name Settings Description Reset Access
[7:0] Reset Write Code 0x52 to resets the device, similar to a power-on reset (POR) 0x0 W
ADXL354/ADXL355 Data Sheet
Rev. A | Page 40 of 42
RECOMMENDED SOLDERING PROFILE
Figure 75 and Table 51 provide details about the recommended soldering profile.
t
P
t
L
t
25°C TO PEAK
t
S
PREHEAT
CRITICAL Z ONE
T
L
TO T
P
TEMPERATURE
TIME
RAMP-DOWN
RAMP-UP
T
SMIN
T
SMAX
T
P
T
L
14205-039
Figure 75. Recommended Soldering Profile
Table 51. Recommended Soldering Profile
Condition
Profile Feature Sn63/Pb37 Pb-Free
Average Ramp Rate from Liquid Temperature (TL) to Peak Temperature (TP) 3°C/sec maximum 3°C/sec maximum
Preheat
Minimum Temperature (TSMIN) 100°C 150°C
Maximum Temperature (TSMAX) 150°C 200°C
Time from TSMIN to TSMAX (tS) 60 sec to 120 sec 60 sec to 180 sec
TSMAX to TL Ramp-Up Rate 3°C/sec maximum 3°C/sec maximum
Liquid Temperature (TL) 183°C 217°C
Time Maintained Above TL (tL) 60 sec to 150 sec 60 sec to 150 sec
Peak Temperature (TP) 240°C + 0°C/−5°C 260°C + 0°C/−5°C
Time of Actual TP − 5°C (tP) 10 sec to 30 sec 20 sec to 40 sec
Ramp-Down Rate 6°C/sec maximum 6°C/sec maximum
Time from 25°C to Peak Temperature (t25°C TO PEAK) 6 minutes maximum 8 minutes maximum
ADXL354/ADXL355 Data Sheet
Rev. A | Page 42 of 42
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
BO T T OM VI E W
SIDE VIEW
TOP VIEW
0.510 REF
2.20 REF
3.81
REF
2.54 REF 0.914
BSC
0.508
BSC
0.80
BSC
6.25
6.00 SQ
5.85
05-27-2016-B
2.25
2.05
1.85
1
4
57
8
11 12 14
R 0.103
(14 PLCS)
R 0.203
(14 PLCS)
R 0.25
(4 PLCS) 0.10 BS C
5.60
SQ
0.15
BSC
0.30 SQ
(PIN 1 INDEX)
PKG-004554
1.674 BS C
DETAIL A
DETAIL A
Figure 77. 14-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-14-1)
Dimensions shown in millimeters
BRANDING INFORMATION
ADXL 354 B, ADXL354C, O R ADXL3 55B
#YYWW
PI N ONE LO CATOR, NO O THER BRA ND ON THI S LI NE
6 DIGI T L OT NUMBER
PART NUM BER
TWO DIGITYEAR, TWO DIGIT WEEK ID
SIX DIGIT LOT NUMBER
NO BRAND O N THIS LI NE
14205-078
Figure 78. Branding Information
ORDERING GUIDE
Model1
Output
Mode
Measurement
Range (g)
Specified
Voltage (V) Temperature Range Package Description
Package
Option
ADXL354BEZ Analog ±2, ±4 3.3 −40°C to +125°C 14-Terminal LCC E-14-1
ADXL354BEZ-RL Analog ±2, ±4 3.3 −40°C to +125°C 14-Terminal LCC E-14-1
ADXL354BEZ-RL7 Analog ±2, ±4 3.3 −40°C to +125°C 14-Terminal LCC E-14-1
ADXL354CEZ Analog ±2, ±8 3.3 −40°C to +125°C 14-Terminal LCC E-14-1
ADXL354CEZ-RL Analog ±2, ±8 3.3 −40°C to +125°C 14-Terminal LCC E-14-1
ADXL354CEZ-RL7 Analog ±2, ±8 3.3 −40°C to +125°C 14-Terminal LCC E-14-1
ADXL355BEZ Digital
±2.048, ±4.096,
±8.192
3.3 −40°C to +125°C 14-Terminal LCC E-14-1
ADXL355BEZ-RL Digital ±2.048, ±4.096,
±8.192
3.3 −40°C to +125°C 14-Terminal LCC E-14-1
ADXL355BEZ-RL7 Digital ±2.048, ±4.096,
±8.192
3.3 −40°C to +125°C 14-Terminal LCC E-14-1
EVAL-ADXL354BZ Evaluation Board for ADXL354BEZ
EVAL-ADXL354CZ Evaluation Board for ADXL354CEZ
EVAL-ADXL355Z Evaluation Board for ADXL355BEZ
1 Z = RoHS-Compliant Part.
©2016–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14205-0-4/18(A)
