Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 LMH6552 1.5-GHz Fully Differential Amplifier 1 Features * 1 * * * * * * * 3 Description The LMH6552 device is a high-performance, fully differential amplifier designed to provide the exceptional signal fidelity and wide large-signal bandwidth necessary for driving 8-bit to 14-bit highspeed data acquisition systems. Using TI's proprietary differential current mode input stage architecture, the LMH6552 allows operation at gains greater than unity without sacrificing response flatness, bandwidth, harmonic distortion, or output noise performance. 1.5-GHz -3 dB Small Signal Bandwidth at AV = 1 1.25-GHz -3 dB Large Signal Bandwidth at AV = 1 800-MHz Bandwidth at AV = 4 450-MHz 0.1 dB Flatness 3800-V/s Slew Rate 10-ns Settling Time to 0.1% - -90 dB THD at 20 MHz - -74 dB THD at 70 MHz 20-ns Enable/Shutdown Pin 5-V to 12-V Operation With external gain set resistors and integrated common mode feedback, the LMH6552 can be configured as either a differential input to differential output or single-ended input to differential output gain block. The LMH6552 can be AC- or DC-coupled at the input which makes it suitable for a wide range of applications, including communication systems and high-speed oscilloscope front ends. The performance of the LMH6552 driving an ADC14DS105 device is 86 dBc SFDR and 74 dBc SNR up to 40 MHz. 2 Applications * * * * * * * * Differential ADC Driver Video Over Twisted Pair Differential Line Driver Single End to Differential Converter High-Speed Differential Signaling IF/RF Amplifier Level Shift Amplifier SAW Filter Buffer/Driver The LMH6552 is available in an 8-pin SOIC package as well as a space-saving, thermally enhanced 8-pin WSON package for higher performance. Device Information(1) PART NUMBER PACKAGE LMH6552 BODY SIZE (NOM) SOIC (8) 4.90 mm x 3.91 mm WSON (8) 3.00 mm x 2.50 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application Schematic 274: 50: Single-Ended AC-coupled Source 127: 68.1: - 0.1 PF 100: 620 nH + LMH6552 + 49.9: ADC14DS105 + V 127: 22 pF - V 100: 620 nH 14-Bit 105 MSPS VREF 68.1: 274: Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 7 9 Detailed Description ............................................ 16 7.1 7.2 7.3 7.4 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics: 5 V ................................. Electrical Characteristics: 2.5 V .............................. Typical Characteristics V+ = +5 V, V- = -5 V ........... Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 16 16 16 17 Application and Implementation ........................ 17 8.1 Application Information............................................ 17 8.2 Typical Applications ................................................ 17 9 Power Supply Recommendations...................... 26 9.1 Power Supply Bypassing ........................................ 26 10 Layout................................................................... 27 10.1 10.2 10.3 10.4 10.5 Layout Guidelines ................................................. Layout Example .................................................... Thermal Considerations ........................................ Power Dissipation ................................................. ESD Protection...................................................... 27 28 29 29 30 11 Device and Documentation Support ................. 31 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 31 31 31 31 31 31 12 Mechanical, Packaging, and Orderable Information ........................................................... 31 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (January 2015) to Revision J Page * Changed footnote 4 in Electrical Characteristics: 5 V table ................................................................................................. 5 * Changed Miscellaneous Performance, Enable Voltage Threshold parameter minimum specification in Electrical Characteristics: 5 V table...................................................................................................................................................... 6 * Changed footnote 4 in Electrical Characteristics: 2.5 V table ............................................................................................. 7 * Changed minimum specifications of Miscellaneous Performance, Enable Voltage Threshold and Disable Voltage Threshold parameters in Electrical Characteristics: 2.5 V table .......................................................................................... 8 * Added Community Resources section ................................................................................................................................ 31 Changes from Revision H (March 2013) to Revision I * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Changes from Revision G (March 2013) to Revision H * 2 Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 27 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 5 Pin Configuration and Functions D Package 8 Pins Top View 1 8 +IN -IN - 2 + 7 VCM 3 6 4 5 EN V- V+ +OUT -OUT NGS Package 8 Pins Top View - IN 1 8 + IN VCM 2 7 EN V+ 3 6 V- + OUT 4 5 - OUT DAP Pin Functions PIN NAME DESCRIPTION NO. EN 7 Enable -IN 1 Negative Input +IN 8 Positive Input -OUT 5 Negative Output +OUT 4 Positive Output V- 6 Negative Supply V+ 3 Positive Supply VCM 2 Output Common Mode Control DAP DAP Die Attach Pad (See Thermal Considerations for more information) Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 3 LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) MAX UNIT Supply Voltage MIN 13.2 V Common Mode Input Voltage VS V Maximum Input Current (pins 1, 2, 7, 8) 30 mA (3) Maximum Output Current (pins 4, 5) mA Maximum Junction Temperature -65 Storage temperature, Tstg (1) (2) (3) 150 C 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. For soldering specifications see SNOA549 The maximum output current (IOUT) is determined by device power dissipation limitations. See Power Dissipation for more details. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 750 Machine model (MM) 250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN Operating Temperature Range (1) Total Supply Voltage (1) MAX UNIT -40 NOM +85 C 4.5 12 V The maximum power dissipation is a function of TJ(MAX), JA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX)- TA) / JA. All numbers apply for packages soldered directly onto a PC Board. 6.4 Thermal Information LMH6552 THERMAL METRIC (1) RJA (1) 4 Junction-to-ambient thermal resistance D NGS 8 PINS 8 PINS 150 58 UNIT C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 6.5 Electrical Characteristics: 5 V Unless otherwise specified, all limits are ensured for TA = 25C, V+ = +5 V, V- = -5 V, AV= 1, VCM = 0 V, RF = RG = 357 , RL = 500 , for single ended in, differential out. (1) PARAMETER MIN (2) TEST CONDITIONS TYP (3) MAX (2) UNIT AC PERFORMANCE (DIFFERENTIAL) SSBW Small Signal -3-dB Bandwidth (2) VOUT = 0.2 VPP, AV = 1, RL = 1 k 1500 VOUT = 0.2 VPP, AV = 1 1000 VOUT = 0.2 VPP, AV = 2 930 VOUT = 0.2 VPP, AV = 4 810 VOUT = 0.2 VPP, AV = 8 LSBW Large Signal -3 dB Bandwidth 590 VOUT = 2 VPP, AV = 1, RL = 1 k 1250 VOUT = 2 VPP, AV = 1 950 VOUT = 2 VPP, AV = 2 820 VOUT = 2 VPP, AV = 4 740 VOUT = 2 VPP, AV = 8 590 0.1-dB Bandwidth VOUT = 0.2 VPP, AV = 1 Slew Rate 4-V Step, AV = 1 Rise, Fall Time, 10%-90% MHz MHz 450 MHz 3800 V/s 2-V Step 600 ps 0.1% Settling Time 2-V Step 10 ns Overdrive Recovery Time VIN = 1.8-V to 0-V Step, AV = 5 V/V 6 ns DISTORTION AND NOISE RESPONSE HD2 HD3 IMD3 2nd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz, RL = 800 -92 VOUT = 2 VPP, f = 70 MHz, RL = 800 -74 VOUT = 2 VPP, f = 20 MHz, RL = 800 -93 VOUT = 2 VPP, f = 70 MHz, RL = 800 -84 Two-Tone Intermodulation f 70 MHz, Third-Order Products, VOUT = 2-VPP Composite -87 dBc Input Noise Voltage f 1 MHz 1.1 nV/Hz Input Noise Current f 1 MHz 19.5 pA/Hz Noise Figure (See Figure 46) 50- System, AV = 9, 10 MHz 10.3 dB 3rd Harmonic Distortion dBc dBc INPUT CHARACTERISTICS (4) IBI Input Bias Current IBoffset Input Bias Current Differential CMRR Common Mode Rejection Ratio RIN Input Resistance CIN Input Capacitance Differential CMVR Input Common Mode Voltage Range CMRR > 38 dB (1) (2) (3) (4) 60 110 A VCM = 0 V, VID = 0 V, IBoffset = (IB - IB )/2 2.5 18 A DC, VCM = 0 V, VID = 0 V 80 dBc Differential 15 0.5 pF 3.8 V - (3) (3) + 3.5 Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Overview for information on temperature de-rating of this device. Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values can vary over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. IBoffset is referred to a differential output offset voltage by the following relationship: VOD(offset) = IBI*2RF. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 5 LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 www.ti.com Electrical Characteristics: 5 V (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = +5 V, V- = -5 V, AV= 1, VCM = 0 V, RF = RG = 357 , RL = 500 , for single ended in, differential out.(1) PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT OUTPUT PERFORMANCE Output Voltage Swing (3) Differential Output 14.8 15.4 VPP IOUT Linear Output Current (3) VOUT = 0 V 70 80 mA ISC Short Circuit Current One Output Shorted to Ground VIN = 2 V Single Ended (5) 141 mA Output Balance Error VOUT Common Mode / VOUT Differential, VOD = 1 V, f < 1 MHz -60 dB 108 dB MISCELLANEOUS PERFORMANCE ZT Open Loop Transimpedance Differential PSRR Power Supply Rejection Ratio DC, (V+ - |V-|) = 1 V IS Supply Current (3) RL = Enable Voltage Threshold 80 19 22.5 3 2.0 Enable/Disable time 15 Disable Shutdown Current mA V Disable Voltage Threshold ISD dB 25 28 500 V ns 600 A OUTPUT COMMON MODE CONTROL CIRCUIT VOSCM Common Mode Small Signal Bandwidth VIN+ = VIN- = 0 400 Slew Rate VIN+ = VIN- = 0 607 Input Offset Voltage Common Mode, VID = 0, VCM = 0 1.5 16.5 mV -3.2 8 A Input Bias Current (6) Voltage Range CMRR 3.7 Measure VOD, VID = 0 V Input Resistance Gain (5) (6) 6 VO,CM / VCM 0.995 MHz V/s 3.8 V 80 dB 200 k 1.0 1.012 V/V Limit short circuit current in duration to no more than 10 seconds. See Power Dissipation for more details. Negative input current implies current flowing out of the device. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 6.6 Electrical Characteristics: 2.5 V Unless otherwise specified, all limits are ensured for TA = 25C, V+ = +2.5 V, V- = -2.5 V, AV = 1, VCM = 0 V, RF = RG = 357 , RL = 500 , for single ended in, differential out. (1) PARAMETER SSBW LSBW TEST CONDITIONS Small Signal -3-dB Bandwidth (2) MIN (2) VOUT = 0.2 VPP, AV = 1, RL = 1 k TYP (3) MAX (2) UNIT 1100 VOUT = 0.2 VPP, AV = 1 800 VOUT = 0.2 VPP, AV = 2 740 VOUT = 0.2 VPP, AV = 4 660 VOUT = 0.2 VPP, AV = 8 498 VOUT = 2 VPP, AV = 1, RL = 1 k 820 VOUT = 2 VPP, AV = 1 690 VOUT = 2 VPP, AV = 2 620 VOUT = 2 VPP, AV = 4 589 VOUT = 2 VPP, AV = 8 480 0.1 dB Bandwidth VOUT = 0.2 VPP, AV = 1 300 MHz Slew Rate 2-V Step, AV = 1 2100 V/s Rise/Fall Time, 10% to 90% 2-V Step 700 ps 0.1% Settling Time 2-V Step 10 ns Overdrive Recovery Time VIN = 0.7-V to 0-V Step, AV = 5 V/V 6 ns Large Signal -3 dB Bandwidth MHz MHz DISTORTION AND NOISE RESPONSE HD2 HD3 IMD3 2nd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz, RL = 800 -82 VOUT = 2 VPP, f = 70 MHz, RL = 800 -65 VOUT = 2 VPP, f = 20 MHz, RL = 800 -79 VOUT = 2 VPP, f = 70 MHz, RL = 800 -67 Two-Tone Intermodulation f 70 MHz, Third-Order Products, VOUT = 2-VPP Composite -77 dBc Input Noise Voltage f 1 MHz 1.1 nV/Hz Input Noise Current f 1 MHz 19.5 pA/Hz Noise Figure (See Figure 46) 50- System, AV = 9, 10 MHz 10.2 dB 3rd Harmonic Distortion dBc dBc INPUT CHARACTERISTICS (4) IBI Input Bias Current IBoffset Input Bias Current Differential 54 90 A VCM = 0 V, VID = 0 V, IBoffset = (IB- - IB+ )/2 2.3 18 A CMRR Common-Mode Rejection Ratio RIN Input Resistance DC, VCM = 0 V, VID = 0 V 75 Differential 15 CIN Input Capacitance Differential 0.5 pF CMVR Input Common Mode Range CMRR > 38 dB 1.0 1.3 V 6.0 VPP 65 mA 131 mA (3) (3) dBc OUTPUT PERFORMANCE Output Voltage Swing (3) Differential Output 5.6 IOUT Linear Output Current (3) VOUT = 0 V 55 ISC Short Circuit Current (1) (2) (3) (4) (5) One Output Shorted to Ground, VIN = 2 V Single Ended (5) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Overview for information on temperature de-rating of this device." Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values can vary over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. IBoffset is referred to a differential output offset voltage by the following relationship: VOD(offset) = IBI*2RF. Limit short circuit current in duration to no more than 10 seconds. See Power Dissipation for more details. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 7 LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 www.ti.com Electrical Characteristics: 2.5 V (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = +2.5 V, V- = -2.5 V, AV = 1, VCM = 0 V, RF = RG = 357 , RL = 500 , for single ended in, differential out.(1) PARAMETER Output Balance Error TEST CONDITIONS MIN (2) VOUT Common Mode / VOUT Differential, VOD = 1 V, f < 1 MHz TYP (3) MAX (2) UNIT 60 dB 107 dB MISCELLANEOUS PERFORMANCE ZT Open Loop Transimpedance Differential PSRR Power Supply Rejection Ratio DC, VS = 1 V IS Supply Current (3) RL = Enable Voltage Threshold 80 17 20.4 0.5 -0.5 Enable/Disable Time 15 Disable Shutdown Current mA V Disable Voltage Threshold ISD dB 24 27 500 V ns 600 A OUTPUT COMMON MODE CONTROL CIRCUIT VOSCM Common Mode Small Signal Bandwidth VIN+ = VIN- = 0 310 MHz Slew Rate VIN+ = VIN- = 0 430 V/s Input Offset Voltage Common Mode, VID = 0, VCM = 0 Input Bias Current Voltage Range CMRR 1.65 (6) 1.19 Measure VOD, VID = 0 V Input Resistance Gain (6) 8 VO,CM / VCM 0.995 15 mV -2.9 A 1.25 V 80 dB 200 k 1.0 1.012 V/V Negative input current implies current flowing out of the device. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 6.7 Typical Characteristics V+ = +5 V, V- = -5 V (TA = 25C, RF = RG = 357 , RL = 500 , AV = 1, for single ended in, differential out, unless specified). 1 0 -1 -2 AV = 4 AV = 2 -3 -4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1 AV = 1 0 AV = 8 -5 -6 -7 VOUT = 0.2 VPP -8 -1 -3 AV = 4 -4 -5 AV = 2 -6 -7 VOUT = 0.2 VPP -8 DIFFERENTIAL INPUT -9 1 SINGLE-ENDED INPUT 10 100 1000 FREQUENCY (MHz) -9 10000 100 1 VOD = 0.5 VPP 1000 10000 VOD = 0.5 VPP 0 NORMALIZED GAIN (dB) -1 -2 VOD = 2 VPP -3 -4 VOD = 4 VPP -5 -6 V+ = +5V - -7 V = -5V -8 AV = 2 V/V DIFFERENTIAL INPUT -9 1 10 100 1000 -1 -2 -4 VOD = 4 VPP -5 + -6 V = +5V -7 V = -5V -8 AV = 2 V/V SINGLE-ENDED INPUT -9 10000 VOD = 2 VPP -3 - 1 FREQUENCY (MHz) 10 100 1000 10000 FREQUENCY (MHz) Figure 3. Frequency Response vs VOUT Figure 4. Frequency Response vs VOUT 3 3 + 2 V = +5V 1 V = -5V 0 RL = 500: -1 RF = 357: V = +2.5V - -3 V = -2.5V -4 RL = 500: -5 RF = 357: -6 VOD = 0.2 VPP -7 -8 -9 AV = 1 V/V 10 100 0 + -1 V = +2.5V -2 V = -2.5V -3 RL = 1 k: -4 RF = 301: - + -5 V = +5V -6 V = -5V -7 RL = 1 k: - -8 DIFFERENTIAL INPUT 1 AV = 1 V/V DIFFERENTIAL INPUT 1 + -2 VOD = 0.2 VPP 2 - NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 10 Figure 2. Frequency Response vs Gain 0 NORMALIZED GAIN (dB) 1 FREQUENCY (MHz) Figure 1. Frequency Response vs Gain 1 AV = 1 AV = 8, RF = 400: -2 1000 -9 10000 RF = 301: 1 10 100 1000 10000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Frequency Response vs Supply Voltage Figure 6. Frequency Response vs Supply Voltage Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 9 LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 www.ti.com Typical Characteristics V+ = +5 V, V- = -5 V (continued) (TA = 25C, RF = RG = 357 , RL = 500 , AV = 1, for single ended in, differential out, unless specified). 1 RL = 200: -1 RL = 500: -2 RL = 800: -3 -4 V+ = +5V -5 V = -5V -6 AV = 1 V/V RF = 357: -7 VOUT = 0.2 VPP -8 SINGLE-ENDED INPUT -9 1 10 100 RL = 1 k: 0 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1 RL = 1 k: 0 RL = 200: -1 RL = 500: -2 RL = 800: -3 -4 + V = +5V -5 V- = -5V -6 AV = 1 V/V -7 RF = 357: VOUT = 2 VPP -8 SINGLE-ENDED INPUT 1000 -9 10000 1 10 FREQUENCY (MHz) Figure 7. Frequency Response vs Resistive Load 1000 10000 Figure 8. Frequency Response vs Resistive Load 2 0.8 RF = 301: 1 0.6 0 0.4 -1 RF = 357: -2 0.2 RF = 400: -3 VOD (V) NORMALIZED GAIN (dB) 100 FREQUENCY (MHz) + -4 V = +5V -5 V = -5V RL = 1 k: -8 + V = +2.5V - -0.4 VOUT = 2 VPP -7 -9 -0.2 AV = 1 V/V -6 0 V = -2.5V RL = 500: -0.6 RF = 357: DIFFERENTIAL INPUT 1 100 10 1000 -0.8 10000 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) TIME (ns) Figure 9. Frequency Response vs RF Figure 10. 1 VPP Pulse Response Single Ended Input 1.5 2.5 2 1 1.5 1 VOD (V) VOD (V) 0.5 0 + V = +5 V = -5V -1 RL = 500: -2 RF = 357: 5 - V = -5V -1.5 RL = 500: 0 V = +5V -1 - 10 15 20 25 30 35 40 45 50 -2.5 RF = 357: 0 5 10 15 20 25 30 35 40 45 50 TIME (ns) TIME (ns) Figure 11. 2 VPP Pulse Response Single Ended Input 10 0 -0.5 + -0.5 -1.5 0.5 Submit Documentation Feedback Figure 12. Large Signal Pulse Response Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 Typical Characteristics V+ = +5 V, V- = -5 V (continued) (TA = 25C, RF = RG = 357 , RL = 500 , AV = 1, for single ended in, differential out, unless specified). 80 -50 V+ = +5V -55 V- = -5V -60 RL = 800O VOD = 2 VPP -65 VOCM = 0V 40 DISTORTION (dBc) COMMON MODE VOUT (mV) 60 20 0 + V = +5V -20 - V = -5V -40 RL = 500: -60 RL = 357: 0 5 -70 -75 HD3 -80 -85 -90 -95 -100 VOD = 2 VPP -80 HD2 10 15 20 25 30 35 40 45 50 -105 1 25 50 75 100 125 150 175 200 225 250 TIME (ns) FREQUENCY (MHz) Figure 13. Output Common Mode Pulse Response Figure 14. Distortion vs Frequency Single Ended Input -20 RL = 800: VOUT = 2 VPP -30 DISTORTION (dBc) fc = 75 MHz -40 -50 HD2 -60 -70 -80 HD3 -90 3 5 7 9 11 12 TOTAL SUPPLY VOLTAGE (V) Figure 15. Distortion vs Supply Voltage Figure 16. Distortion vs Supply Voltage -40 -40 + + V = +5V - - -50 V = -5V -60 VOUT = 2 VPP V = -5V -50 RL = 800: DISTORTION (dBc) DISTORTION (dBc) V = +5V fc = 20 MHz -70 HD2 -80 RL = 800: VOUT = 2 VPP -60 fc = 75 MHz HD2 -70 -80 -90 HD3 HD3 -100 -90 0 0.5 1 1.5 2 2.5 0 3 0.5 1 1.5 2 2.5 3 VOCM (V) VOCM (V) Figure 17. Distortion vs Output Common Mode Voltage Figure 18. Distortion vs Output Common Mode Voltage Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 11 LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 www.ti.com Typical Characteristics V+ = +5 V, V- = -5 V (continued) 4 -2 3.8 -2.2 3.6 -2.4 MINIMUM VOUT (V) 3.4 3.2 3 2.8 + 2.6 V = +5V V = -5V 2.4 RF = 357: 2.2 V = 3.8V SINGLE-ENDED INPUT 0 -10 -20 -30 -40 - V = -5V RF = 357: -2.6 VIN = 3.8V SINGLE-ENDED -2.8 3 -3.2 -3.4 -3.6 -3.8 IN 2 + V = +5V -50 -4 -60 0 10 OUTPUT CURRENT (mA) Figure 19. Maximum VOUT vs IOUT 40 50 60 120 110 MAGNITUDE 100 PHASE () 90 0 80 PHASE -45 70 -90 60 + 50 V = +5V V = -5V 40 0.01 0.1 -135 10 1 -180 1000 100 MAGNITUDE, |Z| (dB :) 110 MAGNITUDE, |Z| (dB :) 30 Figure 20. Minimum VOUT vs IOUT 120 MAGNITUDE 100 90 0 80 PHASE -45 70 -90 60 + 50 V = +2.5V V = -2.5V 40 0.01 0.1 FREQUENCY (MHz) 1000 10 1 -180 1000 100 Figure 22. Open Loop Transimpedance 1000 + V = +5V + V = +2.5V - - 100 V = -5V 10 -135 FREQUENCY (MHz) Figure 21. Open Loop Transimpedance 100 VIN = 0V AV = 1 V/V V = -2.5 VIN = 0V AV = 1 V/V 10 1 |Z| (:) |Z| (:) 20 OUTPUT CURRENT (mA) PHASE () MAXIMUM VOUT (V) (TA = 25C, RF = RG = 357 , RL = 500 , AV = 1, for single ended in, differential out, unless specified). 0.1 1 0.01 0.1 0.001 0.0001 0.01 0.1 1 10 100 1000 0.01 0.01 Figure 23. Closed Loop Output Impedance 12 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 24. Closed Loop Output Impedance Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 Typical Characteristics V+ = +5 V, V- = -5 V (continued) (TA = 25C, RF = RG = 357 , RL = 500 , AV = 1, for single ended in, differential out, unless specified). 2 0.4 0 0 + -0.4 -2 V = +5V -4 V = -5V -0.8 -6 AV = 5 V/V -1.2 - RF = 324: -8 RL = 200: -10 0 200 400 600 800 -1.6 -2 1000 INPUT VOLTAGE (V) 0.8 OUTPUT OUTPUT VOLTAGE (VOD) 3 1.2 4 0.8 INPUT 1.6 6 OUTPUT VOLTAGE (VOD) 4 2 INPUT 8 0.6 2 0.4 OUTPUT 1 0 0 + V = +2.5V -1 - -2 -3 0 200 PSRR (dBc DIFFERENTIAL) PSRR (dBc DIFFERENTIAL) -100 80 +PSRR 70 60 -PSRR 50 40 V+ = +5V 30 V- = -5V 400 800 -0.8 1000 -90 -PSRR -70 +PSRR -60 -50 + V = +2.5V -40 - V = -2.5V -30 AV = 2 V/V -20 RL = 500: VIN = 0V 0 1 10 100 0.1 1000 10 1 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 28. PSRR Figure 27. PSRR 85 80 -10 -15 BALANCE ERROR (dBc) 75 70 65 CMRR (dB) 600 -80 -10 VIN = 0V 60 55 50 45 40 AV = 2 V/V 35 RL = 500: 30 R = 357: F 25 VOUT = 1.0 VPP 20 0.1 -0.6 TIME (ns) -110 0 0.1 RF = 324: Figure 26. Overdrive Recovery 90 10 -0.4 -4 100 RL = 500: AV = 5 V/V RL = 200: TIME (ns) AV = 2 V/V -0.2 V = -2.5V Figure 25. Overdrive Recovery 20 0.2 INPUT VOLTAGE (V) 10 1 10 100 1000 + -20 V = +2.5V -25 V = -2.5V - -30 -35 + -40 V = +5V -45 V = -5V - -50 -55 RL = 500: -60 -65 -70 AV = 1 V/V RF = 357: 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 29. CMRR Figure 30. Balance Error Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 13 LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 www.ti.com Typical Characteristics V+ = +5 V, V- = -5 V (continued) (TA = 25C, RF = RG = 357 , RL = 500 , AV = 1, for single ended in, differential out, unless specified). 15 15 + + V = +5V V = +2.5V - 14 AV = 9 V/V RF = 275: 50: SYSTEM 13 12 AV = 9 V/V RF = 275: 50: SYSTEM 13 12 11 11 10 V = -2.5V 14 NOISE FIGURE (dB) NOISE FIGURE (dB) - V = -5V 0 10 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) FREQUENCY (MHz) Figure 32. Noise Figure 5 175 NOISE VOLTAGE 140 4 INVERTING CURRENT NOISE CURRENT 3 105 NON-INVERTING CURRENT 70 NOISE CURRENT 2 35 1 0 S21 -10 S22 S11 -20 (SINGLE-ENDED INPUT) MAGNITUDE (dB) 210 CURRENT NOISE (pA/ Hz) VOLTAGE NOISE (nV/ Hz) Figure 31. Noise Figure 6 -30 -40 S11 -50 S12 -60 - V = -5V -70 0 0.0001 0.001 0.01 0.1 1 AV = 1 V/V 0 100 10 -80 10 100 Figure 33. Input Noise vs Frequency Figure 34. Differential S-Parameter Magnitude vs Frequency -20 400 V = +5V - 0 AV = 1 V/V S12 -50 AV = 2 V/V IMD 3 (dBc) PHASE () V = -5V S22 - V = -5V -40 RF = 357: + 200 100 + V = +5V -30 S11 1000 FREQUENCY (MHz) FREQUENCY (MHz) 300 + V = +5V RL = 200: -60 -70 -80 -100 RL = 800: -90 -200 -300 10 14 S11 (SINGLE-ENDED INPUT) 100 -100 S21 1000 -110 fc = 75 MHz (200 kHz SPACING) SINGLE-ENDED INPUT 0 1 2 3 4 5 6 7 FREQUENCY (MHz) DIFFERENTIAL VOUT (VPP) Figure 35. Differential S-Parameter Phase vs Frequency Figure 36. 3rd Order Intermodulation Products vs VOUT Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 Typical Characteristics V+ = +5 V, V- = -5 V (continued) (TA = 25C, RF = RG = 357 , RL = 500 , AV = 1, for single ended in, differential out, unless specified). -20 -65 + V = +2.5V - V = -2.5V -40 RF = 357: A = 2 V/V -50 V + V = +2.5V - V = -2.5V -75 VOD = 2 VPP -60 RL = 800: -70 -80 RL = 800: -70 RF = 360: AV = +2 IMD 3 (dBc) IMD 3 (dBc) -30 RL = 200: -80 -85 + -90 V = +5V -90 - -100 fc = 75 MHz (200 kHz SPACING) SINGLE-ENDED INPUT -110 0 1 2 3 4 5 6 -95 SINGLE-ENDED INPUT 200 kHz SPACING -100 50 60 70 80 7 DIFFERENTIAL VOUT (VPP) V = -5V 90 100 CENTER FREQUENCY (MHz) Figure 37. 3rd Order Intermodulation Products vs VOUT Figure 38. 3rd Order Intermodulation Products vs Center Frequency Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 15 LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 www.ti.com 7 Detailed Description 7.1 Overview The LMH6552 is a fully differential current feedback amplifier with integrated output common mode control, designed to provide low distortion amplification to wide bandwidth differential signals. The common mode feedback circuit sets the output common mode voltage independent of the input common mode, as well as forcing the V+ and V- outputs to be equal in magnitude and opposite in phase, even when only one of the inputs is driven as in single to differential conversion. 7.2 Functional Block Diagram V+ +OUT -IN 2.5 k High-Aol + Differential I/O Amplifier +IN 2.5 k + -OUT V+ Vcm Error Amplifier + VEN High Impedance VCM Buffer V Copyright (c) 2016, Texas Instruments Incorporated 7.3 Feature Description The proprietary current feedback architecture of the LMH6552 offers gain and bandwidth independence with exceptional gain flatness and noise performance, even at high values of gain, simply with the appropriate choice of RF1 and RF2. Generally, RF1 is set equal to RF2, and RG1 equal to RG2, so that the gain is set by the ratio RF/RG. Matching of these resistors greatly affects CMRR, DC offset error, and output balance. A maximum of 0.1% tolerance resistors are recommended for optimal performance, and the amplifier is internally compensated to operate with optimum gain flatness with RF value of 200 depending on PCB layout, and load resistance. The output common mode voltage is set by the VCM pin with a fixed gain of 1 V/V. Drive this pin by a low impedance reference and bypassed to ground with a 0.1-F ceramic capacitor. Any unwanted signal coupling into the VCM pin is passed along to the outputs, reducing the performance of the amplifier. The LMH6552 can be configured to operate on a single 10V supply connected to V+ with V- grounded or configured for a split supply operation with V+ = +5 V and V- = -5 V. Operation on a single 10-V supply, depending on gain, is limited by the input common mode range; therefore, AC coupling may be required. 16 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 7.4 Device Functional Modes This wideband FDA requires external resistors for correct signal-path operation. When configured for the desired input impedance and gain setting with these external resistors, the amplifier can be either on with the PD pin asserted to a voltage greater than Vs- + 3.0 V, or turned off by asserting PD low. Disabling the amplifier shuts off the quiescent current and stops correct amplifier operation. The signal path is still present for the source signal through the external resistors. The Vocm control pin sets the output average voltage. Left open, Vocm floats to an indeterminate voltage. Driving this high-impedance input with a voltage reference within its valid range sets a target for the internal Vcm error amplifier. 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The proprietary current feedback architecture of the LMH6552 offers gain and bandwidth independence with exceptional gain flatness and noise performance, even at high values of gain, simply with the appropriate choice of RF1 and RF2. Generally RF1 is set equal to RF2, and RG1 equal to RG2, so that the gain is set by the ratio RF/RG. Matching of these resistors greatly affects CMRR, DC offset error, and output balance. A minimum of 0.1% tolerance resistors are recommended for optimal performance, and the amplifier is internally compensated to operate with optimum gain flatness with values of RF between 270 and 390 depending on package selection, PCB layout, and load resistance. The output common mode voltage is set by the VCM pin with a fixed gain of 1 V/V. This pin must be driven by a low impedance reference and must be bypassed to ground with a 0.1 F ceramic capacitor. Any unwanted signal coupling into the VCM pin is passed along to the outputs, reducing the performance of the amplifier. This pin must not be left floating. The LMH6552 can be operated on a supply range as either a single 5V supply or as a split +5 V and -5 V. Operation on a single 5-V supply, depending on gain, is limited by the input common mode range; therefore, AC coupling may be required. For example, in a DC coupled input application on a single 5-V supply, with a VCM of 1.5 V, the input common voltage at a gain of 1 is 0.75 V, which is outside the minimum 1.2-V to 3.8-V input common mode range of the amplifier. The minimum VCM for this application must be greater than 2.5 V depending on output signal swing. Alternatively, AC coupling of the inputs in this example results in equal input and output common mode voltages, so a 1.5 V VCM would be achievable. Split supplies allow much less restricted AC and DC coupled operation with optimum distortion performance. The LMH6552 is equipped with an ENABLE pin to reduce power consumption when not in use. The ENABLE pin, when not driven, floats high (on). When the ENABLE pin is pulled low the amplifier is disabled and the amplifier output stage goes into a high impedance state so the feedback and gain set resistors determine the output impedance of the circuit. For this reason input to output isolation is poor in the disabled state and the part is not recommended in multiplexed applications where outputs are all tied together. 8.2 Typical Applications 8.2.1 Typical Fully Differential Application In many applications, it is required to drive a differential input ADC from a single ended source. Traditionally, transformers have been used to provide single to differential conversion, but these are inherently bandpass by nature and cannot be used for DC coupled applications. The LMH6552 provides excellent performance as a single-to-differential converter down to DC. Figure 45 illustrates a typical application circuit where an LMH6552 is used to produce a differential signal from a single ended source. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 17 LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 www.ti.com Typical Applications (continued) RF RO RG VS + a CL VCM RL VO RG RO RF ENABLE Copyright (c) 2016, Texas Instruments Incorporated Figure 39. Typical Fully Differential Application Schematic 8.2.1.1 Design Requirements One typical application for the LMH6552 is to drive an ADC. The following design is a single ended to differential circuit with an input impedance of 50 and an output impedance of 100 . The VCM voltage of the amplifier needs to be set to the same voltage as the ADC reference voltage which is typically 1.2 V. Figure 45 illustrates the design equations required to set the external resistor values. This design also requires a gain of 1 and -74 dBc THD at 70 MHz. 8.2.1.2 Detailed Design Procedure To match the input impedance of the circuit in Figure 45 to a specified source resistance, RS, requires that RT || RIN = RS. The equations governing RIN and AV for single-to-differential operation are also provided in Figure 45. These equations, along with the source matching condition, must be solved iteratively to achieve the desired gain with the proper input termination. Component values for several common gain configurations in a 50- environment are given in Table 1. Gain Component Values for 50- System WSON Package. Typically RS=50 and RM=RS||RT. 8.2.1.2.1 WSON Package Due to its size and lower parasitics, the WSON requires the lower optimum value of 275 for RF. This gives a flat frequency response with minimal peaking. With a lower RF value the WSON package has a reduction in noise compared to the SOIC with its optimum RF = 360 . 8.2.1.2.2 Fully Differential Operation The LMH6552 performs best in a fully differential configuration. The circuit illustrated in Figure 39 is a typical fully differential application circuit as might be used to drive an analog to digital converter (ADC). In this circuit the closed loop gain AV = VOUT/ VIN = RF/RG, where the feedback is symmetric. The series output resistors, RO, are optional and help keep the amplifier stable when presented with a capacitive load. Refer to Driving Capacitive Loads for details. When driven from a differential source, the LMH6552 provides low distortion, excellent balance, and common mode rejection. This is true provided the resistors RF, RG and RO are well matched and strict symmetry is observed in board layout. With an intrinsic device CMRR of 80 dB, using 0.1% resistors gives a worst case CMRR of around 60 dB for most circuits. The circuit configuration illustrated in Figure 40 was used to measure differential S parameters in a 50- environment at a gain of 1 V/V. Refer to Figure 34 and Figure 35 in the Typical Characteristics for measurement results. 18 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 Typical Applications (continued) 357: 50: 58: RS = 50: VS 357: + VCM a RL RS = 50: 58: 357: ENABLE 50: 357: Figure 40. Differential S-Parameter Test Circuit Table 1. Gain Component Values for 50 System WSON Package Gain RF RG RT RM 0 dB 275 255 59 26.7 6 dB 275 127 68.1 28.7 12 dB 275 54.9 107 34 357: 50: 348: RS = 50: VS a 56.2: VCM + RL 348: 26.4: ENABLE 50: 357: Figure 41. Single Ended Input S-Parameter Test Circuit (50 System) The circuit shown in Figure 41 was used to measure S-parameters for a single-to-differential configuration. Figure 34 and Figure 35 in Typical Characteristics are taken using the recommended component values for 0 dB gain. 8.2.1.2.3 Driving Capacitive Loads As noted previously, capacitive loads must be isolated from the amplifier output with small valued resistors. This is particularly the case when the load has a resistive component that is 500 or higher. A typical ADC has capacitive components of around 10 pF and the resistive component could be 1000 or higher. If driving a transmission line, such as 50 coaxial or 100 twisted pair, using matching resistors is sufficient to isolate any subsequent capacitance. 8.2.1.2.3.1 Balanced Cable Driver With up to 15 VPP differential output voltage swing and 80 mA of linear drive current the LMH6552 makes an excellent cable driver as illustrated in Figure 42. The LMH6552 is also suitable for driving differential cables from a single ended source. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 19 LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 www.ti.com 100: TWISTED PAIR 357: 50: 169: RS = 50: + VS a VCM 61.8: - 2 VPP 169: 27.6: 50: 357: AV = 2 V/V ENABLE Figure 42. Fully Differential Cable Driver 8.2.1.3 Application Curves Many application circuits have capacitive loading. As shown in Figure 43 amplifier bandwidth is reduced with increasing capacitive load, so parasitic capacitance must be strictly limited. In order to ensure stability resistance must be added between the capacitive load and the amplifier output pins. The value of the resistor is dependent on the amount of capacitive load as shown in Figure 44. This resistive value is a suggestion. System testing is required to determine the optimal value. Using a smaller resistor retains more system bandwidth at the expense of overshoot and ringing, and larger values of resistance reduce overshoot but also reduce system bandwidth. 30 1 20 -2 -3 CL = 82 pF, RO = 16: SUGGESTED RO (:) NORMALIZED GAIN (dB) 0 -1 CL = 39 pF, RO = 21: CL = 15 pF, RO = 24: -4 -5 CL = 5.6 pF, RO = 23: -6 VOD = 200 mVPP -7 AV = 1 LOAD = (CL || 1 k:) IN -8 SERIES WITH 2 ROUTS -9 1 10 100 20 10 + V = +5V - 0 1000 V = -5V LOAD = 1 k: || CAP LOAD 1 10 100 FREQUENCY (MHz) CAPACITIVE LOAD (pF) Figure 43. Frequency Response vs Capacitive Load Figure 44. Suggested ROUT vs Capacitive Load Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 8.2.2 Single-Ended Input to Differential Output Operation In many applications, it is required to drive a differential input ADC from a single-ended source. Traditionally, transformers have been used to provide single to differential conversion, but these are inherently bandpass by nature and cannot be used for DC coupled applications. The LMH6552 provides excellent performance as a single-to-differential converter down to DC. Figure 45 shows a typical application circuit where an LMH6552 is used to produce a differential signal from a single-ended source. RF AV, RIN RS VS a + V RG RO + VCM RT - RG + - ADC + RM IN- VO LMH6552 IN+ RO - V RF (c) 2RG + RM (1-E2) RIN = 1 + E2 (c) (c) (c) RG E1 = R + R G F (c) (c) 2(1 - E1) AV = (c) E1 + E2 RG + RM E2 = R + R + R F M (c) G RS = RT || RIN RM = RT || RS Copyright (c) 2016, Texas Instruments Incorporated Figure 45. Single-Ended Input with Differential Output When using the LMH6552 in single-to-differential mode, the complementary output is forced to a phase inverted replica of the driven output by the common mode feedback circuit as opposed to being driven by its own complimentary input. Consequently, as the driven input changes, the common mode feedback action results in a varying common mode voltage at the amplifier's inputs, proportional to the driving signal. Due to the non-ideal common mode rejection of the amplifier's input stage, a small common mode signal appears at the outputs which is superimposed on the differential output signal. The ratio of the change in output common mode voltage to output differential voltage is commonly referred to as output balance error. The output balance error response of the LMH6552 over frequency is shown in the Typical Characteristics. To match the input impedance of the circuit in Figure 45 to a specified source resistance, RS, requires that RT || RIN = RS. The equations governing RIN and AV for single-to-differential operation are also provided in Figure 45. These equations, along with the source matching condition, must be solved iteratively to achieve the desired gain with the proper input termination. Component values for several common gain configurations in a 50- environment are given in Table 1. Typically RS=50 and RM=RS||RT. 8.2.3 Single Supply Operation Single supply operation is possible on supplies from 5 V to 10 V; however, as discussed earlier, AC input coupling is recommended for low supplies such as 5 V due to input common mode limitations. An example of an AC coupled, single supply, single-to-differential circuit is illustrated in Figure 46. Note that when AC coupling, both inputs need to be AC coupled irrespective of single-to-differential or differential-to-differential configuration. For higher supply voltages DC coupling of the inputs may be possible provided that the output common mode DC level is set high enough so that the amplifier's inputs and outputs are within their specified operating ranges. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 21 LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 www.ti.com RF RO RG RS VS VO1 VI1 + a RT RL CL VCM VO RG RM VI2 VO2 RO RF ENABLE *VCM = VICM = VOCM VO1 + VO2 2 *BY DESIGN VICM = VI1 + VI2 2 Copyright (c) 2016, Texas Instruments Incorporated Figure 46. AC Coupled for Single Supply Operation 8.2.4 Split Supply Operation For optimum performance, split supply operation is recommended using +5 V and -5 V supplies; however, operation is possible on split supplies as low as +2.25 V and -2.25 V and as high as +6 V and -6 V. Provided the total supply voltage does not exceed the 4.5-V to 12-V operating specification, non-symmetric supply operation is also possible and in some cases advantageous. For example, if a 5-V DC coupled operation is required for low power dissipation but the amplifier input common mode range prevents this operation, it is still possible with split supplies of (V+) and (V-). Where (V+) - (V-) = 5V and V+ and V- are selected to center the amplifier input common mode range to suit the application. 357: 50: Single-Ended AC-coupled Source 169: 61.8: 125: - + LMH6552 169: 61.8: 2.2 pF - + 49.9: ADC12DL080 + V 12-Bit 80 MSPS CIN ~ 7- 8 pF 125: VREF - V 0.1 PF 357: Copyright (c) 2016, Texas Instruments Incorporated Figure 47. Split Supply 8.2.5 Output Noise Performance and Measurement Unlike differential amplifiers based on voltage feedback architectures, noise sources internal to the LMH6552 refer to the inputs largely as current sources, hence the low input referred voltage noise and relatively higher input referred current noise. The output noise is therefore more strongly coupled to the value of the feedback resistor and not to the closed loop gain, as would be the case with a voltage feedback differential amplifier. This allows operation of the LMH6552 at much higher gain without incurring a substantial noise performance penalty, simply by choosing a suitable feedback resistor. 22 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 Figure 48 shows a circuit configuration used to measure noise figure for the LMH6552 in a 50- system. An RF value of 275 is chosen for the SOIC package to minimize output noise and simultaneously allows both high gain (9 V/V) and proper 50- input termination. Refer to Single-Ended Input to Differential Output Operation for calculation of resistor and gain values. Noise figure values at various frequencies are shown Figure 31 in the Typical Characteristics. 275: + V RS = 50: VS 1 PF 2:1 (TURNS) 10: VCM a + - + 10: 50: 50: VO LMH6552 1 PF - V 275: AV = 9 V/V Copyright (c) 2016, Texas Instruments Incorporated Figure 48. Noise Figure Circuit Configuration 8.2.6 Driving Analog to Digital Converters Analog-to-digital converters present challenging load conditions. They typically have high impedance inputs with large and often variable capacitive components. As well, there are usually current spikes associated with switched capacitor or sample and hold circuits. Figure 49 shows a combination circuit of the LMH6552 driving the ADC12DL080. The two 125- resistors serve to isolate the capacitive loading of the ADC from the amplifier and ensure stability. In addition, the resistors, along with a 2.2-pF capacitor across the outputs (in parallel with the ADC input capacitance), form a low pass anti-aliasing filter with a pole frequency of about 60 MHz. For switched capacitor input ADCs, the input capacitance varies based on the clock cycle, as the ADC switches between the sample and hold mode. See your particular ADC's datasheet for details. 357: 50: Single-Ended AC-coupled Source 61.8: 125: - + LMH6552 61.8: 2.2 pF - + 169: 49.9: ADC12DL080 + V 169: 12-Bit 80 MSPS CIN ~ 7- 8 pF 125: VREF - V 0.1 PF 357: Copyright (c) 2016, Texas Instruments Incorporated Figure 49. Driving a 12-Bit ADC Figure 50 illustrates the SFDR and SNR performance vs frequency for the LMH6552 and ADC12DL080 combination circuit with the ADC input signal level at -1 dBFS. The ADC12DL080 is a dual 12-bit ADC with maximum sampling rate of 80 MSPS. The amplifier is configured to provide a gain of 2 V/V in single to differential mode. An external band-pass filter is inserted in series between the input signal source and the amplifier to reduce harmonics and noise from the signal generator. In order to properly match the input impedance seen at the LMH6552 amplifier inputs, RM is chosen to match ZS || RT for proper input balance. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 23 LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 www.ti.com 90 SFDR (dBc) 85 80 (dB) 75 70 65 SNR (dBFs) 60 55 50 0 5 10 15 20 25 30 35 40 INPUT FREQUENCY (MHz) Figure 50. LMH6552/ADC12DL080 SFDR and SNR Performance vs. Frequency Figure 51 shows a combination circuit of the LMH6552 driving the ADC14DS105. The ADC14DS105 is a dual channel 14-bit ADC with a sampling rate of 105 MSPS. The circuit in Figure 51 has a 2nd order low-pass LC filter formed by the 620 nH inductor along with the 22-pF capacitor across the differential outputs of the LMH6552. The filter has a pole frequency of about 50 MHz. Figure 52 shows the combined SFDR and SNR performance over frequency with a -1 dBFs input signal and a sampling rate of 1000 MSPS. 274: 50: Single-Ended AC-coupled Source 127: 68.1: - 0.1 PF 100: 620 nH 127: 14-Bit 105 MSPS + LMH6552 + 49.9: ADC14DS105 + V 22 pF - V VREF 100: 620 nH 68.1: 274: Copyright (c) 2016, Texas Instruments Incorporated Figure 51. Driving a 14-bit ADC The amplifier is configured to provide a gain of 2 V/V in a single-to-differential mode. The LMH6552 common mode voltage is set by the ADC14DS105. Circuit testing is the same as described for the LMH6552 and ADC12DL080 combination circuit. The 0.1-F capacitor, in series with the 49.9- resistor, is inserted to ground across the 68.1-resistor to balance the amplifier inputs. 24 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 100 95 SFDR (dBc) 90 85 (dB) 80 75 70 SNR (dBFs) 65 60 55 50 0 5 10 15 20 25 30 35 40 INPUT FREQUENCY (MHz) Figure 52. LMH6552/ADC14DS105 SFDR and SNR Performance vs. Frequency The amplifier and ADC must be located as close as possible. Both devices require that the filter components be in close proximity to them. The amplifier needs to have minimal parasitic loading on the output traces and the ADC is sensitive to high frequency noise that may couple in on its input lines. Some high performance ADCs have an input stage that has a bandwidth of several times its sample rate. The sampling process results in all input signals presented to the input stage mixing down into the first Nyquist zone (DC to Fs/2). The LMH6552 is capable of driving a variety of Texas Instruments Analog-to-Digital Converters. This is shown in Table 2, which offers a list of possible signal path ADC and amplifier combinations. The use of the LMH6552 to drive an ADC is determined by the application and the desired sampling process (Nyquist operation, subsampling or over-sampling). See application note AN-236 for more details on the sampling processes and application note AN-1393 'Using High Speed Differential Amplifiers to Drive ADCs. For more information regarding a particular ADC, refer to the particular ADC datasheet for details. Table 2. Differential Input ADCs Compatible With LMH6552 Driver Product Number Max Sampling Rate (MSPS) Resolution Channels ADC1173 15 8 SINGLE ADC1175 20 8 SINGLE ADC08351 42 8 SINGLE ADC1175-50 50 8 SINGLE ADC08060 60 8 SINGLE ADC08L060 60 8 SINGLE ADC08100 100 8 SINGLE ADC08200 200 8 SINGLE ADC08500 500 8 SINGLE ADC081000 1000 8 SINGLE ADC08D1000 1000 8 DUAL ADC10321 20 10 SINGLE ADC10D020 20 10 DUAL ADC10030 27 10 SINGLE ADC10040 40 10 DUAL ADC10065 65 10 SINGLE ADC10DL065 65 10 DUAL ADC10080 80 10 SINGLE ADC11DL066 66 11 DUAL ADC11L066 66 11 SINGLE ADC11C125 125 11 SINGLE Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 25 LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 www.ti.com Table 2. Differential Input ADCs Compatible With LMH6552 Driver (continued) Product Number Max Sampling Rate (MSPS) Resolution Channels ADC11C170 170 11 SINGLE ADC12010 10 12 SINGLE ADC12020 20 12 SINGLE ADC12040 40 12 SINGLE ADC12D040 40 12 DUAL ADC12DL040 40 12 DUAL ADC12DL065 65 12 DUAL ADC12DL066 66 12 DUAL ADC12L063 63 12 SINGLE ADC12C080 80 12 SINGLE ADC12DS080 80 12 DUAL ADC12L080 80 12 SINGLE ADC12C105 105 12 SINGLE ADC12DS105 105 12 DUAL ADC12C170 170 12 SINGLE ADC14L020 20 14 SINGLE ADC14L040 40 14 SINGLE ADC14C080 80 14 SINGLE ADC14DS080 80 14 DUAL ADC14C105 105 14 SINGLE ADC14DS105 105 14 DUAL ADC14155 155 14 SINGLE 9 Power Supply Recommendations The LMH6552 can be used with any combination of positive and negative power supplies as long as the combined supply voltage is between 4.5 V and 12 V. The LMH6552 provides best performance when the output voltage is set at the mid supply voltage, and when the total supply voltage is between 9 V and 12 V. When selecting a supply voltage that is less than 9 V, it is important to consider both the input common mode voltage range as well as the output voltage range. Power supply bypassing as shown in Power Supply Bypassing is important and power supply regulation must be within 5% or better using a supply voltage near the edges of the operating range. 9.1 Power Supply Bypassing The LMH6552 requires supply bypassing capacitors as illustrated in Figure 53 and Figure 54. The 0.01-F and 0.1-F capacitors must be leadless SMT ceramic capacitors and must be no more than 3 mm from the supply pins. These capacitors must be star routed with a dedicated ground return plane or trace for best harmonic distortion performance. A small capacitor, ~0.01 F, placed across the supply rails, and as close to the chip's supply pins as possible, can further improve HD2 performance. Thin traces or small vias reduce the effectiveness of bypass capacitors. Also shown in both figures is a capacitor from the VCM and ENABLE pins to ground. These inputs are high impedance and can provide a coupling path into the amplifier for external noise sources, possibly resulting in loss of dynamic range, degraded CMRR, degraded balance and higher distortion. 26 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 Power Supply Bypassing (continued) + V 10 PF 0.1 PF + VCM 0.01 PF ENABLE 0.1 PF 0.1 PF 10 PF - V 0.1 PF Figure 53. Split Supply Bypassing Capacitors V 10 PF + 0.1 PF 0.01 PF + VCM 0.1 PF ENABLE 0.01 PF Figure 54. Single Supply Bypassing Capacitors 10 Layout 10.1 Layout Guidelines The LMH6552 is a very high performance amplifier. In order to get maximum benefit from the differential circuit architecture board layout and component selection is very critical. The circuit board must have a low inductance ground plane and well bypassed broad supply lines. External components must be leadless surface mount types. The feedback network and output matching resistors must be composed of short traces and precision resistors (0.1%). The output matching resistors must be placed within 3 or 4 mm of the amplifier as must the supply bypass capacitors. Refer to Power Supply Bypassing for recommendations on bypass circuit layout. Evaluation boards are available free of charge through the product folder on ti.com. By design, the LMH6552 is relatively insensitive to parasitic capacitance at its inputs. Nonetheless, ground and power plane metal must be removed from beneath the amplifier and from beneath RF and RG for best performance at high frequency. With any differential signal path, symmetry is very important. Even small amounts of asymmetry can contribute to distortion and balance errors. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 27 LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 www.ti.com 10.2 Layout Example Figure 55. Layout Schematic 28 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 10.3 Thermal Considerations The WSON package is designed for enhanced thermal performance and features an exposed die attach pad (DAP) at the bottom center of the package that creates a direct path to the PCB for maximum power dissipation. The DAP is floating and is not electrically connected to internal circuitry. Compared to the traditional leaded packages where the die attach pad is embedded inside the molding compound, the WSON reduces one layer in the thermal path. The thermal advantage of the WSON package is fully realized only when the exposed die attach pad is soldered down to a thermal land on the PCB board with thermal vias planted underneath the thermal land. The thermal land can be connected to any power or ground plane within the allowable supply voltage range of the device. Based on thermal analysis of the WSON package, the junction-to-ambient thermal resistance (JA) can be improved by a factor of two when the die attach pad of the WSON package is soldered directly onto the PCB with thermal land and thermal vias are 1.27 mm and 0.33 mm respectively. Typical copper via barrel plating is 1 oz, although thicker copper may be used to further improve thermal performance. For more information on board layout techniques, refer to Application Note 1187 Leadless Lead Frame Package (LLP). This application note also discusses package handling, solder stencil and the assembly process. 10.4 Power Dissipation The LMH6552 is optimized for maximum speed and performance in the small form factor of the standard SOIC package, and is essentially a dual channel amplifier. To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAXof 150C is never exceeded due to the overall power dissipation. Follow these steps to determine the maximum power dissipation for the LMH6552: 1. Calculate the quiescent (no-load) power: PAMP = ICC* (VS) where VS = V+ - V-. (Be sure to include any current through the feedback network if VOCM is not mid-rail.) * (1) 2. Calculate the RMS power dissipated in each of the output stages: PD (rms) = rms ((VS - V+OUT) * I+OUT) + rms ((VS - V-OUT) * I-OUT) where * VOUT and IOUT are the voltage and the current measured at the output pins of the differential amplifier as if they were single ended amplifiers and VS is the total supply voltage (2) 3. Calculate the total RMS power: PT = PAMP + PD (3) The maximum power that the LMH6552 package can dissipate at a given temperature can be derived with the following equation: PMAX = (150 - TAMB)/ JA where * * * * TAMB = Ambient temperature (C) JA = Thermal resistance, from junction to ambient, for a given package (C/W) For the SOIC package JA is 150C/W For WSON package JA is 58C/W (4) NOTE If VCM is not 0V then there is quiescent current flowing in the feedback network. This current must be included in the thermal calculations and added into the quiescent power dissipation of the amplifier. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 29 LMH6552 SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 www.ti.com 10.5 ESD Protection The LMH6552 is protected against electrostatic discharge (ESD) on all pins. The LMH6552 can survive 2000 V Human Body model and 200 V Machine model events. Under normal operation the ESD diodes have no affect on circuit performance. There are occasions, however, when the ESD diodes are evident. If the LMH6552 is driven by a large signal when the device is powered down the ESD diodes conduct. The current that flows through the ESD diodes either exits the chip through the supply pins or flows through the device, hence a chip can be powered up with a large signal applied to the input pins. Using the shutdown mode is one way to conserve power and still prevent unexpected operation. 30 Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9J - APRIL 2007 - REVISED APRIL 2016 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: * Leadless Lead Frame Package (LLP), SNOA401 11.2.1.1 Evaluation Board See the LMH6552 Product Folder for evaluation board availability and ordering information. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2007-2016, Texas Instruments Incorporated Product Folder Links: LMH6552 31 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LMH6552MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH65 52MA LMH6552MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH65 52MA LMH6552SD/NOPB ACTIVE WSON NGS 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 6552 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Apr-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMH6552MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMH6552SD/NOPB WSON NGS 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Apr-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6552MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMH6552SD/NOPB WSON NGS 8 1000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE NGS0008C WSON - 0.8 mm max height SCALE 5.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 2.9 B A PIN 1 INDEX AREA 2.6 2.4 C 0.8 0.7 SEATING PLANE 0.08 C 1.6 0.1 (0.1) TYP SYMM EXPOSED THERMAL PAD 0.05 0.00 5 4 SYMM 9 2X 1.5 1.5 0.1 1 8 6X 0.5 8X PIN 1 ID 8X 0.5 0.3 0.3 0.2 0.1 0.05 C A B C 4214924/A 07/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT NGS0008C WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.6) SYMM 8X (0.6) 8 1 8X (0.25) (0.5) 9 SYMM (1.5) 6X (0.5) 4 (R0.05) TYP 5 ( 0.2) VIA TYP (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND EXPOSED METAL EXPOSED METAL SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4214924/A 07/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN NGS0008C WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 8X (0.6) SYMM METAL TYP 8 1 8X (0.25) 9 SYMM (1.38) 6X (0.5) 4 5 (R0.05) TYP (1.47) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 9: 82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4214924/A 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 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