K4D263238K-VC50 - Samsung - Product.Network

128M GDDR SDRAM

K4D263238K

- 1/19 - Rev. 1.1 July 2007

128Mbit GDDR SDRAM

Revision 1.1

July 2007

Notice

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

128M GDDR SDRAM

K4D263238K

- 2/19 - Rev. 1.1 July 2007

Revision History

Revision Month Year History

1.0 January 2007 - Release revision 1.0 SPEC

- Corrected Package Outline

1.1 July 2007 - Revised comment about voltage of power up sequence

- Revised ICC2P current to 20mA

128M GDDR SDRAM

K4D263238K

- 3/19 - Rev. 1.1 July 2007

The K4D263238K is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by

32 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow

extremely high performance up to 2.0GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of

operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety

of high performance memory system applications.

• 2.5V ± 5% power supply for device operation

• 2.5V ± 5% power supply for I/O interface

• SSTL_2 compatible inputs/outputs

• 4 banks operation

• MRS cycle with address key programs

-. Read latency 3 (clock)

-. Burst length (2, 4, 8 and Full page)

-. Burst type (sequential & interleave)

• Full page burst length for sequential burst type only

• Start address of the full page burst should be even

• All inputs except data & DM are sampled at the positive

going edge of the system clock

• Differential clock input

• Write Interrupted by Read function

GENERAL DESCRIPTION

FEATURES

• Data I/O transactions on both edges of Data strobe

• DLL aligns DQ and DQS transitions with Clock transition

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

• DM for write masking only

• Auto & Self refresh

• 32ms refresh period (4K cycle)

• 144pin FBGA package

• Maximum clock frequency up to 250MHz

• Maximum data rate up to 500Mbps/pin

FOR 1M x 32Bit x 4 Bank DDR SDRAM

1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM

with Bi-directional Data Strobe and DLL

ORDERING INFORMATION

K4D263238K-GC is the Leaded package part number.

Part NO. Max Freq. Max Data Rate Interface Package

K4D263238K-VC40 250MHz 500Mbps/pin SSTL_2 144FBGA

K4D263238K-VC50 200MHz 400Mbps/pin

128M GDDR SDRAM

K4D263238K

- 4/19 - Rev. 1.1 July 2007

PIN CONFIGURATION (Top View)

PIN DESCRIPTION

CK,CK Differential Clock Input BA0, BA1 Bank Select Address

CKE Clock Enable A0 ~A11 Address Input

CS Chip Select DQ0 ~ DQ31 Data Input/Output

RAS Row Address Strobe VDD Power

CAS Column Address Strobe VSS Ground

WE Write Enable VDDQ Power for DQ’s

DQS Data Strobe VSSQ Ground for DQ’s

DM Data Mask NC No Connection

RFU Reserved for Future Use

DQS0

VSS

RFU1

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSS

Thermal

VSSQ

VSSQ VSSQ VSSQ

VSSQ

VSSQ VSSQ

VSSQ

VSS VSS VSS VSS

VSSVSSVSSVSS

VSS

RFU2A5

DQ4

DQ6

DQ7

DQ17

DQ19

DQS2

DQ21

DQ22

CAS

RAS

DM0

VDDQ

DQ5

VDDQ

DQ16

DQ18

DM2

DQ20

DQ23

VDD

VDDQ

VDD

BA0

BA1

DQ3

VDDQ

DQ31

DQ1

A10

VDD VDD

VDD

DQ2

VDDQ

VDD

A11

DQ0

VDDQ

VDD

DQ29

DQ30

DQ28

VDDQ NC

VSS

VDDQ

VDD

A8/AP

DM3

VDDQ

DQ26

VDDQ

DQ15

DQ13

DM1

DQ11

DQ9

CKE

DQS3

DQ27

DQ25

DQ24

DQ14

DQ12

DQS1

DQ10

DQ8

VREF

2345678910111213

NOTE:

1. RFU1 is reserved for A12

2. RFU2 is reserved for BA2

3. VSS Thermal balls are optional

128M GDDR SDRAM

K4D263238K

- 5/19 - Rev. 1.1 July 2007

INPUT/OUTPUT FUNCTIONAL DESCRIPTION

*1 : The timing reference point for the differential clocking is the cross point of CK and CK.

For any applications using the single ended clocking, apply VREF to CK pin.

Symbol Type Function

CK, CK*1 Input

The differential system clock Input.

All of the inputs are sampled on the rising edge of the clock except

DQ′s and DM′s that are sampled on both edges of the DQS.

CKE Input

Activates the CK signal when high and deactivates the CK signal

when low. By deactivating the clock, CKE low indicates the Power

down mode or Self refresh mode.

CS Input

CS enables the command decoder when low and disabled the com-

mand decoder when high. When the command decoder is disabled,

new commands are ignored but previous operations continue.

RAS Input Latches row addresses on the positive going edge of the CK with

RAS low. Enables row access & precharge.

CAS Input Latches column addresses on the positive going edge of the CK with

CAS low. Enables column access.

WE Input Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

DQS Input/Output Data input and output are synchronized with both edge of DQS.

DM0 ~ DM3Input

Data In mask. Data In is masked by DM Latency=0 when DM is high

in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for

DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31.

DQ0 ~ DQ31 Input/Output Data inputs/Outputs are multiplexed on the same pins.

BA0, BA1Input Selects which bank is to be active.

A0 ~ A11 Input

Row/Column addresses are multiplexed on the same pins.

Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7.

Column address CA8 is used for auto precharge.

VDD/VSS Power Supply Power and ground for the input buffers and core logic.

VDDQ/VSSQ Power Supply Isolated power supply and ground for the output buffers to provide

improved noise immunity.

VREF Power Supply Reference voltage for inputs, used for SSTL interface.

128M GDDR SDRAM

K4D263238K

- 6/19 - Rev. 1.1 July 2007

BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank)

Bank Select

Timing Register

Address Register

Refresh Counter

Row Buffer

Row Decoder Col. Buffer

Data Input Register

Serial to parallel

1Mx32

Sense AMP

2-bit prefetch

Output BufferI/O Control

Column Decoder

Latency & Burst Length

Programming Register

Strobe

Gen.

CK,CK

ADDR

LCKE

CK,CK CKE CS RAS CAS WE DMi

LDMi

CK,CK

LCAS

LRAS LCBR LWE

LWCBR

LRAS

LCBR

CK, CK

64 32

LWE

LDMi

x32

DQi

Data Strobe

Intput Buffer

DLL

128M GDDR SDRAM

K4D263238K

- 7/19 - Rev. 1.1 July 2007

• Power-Up Sequence

DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and keep CKE at low state (All other inputs may be undefined)

- Apply VDD before or with VDDQ .

- Apply VDDQ before or with VREF & VTT

- The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps

from 300 mV to VDD min and the power voltage ramps are without any slope reversal.

2. Start clock and maintain stable condition for minimum 200us.

3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high.

4. Issue precharge command for all banks of the device.

5. Issue a EMRS command to enable DLL

*1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.

*1,2 7. Issue precharge command for all banks of the device.

8. Issue at least 2 or more auto-refresh commands.

9. Issue a mode register set command with A8 to low to initialize the mode register.

*1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL.

*2 Sequence of 6&7 is regardless of the order.

FUNCTIONAL DESCRIPTION

Power up & Initialization Sequence

Command

012345678910111213141516171819

tRP 2 Clock min.

precharge

ALL Banks

2nd Auto

Refresh

Mode

Any

Command

tRFC

1st Auto

Refresh

tRFC

EMRS MRS

2 Clock min.

DLL Reset

precharge

ALL Banks

tRP

Inputs must be

stable for 200us

∼

200 Clock min.

∼

2 Clock min.

* When the operating frequency is changed, DLL reset should be required again.

After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.

128M GDDR SDRAM

K4D263238K

- 8/19 - Rev. 1.1 July 2007

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,

addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for

variety of different applications. The default value of the mode register is not defined, therefore the mode register must be

written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and

WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of

address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.

Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents

can be changed using the same command and clock cycle requirements during operation as long as all banks are in the

idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2,

addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is

used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes

for various burst length, addressing modes and CAS latencies.

MODE REGISTER SET(MRS)

Address Bus

Mode

CAS Latency

A6A5A4Latency

0 0 0 Reserved

0 0 1 Reserved

0 1 0 Reserved

011 3

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved

Burst Length

A2A1A0

Burst Type

Sequential Interleave

0 0 0 Reserve Reserve

001 2 2

010 4 4

011 8 8

1 0 0 Reserve Reserve

1 0 1 Reserve Reserve

1 1 0 Reserve Reserve

1 1 1 Full page Reserve

Burst Type

A3Type

0 Sequential

1 Interleave

* RFU(Reserved for future use)

should stay "0" during MRS

cycle.

MRS Cycle

Command

*1: MRS can be issued only at all banks precharge state.

*2: Minimum tRP is required to issue MRS command.

CK, CK

Precharge NOP NOPMRS NOPNOP

201 534 867

Any

NOP All Banks Command

tRP tMRD=2 tCK

BA1BA0A11 A10 A9A8A7A6A5A4A3A2A1A0

RFU 0 RFU DLL TM CAS Latency BT Burst Length

BA0An ~ A0

0MRS

1EMRS

DLL

A8DLL Reset

0No

1Yes

Test Mode

A7mode

0Normal

1Test

NOP

128M GDDR SDRAM

K4D263238K

- 9/19 - Rev. 1.1 July 2007

The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The

default value of the extended mode register is not defined, therefore the extend mode register must be written after power

up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high

on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode

low are written in the extended mode register. A1 and A6 are used for setting driver strength to weak or matched imped-

ance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register

contents can be changed using the same command and clock cycle requirements during operation as long as all banks

are in the idle state. A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins

except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.

A0DLL Enable

0 Enable

1 Disable

BA0An ~ A0

0MRS

1EMRS

Figure 7. Extend Mode Register set

EXTENDED MODE REGISTER SET(EMRS)

Address Bus

Extended

BA1BA0A11 A10 A9A8A7A6A5A4A3A2A1A0

RFU 1 RFU D.I.C RFU D.I.C DLL Mode Register

* RFU(Reserved for future use)

should stay "0" during EMRS

cycle.

A6A1Output Driver Impedance Control

00 Full 100%

01 Weak 60%

10 N/A Do not use

11 Matched 30%

128M GDDR SDRAM

K4D263238K

- 10/19 - Rev. 1.1 July 2007

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V

Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V

Voltage on VDD supply relative to Vss VDDQ -0.5 ~ 3.6 V

Storage temperature TSTG -55 ~ +150 °C

Power dissipation PD1.8 W

Short circuit current IOS 50 mA

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)

Parameter Symbol Min Typ Max Unit Note

Device Supply voltage VDD 2.375 2.50 2.625 V 1

Output Supply voltage VDDQ 2.375 2.50 2.625 V 1

Reference voltage VREF 0.49*VDDQ - 0.51*VDDQ V2

Termination voltage Vtt VREF-0.04 VREF VREF+0.04 V 3

Input logic high voltage VIH VREF+0.15 - VDDQ+0.30 V 4

Input logic low voltage VIL -0.30 - VREF-0.15 V 5

Output logic high voltage VOH Vtt+0.76 - - V IOH=-15.2mA

Output logic low voltage VOL - - Vtt-0.76 V IOL=+15.2mA

Input leakage current IIL -5 - 5 uA 6

Output leakage current IOL -5 - 5 uA 6

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to

peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error

and an additional + 25mV for AC noise.

3. Vtt of the transmitting device must track VREF of the receiving device.

4. VIH(max.)= VDDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate.

5. VIL(min.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

6. For any pin under test input of 0V ≤ VIN ≤ VDD is acceptable. For all other pins that are not under test VIN=0V.

Note :

128M GDDR SDRAM

K4D263238K

- 11/19 - Rev. 1.1 July 2007

DC CHARACTERISTICS

Note: 1. Measured with outputs open.

2. Refresh period is 32ms.

Parameter Symbol Test Condition

Version Unit Note

-40 -50

Operating Current

(One Bank Active) ICC1 Burst Lenth=2 tRC ≥ tRC(min)

IOL=0mA, tCC= tCC(min) 189 170 mA 1

Precharge Standby Current

in Power-down mode ICC2PCKE ≤ VIL(max), tCC= tCC(min) 20 20 mA

Precharge Standby Current

in Non Power-down mode ICC2NCKE ≥ VIH(min), CS ≥ VIH(min),

tCC= tCC(min). 48 43 mA

Active Standby Current

power-down mode ICC3PCKE ≤ VIL(max), tCC= tCC(min) 78 67 mA

Active Standby Current in

in Non Power-down mode ICC3NCKE ≥ VIH(min), CS ≥ VIH(min),

tCC= tCC(min) . 153 134 mA

Operating Current

( Burst Mode) ICC4 IOL=0mA ,tCC= tCC(min), Page

Burst, All Banks activated. 402 344 mA

Refresh Current ICC5 tRC ≥ tRFC(min) 159 135 mA 2

Self Refresh Current ICC6 CKE ≤ 0.2V 10 mA

Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C)

AC INPUT OPERATING CONDITIONS

Recommended operating conditions(Voltage referenced to VSS=0V, VDD/ VDDQ=2.5V+ 5%, TA=0 to 65°C)

Parameter Symbol Min Typ Max Unit Note

Input High (Logic 1) Voltage; DQ VIH VREF+0.35 - - V

Input Low (Logic 0) Voltage; DQ VIL --VREF-0.35 V

Clock Input Differential Voltage; CK and CK VID 0.7 - VDDQ+0.6 V 1

Clock Input Crossing Point Voltage; CK and CK VIX 0.5*VDDQ-0.2 - 0.5*VDDQ+0.2 V 2

1. VID is the magnitude of the difference between the input level on CK and the input level on CK

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same

Note :

128M GDDR SDRAM

K4D263238K

- 12/19 - Rev. 1.1 July 2007

AC OPERATING TEST CONDITIONS (VDD/ VDDQ=2.5V+ 5% , TA= 0 to 65°C)

Parameter Value Unit Note

Input reference voltage for CK(for single ended) 0.50*VDDQ V

CK and CK signal maximum peak swing 1.5 V

CK signal minimum slew rate 1.0 V/ns

Input Levels(VIH/VIL)VREF+0.35/VREF-0.35 V

Input timing measurement reference level VREF V

Output timing measurement reference level Vtt V

Output load condition See Fig.1

RT=50Ω

Output

CLOAD=30pF

(Fig. 1) Output Load Circuit

Z0=50Ω

VREF

=0.5*VDDQ

Vtt=0.5*VDDQ

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter Symbol Value Unit

Decoupling Capacitance between VDD and VSS CDC1 0.1 + 0.01 uF

Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01 uF

1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other

All VSS pins are connected in chip. All VSSQ pins are connected in chip.

Note :

CAPACITANCE (VDD=2.5V, TA= 25°C, f=1MHz)

Parameter Symbol Min Max Unit

Input capacitance( CK, CK )CIN1 1.0 5.0 pF

Input capacitance(A0~A11, BA0~BA1)CIN2 1.0 4.0 pF

Input capacitance

( CKE, CS, RAS,CAS, WE ) CIN3 1.0 4.0 pF

Data & DQS input/output capacitance(DQ0~DQ31)COUT 1.0 6.0 pF

Input capacitance(DM0 ~ DM3) CIN4 1.0 6.0 pF

128M GDDR SDRAM

K4D263238K

- 13/19 - Rev. 1.1 July 2007

13467

tCL

tCK

Hi-Z

CK, CK

DQS

tIS

tIH

tDS tDH

tRPST

tRPRE

Db0 Db1

tDQSS tDQSH

tCH

Da1

Da2

tWPST

COMMAND

READA WRITEB

tDQSQ

tWPRES

tWPREH

tDQSCK

tAC

AC CHARACTERISTICS

Simplified Timing @ BL=2, CL=3

Parameter Symbol -40 -50 Unit Note

Min Max Min Max

CK cycle time CL=3 tCK 4.0 10 5.0 10 ns

CK high level width tCH 0.45 0.55 0.45 0.55 tCK

CK low level width tCL 0.45 0.55 0.45 0.55 tCK

DQS out access time from CK tDQSCK -0.6 0.6 -0.7 +0.7 ns

Output access time from CK tAC -0.6 0.6 -0.7 +0.7 ns

Data strobe edge to Dout edge tDQSQ - 0.4 - +0.45 ns

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK

CK to valid DQS-in tDQSS 0.85 1.15 0.8 1.2 tCK

DQS-In setup time tWPRES 0 - 0 - ns

DQS-in hold time tWPREH 0.35 - 0.25 - tCK

DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK

DQS-In high level width tDQSH 0.4 0.6 0.4 0.6 tCK

DQS-In low level width tDQSL 0.4 0.6 0.4 0.6 tCK

Address and Control input setup tIS 0.9 - 1.0 - ns

Address and Control input hold tIH 0.9 - 1.0 - ns

DQ and DM setup time to DQS tDS 0.4 - 0.45 - ns

DQ and DM hold time to DQS tDH 0.4 - 0.45 - ns

Clock half period tHP

tCLmin

tCHmin

tCLmin

tCHmin

-ns

Data output hold time from DQS tQH tHP-0.4 - tHP-0.45 - ns

128M GDDR SDRAM

K4D263238K

- 14/19 - Rev. 1.1 July 2007

Note 1 :

- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data

strobe and all data associated with that data strobe are coincidentally valid.

- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case

output valid window even then the clock duty cycle applied to the device is better than 45/55%

- A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle

variation and replaces tDV

- tQHmin = tHP-X where

. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)

. X=A frequency dependent timing allowance account for tDQSQmax

tQH Timing (CL3, BL2)

134

tHP

CK, CK

DQS

COMMAND

READA

tQH

Da0

tDQSQ(max)

Da1

128M GDDR SDRAM

K4D263238K

- 15/19 - Rev. 1.1 July 2007

AC CHARACTERISTICS (I)

Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM

2. The number of clock of tRP is restricted by the number of clock of tRAS and tRP

3. The number of clock of tWR_A is fixed. It can’t be changed by tCK

4. tRCDWR is equal to tRCDRD-2tCK and the number of clock can not be lower than 2tCK.

5. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

rounding off to the next higher integer unconditionally.

Parameter Symbol -40 -50 Unit Note

Min Max Min Max

Row cycle time tRC 48 - 50 - ns 2,5

Refresh row cycle time tRFC 56 - 55 - ns 5

Row active time tRAS 32 100K 35 100K ns 5

RAS to CAS delay for Read tRCDRD 16 - 15 - ns 5

RAS to CAS delay for Write tRCDWR 8 10 ns 4

Row precharge time tRP 16 - 15 - ns 5

Row active to Row active tRRD 10 - 10 - ns 5

Last data in to Row precharge tWR 15 - 15 - ns 5

Last data in to Row precharge

@Auto Precharge tWR_A 3 - 3 - tCK 3

Auto precharge write recovery + Pre-

charge tDAL 7 - 6 - tCK 3,5

Last data in to Read command tCDLR 2 - 2 - tCK 1

Col. address to Col. address tCCD 1 - 1 - tCK

Mode register set cycle time tMRD 2 - 2 - tCK

Exit self refresh to read command tXSR 200 - 200 - tCK

Power down exit time tPDEX 3tCK+tIS -

3tCK+tIS

-ns

Refresh interval time tREF - 7.8 - 7.8 us

AC CHARACTERISTICS (II)

* 200/166MHz are supported in K4D263238K-VC40

* 166MHz is supported in K4D263238K-VC50

K4D263238K-VC40

Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit

250MHz ( 4.0ns ) 3 12 14 8 4 2 4 3 7 tCK

200MHz ( 5.0ns ) 3 10 11 7 3 2 3 2 6 tCK

166MHz ( 6.0ns ) 3 9 9 6 3 2 3 2 6 tCK

K4D263238K-VC50

Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit

200MHz ( 5.0ns ) 3 10 11 7 3 2 3 2 6 tCK

166MHz ( 6.0ns ) 3 9 9 6 3 2 3 2 6 tCK

128M GDDR SDRAM

K4D263238K

- 16/19 - Rev. 1.1 July 2007

01 23 45 678

BAa

tRCD

ACTIVEA ACTIVEB WRITEA WRITEB

Db0 Db1 Db3

13 14 15 16 17 18 19 20 21

BAa BAb

Ca Cb

BAa

9101112

PRECH

BAa

Da0 Da1 Da2 Da3

Normal Write Burst

(@ BL=4)

Multi Bank Interleaving Write Burst

(@ BL=4)

BAa

BAb

Db2

tRAS

tRC

tRP

tRRD

COMMAND

DQS

CK, CK

A8/AP

ADDR

(A0~A7,

BA[1:0]

A9~,A11)

ACTIVEA WRITEA

Da0 Da1 Da2 Da3

Simplified Timing(2) @ BL=4, CL=3

128M GDDR SDRAM

K4D263238K

- 17/19 - Rev. 1.1 July 2007

PACKAGE DIMENSIONS (144-Ball FBGA)

Unit : mm

12.0

0.8

0.35 ± 0.05

1.40 Max

0.45 ± 0.05

0.8x11=8.8

0.40

0.8x11=8.8

0.40

13 12 11 10 9 8 7 6 5 4 3 2

A1 INDEX MARK

0.10 Max

128M GDDR SDRAM

K4D263238K

- 18/19 - Rev. 1.1 July 2007

Minimum Maximum Minimum Maximum

00000

0.1 4.2 5.24 1.84 2.44

0.2 9.92 11.36 -2.88 -2.88

0.3 15.28 17.24 -7.44 -8.16

0.4 20.56 23.12 -11.84 -13.16

0.5 25.6 28.76 -16 -18.24

0.6 30.36 34.24 -20.04 -23.08

0.7 34.88 39.48 -23.92 -27.84

0.8 38.96 44.64 -27.52 -32.4

0.9 42.64 49.48 -30.8 -36.84

1 45.76 53.92 -33.88 -41.04

1.1 48.4 57.92 -36.6 -45.04

1.2 50.48 61.56 -39 -48.84

1.3 52.04 64.72 -41.08 -52.48

1.4 53.24 67.28 -42.84 -55.76

1.5 54.16 69.44 -44.24 -58.84

1.6 54.8 71.2 -45.44 -61.56

1.7 55.32 72.52 -46.44 -64.04

1.8 55.76 73.48 -47.28 -66.16

1.9 56.16 74.28 -47.96 -68.04

2 56.48 74.92 -48.68 -69.64

2.1 56.8 75.4 -49.28 -71.04

2.2 57.08 75.84 -49.84 -72.24

2.3 57.36 76.24 -50.36 -73.36

2.4 57.64 76.56 -50.48 -74.24

2.5 57.84 76.8 -50.52 -75.08

2.6 58.08 77.12 -50.55 -75.84

2.7 58.28 77.36 -50.58 -76.56

Voltage(V) Pulldown Current(mA) Pullup Current(mA)

IBIS :I/V Characteristics for Input and Output Buffers

Full Strength Driver Characteristics

128M GDDR SDRAM

K4D263238K

- 19/19 - Rev. 1.1 July 2007

Minimum Maximum Minimum Maximum

0 0000

0.1 3.48 4.32 0.96 -2.68

0.2 7.96 9.2 -2.92 -7.4

0.3 12.24 14 -6.56 -11.96

0.4 16.44 18.76 -10.12 -16.4

0.5 20.36 23.2 -13.64 -20.68

0.6 24.08 27.6 -16.8 -24.84

0.7 27.36 31.8 -19.88 -28.88

0.8 30.48 35.68 -22.72 -32.8

0.9 33.12 39.36 -25.32 -36.48

1 35.32 42.6 -27.64 -40.08

1.1 37.08 45.6 -29.72 -43.44

1.2 38.4 48.08 -31.52 -46.44

1.3 39.44 50.2 -33.04 -49.36

1.4 40.16 51.92 -34.28 -51.96

1.5 40.72 53.28 -35.36 -54.4

1.6 41.12 54.32 -36.2 -56.48

1.7 41.52 55.08 -36.92 -58.36

1.8 41.84 55.68 -37.6 -60

1.9 42.08 56.2 -38.12 -61.48

2 42.32 56.56 -38.6 -62.72

2.1 42.56 56.92 -39.08 -63.8

2.2 42.76 57.24 -39.48 -64.8

2.3 42.96 57.44 -39.92 -65.64

2.4 43.16 57.72 -40.12 -66.4

2.5 43.32 57.92 -40.15 -67.12

2.6 43.52 58.12 -40.18 -67.72

2.7 43.68 58.32 -40.2 -68.32

Pulldown Current(mA) Pullup Current(mA)

Voltage(V)

Weak Strength Driver Characteristics

128M GDDR SDRAM

K4D263238K

- 20/19 - Rev. 1.1 July 2007

Minimum Maximum Minimum Maximum

00000

0.1 3.08 0.84 0.24 -2.36

0.2 6.76 4.84 -2.76 -5.88

0.3 10.28 8.56 -5.68 -9.36

0.4 13.72 12.32 -8.44 -12.8

0.5 16.84 15.92 -11.08 -16.16

0.6 19.84 19.36 -13.56 -19.24

0.7 22.48 22.64 -15.8 -22.32

0.8 24.88 25.72 -17.96 -25.16

0.9 26.8 28.56 -19.88 -27.92

1 28.44 31.16 -21.56 -30.52

1.1 29.6 33.44 -23.04 -32.92

1.2 30.52 35.36 -24.36 -35.12

1.3 31.24 36.96 -25.36 -37.12

1.4 31.8 38.16 -26.24 -38.88

1.5 32.12 39.12 -26.96 -40.52

1.6 32.44 39.84 -27.56 -41.96

1.7 32.68 40.4 -28.04 -43.12

1.8 32.92 40.84 -28.56 -44.24

1.9 33.16 41.2 -28.92 -45.12

2 33.28 41.44 -29.28 -45.96

2.1 33.48 41.72 -29.6 -46.6

2.2 33.64 41.88 -29.96 -47.28

2.3 33.8 42.08 -30.24 -47.84

2.4 33.92 42.24 -30.34 -48.36

2.5 34.12 42.44 -30.38 -48.84

2.6 34.24 42.56 -30.41 -49.28

2.7 34.36 42.68 -30.42 -49.68

Pulldown Current(mA) Pullup Current(mA)

Voltage(V)

Matched Strength Driver Characteristics